ASM5P2309A-1H-16-TT - Alliance Semiconductor

ASMP5P2309A

August 2004ASMP5P2305A

rev 2.0

Alliance Semiconducto

2575, Augustine Drive Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com

Notice: The information in this document is subject to change without notice.

CLKA1

CLKA2

CLKA3

CLKA4

CLKB1

CLKB2

CLKB3

CLKB4

CLKOUT

REF

Select Input

MUX

ASM5P2309A

Decoding

PLL

CLKOUT

CLK1

CLK2

CLK3

CLK4

REF

ASM5P2305A

3.3V Zero Delay Buffer

General Features

10 MHz to 133-MHz operating range, compatible

with CPU and PCI bus frequencies.

Zero input -output propagation delay.

Multiple low-skew outputs.

Output-output skew less than 250 ps.

Device-device skew less than 700 ps.

One input drives 9 outputs, grouped as 4 + 4

+ 1 (ASM5P2309A).

One input drives 5 outputs (ASM5P2305A).

Less than 200 ps cycle-to-cycle jitter is compatible

with Pentium®based systems.

Test Mode to bypass PLL (ASM5P2309A only,

refer Select Input Decoding Table).

Available in 16-pin, 150-mil SOIC, 4.4 mm

TSSOP, and 150-mil SSOP packages

(ASM5P2309A) or in 8-pin, 150-mil SOIC

package (ASM5P2305A).

3.3V operation, advanced 0.35µ CMOS

technology.

Functional Description

ASM5P2309A is a versatile, 3.3V zero-delay buffer

designed to distribute high-speed clocks. It accepts one

reference input and drives out nine low-skew clocks. It is

available in a 16-pin package. The ASM5P2305A is the

eight-pin version of the ASM5P2309A. It accepts one

reference input and drives out five low-skew clocks.

The -1H version of the ASM5P23XXA operates at up to

133-MHz frequencies, and has higher drive than the -1

devices. All parts have on-chip PLL’s that lock to an input

clock on the REF pin. The PLL feedback is on-chip and is

obtained from the CLKOUT pad.

The ASM5P2309A has two banks of four outputs each,

which can be controlled by the Select inputs as shown in

the Select Input Decoding Table. If all the output clocks are

not required, Bank B can be three-stated. The select input

also allows the input clock to be directly applied to the

outputs for chip and system testing purposes.

Multiple ASM5P2309A and ASM5P2305A devices can

accept the same input clock and distribute it. In this case

the skew between the outputs of the two devices is

guaranteed to be less than 700ps.

All outputs have less than 200 ps of cycle-to-cycle jitter.

The input and output propagation delay is guaranteed to be

less than 250 ps, and the output to output skew is

guaranteed to be less than 250ps.

The ASM5P2309A and the ASM5P2305A are available in

two different configurations, as shown in the ordering

information table. The ASM5P23XXA-1 is the base part.

The ASM5P23XXA-1H is the high drive version of the -1

and its rise and fall times are much faster than -1 part.

Block Diagram

ASMP5P2309A

August 2004ASMP5P2305A

rev 2.0

3.3V Zero Delay Buffer 2 of 14

Notice: The information in this document is subject to change without not

ice.

Select Input Decoding for ASM5P2309A

S2 S1 Clock A1 - A4 Clock B1 - B4 CLKOUT 1Output Source PLL

Shut-Down

0 0 Three-state Three-state Driven PLL N

0 1 Driven Three-state Driven PLL N

1 0 Driven Driven Driven Reference Y

1 1 Driven Driven Driven PLL N

Notes:

1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to

change the skew between the reference and the output.

Zero Delay and Skew Control

All outputs should be uniformly loaded to achieve

Zero Delay between input and output. Since the

CLKOUT pin is the internal feedback to the PLL, its

relative loading can adjust the input-output delay.

For applications requiring zero input-output delay, all

outputs, including CLKOUT, must be equally loaded.

Even if CLKOUT is not used, it must have a

capacitive load equal to that on other outputs, for

obtaining zero-input-output delay.

Pin Configuration

8 9

REF

CLKA1

CLKA2 CLKA3

CLKA4

CLKB1

CLKB2 CLKB3

CLKB4

VDD

GND

CLKOUT

GND

VDD ASM5P2309A

4 5

REF

CLK2

CLK1

CLK4

CLK3

VDD

CLKOUT

GND

ASM5P2305A

ASM5P2309A

August 2004ASM5P2305A

rev 2.0

3.3VZero Delay Buffer 3 of 14

Notice: The information in this document is subject to change without notice.

Pin Description for ASM5P2309A

Pin #Pin Name Description

1REF2Input reference frequency, 5V tolerant input

2CLKA13Buffered clock output, bank A

3CLKA23Buffered clock output, bank A

4 VDD 3.3V supply

5GND Ground

6CLKB13Buffered clock output, bank B

7CLKB2 3Buffered clock output, bank B

8 S2 4Select input, bit 2

9 S1 4Select input, bit 1

10 CLKB3 3Buffered clock output, bank B

11 CLKB4 3Buffered clock output, bank B

12 GND Ground

13 VDD 3.3V supply

14 CLKA3 3Buffered clock output, bank A

15 CLKA4 3Buffered clock output, bank A

16 CLKOUT3Buffered output, internal feedback on this pin

Pin Description for ASM5P2305A

Pin #Pin Name Description

1REF2Input reference frequency, 5V-tolerant input

2CLK2 3Buffered clock output

3CLK13Buffered clock output

4GND Ground

5CLK3 3Buffered clock output

6 VDD 3.3V supply

7CLK43Buffered clock output

8CLKOUT 3Buffered clock output, internal feedback on this pin

Notes:

2. Weak pull-down.

3. Weak pull-down on all outputs.

4. Weak pull-up on these inputs.

ASM5P2309A

August 2004ASM5P2305A

rev 2.0

3.3VZero Delay Buffer 4 of 14

Notice: The information in this document is subject to change without notice.

Absolute Maximum Ratings

Parameter Min Max Unit

Supply Voltage to Ground Potential -0.5 +7.0 V

DC Input Voltage (Except REF) -0.5 VDD + 0.5 V

DC Input Voltage (REF) -0.5 7 V

Storage Temperature -65 +150 °C

Max. Soldering Temperature (10 sec) 260 °C

Junction Temperature 150 °C

Static Discharge Voltage

(per MIL-STD-883, Method 3015) 2000 V

Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum

ratings for prolonged periods can affect device reliability.

Operating Conditions for ASM5P2305A and ASM5P2309A -Commercial Temperature Devices

Parameter Description Min Max Unit

VDD Supply Voltage 3.0 3.6 V

TAOperating Temperature (Ambient Temperature) 0 70 °C

CLLoad Capacitance, below 100 MHz 30 pF

CLLoad Capacitance, from 100 MHz to 133 MHz 10 pF

CIN Input Capacitance 7 pF

ASM5P2309A

August 2004ASM5P2305A

rev 2.0

3.3VZero Delay Buffer 5 of 14

Notice: The information in this document is subject to change without notice.

lectrical Characteristics for ASM5P2305A and ASM5P2309A -Commercial Temperature Devices

Parameter Description Test Conditions Min Max Unit

VIL Input LOW Voltage 50.8 V

VIH Input HIGH Voltage 52.0 V

IIL Input LOW Current VIN = 0V 50.0 µA

IIH Input HIGH Current VIN = VDD 100.0 µA

VOL Output LOW Voltage 6IOL = 8mA (-1)

IOH = 12mA (-1H) 0.4 V

VOH Output HIGH Voltage 6IOL = -8mA (-1)

IOH = -12mA (-1H) 2.4 V

IDD Supply Current Unloaded outputs at 66.67 MHz,

SEL inputs at VDD

TBD mA

S1 / S2 inputs are CMOS, TTL compatible inputs –

The input must toggle somewhere between 0.8 and 2.0. We guarantee the limits of 0.8 and 2.0, but can't guarantee anything tighter than

that. As Vdd moves higher the toggle point will move higher, but will always stay below 2.0V. As Vdd moves lower, the toggle point will

move lower, but always stay higher than 0.8V. What the 2.0V MIN Vih specification means is that you put 2.0V or a higher voltage into the

device, and you will have a logic HIGH. If you put 0.8V or a lower voltage into the device, you will have a logic LOW ( Vil spec = 0.8V max).

It will toggle someplace in between 0.8V and 2.0V, but we don't guarantee exactly where, and the exact point will change depending upon

conditions. Characterization shows we toggle at 1.1V and 1.5V (showing a little hysteresis), everything is perfect. We meet spec, plus have

~ 300mV noise immunity on the low end and ~500mV noise immunity on the high side. Under nominal conditions, with no hysteresis, most

devices will toggle at about 1.5V for both high and low.

Switching Characteristics for ASM5P2305A-1 and ASM5P2309A-1 - Commercial Temperature Devices7

Parameter Description Test Conditions Min Typ Max Unit

1/t1Output Frequency 30-pF load

10-pF load 10

10 100

133.3 3MHz

Duty Cycle 6= (t2 / t1) * 100 Measured at 1.4V, FOUT = 66.67 MHz 40.0 50.0 60.0 %

t3Output Rise Time 6Measured between 0.8V and 2.0V 2.50 ns

t4Output Fall Time 6Measured between 2.0V and 0.8V 2.50 ns

t5Output-to-output skew 6All outputs equally loaded 250 ps

t6Delay, REF Rising Edge to

CLKOUT Rising Edge 6Measured at VDD /2 0 ±350 ps

t7Device-to-Device Skew 6Measured at VDD/2 on the CLKOUT

pins of

the device 0700 ps

tJCycle-to-cycle jitter 6Measured at 66.67 MHz, loaded outputs 200 ps

tLOCK PLL Lock Time 6Stable power supply, valid clock pre

sented

on REF pin 1.0 ms

Notes:

5. REF input has a threshold voltage of VDD/2

6. Parameter is guaranteed by design and characterization. Not 100% tested in production

7. All parameters specified with loaded outputs.

ASM5P2309A

August 2004ASM5P2305A

rev 2.0

3.3VZero Delay Buffer 6 of 14

Notice: The information in this document is subject to change without notice.

Switching Characteristics for ASM5I2305A-1H and ASM5I2309A-1H - Industrial Temperature Devices7

Parameter Description Test Conditions Min Typ Max Unit

1/t1Output Frequency 30-pF load

10-pF load 10

10 100

133.33 MHz

Duty Cycle 6= (t2 / t1) * 100 Measured at 1.4 V, FOUT = 66.67 MHz 40.0 50.0 60.0 %

Duty Cycle 6= (t2 / t1) * 100 Measured at 1.4 V, FOUT < 50.0 MHz 45.0 50.0 55.0

t3 Output Rise Time 6Measured between 0.8V and 2.0V 1.50 ns

t4 Output Fall Time 6Measured between 2.0V and 0.8V 1.50 ns

t5 Output-to-output skew 6All outputs equally loaded 250 ps

t6 Delay, REF Rising Edge to

CLKOUT Rising Edge 6Measured at VDD /2 0 ± 350 ps

t7 Device-to-Device Skew 6

Measured at VDD/2 on the CLKOUT pins of

the device 0700 ps

t8 Output Slew Rate 6Measured between 0.8V and 2.0V using

Test Circuit #2 1V/ns

tJ Cycle-to-cycle jitter 6Measured at 66.67 MHz, loaded outputs 200 ps

tLOCK PLL Lock Time 6Stable power supply, valid clock pre sented

on REF pin 1.0 ms

ASM5P2309A

August 2004ASM5P2305A

rev 2.0

3.3VZero Delay Buffer 7 of 14

Notice: The information in this document is subject to change without notice.

Switching Waveforms

Duty Cycle Timing t1

1.4 V1.4 V1.4 V

All Outputs Rise/Fall Time

OUTPUT

2.0 V

0.8 V

t3 t4

3.3 V

0 V

2.0 V

0.8 V

Output -Output Skew

1.4 V

OUTPUT

Input -Output Propagation Delay

VDD /2

INPUT

OUTPUT

VDD /2

Device -Device Skew

VDD /2

CLKOUT, Device 1

VDD /2

CLKOUT, Device 2

ASM5P2309A

August 2004ASM5P2305A

rev 2.0

3.3VZero Delay Buffer 8 of 14

Notice: The information in this document is subject to change without notice.

Test Circuits

1k

10 pF

VDD

GND

OUTPUTS

CLK OUT

CLOAD

0.1 ÿF

1k

0.1 ÿF

VDD

GND GND GND

OUTPUTS

Test Circuit #1 Test Circuit #2

For parameter t

(output slew rate) on -1H devices

ASM5P2309A

August 2004ASM5P2305A

rev 2.0

3.3VZero Delay Buffer 9 of 14

Notice: The information in this document is subject to change without notice.

Package Information: 8-lead (150-mil) SOIC

A2 A



Symbol Dimensions in inches Dimensions in

millimeters

Min Max Min Max

A0.057 0.071 1.45 1.80

A1 0.004 0.010 0.10 0.25

A2 0.053 0.069 1.35 1.75

B0.012 0.020 0.31 0.51

C0.004 0.01 0.10 0.25

D0.186 0.202 4.72 5.12

E0.148 0.164 3.75 4.15

e0.050 BSC 1.27 BSC

H0.224 0.248 5.70 6.30

L0.012 0.028 0.30 0.70

0° 8° 0° 8°

ASM5P2309A

August 2004ASM5P2305A

rev 2.0

3.3VZero Delay Buffer 10 of 14

Notice: The information in this document is subject to change without notice.

Package Information: 16-lead (150 Mil) Molded SOIC



Seating Plane

0.004

PIN 1 ID

916

DIMENSIONS

INCHES MILLIMETERS

MIN MAX MIN MAX

A0.061 0.068 1.55 1.73

A1 0.004 0.0098 0.102 0.249

A2 0.055 0.061 1.40 1.55

B0.013 0.019 0.33 0.49

C0.0075 0.0098 0.191 0.249

D0.386 0.393 9.80 9.98

E0.150 0.157 3.81 3.99

e0.050 BSC 1.27 BSC

H0.230 0.244 5.84 6.20

h0.010 0.016 0.25 0.41

L0.016 0.035 0.41 0.89

0° 8° 0° 8°

ASM5P2309A

August 2004ASM5P2305A

rev 2.0

3.3VZero Delay Buffer 11 of 14

Notice: The information in this document is subject to change without notice.

Package Information: 16-lead Thin Shrunk Small Outline Package (4.40-MM Body)



PIN 1 ID

916 Seating Plane

DIMENSIONS (inches) DIMENSIONS (mm)

MIN MAX MIN MAX

A0.043 1.10

A1 0.002 0.006 0.05 0.15

A2 0.003 0.37 0.85 0.95

B0.007 0.012 0.19 0.30

C0.0040.008 0.09 0.20

D0.193 2.008 4.90 5.10

E0.169 0.177 4.30 4.50

e0.026 BSC 0.65 BSC

H0.246 0.256 6.25 6.50

L0.020 0.028 0.50 0.70

0° 8° 0° 8°

ASM5P2309A

August 2004ASM5P2305A

rev 2.0

3.3VZero Delay Buffer 12 of 14

Notice: The information in this document is subject to change without notice.

Package Information: 16-lead (150-mil) SSOP

E H



0.004

PIN 1 ID

Seating Plane

916

DIMENSIONS (inches) DIMENSIONS (millimeters)

MIN MAX MIN MAX

A0.049 0.065 1.245 1.651

A1 0.004 0.010 0.102 0.254

B0.008 0.012 0.203 0.305

C0.007 0.010 0.178 0.254

D0.189 0.197 4.801 5.004

E0.150 0.157 3.81 3.988

e0.025 BSC 0.635 BSC

H0.228 0.244 5.791 6.198

L0.016 0.050 0.406 1.27

0° 8° 0° 8°

ASM5P2309A

August 2004ASM5P2305A

rev 2.0

3.3VZero Delay Buffer 13 of 14

Notice: The information in this document is subject to change without notice.

Ordering Codes

Ordering Code Package Type Operating Range

ASM5P2309A-1-16-ST 16-pin 150-mil SOIC-TUBE Commercial

ASM5I2309A-1-16-ST 16-pin 150-mil SOIC-TUBE Industrial

ASM5P2309A-1-16-SR 16-pin 150-mil SOIC-TAPE & REEL Commercial

ASM5I2309A-1-16-SR 16-pin 150-mil SOIC-TAPE & REEL Industrial

ASM5P2309A-1-16-TT 16-PIN 150-mil TSSOP -TUBE Commercial

ASM5I2309A-1-16-TT 16-PIN 150-mil TSSOP -TUBE Industrial

ASM5P2309A-1-16-TR 16-PIN 150-mil TSSOP -TAPE & REEL Commercial

ASM5I2309A-1-16-TR 16-PIN 150-mil TSSOP -TAPE & REEL Industrial

ASM5P2309A-1H-16-ST 16-pin 150-mil SOIC-TUBE Commercial

ASM5I2309A-1H-16-ST 16-pin 150-mil SOIC-TUBE Industrial

ASM5P2309A-1H-16-SR 16-pin 150-mil SOIC-TAPE & REEL Commercial

ASM5I2309A-1H-16-SR 16-pin 150-mil SOIC-TAPE & REEL Industrial

ASM5P2309A-1H-16-TT 16-PIN 150-mil TSSOP -TUBE Commercial

ASM5I2309A-1H-16-TT 16-PIN 150-mil TSSOP -TUBE Industrial

ASM5P2309A-1H-16-TR 16-PIN 150-mil TSSOP -TAPE & REEL Commercial

ASM5I2309A-1H-16-TR 16-PIN 150-mil TSSOP -TAPE & REEL Industrial

ASM5P2305A-1-08-ST 8-pin 150-mil SOIC-TUBE Commercial

ASM5I2305A-1-08-ST 8-pin 150-mil SOIC-TUBE Industrial

ASM5P2305A-1-08-SR 8-pin 150-mil SOIC-TAPE & REEL Commercial

ASM5I2305A-1-08-SR 8-pin 150-mil SOIC-TAPE &REEL Industrial

ASM5P2305A-1-08-TT 8-PIN 150-mil TSSOP -TUBE Commercial

ASM5I2305A-1-08-TT 8-PIN 150-mil TSSOP -TUBE Industrial

ASM5P2305A-1-08-TR 8-PIN 150-mil TSSOP -TAPE & REEL Commercial

ASM5I2305A-1-08-TR 8-PIN 150-mil TSSOP -TAPE & REEL Industrial

ASM5P2305A-1H-08-ST 8-pin 150-mil SOIC-TUBE Commercial

ASM5I2305A-1H-08-ST 8-pin 150-mil SOIC-TUBE Industrial

ASM5P2305A-1H-08-SR 8-pin 150-mil SOIC-TAPE & REEL Commercial

ASM5I2305A-1H-08-SR 8-pin 150-mil SOIC-TAPE & REEL Industrial

ASM5P2305A-1H-08-TT 8-PIN 150-mil TSSOP -TUBE Commercial

ASM5I2305A-1H-08-TT 8-PIN 150-mil TSSOP -TUBE Industrial

ASM5P2305A-1H-08-TR 8-PIN 150-mil TSSOP -TAPE & REEL Commercial

ASM5I2305A-1H-08-TR 8-PIN 150-mil TSSOP -TAPE & REEL Industrial

Licensed under US patent Nos 5,488,627 and 5,631,920.

Preliminary datasheet. Specification subject to change without notice.

ASM5P2309A

August 2004ASM5P2305A

rev 2.0

3.3VZero Delay Buffer 14 of 14

Notice: The information in this document is subject to change without notice.

trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their

respective companies. Alliance reserves the right to make changes to this document and its products at any time without

notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein

represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this

data at any time, without notice. If the product described herein is under development, significant changes to these

specifications are possible. The information in this product data sheet is intended to be general descriptive information for

potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or

customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product

described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products

including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual

property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance).

All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of

products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any

other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical

components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant

injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer

assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.

Alliance Semiconductor Corporation

2595, Augustine Drive,

Santa Clara, CA 95054

Tel# 408-855-4900

Fax: 408-855-4999

www.alsc.com

Part Number: ASM5P2309A

ASM5P2305A

Document Version: 2.0 8_30_2004