ASMP5P2309A ASMP5P2305A August 2004 rev 2.0 3.3V Zero Delay Buffer General Features 133- MHz frequencies, and has higher drive than the -1 10 MHz to 133- MHz operating range, compatible devices. All parts have on-chip PLL's that lock to an input with CPU and PCI bus frequencies. clock on the REF pin. The PLL feedback is on-chip and is Zero input - output propagation delay. obtained from the CLKOUT pad. Multiple low-skew outputs. Output-output skew less than 250 ps. The ASM5P2309A has two banks of four outputs each, Device-device skew less than 700 ps. which can be controlled by the Select inputs as shown in One input drives 9 outputs, grouped as 4 + 4 the Select Input Decoding Table. If all the output clocks are + 1 (ASM5P2309A). not required, Bank B can be three-stated. The select input One input drives 5 outputs (ASM5P2305A). also allows the input clock to be directly applied to the Less than 200 ps cycle-to-cycle jitter is compatible outputs for chip and system testing purposes. with Pentium (R) based systems. Test Mode to bypass PLL (ASM5P2309A only, Multiple ASM5P2309A and ASM5P2305A devices can refer Select Input Decoding Table). accept the same input clock and distribute it. In this case Available in 16-pin, 150-mil SOIC, 4.4 mm the skew between the outputs of the two devices is TSSOP, guaranteed to be less than 700ps. and 150-mil SSOP packages (ASM5P2309A) or in 8-pin, 150- mil SOIC package (ASM5P2305A). 3.3V operation, advanced All outputs have less than 200 ps of cycle-to-cycle jitter. 0.35 CMOS The input and output propagation delay is guaranteed to be technology. less than 250 ps, and the output to output skew is guaranteed to be less than 250ps. Functional Description ASM5P2309A is a versatile, 3.3V zero-delay buffer The ASM5P2309A and the ASM5P2305A are available in designed to distribute high-speed clocks. It accepts one two different configurations, as shown in the ordering reference input and drives out nine low-skew clocks. It is information table. The ASM5P23XXA-1 is the base part. available in a 16-pin package. The ASM5P2305A is the The ASM5P23XXA-1H is the high drive version of the -1 eight-pin version of the ASM5P2309A. It accepts one and its rise and fall times are much faster than -1 part. reference input and drives out five low-skew clocks. The -1H version of the ASM5P23XXA operates at up to Block Diagram REF CLKOUT PLL MUX PLL REF CLKOUT CLKA1 CLK1 CLKA2 CLK2 CLKA3 CLK3 CLKA4 CLK4 CLKB1 S2 Select Input Decoding S1 CLKB2 CLKB3 ASM5P2305A CLKB4 ASM5P2309A Alliance Semiconductor 2575, Augustine Drive Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com Notice: The information in this document is subject to change without notice. ASMP5P2309A ASMP5P2305A August 2004 rev 2.0 Select Input Decoding for ASM5P2309A S2 S1 Clock A1 - A4 Clock B1 - B4 CLKOUT 1 Output Source PLL Shut-Down 0 0 Three-state Three-state Driven PLL N 0 1 Driven Three-state Driven PLL N 1 0 Driven Driven Driven Reference Y 1 1 Driven Driven Driven PLL N Notes: 1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and the output. Zero Delay and Skew Control All outputs should be uniformly loaded to achieve Zero Delay between input and output. Since the CLKOUT pin is the internal feedback to the PLL, its relative loading can adjust the input-output delay. For applications requiring zero input-output delay, all outputs, including CLKOUT, must be equally loaded. Even if CLKOUT is not used, it must have a capacitive load equal to that on other outputs, for obtaining zero-input-output delay. Pin Configuration REF 1 16 CLKOUT CLKA1 2 15 CLKA4 CLKA2 3 14 CLKA3 V 4 13 V DD 12 GND DD ASM5P2309A GND 5 CLKB1 6 11 CLKB4 CLKB2 7 10 CLKB3 S2 8 9 S1 1 8 CLKOUT CLK2 2 7 CLK4 CLK1 3 6 V GND 4 5 CLK3 REF ASM5P2305A DD 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 2 of 14 ASM5P2309A ASM5P2305A August 2004 rev 2.0 Pin Description for ASM5P2309A Pin # Pin Name 1 REF 2 2 Input reference frequency, 5V tolerant input 3 Buffered clock output, bank A 3 Buffered clock output, bank A CLKA1 3 CLKA2 4 VDD 5 GND 6 7 8 9 3.3V supply Ground 3 Buffered clock output, bank B 3 Buffered clock output, bank B CLKB1 CLKB2 S2 4 S1 4 Description Select input, bit 2 Select input, bit 1 CLKB3 3 Buffered clock output, bank B 11 CLKB4 3 Buffered clock output, bank B 12 GND 13 VDD 10 14 15 16 Ground 3.3V supply CLKA3 3 Buffered clock output, bank A CLKA4 3 Buffered clock output, bank A 3 CLKOUT Buffered output, internal feedback on this pin Pin Description for ASM5P2305A Pin # Pin Name 2 Description 1 REF 2 CLK2 3 Buffered clock output 3 3 CLK1 Buffered clock output 4 GND 5 CLK3 6 VDD 7 8 Input reference frequency, 5V-tolerant input Ground 3 Buffered clock output 3.3V supply 3 CLK4 CLKOUT Buffered clock output 3 Buffered clock output, internal feedback on this pin Notes: 2. Weak pull-down. 3. Weak pull-down on all outputs. 4. Weak pull-up on these inputs. 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 3 of 14 ASM5P2309A ASM5P2305A August 2004 rev 2.0 Absolute Maximum Ratings Parameter Min Max Unit Supply Voltage to Ground Potential -0.5 +7.0 V DC Input Voltage (Except REF) -0.5 VDD + 0.5 V DC Input Voltage (REF) -0.5 7 V Storage Temperature -65 +150 C Max. Soldering Temperature (10 sec) 260 C Junction Temperature 150 C Static Discharge Voltage 2000 V (per MIL-STD-883, Method 3015) Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum ratings for prolonged periods can affect device reliability. Operating Conditions for ASM5P2305A and ASM5P2309A - Commercial Temperature Devices Parameter Description Min Max Unit 3.0 3.6 V 0 70 C VDD Supply Voltage TA Operating Temperature (Ambient Temperature) CL Load Capacitance, below 100 MHz 30 pF CL Load Capacitance, from 100 MHz to 133 MHz 10 pF CIN Input Capacitance 7 pF 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 4 of 14 ASM5P2309A ASM5P2305A August 2004 rev 2.0 lectrical Characteristics for ASM5P2305A and ASM5P2309A - Commercial Temperature Devices Parameter VIL Description Input LOW Voltage VIH Input HIGH Voltage IIL Input LOW Current IIH Input HIGH Current VOL Test Conditions Min 5 5 Output LOW Voltage Max Unit 0.8 V 2.0 6 V VIN = 0V 50.0 A VIN = VDD 100.0 A 0.4 V IOL = 8mA (-1) IOH = 12mA (-1H) VOH Output HIGH Voltage 6 IOL = -8mA (-1) 2.4 V IOH = -12mA (-1H) IDD Supply Current Unloaded outputs at 66.67 MHz, TBD mA SEL inputs at VDD S1 / S2 inputs are CMOS, TTL compatible inputs - The input must toggle somewhere between 0.8 and 2.0. We guarantee the limits of 0.8 and 2.0, but can't guarantee anything tighter than that. As Vdd moves higher the toggle point will move higher, but will always stay below 2.0V. As Vdd moves lower, the toggle point will move lower, but always stay higher than 0.8V. What the 2.0V MIN Vih specification means is that you put 2.0V or a higher voltage into the device, and you will have a logic HIGH. If you put 0.8V or a lower voltage into the device, you will have a logic LOW ( Vil spec = 0.8V max). It will toggle someplace in between 0.8V and 2.0V, but we don't guarantee exactly where, and the exact point will change depending upon conditions. Characterization shows we toggle at 1.1V and 1.5V (showing a little hysteresis), everything is perfect. We meet spec, plus have ~ 300mV noise immunity on the low end and ~500mV noise immunity on the high side. Under nominal conditions, with no hysteresis, most devices will toggle at about 1.5V for both high and low. Switching Characteristics for ASM5P2305A-1 and ASM5P2309A-1 - Commercial Temperature Devices7 Parameter 1/t1 Description Test Conditions Output Frequency 6 Duty Cycle = (t2 / t1) * 100 t3 t4 Output Rise Time Output Fall Time 6 6 6 t5 Output-to-output skew t6 Delay, REF Rising Edge to CLKOUT Rising Edge t7 Min Typ Max Unit MHz 30-pF load 10 100 10-pF load 10 133.3 3 Measured at 1.4V, FOUT = 66.67 MHz 40.0 50.0 60.0 % Measured between 0.8V and 2.0V 2.50 ns Measured between 2.0V and 0.8V 2.50 ns All outputs equally loaded 250 ps Measured at VDD /2 0 350 ps Measured at VDD/2 on the CLKOUT pins of 0 700 ps Measured at 66.67 MHz, loaded outputs 200 ps Stable power supply, valid clock presented 1.0 ms 6 Device-to-Device Skew 6 the device tJ tLOCK Cycle-to-cycle jitter PLL Lock Time 6 6 on REF pin Notes: 5. REF input has a threshold voltage of VDD/2 6. Parameter is guaranteed by design and characterization. Not 100% tested in production 7. All parameters specified with loaded outputs. 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 5 of 14 ASM5P2309A ASM5P2305A August 2004 rev 2.0 Switching Characteristics for ASM5I2305A-1H and ASM5I2309A-1H - Industrial Temperature Devices7 Parameter 1/t1 Description Output Frequency Test Conditions Min Typ Max Unit MHz 30-pF load 10 100 10-pF load 10 133.33 6 Measured at 1.4 V, FOUT = 66.67 MHz 40.0 50.0 60.0 6 Duty Cycle = (t2 / t1) * 100 Measured at 1.4 V, FOUT < 50.0 MHz 45.0 50.0 55.0 t3 Output Rise Time 6 Measured between 0.8V and 2.0V 1.50 ns t4 Output Fall Time 6 Measured between 2.0V and 0.8V 1.50 ns t5 Output-to-output skew 6 All outputs equally loaded 250 ps t6 Delay, REF Rising Edge to Measured at VDD /2 0 350 ps Measured at VDD/2 on the CLKOUT pins of 0 700 ps Duty Cycle = (t2 / t1) * 100 % CLKOUT Rising Edge 6 t7 Device-to-Device Skew 6 the device t8 Output Slew Rate 6 Measured between 0.8V and 2.0V using 1 V/ns Test Circuit #2 tJ tLOCK Cycle-to-cycle jitter 6 Measured at 66.67 MHz, loaded outputs 200 ps PLL Lock Time 6 Stable power supply, valid clock pre sented 1.0 ms on REF pin 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 6 of 14 ASM5P2309A ASM5P2305A August 2004 rev 2.0 Switching Waveforms Duty Cycle Timing t1 t2 1.4 V 1.4 V 1.4 V All Outputs Rise/Fall Time 2.0 V 0.8 V OUTPUT 2.0 V 0.8 V 3.3 V 0V t4 t3 Output - Output Skew 1.4 V OUTPUT 1.4 V OUTPUT t5 Input - Output Propagation Delay V DD /2 INPUT VDD /2 OUTPUT t6 Device - Device Skew V DD /2 CLKOUT, Device 1 V DD /2 CLKOUT, Device 2 t7 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 7 of 14 ASM5P2309A ASM5P2305A August 2004 rev 2.0 Test Circuits Test Circuit #2 Test Circuit #1 V V DD OUTPUTS 0.1 yF 1k DD CLK OUT OUTPUTS 0.1 yF 1k C LOAD DD DD 0.1 yF GND 10 pF V V GND 0.1 yF GND GND For parameter t8 (output slew rate) on -1H devices 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 8 of 14 ASM5P2309A ASM5P2305A August 2004 rev 2.0 Package Information: 8-lead (150-mil) SOIC H E D A2 A C D e A1 L B Symbol Dimensions in inches Dimensions in millimeters Min Max Min Max A 0.057 0.071 1.45 1.80 A1 0.004 0.010 0.10 0.25 A2 0.053 0.069 1.35 1.75 B 0.012 0.020 0.31 0.51 C 0.004 0.01 0.10 0.25 D 0.186 0.202 4.72 5.12 E 0.148 0.164 3.75 4.15 e 0.050 BSC 1.27 BSC H 0.224 0.248 5.70 6.30 L 0.012 0.028 0.30 0.70 0 8 0 8 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 9 of 14 ASM5P2309A ASM5P2305A August 2004 rev 2.0 Package Information: 16-lead (150 Mil) Molded SOIC PIN 1 ID 1 8 E 9 H 16 h D Seating Plane A2 D A e C 0.004 L A1 B DIMENSIONS INCHES MILLIMETERS MIN MAX MIN MAX A 0.061 0.068 1.55 1.73 A1 0.004 0.0098 0.102 0.249 A2 0.055 0.061 1.40 1.55 B 0.013 0.019 0.33 0.49 C 0.0075 0.0098 0.191 0.249 D 0.386 0.393 9.80 9.98 E 0.150 0.157 3.81 3.99 e 0.050 BSC 1.27 BSC H 0.230 0.244 5.84 6.20 h 0.010 0.016 0.25 0.41 L 0.016 0.035 0.41 0.89 0 8 0 8 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 10 of 14 ASM5P2309A ASM5P2305A August 2004 rev 2.0 Package Information: 16-lead Thin Shrunk Small Outline Package (4.40-MM Body) 1 8 PIN 1 ID E 16 A A2 e A1 Seating Plane C D 9 H B L D DIMENSIONS (inches) MIN MAX A DIMENSIONS (mm) MIN MAX 0.043 1.10 A1 0.002 0.006 0.05 0.15 A2 0.003 0.37 0.85 0.95 B 0.007 0.012 0.19 0.30 C 0.004 0.008 0.09 0.20 D 0.193 2.008 4.90 5.10 E 0.169 0.177 4.30 4.50 e 0.026 BSC 0.65 BSC H 0.246 0.256 6.25 6.50 L 0.020 0.028 0.50 0.70 0 8 0 8 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 11 of 14 ASM5P2309A ASM5P2305A August 2004 rev 2.0 Package Information: 16-lead (150-mil) SSOP 8 1 PIN 1 ID E H 16 9 D A D A1 Seating Plane B e C 0.004 L DIMENSIONS (inches) DIMENSIONS (millimeters) MIN MAX MIN MAX A 0.049 0.065 1.245 1.651 A1 0.004 0.010 0.102 0.254 B 0.008 0.012 0.203 0.305 C 0.007 0.010 0.178 0.254 D 0.189 0.197 4.801 5.004 E 0.150 0.157 3.81 3.988 e 0.025 BSC 0.635 BSC H 0.228 0.244 5.791 6.198 L 0.016 0.050 0.406 1.27 0 8 0 8 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 12 of 14 ASM5P2309A ASM5P2305A August 2004 rev 2.0 Ordering Codes Ordering Code Package Type Operating Range ASM5P2309A-1-16-ST 16-pin 150-mil SOIC-TUBE Commercial ASM5I2309A-1-16-ST 16-pin 150-mil SOIC- TUBE Industrial ASM5P2309A-1-16-SR 16-pin 150-mil SOIC-TAPE & REEL Commercial ASM5I2309A-1-16-SR 16-pin 150-mil SOIC-TAPE & REEL Industrial ASM5P2309A-1-16-TT 16-PIN 150-mil TSSOP - TUBE Commercial ASM5I2309A-1-16-TT 16-PIN 150-mil TSSOP - TUBE Industrial ASM5P2309A-1-16-TR 16-PIN 150-mil TSSOP - TAPE & REEL Commercial ASM5I2309A-1-16-TR 16-PIN 150-mil TSSOP - TAPE & REEL Industrial ASM5P2309A-1H-16-ST 16-pin 150-mil SOIC-TUBE Commercial ASM5I2309A-1H-16-ST 16-pin 150-mil SOIC- TUBE Industrial ASM5P2309A-1H-16-SR 16-pin 150-mil SOIC-TAPE & REEL Commercial ASM5I2309A-1H-16-SR 16-pin 150-mil SOIC-TAPE & REEL Industrial ASM5P2309A-1H-16-TT 16-PIN 150-mil TSSOP - TUBE Commercial ASM5I2309A-1H-16-TT 16-PIN 150-mil TSSOP - TUBE Industrial ASM5P2309A-1H-16-TR 16-PIN 150-mil TSSOP - TAPE & REEL Commercial ASM5I2309A-1H-16-TR 16-PIN 150-mil TSSOP - TAPE & REEL Industrial ASM5P2305A-1-08-ST 8-pin 150-mil SOIC-TUBE Commercial ASM5I2305A-1-08-ST 8-pin 150-mil SOIC- TUBE Industrial ASM5P2305A-1-08-SR 8-pin 150-mil SOIC-TAPE & REEL Commercial ASM5I2305A-1-08-SR 8-pin 150-mil SOIC-TAPE & REEL Industrial ASM5P2305A-1-08-TT 8-PIN 150-mil TSSOP - TUBE Commercial ASM5I2305A-1-08-TT 8-PIN 150-mil TSSOP - TUBE Industrial ASM5P2305A-1-08-TR 8-PIN 150-mil TSSOP - TAPE & REEL Commercial ASM5I2305A-1-08-TR 8-PIN 150-mil TSSOP - TAPE & REEL Industrial ASM5P2305A-1H-08-ST 8-pin 150-mil SOIC-TUBE Commercial ASM5I2305A-1H-08-ST 8-pin 150-mil SOIC- TUBE Industrial ASM5P2305A-1H-08-SR 8-pin 150-mil SOIC-TAPE & REEL Commercial ASM5I2305A-1H-08-SR 8-pin 150-mil SOIC-TAPE & REEL Industrial ASM5P2305A-1H-08-TT 8-PIN 150-mil TSSOP - TUBE Commercial ASM5I2305A-1H-08-TT 8-PIN 150-mil TSSOP - TUBE Industrial ASM5P2305A-1H-08-TR 8-PIN 150-mil TSSOP - TAPE & REEL Commercial ASM5I2305A-1H-08-TR 8-PIN 150-mil TSSOP - TAPE & REEL Industrial Licensed under US patent Nos 5,488,627 and 5,631,920. Preliminary datasheet. Specification subject to change without notice. 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 13 of 14 ASM5P2309A ASM5P2305A August 2004 rev 2.0 Alliance Semiconductor Corporation 2595, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com Copyright (c) Alliance Semiconductor All Rights Reserved Part Number: ASM5P2309A ASM5P2305A Document Version: 2.0 8_30_2004 (c) Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. 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Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 14 of 14