74FST3257 Quad 2:1 Multiplexer/ Demultiplexer Bus Switch The ON Semiconductor 74FST3257 is a quad 2:1, high performance multiplexer/demultiplexer bus switch. The device is CMOS TTL compatible when operating between 4 and 5.5 Volts. The device exhibits extremely low RON and adds nearly zero propagation delay. The device adds no noise or ground bounce to the system. http://onsemi.com MARKING DIAGRAMS Features * * * * * * * * RON t 4 W Typical Less Than 0.25 ns-Max Delay Through Switch Nearly Zero Standby Current No Circuit Bounce Control Inputs are TTL/CMOS Compatible Pin-For-Pin Compatible With QS3257, FST3257, CBT3257 All Popular Packages: SOIC-16, TSSOP-16, QFN16 These Devices are Pb-Free and are RoHS Compliant 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC OE 4B1 4B2 4A 3B1 3B2 3A 1 16 1B1 2 1B2 3 1 16 16 FST 3257 ALYW G G 1 1 15 OE 14 4B1 GND 1A 4 13 4B2 2B1 5 12 4A 2B2 6 11 3B1 2A 7 FST3257G AWLYWW 1 SOIC-16 D SUFFIX CASE 751B TSSOP-16 DT SUFFIX CASE 948F S VCC S 1B1 1B2 1A 2B1 2B2 2A GND 16 16 8 9 GND 3A 10 3B2 Figure 1. 16-Lead Pinout Diagrams 1 3257 ALYWG G QFN16 MN SUFFIX CASE 485AW A WL, L Y WW, W G or G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package (Note: Microdot may be in either location) PIN NAMES OE Function X H Disconnect L L A = B1 H L A = B2 S Figure 2. Truth Table Pin Description OE1, OE2 Bus Switch Enables S0, S1 Select Inputs A Bus A B1, B2, B3, B4 Bus B ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. (c) Semiconductor Components Industries, LLC, 2011 June, 2011 - Rev. 7 1 Publication Order Number: 74FST3257/D 74FST3257 1A 1B 1B2 2A 2B1 2B2 3A 3B1 3B2 4A 4B1 4B2 FLOW CONTROL OE S Figure 3. Logic Diagram ORDERING INFORMATION Package Shipping SOIC-16 (Pb-Free) 2500 Units / Tape & Reel 74FST3257DTR2G TSSOP-16* (Pb-Free) 2500 Units / Tape & Reel 74FST3257MNTWG QFN16 (Pb-Free) 3000 Units / Tape & Reel Device Order Number 74FST3257DR2G For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free. http://onsemi.com 2 74FST3257 MAXIMUM RATINGS Symbol Value Units DC Supply Voltage -0.5 to +7.0 V VI DC Input Voltage -0.5 to +7.0 V VO DC Output Voltage -0.5 to +7.0 V IIK DC Input Diode Current VI t GND -50 IOK DC Output Diode Current VO t GND -50 IO DC Output Sink Current 128 mA ICC DC Supply Current per Supply Pin 100 mA IGND DC Ground Current per Ground Pin 100 mA TSTG Storage Temperature Range VCC Parameter mA mA -65 to +150 _C TL Lead Temperature, 1 mm from Case for 10 Seconds 260 _C TJ Junction Temperature Under Bias +150 _C qJA Thermal Resistance SOIC TSSOP QFN 125 170 N/A MSL Moisture Sensitivity Level 1 FR VESD ILatchup Flammability Rating Oxygen Index: 28 to 34 _C/W UL 94 V-0 @ 0.125 in ESD Withstand Voltage Human Body Model (Note 1) Machine Model (Note 2) Charged Device Model (Note 3) V u2000 u200 N/A Latchup Performance Above VCC and Below GND at 85_C (Note 4) mA 500 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Tested to EIA/JESD22-A114-A. 2. Tested to EIA/JESD22-A115-A. 3. Tested to JESD22-C101-A. 4. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Supply Voltage Operating, Data Retention Only Min Max 4.0 5.5 Units V VI Input Voltage (Note 5) 0 5.5 V VO Output Voltage (HIGH or LOW State) 0 5.5 V TA Operating Free-Air Temperature -40 +85 _C Dt/DV Input Transition Rise or Fall Rate Switch I/O DC 5 ns/V 0 Switch Control Input VCC = 5.0 V 0.5 V 5. Unused control inputs may not be left open. All control inputs must be tied to a high or low logic input voltage level. http://onsemi.com 3 74FST3257 DC ELECTRICAL CHARACTERISTICS VCC Symbol Parameter VIK Clamp Diode Voltage VIH High-Level Input Voltage VIL Low-Level Input Voltage Conditions (V) IIN = -18 mA TA = -40_C to +85_C Min Typ* 4.5 4.0 to 5.5 Max Units -1.2 V 2.0 V 4.0 to 5.5 0.8 V Input Leakage Current 0 VIN 5.5 V 5.5 1.0 mA IOZ Off-State Leakage Current 0 A, B VCC 5.5 1.0 mA RON Switch On Resistance (Note 6) VIN = 0 V, IIN = 64 mA 4.5 4 7 W VIN = 0 V, IIN = 30 mA 4.5 4 7 VIN = 2.4 V, IIN = 15 mA 4.5 8 15 11 20 II VIN = 2.4 V, IIN = 15 mA 4.0 ICC Quiescent Supply Current VIN = VCC or GND, IOUT = 0 5.5 3 mA DICC Increase In ICC per Input One input at 3.4 V, Other inputs at VCC or GND 5.5 2.5 mA *Typical values are at VCC = 5.0 V and TA = 25_C. 6. Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the voltages on the two (A or B) pins. AC ELECTRICAL CHARACTERISTICS TA = -40_C to +85_C CL = 50 pF, RU = RD = 500 W VCC = 4.5-5.5 V Symbol Parameter Conditions Min Max Units 0.25 0.25 ns 1.0 4.7 5.2 VI = OPEN Max VCC = 4.0 V Min tPHL, tPLH Prop Delay Bus to Bus (Note 7) tPZH, tPZL Output Enable Time, Select to Bus B VI = 7 V for tPZL 1.0 5.2 5.7 Output Enable Time, IOE to Bus A, B VI = OPEN for tPZH 1.0 5.1 5.6 tPHZ, tPLZ Output Disable Time, Select to Bus B VI = 7 V for tPLZ 1.0 5.2 5.5 Output Disable Time, IOE to Bus A, B VI = OPEN for tPHZ 1.0 5.5 5.5 Prop Delay, Select to Bus A ns ns 7. This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance). CAPACITANCE (Note 8) Symbol Parameter Conditions Typ Max Units CIN Control Pin Input Capacitance VCC = 5.0 V 3 pF CI/O A Port Input/Output Capacitance VCC, OE = 5.0 V 7 pF CI/O B Port Input/Output Capacitance VCC, OE = 5.0 V 5 pF 8. TA = )25_C, f = 1 MHz, Capacitance is characterized but not tested. http://onsemi.com 4 74FST3257 AC Loading and Waveforms VI 500 W FROM OUTPUT UNDER TEST CL * 500 W NOTES: 1. Input driven by 50 W source terminated in 50 W. 2. CL includes load and stray capacitance. *CL = 50 pF Figure 4. AC Test Circuit tf = 2.5 nS 90 % SWITCH INPUT tf = 2.5 nS 90 % 1.5 V 3.0 V 1.5 V 10 % 10 % tPLH GND tPLH VOH 1.5 V OUTPUT 1.5 V VOL Figure 5. Propagation Delays tf = 2.5 nS tf = 2.5 nS ENABLE INPUT 90 % 90 % 1.5 V 1.5 V 10 % 10 % GND tPLZ tPZL OUTPUT 3.0 V 1.5 V tPZH VOL + 0.3 V VOL tPHZ VOH 1.5 V OUTPUT Figure 6. Enable/Disable Delays http://onsemi.com 5 VOH - 0.3 V 74FST3257 PACKAGE DIMENSIONS SOIC-16 D SUFFIX CASE 751B-05 ISSUE K -A- 16 9 1 8 -B- P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 8 PL 0.25 (0.010) B M S G R K F X 45 _ C -T- SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS http://onsemi.com 6 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 74FST3257 PACKAGE DIMENSIONS TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE B 16X K REF 0.10 (0.004) 0.15 (0.006) T U T U M S V S K S EEE CCC CCC EEE K1 2X L/2 16 9 J1 B -U- L SECTION N-N J PIN 1 IDENT. N 8 1 0.25 (0.010) M 0.15 (0.006) T U S A -V- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. N F DETAIL E -W- C 0.10 (0.004) -T- SEATING PLANE D H G DETAIL E DIM A B C D F G H J J1 K K1 L M SOLDERING FOOTPRINT 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS http://onsemi.com 7 MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ 74FST3257 PACKAGE DIMENSIONS QFN16 MN SUFFIX CASE 485AW-01 ISSUE O D PIN ONE REFERENCE A B EEE EEE EEE 2X DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS E DIM A A1 A3 b D D2 E E2 e K L L1 CCC EEE EXPOSED Cu 0.15 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSIONS b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L1 0.15 C 2X TOP VIEW MOLD CMPD DETAIL B ALTERNATE CONSTRUCTIONS A DETAIL B (A3) 0.10 C 16X L A1 0.08 C SOLDERING FOOTPRINT* NOTE 4 C SIDE VIEW MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 2.50 BSC 0.85 1.15 3.50 BSC 1.85 2.15 0.50 BSC 0.20 --0.35 0.45 --0.15 3.80 SEATING PLANE 2.10 0.15 C A B 0.50 PITCH D2 16X L 8 K 2.80 1.10 10 DETAIL A 0.15 C A B 1 E2 16X 16X 2 15 e 1 b 0.10 C A B 0.05 C NOTE 3 0.60 16X 0.30 PACKAGE OUTLINE DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. e/2 BOTTOM VIEW ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 http://onsemi.com 8 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative 74FST3257/D