Preliminary GS8161Z18/36AT-300/275/250/225/200 18Mb Pipelined and Flow Through Synchronous NBT SRAM Flow Through 2-1-1-1 1.8 V 2.5 V 300 345 300 340 275 320 275 315 250 295 250 285 230 265 225 260 mA mA mA mA tKQ tCycle 5.0 5.0 5.25 5.25 5.5 5.5 6.0 6.0 6.5 6.5 ns ns Curr (x18) Curr (x36) Curr (x18) Curr (x36) 220 265 220 265 215 260 215 260 210 245 210 245 200 235 200 235 tia l en nf id Co The GS8161Z18/36AT is implemented with GSI's high performance CMOS technology and is available in a JEDECstandard 100-pin TQFP package. Te ch 2.5 V 320 375 320 370 G SI 1.8 V tKQ tCycle Curr (x18) Curr (x36) Curr (x18) Curr (x36) y-- Pipeline 3-1-1-1 -300 -275 -250 -225 -200 Unit 2.2 2.4 2.5 2.7 3.0 ns 3.3 3.6 4.0 4.4 5.0 ns The GS8161Z18/36AT may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edgetriggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. y * User-configurable Pipeline and Flow Through mode * NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization * Fully pin-compatible with both pipelined and flow through NtRAMTM, NoBLTM and ZBTTM SRAMs * IEEE 1149.1 JTAG-compatible Boundary Scan * 1.8 V or 2.5 V +10%/-10% core power supply * 1.8 V or 2.5 V I/O supply * LBO pin for Linear or Interleave Burst mode * Pin-compatible with 2M, 4M, and 8M devices * Byte write operation (9-bit Bytes) * 3 chip enable signals for easy depth expansion * ZZ pin for automatic power-down * JEDEC-standard 100-lead TQFP package drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. lo g Features 300 MHz-200 MHz 1.8 V or 2.5 V VDD 1.8 V or 2.5 V I/O no 100-Pin TQFP Commercial Temp Industrial Temp 190 225 190 225 mA mA mA mA Functional Description D ra ft Co p The GS8161Z18/36AT is an 18Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/ single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable, ZZ and Output Enable. Output Enable can be used to override the synchronous control of the output Rev: 1.01 3/2002 1/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 Rev: 1.01 3/2002 y lo g no tia l en A19 NC NC VDDQ VSS NC DQA9 DQA8 DQA7 VSS VDDQ DQA6 DQA5 VSS NC VDD ZZ DQA4 DQA3 VDDQ VSS DQA2 DQA1 NC NC VSS VDDQ NC NC NC A3 A2 A1 A0 TMS TDI VSS VDD TDO TCK A10 A11 A12 A13 A14 A15 A16 LBO A5 A4 D ra ft Co p VSS NC NC DQB1 DQB2 VSS VDDQ DQB3 DQB4 FT VDD NC VSS DQB5 DQB6 VDDQ VSS DQB7 DQB8 DQB9 NC VSS VDDQ NC NC NC Te ch VDDQ 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 1M x 18 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 y-- G SI NC NC NC Co nf id A6 A7 E1 E2 NC NC BB BA E3 VDD VSS CK W CKE G ADV A18 A17 A8 A9 GS8161Z18AT Pinout 2/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 Rev: 1.01 3/2002 y lo g no Te ch tia l en DQB9 DQB8 DQB7 VDDQ VSS DQB6 DQB5 DQB4 DQB3 VSS VDDQ DQB2 DQB1 VSS NC VDD ZZ DQA1 DQA2 VDDQ VSS DQA3 DQA4 DQA5 DQA6 VSS VDDQ DQA7 DQA8 DQA9 A3 A2 A1 A0 TMS TDI VSS VDD TDO TCK A10 A11 A12 A13 A14 A15 A16 LBO A5 A4 D ra ft Co p VSS DQC6 DQC5 DQC4 DQC3 VSS VDDQ DQC2 DQC1 FT VDD NC VSS DQD1 DQD2 VDDQ VSS DQD3 DQD4 DQD5 DQD6 VSS VDDQ DQD7 DQD8 DQD9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 36 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 y-- G SI DQC9 DQC8 DQC7 VDDQ Co nf id A6 A7 E1 E2 BD BC BB BA E3 VDD VSS CK W CKE G ADV A18 A17 A8 A9 GS8161Z36AT Pinout 3/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 100-Pin TQFP Pin Descriptions Symbol Type Description 37, 36 A0, A1 In Burst Address Inputs; Preload the burst counter 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46,47, 48, 49, 50, 83, 84 A2-A18 In Address Inputs 80 A19 In Address Input (x18 Version Only) 89 CK In Clock Input Signal 93 BA In Byte Write signal for data inputs DQA1-DQA9; active low 94 BB In Byte Write signal for data inputs DQB1-DQB9; active low 95 BC In Byte Write signal for data inputs DQC1-DQC9; active low (x36 Version Only) 96 BD In Byte Write signal for data inputs DQD1-DQD9; active low (x36 Version Only) 88 W In 98 E1 In 97 E2 In Chip Enable--Active High. For self decoded depth expansion 92 E3 In Chip Enable--Active Low. For self decoded depth expansion 86 G In 85 ADV In 87 CKE In 58, 59, 62,63, 68, 69, 72, 73, 74 DQA1-DQA9 I/O Byte A Data Input and Output pins.(x18 Version Only) 8, 9, 12, 13, 18, 19, 22, 23, 24 DQB1-DQB9 I/O Byte B Data Input and Output pins.(x18 Version Only) 16, 66 NC -- No Connect 51, 52, 53, 56, 57, 75, 78, 79, 95, 96, 1, 2, 3, 6, 7, 25, 28, 29, 30 NC -- No Connect (x18 Version Only) 63, 62, 59, 58, 57, 56, 53, 52, 51 DQA1-DQA9 I/O Byte A Data Input and Output pins (x36 Version Only) 68, 69, 72, 73, 74, 75, 78, 79, 80 DQB1-DQB9 I/O Byte B Data Input and Output pins (x36 Version Only) 13, 12, 9, 8, 7, 6, 3, 2, 1 DQC1-DQC9 I/O Byte C Data Input and Output pins (x36 Version Only) 18, 19, 22, 23, 24, 25, 28, 29, 30 DQD1-DQD9 I/O Byte D Data Input and Output pins (x36 Version Only) en Co nf id y lo g Write Enable; active low Te ch no Chip Enable; active low Output Enable; active low Advance/Load; Burst address counter control pin y-- G SI D ra ft Co p Rev: 1.01 3/2002 tia l Pin Location Clock Input Buffer Enable; active low 4/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 Symbol Type Description 64 ZZ In Power down control; active high 14 FT In Pipeline/Flow Through Mode Control; active low 31 LBO In Linear Burst Order; active low. 38 TMS Scan Test Mode Select 39 TDI Scan Test Data In 42 TDO Scan Test Data Out 43 TCK Scan Test Clock 15, 41, 65, 91 VDD In Core power supply 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 VSS In Ground 4, 11, 20, 27, 54, 61, 70, 77 VDDQ In lo g y Co nf id en tia l Pin Location D ra ft Co p y-- G SI Te ch no Output driver power supply Rev: 1.01 3/2002 5/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Rev: 1.01 3/2002 W Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 6/37 G CKE CK E3 E2 E1 BD BC BB BA LBO ADV A0-An K K K Match Control Logic Data Coherency FT Register 2 K Register 1 18 SA1' SA0' y-- G SI Burst Counter Write Address K SA1 SA0 Write Address Q Read, Write and D Write Drivers D ra ft Co p Memory Array no Sense Amps Register 2 Write Data Te ch K lo g y Q Q K Co nf id D Register 1 Write Data K K D FT en Parity Check tia l DQa-DQn NC NC Preliminary GS8161Z18/36AT-300/275/250/225/200 GS8161Z18/3A6 NBT SRAM Functional Block Diagram (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 Functional Details tia l Clocking en Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation. Pipeline Mode Read and Write Operations BC BD Read H X X X X Write Byte "a" L L H H H Write Byte "b" L H L H H Write Byte "c" L H H L H Write Byte "d" L H H H L Write all Bytes L L L L L Write Abort/NOP L H H H H y BB lo g BA no W y-- G SI Te ch Function Co nf id All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2 and E3). Deassertion of any one of the Enable inputs will deactivate the device. Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins. D ra ft Co p Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The Byte Write Enable inputs (BA, BB, BC & BD) determine which bytes will be written. All or none may be activated. A write cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock. Flow Through Mode Read and Write Operations Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow Through mode the read pipeline is one cycle shorter than in Pipeline mode. Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of clock. Rev: 1.01 3/2002 7/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 Synchronous Truth Table E3 ZZ ADV W Bx G CKE CK DQ D None H X X L L X X X L L-H High-Z Deselect Cycle, Power Down D None X X H L L X X X L L-H High-Z Deselect Cycle, Power Down D None X L X L L X X X L L-H High-Z Deselect Cycle, Continue D None X X X L H X Read Cycle, Begin Burst R External L H L L L H Read Cycle, Continue Burst B Next X X X L H X NOP/Read, Begin Burst R External L H L L L H Dummy Read, Continue Burst B Next X X X L H Write Cycle, Begin Burst W External L H L L L Write Cycle, Continue Burst B Next X X X L NOP/Write Abort, Begin Burst W None L H L Write Abort, Continue Burst B Next Sleep Mode None Co nf id X L L-H High-Z 1 X L L L-H Q X L L L-H Q 1,10 X H L L-H High-Z 2 X H L L-H High-Z 1,2,10 lo g X X L L X L L-H D 3 H X L X L L-H D 1,3,10 L L L H X L L-H High-Z 2,3 High-Z 1,2,3,10 no Te ch Current en Deselect Cycle, Power Down Clock Edge Ignore, Stall Notes tia l Type Address E1 E2 y Operation X X X L H X H X L L-H X X X L X X X X H L-H - X X X H X X X X X X High-Z 4 D ra ft Co p y-- G SI Notes: 1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Deselect cycle is executed first. 2. Dummy Read and Write abort can be considered NOP's because the SRAM performs no operation. A Write abort occurs when the W pin is sampled low but no Byte Write pins are active so no Write operation is performed. 3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during Write cycles. 4. If CKE High occurs during a pipelined Read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a Write cycle, the bus will remain in High Z. 5. X = Don't Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals are low 6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge. 7. Wait states can be inserted by setting CKE high. 8. This device contains circuitry that ensures all outputs are in High Z during power-up. 9. A 2-bit burst counter is incorporated. 10. The address counter is incriminated for all Burst continue cycles. Rev: 1.01 3/2002 8/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 D en tia l Pipelined and Flow Through Read Write Control State Diagram B Co nf id Deselect W R D D W New Read New Write lo g y R R W Burst Read B Te ch R no B R Burst Write B y-- G SI D Notes: Input Command Code 1. The Hold command (CKE Low) is not shown because it prevents any state change. D ra ft Co p Transition Current State (n) 2. W, R, B, and D represent input command codes as indicated in the Synchronous Truth Table. Next State (n+1) n B W D Key W n+1 n+2 n+3 Clock (CK) Command Current State Next State Current State and Next State Definition for Pipelined and Flow Through Read/Write Control State Diagram Rev: 1.01 3/2002 9/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Pipeline Mode Data I/O State Diagram R B Intermediate R High Z (Data In) Data Out (Q Valid) W D Intermediate Intermediate R High Z Te ch D no B y W lo g D Intermediate en B W Co nf id Intermediate tia l Preliminary GS8161Z18/36AT-300/275/250/225/200 Intermediate Key y-- G SI Input Command Code Transition 1. The Hold command (CKE Low) is not shown because it prevents any state change. Transition Intermediate State (N+1) D ra ft Co p Current State (n) n Notes: Next State (n+2) n+1 2. W, R, B, and D represent input command codes as indicated in the Truth Tables. n+2 n+3 Clock (CK) Command Current State Intermediate State Next State Current State and Next State Definition for Pipeline Mode Data I/O State Diagram Rev: 1.01 3/2002 10/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 R B R W Data Out (Q Valid) Co nf id High Z (Data In) en B W tia l Flow Through Mode Data I/O State Diagram D D W Te ch no D lo g High Z B y R Key y-- G SI Input Command Code 1. The Hold command (CKE Low) is not shown because it prevents any state change. Transition Current State (n) D ra ft Co p 2. W, R, B, and D represent input command codes as indicated in the Truth Tables. Next State (n+1) n Notes: n+1 n+2 n+3 Clock (CK) Command Current State Next State Current State and Next State Definition for: Pipeline and Flow through Read Write Control State Diagram Rev: 1.01 3/2002 11/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 Burst Cycles Co nf id en tia l Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode. Burst Order The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables below for details. Burst Order Control LBO Power Down Control ZZ State Function L Linear Burst no Pin Name H Interleaved Burst Te ch Mode Name lo g y Mode Pin Functions L or NC Active H Standby, IDD = ISB y-- G SI Note: There are pull-up devices on the FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. Burst Counter Sequences Linear Burst Sequence Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 00 01 10 11 1st address 00 01 10 11 2nd address 01 10 11 00 2nd address 01 00 11 10 3rd address 10 11 00 01 3rd address 10 11 00 01 4th address 11 00 01 10 4th address 11 10 01 00 D ra ft Co p 1st address A[1:0] A[1:0] A[1:0] A[1:0] Note: The burst counter wraps to initial state on the 5th clock. Rev: 1.01 3/2002 Note: The burst counter wraps to initial state on the 5th clock. BPR 1999.05.18 12/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 tia l Sleep Mode en During normal operation, ZZ must be pulled low, either by the user or by it's internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. n~~o ~~ lo g Sleep Mode Timing Diagram CK Te ch ZZ Sleep tZZS ~ ~ ~ ~ ~ ~ y Co nf id Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode. tZZR tZZH y-- G SI Designing for Compatibility D ra ft Co p The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipelinemode via the FT signal found on Pin 14. Not all vendors offer this option, however most mark Pin 14 as VDD or VDDQ on pipelined parts and VSS on flow through parts. GSI NBT SRAMs are fully compatible with these sockets. Rev: 1.01 3/2002 13/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 Absolute Maximum Ratings tia l (All voltages reference to VSS) Description Value Unit VDD Voltage on VDD Pins -0.5 to 3.6 VDDQ Voltage in VDDQ Pins -0.5 to 3.6 VCK Voltage on Clock Input Pin -0.5 to 3.6 V VI/O Voltage on I/O Pins -0.5 to VDDQ +0.5 ( 3.6 V max.) V VIN Voltage on Other Input Pins -0.5 to VDD +0.5 ( 3.6 V max.) V IIN Input Current on Any Pin +/-20 mA IOUT Output Current on Any I/O Pin +/-20 mA PD Package Power Dissipation 1.5 W TSTG Storage Temperature TBIAS Temperature Under Bias no lo g y Co nf id en Symbol V V -55 to 125 o C -55 to 125 o C D ra ft Co p y-- G SI Te ch Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Rev: 1.01 3/2002 14/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 Symbol Min. Typ. Max. Unit 2.5 V Supply Voltage VDD2 2.3 2.5 2.7 V 1.8 V Supply Voltage VDD1 1.6 1.8 2.0 2.5 V VDDQ I/O Supply Voltage VDDQ2 2.3 2.5 1.8 V VDDQ I/O Supply Voltage VDDQ1 1.6 1.8 Notes en Parameter tia l Power Supply Voltage Ranges Co nf id V 2.7 V 2.0 V VDDQ2 Range Logic Levels VDD Input High Voltage VDD Input Low Voltage VDDQ I/O Input Low Voltage Min. Typ. Max. Unit Notes VIH 0.6*VDD -- VDD + 0.3 V 1 VIL -0.3 -- 0.3*VDD V 1 VIHQ 0.6*VDD -- VDDQ + 0.3 V 1,3 -0.3 -- 0.3*VDD V 1,3 y-- G SI VDDQ I/O Input High Voltage Symbol Te ch Parameter no lo g y Notes: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be -2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC. VILQ D ra ft Co p Notes: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be -2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. VDDQ1 Range Logic Levels Parameter Symbol Min. Typ. Max. Unit Notes VDD Input High Voltage VIH 0.6*VDD -- VDD + 0.3 V 1 VDD Input Low Voltage VIL -0.3 -- 0.3*VDD V 1 VDDQ I/O Input High Voltage VIHQ 0.6*VDD -- VDDQ + 0.3 V 1,3 VDDQ I/O Input Low Voltage VILQ -0.3 -- 0.3*VDD V 1,3 Notes: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be -2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. Rev: 1.01 3/2002 15/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 Symbol Min. Typ. Max. Unit Ambient Temperature (Commercial Range Versions) TA 0 25 70 C Ambient Temperature (Industrial Range Versions) TA -40 25 85 Notes en Parameter tia l Recommended Operating Temperatures 2 Co nf id C 2 y Note: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be -2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC. Overshoot Measurement and Timing lo g Undershoot Measurement and Timing VIH 20% tKC no VDD + 2.0 V VSS Te ch 50% 50% VSS - 2.0 V Capacitance y-- G SI 20% tKC VDD VIL (TA = 25oC, f = 1 MHZ, VDD = 2.5 V) Parameter Input Capacitance D ra ft Co p Input/Output Capacitance Symbol Test conditions Typ. Max. Unit CIN VIN = 0 V 4 5 pF CI/O VOUT = 0 V 6 7 pF Note: These parameters are sample tested. Package Thermal Characteristics Rating Layer Board Symbol Max Unit Notes Junction to Ambient (at 200 lfm) single RJA 40 C/W 1,2 Junction to Ambient (at 200 lfm) four RJA 24 C/W 1,2 Junction to Case (TOP) -- RJC 9 C/W 3 Notes: 1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance. 2. SCMI G-38-87 3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1 Rev: 1.01 3/2002 16/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 Conditions Input high level VDD - 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level VDD/2 Output reference level VDDQ/2 Co nf id en Parameter tia l AC Test Conditions no lo g y Output load Fig. 1 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. Output Load 1 Te ch DQ 30pF* 50 y-- G SI VDDQ/2 * Distributed Test Jig Capacitance DC Electrical Characteristics Symbol Test Conditions Min Max Input Leakage Current (except mode pins) IIL VIN = 0 to VDD -1 uA 1 uA ZZ Input Current IIN1 VDD VIN VIH 0 V VIN VIH -1 uA -1 uA 1 uA 100 uA FTInput Current IIN2 VDD VIN VIL 0 V VIN VIL -100 uA -1 uA 1 uA 1 uA Output Leakage Current IOL Output Disable, VOUT = 0 to VDD -1 uA 1 uA Output High Voltage VOH2 IOH = -8 mA, VDDQ = 2.3 V VDDQ - 0.4 V -- Output High Voltage VOH1 IOH = -4 mA, VDDQ = 1.6 V VDDQ - 0.4 V -- Output Low Voltage VOL2 IOL = 8 mA, VDD = 2.3 V -- 0.4 V Output Low Voltage VOL1 IOL = 4 mA, VDD = 1.6 V -- 0.4 V D ra ft Co p Parameter Rev: 1.01 3/2002 17/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Rev: 1.01 3/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 18/37 -- Device Deselected; All other inputs VIH or VIL Deselect Current 305 15 175 10 345 25 195 30 IDD IDDQ IDD IDDQ IDD IDDQ IDD Pipeline Flow Through Pipeline IDD 70 95 IDD Pipeline Flow Through 35 ISB 35 ISB Pipeline Flow Through 175 10 305 15 IDDQ IDD IDDQ IDD IDDQ Flow Through Pipeline Flow Through y-- G SI 195 30 IDD IDDQ Pipeline Flow Through 0 to 70C 345 30 Symbol IDD IDDQ Mode 75 100 45 45 185 10 315 15 205 30 70 90 35 35 170 10 285 15 190 30 315 25 170 10 285 15 190 30 315 30 0 to 70C 75 95 45 45 180 10 no 295 15 200 30 325 25 180 10 295 15 200 30 325 30 -40 to 85C -275 Te ch 355 25 185 10 315 15 205 30 355 30 -40 to 85C -300 Notes: 1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation. 2. All parameters listed are worst case scenario. -- ZZ VDD - 0.2 V (x18) (x36) (x18) (x36) Standby Current 1.8 V Operating Current Device Selected; All other inputs VIH or VIL Output open Device Selected; All other inputs VIH or VIL Output open Operating Current 2.5 V Test Conditions D ra ft Co p Parameter Operating Currents 60 85 35 35 165 10 lo g 260 15 185 30 290 25 165 10 260 15 185 30 290 30 0 to 70C 65 60 80 35 35 155 10 235 15 175 30 265 20 155 10 235 15 175 30 265 30 0 to 70C 65 85 45 45 165 10 245 15 185 30 275 20 165 10 245 15 185 30 275 30 -40 to 85C -225 Co nf id 90 45 y 45 175 10 270 15 195 30 300 25 175 10 270 15 195 30 600 60 -40 to 85C -250 en 50 75 35 35 150 10 215 10 165 25 240 20 150 10 215 15 165 25 240 25 0 to 70C tia l 55 80 45 45 160 10 225 10 175 25 250 20 160 10 225 15 175 25 250 25 -40 to 85C -200 mA mA mA mA mA mA mA mA mA mA mA mA Unit Preliminary GS8161Z18/36AT-300/275/250/225/200 (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 AC Electrical Characteristics -250 -225 -200 Unit tia l -275 Min Max Min Max Min Max Min Max Min Max tKC 3.3 -- 3.7 -- 4.0 -- 4.4 -- 5.0 -- Clock to Output Valid tKQ -- 2.2 -- 2.4 -- 2.5 -- 2.7 Clock to Output Invalid tKQX 1.5 -- 1.5 -- 1.5 -- 1.5 -- en Clock Cycle Time -300 1 1.5 -- 1.5 -- 1.5 -- 1.5 -- ns 3.0 ns 1.5 -- ns -- 1.5 -- ns 1.3 -- 1.4 -- ns -- 0.3 -- 0.4 -- ns -- 6.0 -- 6.5 -- ns 5.5 -- 6.0 -- 6.5 ns Co nf id -- tLZ Setup time tS 1.1 -- 1.1 -- 1.2 Hold time tH 0.1 -- 0.1 -- 0.2 Clock Cycle Time tKC 5.0 -- 5.25 -- 5.5 Clock to Output Valid tKQ -- 5.0 -- 5.25 -- Clock to Output Invalid tKQX 3.0 -- 3.0 -- 3.0 -- 3.0 -- 3.0 -- ns Clock to Output in Low-Z tLZ1 3.0 -- 3.0 -- 3.0 -- 3.0 -- 3.0 -- ns Setup time tS 1.4 -- 1.4 -- 1.5 -- 1.5 -- 1.5 -- ns Hold time tH 0.4 -- Clock HIGH Time tKH 1.3 -- Clock LOW Time tKL 1.5 Clock to Output in High-Z tHZ1 G to Output Valid tOE no lo g y Clock to Output in Low-Z 0.4 -- 0.5 -- 0.5 -- 0.5 -- ns 1.3 -- 1.3 -- 1.3 -- 1.3 -- ns -- 1.5 -- 1.5 -- 1.5 -- 1.5 -- ns 1.5 2.3 1.5 2.3 1.5 2.3 1.5 2.5 1.5 3.0 ns -- 2.3 -- 2.3 -- 2.3 -- 2.5 -- 3.0 ns y-- G SI Flow Through Symbol Te ch Pipeline Parameter tOLZ1 0 -- 0 -- 0 -- 0 -- 0 -- ns G to output in High-Z tOHZ1 -- 2.3 -- 2.3 -- 2.3 -- 2.5 -- 3.0 ns ZZ setup time tZZS2 5 -- 5 -- 5 -- 5 -- 5 -- ns ZZ hold time tZZH2 1 -- 1 -- 1 -- 1 -- 1 -- ns ZZ recovery tZZR 20 -- 20 -- 20 -- 20 -- 20 -- ns D ra ft Co p G to output in Low-Z Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.01 3/2002 19/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 1 2 3 4 5 6 7 8 9 10 tS tH tKH tKL en CK tKC Co nf id CKE tS tH E* tS tH ADV lo g y tS tH W no tS tH Bn A1 Te ch tS tH A0-An A2 A3 A4 A5 y-- G SI tKQ DQA-DQD D(A1) tS D ra ft Co p G COMMAND Write D(A1) tia l Pipeline Mode Read/Write Cycle Timing Write D(A2) D(A2) A6 tGLQV tKQHZ A7 tKHQZ tKQLZ D (A2+1) tH BURST Read Write Q(A3) D(A2+1) Q(A3) Q(A4) Q (A4+1) D(A5) Q(A6) tKQX tOEHZ tOELZ Read Q(A4) BURST Read Q(A4+1) Write D(A5) DON'T CARE Read Q(A6) Write D(A7) DESELECT UNDEFINED *Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1 Rev: 1.01 3/2002 20/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 Pipeline Mode No-Op, Stall and Deselect Timing 2 4 3 5 6 7 8 9 CK en tS tH Co nf id CKE tS tH E* tS tH ADV lo g y tS tH W A0-An A3 y-- G SI A2 Write D(A1) Read Q(A2) STALL D(A1) A4 A5 tKHQZ Q(A2) Q(A3) D(A4) Q(A5) tKQHZ Read Q(A3) D ra ft Co p COMMAND A1 Te ch no Bn DQ 10 tia l 1 Write D(A4) STALL NOP DON'T CARE Read Q(A5) DESELECT CONTINUE DESELECT UNDEFINED *Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1 Rev: 1.01 3/2002 21/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 1 4 3 2 5 6 8 7 tia l Flow Through Mode Read/Write Cycle Timing 10 9 tS tH tKH tKL en CK tKC Co nf id CKE tS tH E* tS tH ADV lo g y tS tH W no tS tH Bn A0-An tH A1 Te ch tS A2 A3 A4 tKQ tKQHZ A5 tGLQV A6 A7 tKHQZ DQ y-- G SI tKQLZ D(A1) tS D ra ft Co p G COMMAND Write D(A1) D(A2) D (A2+1) tH Write D(A2) BURST Read Write Q(A3) D(A2+1) Q(A3) Q (A4+1) Q(A4) D(A5) Q(A6) tKQX tOEHZ tOELZ Read Q(A4) BURST Read Q(A4+1) Write D(A5) Read Q(A6) DON'T CARE Write D(A7) DESELECT UNDEFINED *Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1 Rev: 1.01 3/2002 22/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 1 2 4 3 5 6 8 7 tia l Flow Through Mode No-Op, Stall and Deselect Timing 10 9 en CK tS tH Co nf id CKE tS tH E* tS tH lo g y ADV no W DQ A2 A3 D(A1) Write D(A1) Read Q(A2) Q(A2) STALL A4 A5 tKHQZ Q(A3) Q(A5) D(A4) tKQHZ Read Q(A3) D ra ft Co p COMMAND A1 y-- G SI A0-An Te ch Bn Write D(A4) STALL NOP Read Q(A5) DON'T CARE DESELECT CONTINUE DESELECT UNDEFINED *Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1 Rev: 1.01 3/2002 23/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 JTAG Port Operation tia l Overview en The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDDQ. Co nf id Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected. JTAG Pin Descriptions Pin Name I/O Description TCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS Test Mode Select In The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. In The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level. TDO Test Data Out lo g no Te ch Test Data In y-- G SI TDI y Pin Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. D ra ft Co p Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up. JTAG Port Registers Overview The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM's JTAG Port to another device in the scan chain with as little delay as possible. Rev: 1.01 3/2002 24/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 Boundary Scan Register Co nf id en tia l The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM's input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port's TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. JTAG TAP Block Diagram 0 Bypass Register y 2 1 0 lo g Instruction Register TDI * * * * 2 1 0 Te ch 31 30 29 TDO no ID Code Register Boundary Scan Register n * * * * * * TMS Identification (ID) Register 2 1 0 Test Access Port (TAP) Controller y-- G SI TCK * * * D ra ft Co p The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. Die Revision Code GSI Technology JEDEC Vendor ID Code I/O Configuration Not Used Presence Register ID Register Contents Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x36 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1 x18 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 Rev: 1.01 3/2002 25/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 Tap Controller Instruction Set tia l Overview Co nf id en There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. lo g 0 Run Test Idle 1 Select DR 1 Select IR 1 1 Capture DR Capture IR 0 y-- G SI Shift DR 1 D ra ft Co p 1 1 0 0 Te ch 0 Test Logic Reset no 1 y JTAG Tap Controller State Diagram 0 Shift IR 0 1 1 Exit1 DR 0 Exit1 IR 0 0 Pause DR 1 Exit2 DR 1 0 Pause IR 1 Exit2 IR 0 1 Update DR Update IR 1 1 0 0 0 0 Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. Rev: 1.01 3/2002 26/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 Co nf id en tia l SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to ShiftDR state then places the boundary scan register between the TDI and TDO pins. lo g y EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM's input pins; therefore, the RAM's internal state is still determined by its input pins. no Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register's contents, in parallel, on the RAM's data output drivers on the falling edge of TCK when the controller is in the Update-IR state. Te ch Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM's input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM's output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. y-- G SI IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. D ra ft Co p SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Rev: 1.01 3/2002 27/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 JTAG TAP Instruction Set Summary Code Description Notes EXTEST 000 Places the Boundary Scan Register between TDI and TDO. IDCODE 001 Preloads ID Register and places it between TDI and TDO. SAMPLE-Z 010 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. 1 RFU 011 Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1 SAMPLE/ PRELOAD 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. 1 GSI 101 GSI private instruction. 1 RFU 110 Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1 BYPASS 111 Places Bypass Register between TDI and TDO. 1 tia l Instruction 1, 2 no lo g y Co nf id en 1 D ra ft Co p y-- G SI Te ch Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 1.01 3/2002 28/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 JTAG Port Recommended Operating Conditions and DC Characteristics Symbol Min. Max. Unit Notes 3.3 V Test Port Input High Voltage VIHJ3 2.0 VDD3 +0.3 3.3 V Test Port Input Low Voltage VILJ3 -0.3 0.8 2.5 V Test Port Input High Voltage VIHJ2 0.6 * VDD2 2.5 V Test Port Input Low Voltage VILJ2 TMS, TCK and TDI Input Leakage Current tia l Parameter 1 V 1 VDD2 +0.3 V 1 -0.3 0.3 * VDD2 V 1 IINHJ -300 1 uA 2 TMS, TCK and TDI Input Leakage Current IINLJ -1 100 uA 3 TDO Output Leakage Current IOLJ -1 1 uA 4 Test Port Output High Voltage VOHJ 1.7 -- V 5, 6 Test Port Output Low Voltage VOLJ -- 0.4 V 5, 7 Test Port Output CMOS High VOHJC VDDQ - 100 mV -- V 5, 8 Test Port Output CMOS Low VOLJC -- 100 mV V 5, 9 no lo g y Co nf id en V y-- G SI Te ch Notes: 1. Input Under/overshoot voltage must be -2 V > Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC. 2. VILJ VIN VDDn 3. 0 V VIN VILJn 4. Output Disable, VOUT = 0 to VDDn 5. The TDO output driver is served by the VDDQ supply. 6. IOHJ = -4 mA 7. IOLJ = + 4 mA 8. IOHJC = -100 uA 9. IOHJC = +100 uA D ra ft Co p JTAG Port AC Test Conditions Parameter Conditions Input high level 2.3 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level 1.25 V Output reference level 1.25 V 50 30pF* VT = 1.25 V * Distributed Test Jig Capacitance Notes: 1. Include scope and jig capacitance. 2. Test conditions as as shown unless otherwise noted. Rev: 1.01 3/2002 JTAG Port AC Test Load DQ 29/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 JTAG Port Timing Diagram tTKL tTKC tia l tTKH tTH Co nf id tTS en TCK TMS TDI lo g y TDO no tTKQ Te ch JTAG Port AC Electrical Characteristics Symbol Min Max Unit TCK Cycle Time tTKC 50 -- ns TCK Low to TDO Valid tTKQ -- 20 ns TCK High Pulse Width tTKH 20 -- ns y-- G SI Parameter tTKL 20 -- ns TDI & TMS Set Up Time tTS 10 -- ns TDI & TMS Hold Time tTH 10 -- ns D ra ft Co p TCK Low Pulse Width Rev: 1.01 3/2002 30/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 GS8161Z18/36A Boundary Scan Chain Order GS8161Z18/36A Boundary Scan Chain Order x18 Pin x36 x18 x18 PH = 0 30 Pin tia l x36 x36 x36 x18 n/a en Order Order 1 PH = 0 n/a 31 QA4 2 X n/a 32 DA4 3 X n/a 33 4 A10 44 34 5 A11 45 35 QA3 QA2 59 6 A12 46 36 DA3 DA2 59 7 A13 47 37 8 A14 48 9 A15 49 10 A16 50 QA9 NC = 1 51 12 DA9 PH = 0 51 Co nf id y lo g no 38 Te ch 11 QA1 DA1 58 58 NC = 1 n/a PH = 0 n/a NC = 1 n/a PH = 0 n/a 39 QA2 QA3 62 40 DA2 DA3 62 n/a 41 NC = 1 n/a n/a 42 PH = 0 n/a NC = 1 n/a 43 QA1 QA4 63 14 PH = 0 n/a 44 DA1 DA4 63 15 QA8 16 DA8 17 PH = 0 y-- G SI 13 NC = 1 52 n/a 45 NC = 1 n/a PH = 0 52 n/a 46 PH = 0 n/a n/a 47 ZZ 64 n/a 48 PH = 0 n/a NC = 1 n/a NC = 1 PH = 0 D ra ft Co p 18 19 QA7 NC = 1 53 n/a 49 20 DA7 PH = 0 53 n/a 50 QB1 QA5 68 DB1 DA5 68 21 NC = 1 n/a 51 22 PH = 0 n/a 52 NC = 1 n/a PH = 0 n/a 23 QA6 NC = 1 56 n/a 53 24 DA6 PH = 0 56 n/a 54 QB2 QA6 69 DB2 DA6 69 25 NC = 1 n/a 55 26 PH = 0 n/a 56 NC = 1 n/a PH = 0 n/a 27 QA5 NC = 1 57 n/a 57 28 DA5 PH = 0 57 n/a 58 QB3 QA7 72 59 DB3 DA7 72 29 Rev: 1.01 3/2002 NC = 1 n/a 31/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 GS8161Z18/36A Boundary Scan Chain Order x18 Pin x36 x18 Order x36 x18 NC = 1 n/a 90 A18 61 PH = 0 n/a 91 ADV QB4 QA8 73 92 63 DB4 DA8 73 93 87 W 88 NC = 1 n/a NC = 1 n/a NC = 1 n/a NC = 1 n/a 99 CK 89 100 PH = 0 n/a 101 PH = 0 n/a n/a 94 65 PH = 0 n/a 95 QB5 QA9 74 96 67 DB5 DA9 74 97 PH = 0 n/a QB6 NC = 1 75 71 DB6 PH = 0 75 n/a Te ch 70 98 no 69 lo g 66 n/a n/a 85 CKE NC = 1 NC = 1 84 86 64 68 x18 G y 62 x36 Co nf id 60 Pin tia l x36 en Order GS8161Z18/36A Boundary Scan Chain Order NC = 1 n/a 102 E3 92 73 PH = 0 n/a 103 BA 93 74 QB7 75 DB7 y-- G SI 72 NC = 1 78 n/a 104 BB NC = 1 PH = 0 78 n/a 105 BC BB BD NC = 1 94 n/a 95 76 NC = 1 n/a 106 77 PH = 0 n/a 107 E2 97 QB8 79 DB8 n/a NC = 1 79 n/a 108 E1 98 PH = 0 79 n/a 109 A7 99 A6 100 D ra ft Co p 78 96 80 NC = 1 n/a 110 81 PH = 0 n/a 111 QC9 NC = 1 1 n/a DC9 PH = 0 1 n/a 82 QB9 NC = 1 80 n/a 112 83 DB9 PH = 0 80 n/a 113 NC = 1 n/a PH = 0 n/a 84 NC = 1 n/a 114 85 PH = 0 n/a 115 QC8 NC = 1 2 n/a 116 DC8 PH = 0 2 n/a 86 NC = 1 A19 n/a 80 87 A9 81 117 NC = 1 n/a 88 A8 82 118 PH = 0 n/a 89 A17 83 119 Rev: 1.01 3/2002 QC7 32/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. NC = 1 3 n/a (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 GS8161Z18/36A Boundary Scan Chain Order x18 120 DC7 PH = 0 Pin x36 x18 3 n/a Order x36 x18 150 QD8 QB5 DD8 DB5 121 NC = 1 n/a 151 122 PH = 0 n/a 152 Pin tia l x36 x36 x18 18 en Order 18 Co nf id GS8161Z18/36A Boundary Scan Chain Order NC = 1 n/a PH = 0 n/a QC6 NC = 1 6 n/a 153 124 DC6 PH = 0 6 n/a 154 QD7 QB6 19 DD7 DB6 19 125 NC = 1 n/a 155 126 PH = 0 n/a 156 QC5 NC = 1 7 n/a 157 128 DC5 PH = 0 7 n/a 158 n/a 130 PH = 0 n/a no NC = 1 159 Te ch 129 lo g 127 y 123 NC = 1 n/a PH = 0 n/a QD6 QB7 22 DD6 DB7 22 160 NC = 1 n/a PH = 0 n/a 131 QC4 QB1 8 161 132 DC4 DB1 8 162 QD5 QB8 23 n/a 163 DD5 DB8 23 NC = 1 134 PH = 0 135 QC3 136 DC3 y-- G SI 133 n/a 164 NC = 1 n/a QB2 9 165 PH = 0 n/a DB2 9 166 QD4 QB9 24 DD4 DB9 24 NC = 1 n/a 167 138 PH = 0 n/a 168 NC = 1 n/a PH = 0 n/a D ra ft Co p 137 139 QC2 QB3 12 169 140 DC2 DB3 12 170 QD3 NC = 1 25 n/a DD3 PH = 0 25 n/a 141 NC = 1 n/a 171 142 PH = 0 n/a 172 NC = 1 n/a PH = 0 n/a 143 QC1 QB4 13 173 144 DC1 DB4 13 174 QD2 NC = 1 28 n/a DD2 PH = 0 28 n/a 145 NC = 1 n/a 175 146 PH = 0 n/a 176 NC = 1 n/a 147 FT 14 177 PH = 0 n/a 148 NC = 1 n/a 178 QD1 NC = 1 29 n/a 149 NC = 1 n/a 179 DD1 PH = 0 29 n/a Rev: 1.01 3/2002 33/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 GS8161Z18/36A Boundary Scan Chain Order Pin x36 tia l x18 x18 180 NC = 1 n/a 181 PH = 0 n/a en x36 QD9 NC = 1 30 n/a 183 DD9 PH = 0 30 n/a 185 PH = 0 n/a 186 LBO 31 187 A5 32 188 A4 33 189 A3 34 190 A2 35 191 A1 36 192 A0 37 193 PH = 0 n/a 194 G lo g n/a no NC = 1 y-- G SI Te ch 184 y 182 Co nf id Order 86 D ra ft Co p Notes: 1. Depending on the package, some input pads of the scan chain may not be connected to any external pin. In such case: LBO = 1, ZQ = 1, PE = 0, SD = 0, ZZ = 0, FT = 1, and SCD = 1. 2. Every DQ pad consists of two scan registers--D is for input capture, and Q is for output capture. 3. A single register (#194) for controlling tristate of all the DQ pins is at the end of the scan chain (i.e., the last bit shifted in this tristate control is effective after JTAG EXTEST instruction is executed. 4. 1 = no connect, internally set to logic value 1 5. 0 = no connect, internally set to logic value 0 6. X = no connect, value is undefined Rev: 1.01 3/2002 34/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 TQFP Package Drawing Nom. Max A1 Standoff 0.05 0.10 0.15 A2 Body Thickness 1.35 1.40 1.45 b Lead Width 0.20 0.30 0.40 c Lead Thickness 0.09 D Terminal Dimension 21.9 22.0 20.1 D1 Package Body 19.9 20.0 20.1 E Terminal Dimension 15.9 16.0 16.1 E1 Package Body 13.9 14.0 14.1 e Lead Pitch L Foot Length L1 Lead Length Y Coplanarity Lead Angle 0.60 0.75 1.00 Te ch lo g no b y e A1 0.10 A2 Y 0 c 0.20 0.65 0.45 L1 Co nf id Min. 7 D D1 Description Pin 1 Symbol tia l L en TQFP Package Drawing E1 E BPR 1999.05.18 D ra ft Co p y-- G SI Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. Rev: 1.01 3/2002 35/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 Type Package Speed2 (MHz/ns) TA3 1M x 18 GS8161Z18AT-300 NBT Pipeline/Flow Through TQFP 300/5 C 1M x 18 GS8161Z18AT-275 NBT Pipeline/Flow Through TQFP 275/5.25 1M x 18 GS8161Z18AT-250 NBT Pipeline/Flow Through TQFP 250/5.5 1M x 18 GS8161Z18AT-225 NBT Pipeline/Flow Through TQFP 1M x 18 GS8161Z18AT-200 NBT Pipeline/Flow Through TQFP 512K x 36 GS8161Z36AT-300 NBT Pipeline/Flow Through TQFP 512K x 36 GS8161Z36AT-275 NBT Pipeline/Flow Through TQFP 512K x 36 GS8161Z36AT-250 NBT Pipeline/Flow Through TQFP 512K x 36 GS8161Z36AT-225 NBT Pipeline/Flow Through TQFP 512K x 36 GS8161Z36AT-200 NBT Pipeline/Flow Through 1M x 18 GS8161Z18AT-300I NBT Pipeline/Flow Through 1M x 18 GS8161Z18AT-275I NBT Pipeline/Flow Through 1M x 18 GS8161Z18AT-250I NBT Pipeline/Flow Through 1M x 18 GS8161Z18AT-225I 1M x 18 C Co nf id C C 200/6.5 C 300/5 C 275/5.25 C 250/5.5 C 225/6 C TQFP 200/6.5 C TQFP 300/5 I TQFP 275/5.25 I TQFP 250/5.5 I NBT Pipeline/Flow Through TQFP 225/6 I GS8161Z18AT-200I NBT Pipeline/Flow Through TQFP 200/6.5 I 512K x 36 GS8161Z36AT-300I NBT Pipeline/Flow Through TQFP 300/5 I 512K x 36 GS8161Z36AT-275I NBT Pipeline/Flow Through TQFP 275/5.25 I 512K x 36 GS8161Z36AT-250I NBT Pipeline/Flow Through TQFP 250/5.5 I 512K x 36 GS8161Z36AT-225I NBT Pipeline/Flow Through TQFP 225/6 I 512K x 36 GS8161Z36AT-200I NBT Pipeline/Flow Through TQFP 200/6.5 I Te ch no y 225/6 y-- G SI Status tia l Part Number1 en Org lo g Ordering Information--GSI NBT Synchronous SRAM D ra ft Co p Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS8161Z36A-300IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings Rev: 1.01 3/2002 36/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18/36AT-300/275/250/225/200 Types of Changes Format or Content Page;Revisions;Reason * Creation of new datasheet 8161Z18A_r1 Content D ra ft Co p y-- G SI Te ch no 2 diagram y Co nf id * Updated AC Characteristics table * Updated FT power numbers on page 1 and in Operating Currents table * Updated VIH to 2.0 from 1.7 * Updated Mb references to 18Mb from 16Mb * IUpdated BSR table * Removed all ByteSafe references * Updated ZZ recovery time diagram * Updated AC Test Conditions table and removed Output Load lo g 8161Z18A_r1; 8161Z18A_r1_01 en DS/DateRev. Code: Old; New tia l 18Mb Sync SRAM Datasheet Revision History Rev: 1.01 3/2002 37/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc.