Rev: 1.01 3/2002 1/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
GS8161Z18/36AT-300/275/250/225/200
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
300 MHz–200 MHz
1.8 V or 2.5 V VDD
1.8 V or 2.5 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Draft Copy—GSI Technology Confidential
Preliminary
Features
• User-configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
• Fully pin-compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 1.8 V or 2.5 V +10%/–10% core power supply
• 1.8 V or 2.5 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ pin for automatic power-down
• JEDEC-standard 100-lead TQFP package
Functional Description
The GS8161Z18/36AT is an 18Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8161Z18/36AT may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8161Z18/36AT is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 100-pin TQFP package.
-300 -275 -250 -225 -200 Unit
Pipeline
3-1-1-1 tKQ
tCycle 2.2
3.3 2.4
3.6 2.5
4.0 2.7
4.4 3.0
5.0 ns
ns
1.8 V Curr (x18)
Curr (x36)
320
375 300
345 275
320 250
295 230
265 mA
mA
2.5 V Curr (x18)
Curr (x36)
320
370 300
340 275
315 250
285 225
260 mA
mA
Flow
Through
2-1-1-1
tKQ
tCycle 5.0
5.0 5.25
5.25 5.5
5.5 6.0
6.0 6.5
6.5 ns
ns
1.8 V Curr (x18)
Curr (x36)
220
265 215
260 210
245 200
235 190
225 mA
mA
2.5 V Curr (x18)
Curr (x36)
220
265 215
260 210
245 200
235 190
225 mA
mA
Rev: 1.01 3/2002 2/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18/36AT-300/275/250/225/200
Draft Copy—GSI Technology Confidential
Preliminary
GS8161Z18AT Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
VSS
DQB1
DQB2
VSS
VDDQ
DQB3
DQB4
FT
VDD
VSS
DQB5
DQB6
VDDQ
VSS
DQB7
DQB8
DQB9
VSS
VDDQ
VDDQ
VSS
DQA8
DQA7
VSS
VDDQ
DQA6
DQA5
VSS
NC
VDD
ZZ
DQA4
DQA3
VDDQ
VSS
DQA2
DQA1
VSS
VDDQ
LBO
A5
A4
A3
A2
A1
A0
TMS
TDI
VSS
VDD
TDO
TCK
A10
A11
A12
A13
A14
A16
A6
A7
E1
E2
NC
NC
BB
BA
E3
CK
W
CKE
VDD
VSS
G
ADV
A18
A17
A8
A9
A15
1M x 18
Top View
DQA9
A19
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
Rev: 1.01 3/2002 3/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18/36AT-300/275/250/225/200
Draft Copy—GSI Technology Confidential
Preliminary
GS8161Z36AT Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
VSS
DQC4
DQC3
VSS
VDDQ
DQC2
DQC1
FT
VDD
NC
VSS
DQD1
DQD2
VDDQ
VSS
DQD3
DQD4
DQD5
VSS
VDDQ
VDDQ
VSS
DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
NC
VDD
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4
VSS
VDDQ
LBO
A5
A4
A3
A2
A1
A0
TMS
TDI
VSS
VDD
TDO
TCK
A10
A11
A12
A13
A14
A16
A6
A7
E1
E2
BD
BC
BB
BA
E3
CK
W
CKE
VDD
VSS
G
ADV
A18
A17
A8
A9
A15
512K x 36
Top View
DQB5
DQB9
DQB7
DQB8
DQB6
DQA6
DQA5
DQA8
DQA7
DQA9
DQC7
DQC8
DQC6
DQD6
DQD8
DQD7
DQD9
DQC5
DQC9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.01 3/2002 4/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18/36AT-300/275/250/225/200
Draft Copy—GSI Technology Confidential
Preliminary
100-Pin TQFP Pin Descriptions
Pin Location Symbol Type Description
37, 36 A0, A1In Burst Address Inputs; Preload the burst counter
35, 34, 33, 32, 100, 99, 82, 81,
44, 45, 46,47, 48, 49, 50, 83, 84 A2–A18 In Address Inputs
80 A19 In Address Input (x18 Version Only)
89 CK In Clock Input Signal
93 BAIn Byte Write signal for data inputs DQA1–DQA9; active low
94 BBIn Byte Write signal for data inputs DQB1–DQB9; active low
95 BCIn Byte Write signal for data inputs DQC1–DQC9; active low (x36 Version Only)
96 BDIn Byte Write signal for data inputs DQD1–DQD9; active low (x36 Version Only)
88 WIn Write Enable; active low
98 E1In Chip Enable; active low
97 E2In Chip Enable—Active High. For self decoded depth expansion
92 E3In Chip Enable—Active Low. For self decoded depth expansion
86 GIn Output Enable; active low
85 ADV In Advance/Load; Burst address counter control pin
87 CKE In Clock Input Buffer Enable; active low
58, 59, 62,63, 68, 69, 72, 73, 74 DQA1–DQA9 I/O Byte A Data Input and Output pins.(x18 Version Only)
8, 9, 12, 13, 18, 19, 22, 23, 24 DQB1–DQB9 I/O Byte B Data Input and Output pins.(x18 Version Only)
16, 66 NC —No Connect
51, 52, 53, 56, 57, 75, 78, 79,
95, 96, 1, 2, 3, 6, 7, 25, 28, 29,
30 NC —No Connect (x18 Version Only)
63, 62, 59, 58, 57, 56, 53, 52, 51 DQA1–DQA9 I/O Byte A Data Input and Output pins (x36 Version Only)
68, 69, 72, 73, 74, 75,
78, 79, 80 DQB1–DQB9 I/O Byte B Data Input and Output pins (x36 Version Only)
13, 12, 9, 8, 7, 6, 3, 2, 1 DQC1–DQC9 I/O Byte C Data Input and Output pins (x36 Version Only)
18, 19, 22, 23, 24, 25, 28, 29, 30 DQD1–DQD9 I/O Byte D Data Input and Output pins (x36 Version Only)
Rev: 1.01 3/2002 5/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18/36AT-300/275/250/225/200
Draft Copy—GSI Technology Confidential
Preliminary
64 ZZ In Power down control; active high
14 FT In Pipeline/Flow Through Mode Control; active low
31 LBO In Linear Burst Order; active low.
38 TMS Scan Test Mode Select
39 TDI Scan Test Data In
42 TDO Scan Test Data Out
43 TCK Scan Test Clock
15, 41, 65, 91 VDD In Core power supply
5, 10, 17, 21, 26, 40, 55, 60, 67,
71, 76, 90 VSS In Ground
4, 11, 20, 27, 54, 61, 70, 77 VDDQ In Output driver power supply
Pin Location Symbol Type Description
Rev: 1.01 3/2002 6/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18/36AT-300/275/250/225/200
Draft Copy—GSI Technology Confidential
Preliminary
GS8161Z18/3A6 NBT SRAM Functional Block Diagram
K
18
SA1
SA0 Burst
Counter
LBO
ADV
Memory
Array
G
CK
CKE
D Q
FT
NC
NC
DQa–DQn
K
SA1’
SA0’
D Q
Match
Write Address
Register 2
Write Address
Register 1
Write Data
Register 2
Write Data
Register 1
KK
KK
K
K
Sense Amps
Write Drivers
Read, Write and
Data Coherency
Control Logic
D Q
K
Parity
Check
FT
A
0–An
E3
E2
E1
W
BD
BC
BB
BA
Rev: 1.01 3/2002 7/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18/36AT-300/275/250/225/200
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Preliminary
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2 and E3). Deassertion of any one of the Enable
inputs will deactivate the device.
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three
chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The
Byte Write Enable inputs (BA, BB, BC & BD) determine which bytes will be written. All or none may be activated. A write cycle
with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the
write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising
edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the
third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use
of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new
address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Function WBABBBCBD
Read HX X X X
Write Byte “a” L L H H H
Write Byte “b” LHLH H
Write Byte “c” LH H LH
Write Byte “d” LHHHL
Write all Bytes L L L L L
Write Abort/NOP LH H H H
Rev: 1.01 3/2002 8/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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Preliminary
Synchronous Truth Table
Operation Type Address E1E2E3ZZ ADV WBx GCKE CK DQ Notes
Deselect Cycle, Power Down DNone HX X L L X X X LL-H High-Z
Deselect Cycle, Power Down DNone X X HL L X X X LL-H High-Z
Deselect Cycle, Power Down DNone XLXL L X X X LL-H High-Z
Deselect Cycle, Continue DNone X X X LHX X X LL-H High-Z 1
Read Cycle, Begin Burst RExternal LHL L L HXL L L-H Q
Read Cycle, Continue Burst BNext X X X LHX X L L L-H Q1,10
NOP/Read, Begin Burst RExternal LHL L L HXHLL-H High-Z 2
Dummy Read, Continue Burst BNext X X X LHX X HLL-H High-Z 1,2,10
Write Cycle, Begin Burst WExternal LHL L L L L XLL-H D3
Write Cycle, Continue Burst BNext X X X LHXLXLL-H D1,3,10
NOP/Write Abort, Begin Burst WNone LHL L L L HXLL-H High-Z 2,3
Write Abort, Continue Burst BNext X X X LHXHXLL-H High-Z 1,2,3,10
Clock Edge Ignore, Stall Current X X X LX X X X HL-H -4
Sleep Mode None X X X HX X X X X X High-Z
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Deselect
cycle is executed first.
2. Dummy Read and Write abort can be considered NOP’s because the SRAM performs no operation. A Write abort occurs when the W pin
is sampled low but no Byte Write pins are active so no Write operation is performed.
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during Write
cycles.
4. If CKE High occurs during a pipelined Read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a Write cycle, the bus
will remain in High Z.
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals
are low
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
Rev: 1.01 3/2002 9/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18/36AT-300/275/250/225/200
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Preliminary
Deselect
New Read New Write
Burst Read Burst Write
W
R
B
R
B
W
DD
B
B
W
R
DB
W
R
DD
Pipelined and Flow Through Read Write Control State Diagram
Current State (n) Next State (n+1)
Transition
ƒ
Input Command Code
Key Notes:
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Synchronous Truth Table.
Clock (CK)
Command
Current State Next State
ƒ
nn+1 n+2 n+3
ƒƒƒ
Current State and Next State Definition for Pipelined and Flow Through Read/Write Control State Diagram
WR
Rev: 1.01 3/2002 10/37 © 2001, Giga Semiconductor, Inc.
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Preliminary
Intermediate Intermediate
Intermediate
Intermediate Intermediate
Intermediate
High Z
(Data In) Data Out
(Q Valid)
High Z
BWB
R
BD
R
W
R
W
DD
Pipeline Mode Data I/O State Diagram
Current State (n) Next State (n+2)
Transition
ƒ
Input Command Code
Key
Transition
Intermediate State (N+1)
Notes:
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Clock (CK)
Command
Current State Intermediate
ƒ
nn+1 n+2 n+3
ƒƒƒ
Current State and Next State Definition for Pipeline Mode Data I/O State Diagram
Next State
State
Rev: 1.01 3/2002 11/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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Preliminary
High Z
(Data In) Data Out
(Q Valid)
High Z
BWB
R
BD
R
W
R
W
DD
Current State (n) Next State (n+1)
Transition
ƒ
Input Command Code
Key Notes:
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Flow Through Mode Data I/O State Diagram
Clock (CK)
Command
Current State Next State
ƒ
nn+1 n+2 n+3
ƒƒƒ
Current State and Next State Definition for: Pipeline and Flow through Read Write Control State Diagram
Rev: 1.01 3/2002 12/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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Preliminary
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
Note:
There are pull-up devices on the FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip
will operate in the default states as specified in the above tables.
Burst Counter Sequences
BPR 1999.05.18
Mode Pin Functions
Mode Name Pin
Name State Function
Burst Order Control LBO LLinear Burst
HInterleaved Burst
Power Down Control ZZ L or NC Active
H Standby, IDD = ISB
Linear Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
I
nterleaved Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 10 11 00
3rd address 10 11 00 01
4th address 11 00 01 10
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 00 11 10
3rd address 10 11 00 01
4th address 11 10 01 00
Rev: 1.01 3/2002 13/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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Preliminary
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipelinemode via the FT signal found
on Pin 14. Not all vendors offer this option, however most mark Pin 14 as VDD or VDDQ on pipelined parts and VSS on flow
through parts. GSI NBT SRAMs are fully compatible with these sockets.
CK
ZZ tZZR
tZZH
tZZS
~
~
~
~
Sleep
~
~
~
~~
~
Rev: 1.01 3/2002 14/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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Preliminary
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol Description Value Unit
VDD Voltage on VDD Pins –0.5 to 3.6 V
VDDQ Voltage in VDDQ Pins –0.5 to 3.6 V
VCK Voltage on Clock Input Pin –0.5 to 3.6 V
VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 (≤ 3.6 V max.) V
VIN Voltage on Other Input Pins –0.5 to VDD +0.5 (≤ 3.6 V max.) V
IIN Input Current on Any Pin +/–20 mA
IOUT Output Current on Any I/O Pin +/–20 mA
PDPackage Power Dissipation 1.5 W
TSTG Storage Temperature –55 to 125 oC
TBIAS Temperature Under Bias –55 to 125 oC
Rev: 1.01 3/2002 15/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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Preliminary
Power Supply Voltage Ranges
Parameter Symbol Min. Typ. Max. Unit Notes
2.5 V Supply Voltage VDD2 2.3 2.5 2.7 V
1.8 V Supply Voltage VDD1 1.6 1.8 2.0 V
2.5 V VDDQ I/O Supply Voltage VDDQ2 2.3 2.5 2.7 V
1.8 V VDDQ I/O Supply Voltage VDDQ1 1.6 1.8 2.0 V
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.
VDDQ2 Range Logic Levels
Parameter Symbol Min. Typ. Max. Unit Notes
VDD Input High Voltage VIH 0.6*VDD —VDD + 0.3 V1
VDD Input Low Voltage VIL –0.3 —0.3*VDD V1
VDDQ I/O Input High Voltage VIHQ 0.6*VDD —VDDQ + 0.3 V1,3
VDDQ I/O Input Low Voltage VILQ –0.3 —0.3*VDD V1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
VDDQ1 Range Logic Levels
Parameter Symbol Min. Typ. Max. Unit Notes
VDD Input High Voltage VIH 0.6*VDD —VDD + 0.3 V1
VDD Input Low Voltage VIL –0.3 —0.3*VDD V1
VDDQ I/O Input High Voltage VIHQ 0.6*VDD —VDDQ + 0.3 V1,3
VDDQ I/O Input Low Voltage VILQ –0.3 —0.3*VDD V1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
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Preliminary
Note: These parameters are sample tested.
Notes:
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-
ature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1
Recommended Operating Temperatures
Parameter Symbol Min. Typ. Max. Unit Notes
Ambient Temperature (Commercial Range Versions) TA0 25 70 °C2
Ambient Temperature (Industrial Range Versions) TA–40 25 85 °C2
Note:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 2.5 V)
Parameter Symbol Test conditions Typ. Max. Unit
Input Capacitance CIN VIN = 0 V 4 5 pF
Input/Output Capacitance CI/O VOUT = 0 V 6 7 pF
Package Thermal Characteristics
Rating Layer Board Symbol Max Unit Notes
Junction to Ambient (at 200 lfm) single RΘJA 40 °C/W 1,2
Junction to Ambient (at 200 lfm) four RΘJA 24 °C/W 1,2
Junction to Case (TOP) —RΘJC 9°C/W 3
20% tKC
V
SS – 2.0 V
50%
VSS
VIH
Undershoot Measurement and Timing Overshoot Measurement and Timing
20% tKC
VDD + 2.0 V
50%
VDD
VIL
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Preliminary
AC Test Conditions
Parameter Conditions
Input high level VDD – 0.2 V
Input low level 0.2 V
Input slew rate 1 V/ns
Input reference level VDD/2
Output reference level VDDQ/2
Output load Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig.
1 unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
DC Electrical Characteristics
Parameter Symbol Test Conditions Min Max
Input Leakage Current
(except mode pins) IIL VIN = 0 to VDD –1 uA 1 uA
ZZ Input Current IIN1VDD ≥ VIN ≥ VIH
0 V ≤ VIN ≤ VIH
–1 uA
–1 uA 1 uA
100 uA
FTInput Current IIN2VDD ≥ VIN ≥ VIL
0 V ≤ VIN ≤ VIL
–100 uA
–1 uA 1 uA
1 uA
Output Leakage Current IOL Output Disable, VOUT = 0 to VDD –1 uA 1 uA
Output High Voltage VOH2 IOH = –8 mA, VDDQ = 2.3 V VDDQ – 0.4 V —
Output High Voltage VOH1 IOH = –4 mA, VDDQ = 1.6 V VDDQ – 0.4 V —
Output Low Voltage VOL2 IOL = 8 mA, VDD = 2.3 V —0.4 V
Output Low Voltage VOL1 IOL = 4 mA, VDD = 1.6 V —0.4 V
DQ
VDDQ/2
50Ω30pF*
Output Load 1
* Distributed Test Jig Capacitance
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Preliminary
Operating Currents
Notes:
1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation.
2. All parameters listed are worst case scenario.
Parameter Test Conditions Mode Symbol
-300 -275 -250 -225 -200
Unit
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
Operating
Current
2.5 V
Device Selected;
All other inputs
≥VIH or ≤ VIL
Output open
(x36)
Pipeline IDD
IDDQ
345
30 355
30 315
30 325
30 290
30 600
60 265
30 275
30 240
25 250
25 mA
Flow
Through IDD
IDDQ
195
30 205
30 190
30 200
30 185
30 195
30 175
30 185
30 165
25 175
25 mA
(x18)
Pipeline IDD
IDDQ
305
15 315
15 285
15 295
15 260
15 270
15 235
15 245
15 215
15 225
15 mA
Flow
Through IDD
IDDQ
175
10 185
10 170
10 180
10 165
10 175
10 155
10 165
10 150
10 160
10 mA
Operating
Current
1.8 V
Device Selected;
All other inputs
≥VIH or ≤ VIL
Output open
(x36)
Pipeline IDD
IDDQ
345
25 355
25 315
25 325
25 290
25 300
25 265
20 275
20 240
20 250
20 mA
Flow
Through IDD
IDDQ
195
30 205
30 190
30 200
30 185
30 195
30 175
30 185
30 165
25 175
25 mA
(x18)
Pipeline IDD
IDDQ
305
15 315
15 285
15 295
15 260
15 270
15 235
15 245
15 215
10 225
10 mA
Flow
Through
IDD
IDDQ
175
10 185
10 170
10 180
10 165
10 175
10 155
10 165
10 150
10 160
10 mA
Standby
Current ZZ ≥ VDD – 0.2 V —Pipeline ISB 35 45 35 45 35 45 35 45 35 45 mA
Flow
Through ISB 35 45 35 45 35 45 35 45 35 45 mA
Deselect
Current
Device Deselected;
All other inputs
≥ VIH or ≤ VIL
—Pipeline IDD 95 100 90 95 85 90 80 85 75 80 mA
Flow
Through IDD 70 75 70 75 60 65 60 65 50 55 mA
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Preliminary
AC Electrical Characteristics
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Parameter Symbol -300 -275 -250 -225 -200 Unit
Min Max Min Max Min Max Min Max Min Max
Pipeline
Clock Cycle Time tKC 3.3 —3.7 —4.0 —4.4 —5.0 —ns
Clock to Output Valid tKQ —2.2 —2.4 —2.5 —2.7 —3.0 ns
Clock to Output Invalid tKQX 1.5 —1.5 —1.5 —1.5 —1.5 —ns
Clock to Output in Low-Z tLZ11.5 —1.5 —1.5 —1.5 —1.5 —ns
Setup time tS 1.1 —1.1 —1.2 —1.3 —1.4 —ns
Hold time tH 0.1 —0.1 —0.2 —0.3 —0.4 —ns
Flow
Through
Clock Cycle Time tKC 5.0 —5.25 —5.5 —6.0 —6.5 —ns
Clock to Output Valid tKQ —5.0 —5.25 —5.5 —6.0 —6.5 ns
Clock to Output Invalid tKQX 3.0 —3.0 —3.0 —3.0 —3.0 —ns
Clock to Output in Low-Z tLZ13.0 —3.0 —3.0 —3.0 —3.0 —ns
Setup time tS 1.4 —1.4 —1.5 —1.5 —1.5 —ns
Hold time tH 0.4 —0.4 —0.5 —0.5 —0.5 —ns
Clock HIGH Time tKH 1.3 —1.3 —1.3 —1.3 —1.3 —ns
Clock LOW Time tKL 1.5 —1.5 —1.5 —1.5 —1.5 —ns
Clock to Output in
High-Z tHZ11.5 2.3 1.5 2.3 1.5 2.3 1.5 2.5 1.5 3.0 ns
G to Output Valid tOE —2.3 —2.3 —2.3 —2.5 —3.0 ns
G to output in Low-Z tOLZ10—0—0—0—0—ns
G to output in High-Z tOHZ1—2.3 —2.3 —2.3 —2.5 —3.0 ns
ZZ setup time tZZS25—5—5—5—5—ns
ZZ hold time tZZH21—1—1—1—1—ns
ZZ recovery tZZR 20 —20 —20 —20 —20 —ns
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Preliminary
Pipeline Mode Read/Write Cycle Timing
*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1
tH
tS
tH
CK
CKE
E*
ADV
tKH
W
tKL tKC
tS
Bn
A0–An A1
tH
tS
A2 A3
D(A1)
D(A2)
Q(A3) QQ(A6)
tH
tS
DD(A5)
tKQLZ
tKQ tKQHZ
tOEHZ tOELZ
tKQX
tKHQZ
tGLQV
G
1 2 3 4 5 6 7 8 9 10
COMMAND Write
D(A1) Write
D(A2) BURST
Write
D(A2+1)
Read
Q(A3) Read
Q(A4) BURST
Read
Q(A4+1)
Write
D(A5) Read
Q(A6) Write
D(A7) DESELECT
DON’T CARE UNDEFINED
DQA–DQD
tH
tS
tH
tS
tH
tS
A4 A5 A6 A7
Q(A4)
(A4+1)
(A2+1)
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Preliminary
Pipeline Mode No-Op, Stall and Deselect Timing
*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1
CK
CKE
E*
ADV
W
Bn
A0–An A1 A5
D(A1) Q(A2) Q(A3) Q(A5)
DQ
12345 6 78910
COMMAND Write
D(A1) Read
Q(A2) STALL Read
Q(A3) Write
D(A4) STALL NOP Read
Q(A5) CONTINUE
DON’T CARE UNDEFINED
D(A4)
tKHQZ
tKQHZ
DESELECT DESELECT
tH
tS
A2 A3 A4
tH
tS
tH
tS
tH
tS
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Preliminary
Flow Through Mode Read/Write Cycle Timing
*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1
CK
CKE
E*
ADV
tKH
W
tKL tKC
Bn
A0–An
tH
tS
A7
DQ
1 2 345678910
COMMAND Write
D(A1) Write
D(A2) BURST
Write
D(A2+1)
Read
Q(A3) Read
Q(A4) BURST
Read
Q(A4+1)
Write
D(A5) Read
Q(A6) Write
D(A7) DESELECT
DON’T CARE UNDEFINED
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
A1 A2 A3 A4 A5 A6
D(A1)
D(A2)
Q(A3) QQ(A6)
tH
tS
DD(A5)
tKQLZ
tKQ tKQHZ
tOEHZ tOELZ
tKQX
tKHQZ
tGLQV
Q(A4)
(A4+1)
(A2+1)
G
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Preliminary
Flow Through Mode No-Op, Stall and Deselect Timing
*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1
CK
CKE
E*
ADV
W
Bn
A0–An
Q(A5)
DQ
1 2 345 6 78910
COMMAND Write
D(A1) Read
Q(A2) STALL Read
Q(A3) Write
D(A4) STALL NOP Read
Q(A5) CONTINUE
DON’T CARE UNDEFINED
D(A4)
tKHQZ
tKQHZ
DESELECT DESELECT
D(A1) Q(A2) Q(A3)
A1 A5A2 A3 A4
tH
tS
tH
tS
tH
tS
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Preliminary
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output
drivers are powered by VDDQ.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
JTAG Pin Descriptions
Pin Pin Name I/O Description
TCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TMS Test Mode Select In The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
TDI Test Data In In
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
TDO Test Data Out Out Output that is active depending on the state of the TAP state machine. Output changes in
response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
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Preliminary
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Die
Revision
Code Not Used I/O
Configuration
GSI Technology
JEDEC Vendor
ID Code
Presence Register
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
x36 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1
x18 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1
Instruction Register
ID Code Register
Boundary Scan Register
012
012
· · · ·
31 30 29
012
· · ·
· · ·· · ·
n
0
Bypass Register
TDI TDO
TMS
TCK Test Access Port (TAP) Controller
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Preliminary
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
JTAG Tap Controller State Diagram
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when
the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices
in the scan path.
Select DR
Capture DR
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
Select IR
Capture IR
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
Test Logic Reset
Run Test Idle 0
0
1
0
1
1
0
0
1
1
1
0
0
1
1
0
00
0
1
1
0 0
11 0
0
0
1
11 1
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Preliminary
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruc-
tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan
Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the
Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it
is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although
allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be
stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be
paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-
DR state then places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s.
The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input
pins.
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST
command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK
when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected,
the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are trans-
ferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the
value of the Boundary Scan Register location with which each output pin is associated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID
register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any
time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the
Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.
RFUThese instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
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Preliminary
JTAG TAP Instruction Set Summary
Instruction Code Description Notes
EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1
IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2
SAMPLE-Z 010 Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z. 1
RFU 011 Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1
SAMPLE/
PRELOAD 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO. 1
GSI 101 GSI private instruction. 1
RFU 110 Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1
BYPASS 111 Places Bypass Register between TDI and TDO. 1
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Rev: 1.01 3/2002 29/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18/36AT-300/275/250/225/200
Draft Copy—GSI Technology Confidential
Preliminary
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter Symbol Min. Max. Unit Notes
3.3 V Test Port Input High Voltage VIHJ3 2.0 VDD3 +0.3 V1
3.3 V Test Port Input Low Voltage VILJ3 –0.3 0.8 V1
2.5 V Test Port Input High Voltage VIHJ2 0.6 * VDD2 VDD2 +0.3 V1
2.5 V Test Port Input Low Voltage VILJ2 –0.3 0.3 * VDD2 V1
TMS, TCK and TDI Input Leakage Current IINHJ –300 1 uA 2
TMS, TCK and TDI Input Leakage Current IINLJ –1 100 uA 3
TDO Output Leakage Current IOLJ –1 1 uA 4
Test Port Output High Voltage VOHJ 1.7 —V5, 6
Test Port Output Low Voltage VOLJ —0.4 V5, 7
Test Port Output CMOS High VOHJC VDDQ – 100 mV —V5, 8
Test Port Output CMOS Low VOLJC —100 mV V5, 9
Notes:
1. Input Under/overshoot voltage must be –2 V > Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
2. VILJ ≤ VIN ≤ VDDn
3. 0 V ≤ VIN ≤ VILJn
4. Output Disable, VOUT = 0 to VDDn
5. The TDO output driver is served by the VDDQ supply.
6. IOHJ = –4 mA
7. IOLJ = + 4 mA
8. IOHJC = –100 uA
9. IOHJC = +100 uA
Notes:
1. Include scope and jig capacitance.
2. Test conditions as as shown unless otherwise noted.
JTAG Port AC Test Conditions
Parameter Conditions
Input high level 2.3 V
Input low level 0.2 V
Input slew rate 1 V/ns
Input reference level 1.25 V
Output reference level 1.25 V
DQ
VT = 1.25 V
50Ω30pF*
JTAG Port AC Test Load
* Distributed Test Jig Capacitance
Rev: 1.01 3/2002 30/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18/36AT-300/275/250/225/200
Draft Copy—GSI Technology Confidential
Preliminary
JTAG Port Timing Diagram
JTAG Port AC Electrical Characteristics
Parameter Symbol Min Max Unit
TCK Cycle Time tTKC 50 —ns
TCK Low to TDO Valid tTKQ —20 ns
TCK High Pulse Width tTKH 20 —ns
TCK Low Pulse Width tTKL 20 —ns
TDI & TMS Set Up Time tTS 10 —ns
TDI & TMS Hold Time tTH 10 —ns
tTKQ
tTS tTH
tTKH tTKL
TCK
TMS
TDI
TDO
tTKC
Rev: 1.01 3/2002 31/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18/36AT-300/275/250/225/200
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Preliminary
GS8161Z18/36A Boundary Scan Chain Order
Order x36 x18 Pin
x36 x18
1PH = 0 n/a
2Xn/a
3Xn/a
4A10 44
5A11 45
6A12 46
7A13 47
8A14 48
9A15 49
10 A16 50
11 QA9 NC = 1 51 n/a
12 DA9 PH = 0 51 n/a
13 NC = 1 n/a
14 PH = 0 n/a
15 QA8 NC = 1 52 n/a
16 DA8 PH = 0 52 n/a
17 PH = 0 NC = 1 n/a
18 PH = 0 n/a
19 QA7 NC = 1 53 n/a
20 DA7 PH = 0 53 n/a
21 NC = 1 n/a
22 PH = 0 n/a
23 QA6 NC = 1 56 n/a
24 DA6 PH = 0 56 n/a
25 NC = 1 n/a
26 PH = 0 n/a
27 QA5 NC = 1 57 n/a
28 DA5 PH = 0 57 n/a
29 NC = 1 n/a
30 PH = 0 n/a
31 QA4 QA1 58
32 DA4 DA1 58
33 NC = 1 n/a
34 PH = 0 n/a
35 QA3 QA2 59
36 DA3 DA2 59
37 NC = 1 n/a
38 PH = 0 n/a
39 QA2 QA3 62
40 DA2 DA3 62
41 NC = 1 n/a
42 PH = 0 n/a
43 QA1 QA4 63
44 DA1 DA4 63
45 NC = 1 n/a
46 PH = 0 n/a
47 ZZ 64
48 PH = 0 n/a
49 NC = 1 n/a
50 QB1 QA5 68
51 DB1 DA5 68
52 NC = 1 n/a
53 PH = 0 n/a
54 QB2 QA6 69
55 DB2 DA6 69
56 NC = 1 n/a
57 PH = 0 n/a
58 QB3 QA7 72
59 DB3 DA7 72
GS8161Z18/36A Boundary Scan Chain Order
Order x36 x18 Pin
x36 x18
Rev: 1.01 3/2002 32/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18/36AT-300/275/250/225/200
Draft Copy—GSI Technology Confidential
Preliminary
60 NC = 1 n/a
61 PH = 0 n/a
62 QB4 QA8 73
63 DB4 DA8 73
64 NC = 1 n/a
65 PH = 0 n/a
66 QB5 QA9 74
67 DB5 DA9 74
68 NC = 1 n/a
69 PH = 0 n/a
70 QB6 NC = 1 75 n/a
71 DB6 PH = 0 75 n/a
72 NC = 1 n/a
73 PH = 0 n/a
74 QB7 NC = 1 78 n/a
75 DB7 PH = 0 78 n/a
76 NC = 1 n/a
77 PH = 0 n/a
78 QB8 NC = 1 79 n/a
79 DB8 PH = 0 79 n/a
80 NC = 1 n/a
81 PH = 0 n/a
82 QB9 NC = 1 80 n/a
83 DB9 PH = 0 80 n/a
84 NC = 1 n/a
85 PH = 0 n/a
86 NC = 1 A19 n/a 80
87 A981
88 A882
89 A17 83
GS8161Z18/36A Boundary Scan Chain Order
Order x36 x18 Pin
x36 x18
90 A18 84
91 ADV 85
92 G86
93 CKE 87
94 W88
95 NC = 1 n/a
96 NC = 1 n/a
97 NC = 1 n/a
98 NC = 1 n/a
99 CK 89
100 PH = 0 n/a
101 PH = 0 n/a
102 E392
103 BA93
104 BBNC = 1 94 n/a
105 BCBB95
106 BDNC = 1 96 n/a
107 E297
108 E198
109 A799
110 A6100
111 QC9 NC = 1 1n/a
112 DC9 PH = 0 1n/a
113 NC = 1 n/a
114 PH = 0 n/a
115 QC8 NC = 1 2n/a
116 DC8 PH = 0 2n/a
117 NC = 1 n/a
118 PH = 0 n/a
119 QC7 NC = 1 3n/a
GS8161Z18/36A Boundary Scan Chain Order
Order x36 x18 Pin
x36 x18
Rev: 1.01 3/2002 33/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18/36AT-300/275/250/225/200
Draft Copy—GSI Technology Confidential
Preliminary
120 DC7 PH = 0 3n/a
121 NC = 1 n/a
122 PH = 0 n/a
123 QC6 NC = 1 6n/a
124 DC6 PH = 0 6n/a
125 NC = 1 n/a
126 PH = 0 n/a
127 QC5 NC = 1 7n/a
128 DC5 PH = 0 7n/a
129 NC = 1 n/a
130 PH = 0 n/a
131 QC4 QB1 8
132 DC4 DB1 8
133 NC = 1 n/a
134 PH = 0 n/a
135 QC3 QB2 9
136 DC3 DB2 9
137 NC = 1 n/a
138 PH = 0 n/a
139 QC2 QB3 12
140 DC2 DB3 12
141 NC = 1 n/a
142 PH = 0 n/a
143 QC1 QB4 13
144 DC1 DB4 13
145 NC = 1 n/a
146 PH = 0 n/a
147 FT 14
148 NC = 1 n/a
149 NC = 1 n/a
GS8161Z18/36A Boundary Scan Chain Order
Order x36 x18 Pin
x36 x18
150 QD8 QB5 18
151 DD8 DB5 18
152 NC = 1 n/a
153 PH = 0 n/a
154 QD7 QB6 19
155 DD7 DB6 19
156 NC = 1 n/a
157 PH = 0 n/a
158 QD6 QB7 22
159 DD6 DB7 22
160 NC = 1 n/a
161 PH = 0 n/a
162 QD5 QB8 23
163 DD5 DB8 23
164 NC = 1 n/a
165 PH = 0 n/a
166 QD4 QB9 24
167 DD4 DB9 24
168 NC = 1 n/a
169 PH = 0 n/a
170 QD3 NC = 1 25 n/a
171 DD3 PH = 0 25 n/a
172 NC = 1 n/a
173 PH = 0 n/a
174 QD2 NC = 1 28 n/a
175 DD2 PH = 0 28 n/a
176 NC = 1 n/a
177 PH = 0 n/a
178 QD1 NC = 1 29 n/a
179 DD1 PH = 0 29 n/a
GS8161Z18/36A Boundary Scan Chain Order
Order x36 x18 Pin
x36 x18
Rev: 1.01 3/2002 34/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18/36AT-300/275/250/225/200
Draft Copy—GSI Technology Confidential
Preliminary
Notes:
1. Depending on the package, some input pads of the scan chain may not be connected to any external pin. In such case: LBO = 1, ZQ = 1,
PE = 0, SD = 0, ZZ = 0, FT = 1, and SCD = 1.
2. Every DQ pad consists of two scan registers—D is for input capture, and Q is for output capture.
3. A single register (#194) for controlling tristate of all the DQ pins is at the end of the scan chain (i.e., the last bit shifted in this tristate control
is effective after JTAG EXTEST instruction is executed.
4. 1 = no connect, internally set to logic value 1
5. 0 = no connect, internally set to logic value 0
6. X = no connect, value is undefined
180 NC = 1 n/a
181 PH = 0 n/a
182 QD9 NC = 1 30 n/a
183 DD9 PH = 0 30 n/a
184 NC = 1 n/a
185 PH = 0 n/a
186 LBO 31
187 A532
188 A433
189 A334
190 A235
191 A136
192 A037
193 PH = 0 n/a
194 G86
GS8161Z18/36A Boundary Scan Chain Order
Order x36 x18 Pin
x36 x18
Rev: 1.01 3/2002 35/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18/36AT-300/275/250/225/200
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Preliminary
TQFP Package Drawing
BPR 1999.05.18
D1
D
E1
E
Pin 1
b
e
c
L
L1
A2
A1
Y
θ
TQFP Package Drawing
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
Symbol Description Min. Nom. Max
A1 Standoff 0.05 0.10 0.15
A2 Body Thickness 1.35 1.40 1.45
bLead Width 0.20 0.30 0.40
cLead Thickness 0.09 0.20
DTerminal Dimension 21.9 22.0 20.1
D1 Package Body 19.9 20.0 20.1
ETerminal Dimension 15.9 16.0 16.1
E1 Package Body 13.9 14.0 14.1
eLead Pitch 0.65
LFoot Length 0.45 0.60 0.75
L1 Lead Length 1.00
YCoplanarity 0.10
θLead Angle 0°7°
Rev: 1.01 3/2002 36/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18/36AT-300/275/250/225/200
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Preliminary
Ordering Information—GSI NBT Synchronous SRAM
Org Part Number1Type Package Speed2
(MHz/ns) TA3Status
1M x 18 GS8161Z18AT-300 NBT Pipeline/Flow Through TQFP 300/5 C
1M x 18 GS8161Z18AT-275 NBT Pipeline/Flow Through TQFP 275/5.25 C
1M x 18 GS8161Z18AT-250 NBT Pipeline/Flow Through TQFP 250/5.5 C
1M x 18 GS8161Z18AT-225 NBT Pipeline/Flow Through TQFP 225/6 C
1M x 18 GS8161Z18AT-200 NBT Pipeline/Flow Through TQFP 200/6.5 C
512K x 36 GS8161Z36AT-300 NBT Pipeline/Flow Through TQFP 300/5 C
512K x 36 GS8161Z36AT-275 NBT Pipeline/Flow Through TQFP 275/5.25 C
512K x 36 GS8161Z36AT-250 NBT Pipeline/Flow Through TQFP 250/5.5 C
512K x 36 GS8161Z36AT-225 NBT Pipeline/Flow Through TQFP 225/6 C
512K x 36 GS8161Z36AT-200 NBT Pipeline/Flow Through TQFP 200/6.5 C
1M x 18 GS8161Z18AT-300I NBT Pipeline/Flow Through TQFP 300/5 I
1M x 18 GS8161Z18AT-275I NBT Pipeline/Flow Through TQFP 275/5.25 I
1M x 18 GS8161Z18AT-250I NBT Pipeline/Flow Through TQFP 250/5.5 I
1M x 18 GS8161Z18AT-225I NBT Pipeline/Flow Through TQFP 225/6 I
1M x 18 GS8161Z18AT-200I NBT Pipeline/Flow Through TQFP 200/6.5 I
512K x 36 GS8161Z36AT-300I NBT Pipeline/Flow Through TQFP 300/5 I
512K x 36 GS8161Z36AT-275I NBT Pipeline/Flow Through TQFP 275/5.25 I
512K x 36 GS8161Z36AT-250I NBT Pipeline/Flow Through TQFP 250/5.5 I
512K x 36 GS8161Z36AT-225I NBT Pipeline/Flow Through TQFP 225/6 I
512K x 36 GS8161Z36AT-200I NBT Pipeline/Flow Through TQFP 200/6.5 I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8161Z36A-300IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
Rev: 1.01 3/2002 37/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18/36AT-300/275/250/225/200
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Preliminary
18Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old;
New Types of Changes
Format or Content Page;Revisions;Reason
8161Z18A_r1 • Creation of new datasheet
8161Z18A_r1; 8161Z18A_r1_01 Content
• Updated AC Characteristics table
• Updated FT power numbers on page 1 and in Operating Currents
table
• Updated VIH to 2.0 from 1.7
• Updated Mb references to 18Mb from 16Mb
• IUpdated BSR table
• Removed all ByteSafe references
• Updated ZZ recovery time diagram
• Updated AC Test Conditions table and removed Output Load
2 diagram
