10/20/11
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HEXFET® Power MOSFET
AUIRF1324WL
GDS
Gate Drain Source
Description
Specifically design for automotive applications this Widelead TO-
262 package part has the advantage of having over 50% lower
lead resistance and delivering over 20% lower Rds(on) when
compared with a traditional TO-262 package housing the same
silicon die. This greatly helps in reducing condition losses, achieving
higher current levels or enabling a system to run cooler and have
improved efficiency. Additional features of this design are a 175°C
junction operating temperature, fast switching speed and improved
repetitive avalanche rating . These features combine to make this
design an extremely efficient and reliable device for use in
Automotive and other applications.
Features
lAdvanced Process Technology
lUltra Low On-Resistance
l50% Lower Lead Resistance
l175°C Operating Temperature
lFast Switching
lRepetitive Avalanche Allowed up to Tjmax
lLead-Free, RoHS Compliant
lAutomotive Qualified *
HEXFET® is a registered trademark of International Rectifier.
*Qualification standards can be found at http://www.irf.com/
AUTOMOTIVE GRADE
Absolute Maximum Ratings
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only; and functional operation of the device at these or any other condition beyond those
indicated in the specifications is not implied.Exposure to absolute-maximum-rated conditions for extended
periods may affect device reliability. The thermal resistance and power dissipation ratings are measured under
board mounted and still air conditions. Ambient temperature (TA) is 25°C, unless otherwise specified.
S
D
G
V
(BR)DSS
24V
R
DS(on)
typ. 1.16m
max. 1.30m
I
D (Silicon Limited)
382A
c
I
D (Package Limited)
240A
TO-262 WideLead
G
D
S
Parameter
Units
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
I
D
@ T
C
= 100°C
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V (Package Limited)
I
DM
Pulsed Drain Current
d
P
D
@T
C
= 25°C
Maximum Power Dissipation W
Linear Derating Factor W/°C
V
GS
Gate-to-Source Voltage V
E
AS (Thermally limited)
e
mJ
I
AR
Avalanche Current
d
A
E
AR
Repetitive Avalanche Energy
d
mJ
dv/dt Peak Diode Recovery
f
V/ns
T
J
Operating Junction and
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
Thermal Resistance
Parameter
Typ.
Max.
Units
R
JC
Junction-to-Case
j
––– 0.50
A
°C
°C/W
300 (1.6mm from case)
530
See Fig. 14, 15, 22a, 22b,
Max.
382
c
270
c
1530
240
300
1.3
-55 to + 175
± 20
2.0
PD - 97676A
AUIRF1324WL
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Notes:
Calculated continuous current based on maximum allowable junction
temperature. Package limitation current is 240A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements.(Refer to AN-1140
http://www.irf.com/technical-info/appnotes/an-1140.pdf
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.028mH
RG = 50, IAS = 195A, VGS =10V. Part not recommended for use
above this value.
S
D
G
ISD 195A, di/dt 600A/μs, VDD V(BR)DSS, TJ 175°C.
Pulse width 400μs; duty cycle 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
R is measured at TJ approximately 90°C.
Static Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
Parameter
Min.
Typ.
Max.
Units
V
(BR)DSS
Drain-to-Source Breakdown Voltage
24
–––
–––
V
V
(BR)DSS
/
T
J
Breakdown Voltage Temp. Coefficient
–––
0.022
–––
V/°C
R
DS(on)
Static Drain-to-Source On-Resistance
–––
1.16
1.30
m
V
GS(th)
Gate Threshold Voltage
2.0
–––
4.0
V
gfs
Forward Transconductance
210
–––
–––
S
R
G
Internal Gate Resistance
–––
2.4
–––
I
DSS
Drain-to-Source Leakage Current
–––
–––
20
–––
–––
250
I
GSS
Gate-to-Source Forward Leakage
–––
–––
200
Gate-to-Source Reverse Leakage
–––
–––
-200
Dynamic Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
Parameter
Min.
Typ.
Max.
Units
Q
g
Total Gate Charge
–––
120
180
Q
gs
Gate-to-Source Charge
–––
58
–––
Q
gd
Gate-to-Drain ("Miller") Charge
–––
36
–––
Q
sync
Total Gate Charge Sync. (Q
g
- Q
gd
)
–––
84
–––
t
d(on)
Turn-On Delay Time
–––
18
–––
t
r
Rise Time
–––
200
–––
t
d(off)
Turn-Off Delay Time
–––
75
–––
t
f
Fall Time
–––
110
–––
C
iss
Input Capacitance
–––
7630
–––
C
oss
Output Capacitance
–––
3390
–––
C
rss
Reverse Transfer Capacitance
–––
1960
–––
C
oss
eff. (ER)
Effective Output Capacitance (Energy Related)
–––
4660
–––
C
oss
eff. (TR)
Effective Output Capacitance (Time Related)
–––
4685
–––
Diode Characteristics
Parameter
Min.
Typ.
Max.
Units
I
S
Continuous Source Current
–––
–––
382
c
(Body Diode)
I
SM
Pulsed Source Current
–––
–––
1530
(Body Diode)
d
V
SD
Diode Forward Voltage
–––
–––
1.3
V
t
rr
Reverse Recovery Time
–––
46
69
T
J
= 25°C
V
R
= 20V,
–––
45
68
T
J
= 125°C
I
F
= 195A
Q
rr
Reverse Recovery Charge
–––
395
593
T
J
= 25°C
di/dt = 100A/μs
g
–––
345
518
T
J
= 125°C
I
RRM
Reverse Recovery Current
–––
1.9
–––
A
T
J
= 25°C
t
on
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
I
D
= 195A
R
G
= 2.7
V
GS
= 10V
g
V
DD
= 16V
I
D
= 195A, V
DS
=0V, V
GS
= 10V
g
T
J
= 25°C, I
S
= 195A, V
GS
= 0V
g
integral reverse
p-n junction diode.
Conditions
V
GS
= 0V, I
D
= 250μA
Reference to 25°C, I
D
= 5mA
g
V
GS
= 10V, I
D
= 195A
g
V
DS
= V
GS
, I
D
= 250μA
V
DS
= 24V, V
GS
= 0V
V
DS
= 19V, V
GS
= 0V, T
J
= 125°C
MOSFET symbol
showing the
V
DS
=12V
Conditions
V
GS
= 10V
g
V
GS
= 0V
V
DS
= 19V
ƒ = 1.0MHz, See Fig.5
V
GS
= 0V, V
DS
= 0V to 19V
i
, See Fig.11
V
GS
= 0V, V
DS
= 0V to 19V
h
Conditions
V
DS
= 10V, I
D
= 195A
I
D
= 195A
V
GS
= 20V
V
GS
= -20V
nA
μA
nC
ns
pF
A
ns
nC
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Qualification standards can be found at International Rectifiers web site: http//www.irf.com/
 Exceptions (if any) to AEC-Q101 requirements are noted in the qualification report.
 Highest passing voltage.
Qualification Information
†
TO-262
WideLead MSL1
Qualification Level
Automotive
(per AEC-Q101) ††
Comments: This part number(s) passed Automotive
qualification. IR’s Industrial and Consumer qualification
level is granted by extension of the higher Automotive level.
Charged Device
Model
Class C5 (+/- 1125V)†††
AEC-Q101-005
Moisture Sensitivity Level
RoHS Compliant Yes
ESD
Machine Model Class M4 (+/- 425V)†††
AEC-Q101-002
Human Body Model Class H2 (+/- 4000V)†††
AEC-Q101-001
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Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature
Fig 2. Typical Output Characteristics
Fig 6. Typical Gate Charge vs. Gate-to-Source VoltageFig 5. Typical Capacitance vs. Drain-to-Source Voltage
0.1 110 100
VDS, Drain-to-Source Voltage (V)
10
100
1000
10000
ID, Drain-to-Source Current (A)
VGS
TOP 15V
10V
6.5V
5.8V
5.4V
5.0V
4.8V
BOTTOM 4.5V
60μs PULSE WIDTH
Tj = 25°C
4.5V
0.1 110 100
VDS, Drain-to-Source Voltage (V)
10
100
1000
10000
ID, Drain-to-Source Current (A)
4.5V
60μs PULSE WIDTH
Tj = 175°C
VGS
TOP 15V
10V
6.5V
5.8V
5.4V
5.0V
4.8V
BOTTOM 4.5V
2 3 4 5 6 7 8 9
VGS, Gate-to-Source Voltage (V)
0.1
1
10
100
1000
10000
ID, Drain-to-Source Current (A)
TJ = 25°C
TJ = 175°C
VDS = 15V
60μs PULSE WIDTH
-60 -40 -20 020 40 60 80 100120140160180
TJ , Junction Temperature (°C)
0.0
0.5
1.0
1.5
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 195A
VGS = 10V
110 100
VDS, Drain-to-Source Voltage (V)
1000
10000
100000
C, Capacitance (pF)
VGS = 0V, f = 1 MHZ
Ciss = C gs + Cgd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
0 20 40 60 80 100 120 140 160 180
QG, Total Gate Charge (nC)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
VGS, Gate-to-Source Voltage (V)
VDS= 19V
VDS= 12V
ID= 195A
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Fig 8. Maximum Safe Operating Area
Fig 10. Drain-to-Source Breakdown Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
Fig 11. Typical COSS Stored Energy
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
VSD, Source-to-Drain Voltage (V)
1.0
10
100
1000
10000
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
25 50 75 100 125 150 175
TC , Case Temperature (°C)
0
100
200
300
400
ID, Drain Current (A)
Limited By Package
-60 -40 -20 020 40 60 80 100120140160180
TJ , Temperature ( °C )
24
25
26
27
28
29
30
V(BR)DSS, Drain-to-Source Breakdown Voltage (V)
Id = 5mA
-5 0 5 10 15 20 25
VDS, Drain-to-Source Voltage (V)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Energy (μJ)
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
500
1000
1500
2000
2500
EAS , Single Pulse Avalanche Energy (mJ)
ID
TOP 99A
100A
BOTTOM 195A
0.1 1 10 100
VDS, Drain-toSource Voltage (V)
0.1
1
10
100
1000
10000
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 175°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100μsec
DC
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Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1E-006 1E-005 0.0001 0.001 0.01 0.1 1
t1 , Rectangular Pulse Duration (sec)
0.0001
0.001
0.01
0.1
1
Thermal Response ( Z thJC ) °C/W
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE ) Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
Ri (°C/W) i (sec)
0.0493 0.000124
0.1910 0.003004
0.2586 0.021684
J
J
1
1
2
23
3
R1
R1R2
R2R3
R3
C
Ci iRi
Ci= iRi
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
1
10
100
1000
Avalanche Current (A)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming  j = 25°C and
Tstart = 150°C.
0.01
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming Tj = 150°C and
Tstart =25°C (Single Pulse)
Fig 14. Typical Avalanche Current vs. Pulsewidth
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Fig 15. Maximum Avalanche Energy vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figure 22a, 22b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 16. Threshold Voltage vs. Temperature
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
100
200
300
400
500
600
EAR , Avalanche Energy (mJ)
TOP Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 195A
-75 -50 -25 025 50 75 100 125 150 175
TJ , Temperature ( °C )
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VGS(th), Gate threshold Voltage (V)
ID = 250μA
ID = 1.0mA
ID = 1.0A
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Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
 Low Stray Inductance
Ground Plane
Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P. W .
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
D.U.T
Inductor Current
R
G
I
AS
0.01
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
VDD
VDS
LD
D.U.T
+
-
Second Pulse Width < 1μs
Duty Factor < 0.1%
tp
V
(BR)DSS
I
AS
1K
VCC
DUT
0
L
S
20K
Vds
Vgs
Id
Vgs(th)
Qgs1
Qgs2QgdQgodr
VDS
VGS
90%
10%
td(off) td(on)
tftr
AUIRF1324WL
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TO-262 WideLead Package Outline
Dimensions are shown in millimeters (inches)
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
TO-262 WideLead Part Marking Information
YWWA
XX or XX
Part Number
IR Logo
Lot Code
AUIRF1324WL
Date Code
Y= Year
WW= Work Week
A= Automotive, Lead Free
AUIRF1324WL
10 www.irf.com
Ordering Information
Base part number
Package Type
Standard Pack
Complete Part Number
Form
Quantity
AUIRF1324WL TO-262 WideLead Tube 50 AUIRF1324WL
AUIRF1324WL
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corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or
services without notice. Part numbers designated with the “AU” prefix follow automotive industry and / or customer specific requirements with regards
to product discontinuance and process change notification. All products are sold subject to IR’s terms and conditions of sale supplied at the time of order
acknowledgment.
IR warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with IR’s standard warranty. Testing
and other quality control techniques are used to the extent IR deems necessary to support this warranty. Except where mandated by government
requirements, testing of all parameters of each product is not necessarily performed.
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