Publication# 16072 Rev. EAmendment/0
Issue Date: February 1996
2-306
PALCE26V12 Family
28-Pin EE CMOS Versatile PAL Device
FINAL COM’L: H-7/10/15/20 IND: H-10/15/20
DISTINCTIVE CHARACTERISTICS
■ 28-pin versatile PAL programmable logic
device architecture
■ Electrically erasable CMOS technology
provides half power (only 115 mA) at high
speed (7.5 ns propagation delay)
■ 14 dedicated inputs and 12 input/output
macrocells for architectural flexibility
■ Macrocells can be registered or combinatorial,
and active high or active low
■ Varied product term distribution allows up to
16 product terms per output
■ Two clock inputs for independent functions
■ Global asynchronous reset and synchronous
preset for initialization
■ Register preload for testability and built-in
register reset on power-up
■ Space-efficient 28-pin SKINNYDIP and PLCC
packages
■ Center VCC and GND pins to improve signal
characteristics
■ Extensive third-party software and programmer
support through FusionPLD partners
GENERAL DESCRIPTION
The PALCE26V12 is a 28-pin version of the popular
PAL22V10 architecture. Built with low-power, high-
speed, electrically-erasable CMOS technology, the
PALCE26V12 offers many unique advantages.
Device logic is automatically configured according to
the user’s design specification. Design is simplified by
design software, allowing automatic creation of a
programming file based on Boolean or state equations.
The software can also be used to verify the design and
can provide test vectors for the programmed device.
The PALCE26V12 utilizes the familiar sum-of-products
(AND/OR) architecture that allows users to implement
complex logic functions easily and efficiently. Multiple
levels of combinatorial logic can always be reduced
to sum-of-products form, taking advantage of the
very wide input gates available in PAL devices. The
functions are programmed into the device through
electrically-erasable floating-gate cells in the AND logic
array and the macrocells. In the unprogrammed state,
all AND product terms float HIGH. If both true and
complement of any input are connected, the term will be
permanently LOW.
The product terms are connected to the fixed OR array
with a varied distribution from 8 to 16 across the outputs
(see Block Diagram). The OR sum of the products feeds
the output macrocell. Each macrocell can be pro-
grammed as registered or combinatorial, active high or
active low, with registered I/O possible. The flip-flop can
be clocked by one of two clock inputs. The output
configuration is determined by four bits controlling three
multiplexers in each macrocell.
AMD’s FusionPLD program allows PALCE26V12
designs to be implemented using a wide variety of
popular industry-standard design tools. By working
closely with the FusionPLD partners, AMD certifies that
the tools provide accurate, quality support. By ensuring
that third-party tools are available, costs are lowered
because a designer does not have to buy a complete set
of new tools for each device. The FusionPLD program
also greatly reduces design time since a designer can
use a tool that is already installed and familiar. Please
refer to the PLD Software Reference Guide for certified
development systems and the Programmer Reference
Guide for approved programmers.
AMD
2–307PALCE26V12 Family
BLOCK DIAGRAM
16072E-1
MACRO
I/O 0
8
12
I
2
CLK/I
MACRO
I/O 1
8
MACRO
I/O 2
10
MACRO
I/O 3
12
MACRO
I/O 4
14
MACRO
I/O 5
16
MACRO
I/O 6
16
MACRO
I/O 7
14
MACRO
I/O 8
12
MACRO
I/O 9
10
MACRO
I/O10
8
MACRO
I/O 11
8
ASYNC.
RESET
PROGRAMMABLE
AND ARRAY
(52x150)
SYNC.
PRESET
CONNECTION DIAGRAMS
Top View PLCC
16072E-2
Note:
Pin 1 is marked for orientation.
1
234 28 27 26
255
24
23
22
21
20
19
1817
1615
6
7
8
9
10
11 12 13 14
I/O9
I/O8
I/O7
I/O6
GND
I/O5
I/O4
I4
I5
VCC
I6
I7
I8
I9
I10
I11
I12
I/O0
I/O1
I/O2
I/O3
CLK2/I3
I2
I1
CLK1/I0
I13
I/O11
I/O10
1
3
5
7
9
11
12
10
2
4
8
6
28
26
24
22
20
14
17
19
27
25
21
23
13
18
16
15
DIP
CLK1/I0
I1
I2
CLK2/I3
I4
I5
VCC
I6
I7
I8
I9
I10
I11
I12
I13
I/O11
I/O10
I/O9
I/O8
I/O7
I/O6
GND
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
16072E-3
PIN DESCRIPTION
CLK = Clock
GND = Ground
I = Input
I/O = Input/Output
VCC = Supply Voltage
AMD
2–308 PALCE26V12H-7/10/15/20 (Com’l), H-10/15/20 (Ind)
ORDERING INFORMATION
Commercial and Industrial Products
AMD commercial and industrial programmable logic products are available with several ordering options. The order
number (Valid Combination) is formed by a combination of:
JC
Valid Combinations Valid Combinations
PAL CE 26 V 12 -7 P
FAMILY TYPE
PAL = Programmable Array Logic
NUMBER OF
ARRAY INPUTS
OUTPUT TYPE
V= Versatile
NUMBER OF OUTPUTS
SPEED
-7 = 7.5 ns tPD
-10= 10 ns tPD
-15= 15 ns tPD
-20= 20 ns tPD
PACKAGE TYPE
P= 28-Pin 300 mil Plastic
SKINNYDIP (PD3028)
J = 28-Pin Plastic Leaded Chip
Carrier (PL 028)
OPERATING CONDITIONS
C = Commercial (0°C to +75°C)
I = Industrial (–40°C to +85°C)
OPTIONAL PROCESSING
Blank = Standard Processing
TECHNOLOGY
CE=CMOS Electrically Erasable
/4
C
PROGRAMMING DESIGNATOR
/4 = First Revision
(May require programmer
update)
H
POWER
H= Half Power (115 mA ICC)
Valid Combinations list configurations planned to be
supported in volume for this device. Consult the lo-
cal AMD sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.
PALCE26V12H-7
PALCE26V12H-10
PALCE26V12H-15
PALCE26V12H-20
/4
PC, JC, PI, JI
AMD
2–309PALCE26V12 Family
FUNCTIONAL DESCRIPTION
The PALCE26V12 has fourteen dedicated input lines,
two of which can be used as clock inputs. Unused inputs
should be tied directly to ground or VCC. Buffers for
device inputs and feedbacks have both true and
complementary outputs to provide user-selectable
signal polarity. The inputs drive a programmable AND
logic array, which feeds a fixed OR logic array.
The OR gates feed the twelve I/O macrocells (see
Figure 1). The macrocell allows one of eight potential
output configurations; registered or combinatorial, ac-
tive high or active low, with register or I/O pin feedback
(see Figure 2). In addition, registered configurations can
be clocked by either of the two clock inputs.
The configuration choice is made according to the
user’s design specification and corresponding program-
ming of the configuration bits S0–S3 (see Table 1).
Multiplexer controls initially float to VCC (1) through a
programmable cell, selecting the “1” path through the
multiplexer. Programming the cell connects the control
line to GND (0), selecting the “0” path.
Table 1. Macrocell Configuration Table
S3 S1 S0 Output Configuration
1 0 0 Registered Output and Feedback,
Active Low
1 0 1 Registered Output and Feedback,
Active High
1 1 0 Combinatorial I/O, Active Low
1 1 1 Combinatorial I/O, Active High
0 0 0 Registered I/O, Active Low
0 0 1 Registered I/O, Active High
0 1 0 Combinatorial Output, Registered
Feedback, Active Low
0 1 1 Combinatorial Output, Registered
Feedback, Active High
S2 Clock Input
1 CLK1/I0
0 CLK2/I3
1 = Unprogrammed EE bit
0 = Programmed EE bit
16072E-4
*
DARQ
Q
SP
AR
P1
Pn
0
1
10
11
00
01
OE
SP
1
0
0
S
3
S
1
S
2
S
CLK2
CLK1
n = 8,8,10,12,14,16
When S = 1 (unprogrammed) the feedback is selected by S .
When S = 0 (programmed), the feedback is the opposite of
that selected by S .
*3
31
1
Figure 1. PALCE26V12 Macrocell
Registered or Combinatorial
Each macrocell of the PALCE26V12 includes a D-type
flip-flop for data storage and synchronization. The
flip-flop is loaded on the LOW-to-HIGH edge of the
selected clock input. Any macrocell can be configured
as combinatorial by selecting a multiplexer path that
bypasses the flip-flop. Bypass is controlled by bit S1.
Programmable Clock
The clock input for any flip-flop can be selected to be
from either pin 1 or pin 4. A 2:1 multiplexer controlled by
bit S2 determines the clock input.
Programmable Feedback
A 2:1 multiplexer allows the user to determine whether
the macrocell feedback comes from the flip-flop or
from the I/O pin, independent of whether the output is
registered or combinatorial. Thus, registered outputs
may have internal register feedback for higher speed
(fMAX internal), or I/O feedback for use of the pin as a
direct input (fMAX external). Combinatorial outputs may
have I/O feedback, either for use of the signal in other
equations or for use as another direct input, or register
feedback.
AMD
2–310 PALCE26V12 Family
The feedback multiplexer is controlled by the same bit
(S1) that controls whether the output is registered or
combinatorial, as on the 22V10, with an additional
control bit (S3) that allows the alternative feedback path
to be selected. When S3 = 1, S1 selects register
feedback for registered outputs (S1 = 0) and I/O
feedback for combinatorial outputs (S1 = 1). When S3 =
0, the opposite is selected: I/O feedback for registered
outputs and register feedback for combinatorial outputs.
Programmable Enable and I/O
Each macrocell has a three-state output buffer con-
trolled by an individual product term. Enable and disable
can be a function of any combination of device inputs or
feedback. The macrocell provides a bidirectional I/O pin
if I/O feedback is selected, and may be configured as a
dedicated input if the buffer is always disabled. This is
accomplished by connecting all inputs to the enable
term, forcing the AND of the complemented inputs to be
always LOW. To permanently enable the outputs, all
inputs are left disconnected from the term (the
unprogrammed state).
Programmable Output Polarity
The polarity of each macrocell output can be active high
or active low, either to match output signal needs or to
reduce product terms. Programmable polarity allows
Boolean expressions to be written in their most compact
form (true or inverted), and the output can still be of the
desired polarity. It can also save “DeMorganizing”
efforts.
Selection is controlled by programmable bit S0 in the
output macrocell, and affects both registered and
combinatorial outputs. Selection is automatic, based on
the design specification and pin definitions. If the pin
definition and output equation have the same polarity,
the output is programmed to be active high.
Preset/Reset
For initialization, the PALCE26V12 has additional
Preset and Reset product terms. These terms are
connected to all registered outputs. When the Synchro-
nous Preset (SP) product term is asserted high, the
output registers will be loaded with a HIGH or the next
LOW-to-HIGH clock transition. When the Asynchronous
Reset (AR) product term is asserted high, the output
registers will be immediately loaded with a LOW
independent of the clock.
Note that preset and reset control the flip-flop, not the
output pin. The output level is determined by the output
polarity selected.
Power-Up Reset
All flip-flops power up to a logic LOW for predictable
system initialization. Outputs of the PALCE26V12 will
be HIGH or LOW depending on whether the output is
active low or active high, respectively. The VCC rise must
be monotonic, and the reset delay time is 1000 ns
maximum.
Register Preload
The register on the PALCE26V12 can be preloaded
from the output pins to facilitate functional testing of
complex state machine designs. This feature allows
direct loading of arbitrary states, thereby making it
unnecessary to cycle through long test vector se-
quences to reach a desired state. In addition, transitions
from illegal states can be verified by loading illegal
states and observing proper recovery.
Security Bit
After programming and verification, a PALCE26V12
design can be secured by programming the security bit.
Once programmed, this bit defeats readback of the
internal programmed pattern by a device programmer,
securing proprietary designs from competitors. Pro-
gramming the security bit disables preload, and the
array will read as if every bit is disconnected. The
security bit can only be erased in conjunction with
erasure of the entire pattern.
Programming and Erasing
The PALCE26V12 can be programmed on standard
logic programmers. It also may be erased to reset a
previously configured device back to its virgin state.
Erasure is automatically performed by the programming
hardware. No special erase operation is required.
Quality and Testability
The PALCE26V12 offers a very high level of built-in
quality. The erasability of the device provides a means
of verifying performance of all AC and DC parameters.
In addition, this verifies complete programmability and
functionality of the device to provide the highest
programming yields and post-programming functional
yields in the industry.
Technology
The high-speed PALCE26V12 is fabricated with AMD’s
advanced electrically erasable (EE) CMOS process.
The array connections are formed with proven EE cells.
Inputs and outputs are designed to be compatible with
TTL devices. This technology provides strong input
clamp diodes, output slew-rate control, and a grounded
substrate for clean switching.
AMD
2–311PALCE26V12 Family
16072E-5
DQ
Q
CLK SP
AR
Registered Active-Low Output,
Register Feedback
DQ
Q
CLK SP
AR
Registered Active-High Output,
Register Feedback
DQ
Q
CLK SP
AR
Registered Active-Low I/O
DQ
Q
CLK SP
AR
Registered Active-High I/O
Registered Outputs
Combinatorial Active-Low I/O
DQ
Q
CLK SP
AR
Combinatorial Active-Low Output,
Register Feedback
Combinatorial Active-High I/O
DQ
Q
CLK SP
AR
Combinatorial Active-High Output,
Register Feedback
Combinatorial Outputs
Figure 2. PALCE26V12 Macrocell Configuration Options
AMD
2–312 PALCE26V12 Family
LOGIC DIAGRAM PALCE26V12
2
I
4
CLK /I
5
I
6
I
04 128 162024 28 3236 40 44 48 ASYNCH.
RESET
3
I
8
I
28
I
27
I/O
22
I/O
24
I/O
25
I/O
26
I/O
23
I/O
Q
DQ
AR
10
11
00
01
1
0SP
0
1
Q
DQ
AR
10
11
00
01
1
0SP
0
1
Q
DQ
AR
10
11
00
01
1
0SP
0
1
Q
DQ
AR
10
11
00
01
1
0SP
0
1
Q
DQ
AR
10
11
00
01
1
0SP
0
1
Q
DQ
AR
10
11
00
01
1
0SP
0
1
S3
S0
S1
S3
S2
S0
S1
S3
S2
S0
S1
S3
S2
S0
S1
S3
S2
S0
S1
S3
S2
*
*
*
*
*
*
S0
S1
S2
04 128 162024 28 3236 40 44 48 CLK
CLK
SP
AR
0
1
9
10
18
19
29
30
42
43
57
58
74
1
2
23
4
5
6
6
7
8
9
10
11
13
12
1
R11
R10
R9
R8
R7
R6
*21
GND
1
When S = 1 (unprogrammed) the feedback is selected by S .
When S = 0 (programmed), the feedback is the opposite of
that selected by S .
1
33
CLK /I
10
16072E-6
AMD
2–313PALCE26V12 Family
LOGIC DIAGRAM (continued)
16072E-6
(concluded)
PALCE26V12
04 128 162024 28 3236 40 44 48
20
I/O
15
I/O
17
I/O
18
I/O
19
I/O
16
I/O
SYNCH
PRESET
10
I
11
I
12
I
13
I
14
I
9
I
Q
DQ
AR
10
11
00
01
1
0SP
0
1
Q
DQ
AR
10
11
00
01
1
0SP
0
1
Q
DQ
AR
10
11
00
01
1
0SP
0
1
Q
DQ
AR
10
11
00
01
1
0SP
0
1
Q
DQ
AR
10
11
00
01
1
0SP
0
1
Q
DQ
AR
10
11
00
01
1
0SP
0
1
CLK
CLK
SP
AR
04 128 162024 28 3236 40 44 48
S0
S1
S3
S2
S0
S1
S3
S2
S0
S1
S2
S0
S1
S2
S0
S1
S2
S0
S1
S2
When S = 1 (unprogrammed) the feedback is selected by S .
When S = 0 (programmed), the feedback is the opposite of
that selected by S .
*
75
91
92
106
107
119
120
130
131
139
140
148
149
1
3
31
1
2
7
8
9
10
11
12
0
1
2
3
4
5
S3
S3
*
*
*
*
*
S3
R5
R4
R3
R2
R1
R0
*
S3
AMD
2–314 PALCE26V12H-7/10 (Com’l), H-10 (Ind)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature –65°C to +150°C. . . . . . . . . . .
Ambient Temperature with
Power Applied –55°C to +125°C. . . . . . . . . . . . . . . . .
Supply Voltage with
Respect to Ground –0.5 V to +7.0 V. . . . . . . . . . . . .
DC Input Voltage –0.6 V to +7.0 V. . . . . . . . . . . . . . .
DC Output or I/O
Pin Voltage –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . .
Static Discharge Voltage 2001 V. . . . . . . . . . . . . . . . .
Stresses above those listed under Absolute Maximum Rat-
ings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maxi-
mum Ratings for extended periods may affect device reliabil-
ity. Programming conditions may differ.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA)
Operating in Free Air 0°C to +75°C. . . . . . . . . . . . . .
Supply Voltage (VCC)
with Respect to Ground +4.75 V to +5.25 V. . . . . . . .
Industrial (I) Devices
Ambient Temperature (TA)
Operating in Free Air –40°C to +85°C. . . . . . . . . . . .
Supply Voltage (VCC)
with Respect to Ground +4.5 V to +5.5 V. . . . . . . . . .
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges unless
otherwise specified
Parameter
Symbol Parameter Description Test Conditions Min Max Unit
VOH Output HIGH Voltage IOH = –3.2 mA VIN = VIH or VIL 2.4 V
V
CC = Min
VOL Output LOW Voltage IOL = 16 mA VIN = VIH or VIL 0.4 V
VCC = Min
VIH Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V
Voltage for all Inputs (Note 1)
VIL Input LOW Voltage Guaranteed Input Logical LOW 0.8 V
Voltage for all Inputs (Note 1)
IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA
IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) –10 µA
IOZH Off-State Output Leakage VOUT = 5.25 V, VCC = Max 10 µA
Current HIGH VIN = VIH or VIL (Note 2)
IOZL Off-State Output Leakage VOUT = 0 V, VCC = Max –10 µA
Current LOW VIN = VIH or VIL (Note 2)
ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –30 –170 mA
ICC VIN = 0 V, Outputs Open (IOUT = 0 mA) H-7/10 115 mA
(Static) VCC = Max, f = 0 MHz
ICC H-7/10 140 mA
(Dynamic)
ICC Industrial Supply Current H-10 150 mA
(Dynamic)
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT
= 0.5 V
has been chosen to avoid test problems caused by tester ground degradation.
Commercial Supply Current
VIN = 0 V, Outputs Open (IOUT = 0 mA)
VCC = Max, f = 15 MHz
AMD
2–315PALCE26V12H-7/10 (Com’l), H-10 (Ind)
CAPACITANCE (Note 1)
Parameter
Symbol Parameter Description Test Conditions Typ Unit
CIN Input Capacitance VIN = 0 V VCC = 5.0 V 5
COUT Output Capacitance VOUT = 0 V f = 1 MHz 8
TA = +25°CpF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges
(Note 2)
Parameter
Symbol Parameter Description Min Max Min Max Unit
tPD Input or Feedback to Combinatorial Output 7.5 10 ns
tS1 Setup Time from Input or Feedback 3.5 5 ns
tS2 Setup Time from SP to Clock 4.5 5 ns
tHHold Time 0 0 ns
tCO Clock to Output 6 9 ns
tAR Asynchronous Reset to Registered Output 11 13 ns
tARW Asynchronous Reset Width 6 8 ns
tARR Asynchronous Reset Recovery Time 5 8 ns
tSPR Synchronous Preset Recovery Time 5 8 ns
tWL LOW 3.5 4 ns
tWH HIGH 3.5 4 ns
fMAX External Feedback 1/(tS + tCO) 105.3 71.4 MHz
Internal Feedback (fCNT) 1/(tS + tCF) 125 105 MHz
tEA Input to Output Enable Using Product Term Control 8 10 ns
tER Input to Output Disable Using Product Term Control 7.5 10 ns
Maximum
Frequency
(Notes 3 and 4)
-7
Clock Width
Notes:
2. See Switching Test Circuit for test conditions.
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.
4. t
CF
is a calculated value and is not guaranteed. t
CF
can be found using the following equation:
t
CF
= 1/f
MAX
(internal feedback) – t
S
.
-10
AMD
2–316 PALCE26V12H-15/20 (Com’l, Ind)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature –65°C to +150°C. . . . . . . . . . .
Ambient Temperature with
Power Applied –55°C to +125°C. . . . . . . . . . . . . . . . .
Supply Voltage with
Respect to Ground –0.5 V to +7.0 V. . . . . . . . . . . . .
DC Input Voltage –0.6 V to +7.0 V. . . . . . . . . . . . . . .
DC Output or I/O
Pin Voltage –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . .
Static Discharge Voltage 2001 V. . . . . . . . . . . . . . . . .
Stresses above those listed under Absolute Maximum Rat-
ings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maxi-
mum Ratings for extended periods may affect device reliabil-
ity. Programming conditions may differ.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA)
Operating in Free Air 0°C to +75°C. . . . . . . . . . . . . .
Supply Voltage (VCC)
with Respect to Ground +4.75 V to +5.25 V. . . . . . . .
lndustrial (I) Devices
Ambient Temperature (TA)
Operating in Free Air –40°C to +85°C. . . . . . . . . . . .
Supply Voltage (VCC)
with Respect to Ground +4.5 V to +5.5 V. . . . . . . . . .
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges unless
otherwise specified
Parameter
Symbol Parameter Description Test Conditions Min Max Unit
VOH Output HIGH Voltage IOH = –3.2 mA VIN = VIH or VIL 2.4 V
VCC = Min
VOL Output LOW Voltage IOL = 16 mA VIN = VIH or VIL 0.4 V
VCC = Min
VIH Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V
Voltage for all Inputs (Note 1)
VIL Input LOW Voltage Guaranteed Input Logical LOW 0.8 V
Voltage for all Inputs (Note 1)
IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA
IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) –10 µA
IOZH Off-State Output Leakage VOUT = 5.25 V, VCC = Max 10 µA
Current HIGH VIN = VIH or VIL (Note 2)
IOZL Off-State Output Leakage VOUT = 0 V, VCC = Max –10 µA
Current LOW VIN = VIH or VIL (Note 2)
ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –30 –160 mA
ICC Commerical Supply Current VIN = 0 V, Outputs Open (IOUT = 0 mA) H-15/20 105 mA
(Static) VCC = Max, f = 0 MHz
ICC VIN = 0 V, Outputs Open (IOUT = 0 mA) H-15 150 mA
(Dynamic) VCC = Max, f = 15 MHz
ICC VIN = 0 V, Outputs Open (IOUT = 0 mA) H-20 130 mA
(Static) VCC = Max
ICC VIN = 0 V, Outputs Open (IOUT = 0 mA) H-20 150 mA
(Dynamic) VCC = Max, f = 15 MHz
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT
= 0.5 V
has been chosen to avoid test problems caused by tester ground degradation.
Industrial Supply Current
AMD
2–317PALCE26V12H-15/20 (Com’l, Ind)
CAPACITANCE (Note 1)
Parameter
Symbol Parameter Description Test Conditions Typ Unit
CIN Input Capacitance VIN = 0 V VCC = 5.0 V 5
TA = +25°C
COUT Output Capacitance VOUT = 0 V f = 1 MHz 8 pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges
(Note 2)
Parameter
Symbol Parameter Description Min Max Min Max Unit
tPD Input or Feedback to Combinatorial Output 15 20 ns
tSSetup Time from Input, Feedback, or SP to Clock 10 13 ns
tHHold Time 0 0 ns
tCO Clock to Output 10 12 ns
tAR Asynchronous Reset to Registered Output 20 25 ns
tARW Asynchronous Reset Width 15 20 ns
tARR Asynchronous Reset Recovery Time 15 20 ns
tSPR Synchronous Preset Recovery Time 10 13 ns
tWL LOW 8 10 ns
tWH HIGH 8 10 ns
External Feedback 1/(tS + tCO) 50 40 MHz
Internal Feedback (fCNT) 1/(tS + tCF) 58.8 43 MHz
tEA Input to Output Enable Using Product Term Control 15 20 ns
tER Input to Output Disable Using Product Term Control 15 20 ns
Maximum
Frequency
(Notes 3 and 4)
fMAX
-20-15
Clock Width
Notes:
2. See Switching Test Circuit for test conditions.
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.
6. t
CF
is a calculated value and is not guaranteed. t
CF
can be found using the following equation:
t
CF
= 1/f
MAX
(internal feedback) – t
S
.
AMD
2–318 PALCE26V12 Family
SWITCHING WAVEFORMS
Notes:
1. VT = 1.5 V
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns–5 ns typical.
tPD
Input or
Feedback
Combinatorial
Output
VT
VT
16072E-7
Combinatorial Output
VT
VT
Input
Output
Input to Output Disable/Enable
16072E-8
tER tEA
VT
Input or
Feedback
Registered
Output
Registered Output
16072E-9
tS
tCO
VT
tH
VT
Clock
tWH
Clock
Clock Width
VT
tWL 16072E-10
VOH - 0.5V
VOL + 0.5V
VT
VT
tARW
VT
tAR
Asynchronous Reset 16072E-11
Input Asserting
Asynchronous
Reset
Registered
Outputs
Clock
tARR
VT
tCO
VT
VT
tStHtSPR
Input Asserting
Synchronous
Preset
Clock
Registered
Outputs
Synchronous Preset 16072E-12
AMD
2–319PALCE26V12 Family
KEY TO SWITCHING WAVEFORMS
KS000010-PAL
Must be
Steady
May
Change
from H to L
May
Change
from L to H
Does Not
Apply
Don’t Care,
Any Change
Permitted
Will be
Steady
Will be
Changing
from H to L
Will be
Changing
from L to H
Changing,
State
Unknown
Center
Line is High-
Impedance
“Off” State
WAVEFORM INPUTS OUTPUTS
SWITCHING TEST CIRCUIT
Measured
Specification S1 CLR1 Output Value
tPD, tCO Closed 1.5 V
tEA Z → H: Open 50 pF 1.5 V
Z → L: Closed 300 Ω
tER H →Z: Open 5 pF H →Z: VOH – 0.5 V
L →Z: Closed L →Z: VOL + 0.5 V
16072E-13
CL
Output
R1
R2
S1
Test Point
5 V
Com’l: H-15/20
Ind: H-20
390 Ω
Com’l: H-7/10
Ind: H-10/15
300 Ω
R2
AMD
2–320 PALCE26V12 Family
TYPICAL ICC CHARACTERISTICS FOR THE PALCE26V12H-7/10
VCC = 5.0 V, TA = 25°C
16072E-14
150
125
100
75
50
25
00 10 203040 50
ICC (mA)
Frequency (MHz)
The selected “typical” pattern utilized 50% of the device resources. Half of the macrocells were programmed as registered, and the
other half were programmed as combinatorial. Half of the available product terms were used for each macrocell. On any vector,
half of the outputs were switching.
By utilizing 50% of the device, a midpoint is defined for ICC. From this midpoint, a designer may scale the ICC graphs up or down to
estimate the ICC requirements for a particular design.
AMD
2–321PALCE26V12 Family
ENDURANCE CHARACTERISTICS
The PALCE26V12 is manufactured using AMD’s ad-
vanced Electrically Erasable process. This technology
uses an EE cell to replace the fuse link used in bipolar
parts. As a result, the device can be erased and
reprogrammed—a feature which allows 100% testing at
the factory.
Symbol Parameter Test Conditions Min Unit
tDR Min Pattern Data Retention Time Max Storage Temperature 10 Years
Max Operating Temperature 20 Years
N Min Reprogramming Cycles Normal Programming Conditions 100 Cycles
AMD
2–322 PALCE26V12 Family
Bus-Friendly Inputs
The PALCE26V12H-7/10 (Com’l) and H-10/15 (Ind)
inputs and I/O loop back to the input after the second
stage of the input buffer. This configuration reinforces
the state of the input and pulls the voltage away from the
input threshold voltage where noise can cause oscilla-
tions. For an illustration of this configuration, see below.
INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR REV. C VERSION*
Input
Output
Preload
Circuitry
ESD
Protection
Feedback
Input
VCC
VCC
100 kΩ
100 kΩ
VCC
VCC
Device Rev. Letter
PALCE26V12H-7
PALCE26V12H-10
PALCE26V12H-15
*
VCC
16072E-15
C
Topside Marking:
AMD CMOS PLD’s are marked on top of the package in the
following manner:
PALCE xxxx
Datecode (4 numbers) LOT ID (3 characters) – – (Rev. Letter)
The Lot ID and Rev. letter are separated by two spaces.
AMD
2–323PALCE26V12 Family
ROBUSTNESS FEATURES
The PALCE26V12 has some unique features that make
it extremely robust, especially when operating in high
speed design environments. Input clamping circuitry
limits negative overshoot, eliminating the possibility of
false clocking caused by subsequent ringing. A special
noise filter makes the programming circuitry completely
insensitive to any positive overshoot that has a pulse
width of less than about 100 ns.
INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR REV. B VERSION*
16072E-16
Typical Input
Typical Output
Preload
Circuitry
ESD
Protection
and
Clamping
Feedback
Input
VCC
VCC
> 50 kΩ
VCC
Programming
Voltage
Detection
Positive
Overshoot
Filter Programming
Circuitry
VCC
> 50 kΩ
Provides ESD
Protection and
Clamping
Programming
Pins only
Device Rev. Letter
PALCE26V12-15
PALCE26V12-20
Topside Marking:
AMD CMOS PLD’s are marked on top of the package in the
following manner:
PALCE xxxx
Datecode (4 numbers) LOT ID (3 characters) – – (Rev. Letter)
The Lot ID and Rev. letter are separated by two spaces.
B
*
AMD
2–324 PALCE26V12 Family
POWER-UP RESET
The power-up reset feature ensures that all flip-flops will
be reset to LOW after the device has been powered up.
The output state will depend on the programmed
configuration. This feature is valuable in simplifying
state machine initialization. A timing diagram and
parameter table are shown below. Due to the synchro-
nous operation of the power-up reset and the wide
range of ways VCC can rise to its steady state, two
conditions are required to ensure a valid power-up
reset. These conditions are:
The VCC rise must be monotonic.
Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.
Parameter
Symbol Parameter Description Max Unit
tPR Power-Up Reset Time 1000 ns
tSInput or Feedback Setup Time
tWL Clock Width LOW
tPR
tWL
tS
4 V VCC
Power
Registered
Active-Low
Output
Clock
16072E-17
See Switching
Characteristics
Power-Up Reset Waveform
AMD
2–325
PALCE26V12H-15/20
TYPICAL THERMAL CHARACTERISTICS
Measured at 25°C ambient. These parameters are not tested.
PALCE26V12
Parameter
Symbol Parameter Description SKINNYDIP PLCC Unit
θjc Thermal impedance, junction to case 19 18 °C/W
θja Thermal impedance, junction to ambient 65 55 °C/W
θjma Thermal impedance, junction to ambient with air flow 200 lfpm air 59 48 °C/W
400 lfpm air 54 44 °C/W
600 lfpm air 50 39 °C/W
800 lfpm air 50 37 °C/W
Typ
Plastic
θ
jc Considerations
The data listed for plastic
θ
jc are for reference only and are not recommended for use in calculating junction temperatures. The
heat-flow paths in plastic-encapsulated devices are complex, making the
θ
jc measurement relative to a specific location on the
package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of
the package. Furthermore,
θ
jc tests on packages are performed in a constant-temperature bath, keeping the package surface at
a constant temperature. Therefore, the measurements can only be used in a similar environment.
AMD
2–326 PALCE26V12 Family
fMAX Parameters
The parameter fMAX is the maximum clock rate at which
the device is guaranteed to operate. Because the flexi-
bility inherent in programmable logic devices offers a
choice of clocked flip-flop designs, fMAX is specified for
three types of synchronous designs.
The first type of design is a state machine with feedback
signals sent off-chip. This external feedback could go
back to the device inputs, or to a second device in a
multi-chip state machine. The slowest path defining the
period is the sum of the clock-to-output time and the in-
put setup time for the external signals (tS + tCO). The re-
ciprocal, fMAX, is the maximum frequency with external
feedback or in conjunction with an equivalent speed de-
vice. This fMAX is designated “fMAX external.”
The second type of design is a single-chip state ma-
chine with internal feedback only. In this case, flip-flop
inputs are defined by the device inputs and flip-flop out-
puts. Under these conditions, the period is limited by the
internal delay from the flip-flop outputs through the inter-
nal feedback and logic to the flip-flop inputs. This fMAX is
designated “fMAX internal”. A simple internal counter is a
good example of this type of design, therefore, this pa-
rameter is sometimes called “fCNT.”
The third type of design is a simple data path applica-
tion. In this case, input data is presented to the flip-flop
and clocked through; no feedback is employed. Under
these conditions, the period is limited by the sum of the
data setup time and the data hold time (tS + tH). How-
ever, a lower limit for the period of each fMAX type is the
minimum clock period (tWH + tWL). Usually, this minimum
clock period determines the period for the third fMAX,
designated “fMAX no feedback.”
fMAX external and fMAX no feedback are calculated pa-
rameters. fMAX external is calculated from tS and tCO, and
fMAX no feedback is calculated from tWL and tWH. fMAX in-
ternal is measured.
LOGIC REGISTER
tt
CLK
(SECOND
CHIP)
SCO
t
S
f
MAX External; 1/(tS + tCO)
LOGIC REGISTER
CLK
LOGIC REGISTER
t
CLK
S
fMAX No Feedback; 1/(tS + tH) or 1/(tWH + tWL)fMAX Internal (fCNT)
16072E-18
