General Description
The MAX7321 2-wire serial-interfaced peripheral features
eight open-drain I/O ports with selectable internal pullups
and transition detection. Any port may be used as a logic
input or an open-drain output. Ports are overvoltage pro-
tected to +6V independent of supply voltage.
All I/O ports configured as inputs are continuously mon-
itored for state changes (transition detection). State
changes are indicated by the open-drain, +6V tolerant
INT output. The interrupt is latched, allowing detection
of transient changes. When the MAX7321 is subse-
quently accessed through the serial interface, any
pending interrupt is cleared.
The open-drain outputs are rated to sink 20mA and are
capable of driving LEDs.
The +6V tolerant RST input clears the serial interface,
terminating any I2C* communication to or from the
MAX7321.
The MAX7321 uses two address inputs with four-level
logic to allow 16 I2C slave addresses. The slave
address also determines the power-up logic level for
the I/O ports, and enables or disables internal 40kΩ
pullups in groups of four ports.
The MAX7321 supports hot insertion. All eight I/O ports,
the serial interface SDA, SCL, AD0, AD2, INT, and RST
remain high impedance in power-down (V+ = 0) with
up to +6V asserted on them.
The MAX7321 is one device in a family of pin-compatible
port expanders with a choice of input ports, open-drain
I/O ports, and push-pull output ports (see Table 1).
The MAX7321 is available in 16-pin QSOP and 16-pin
TQFN packages, and is specified over the automotive
temperature range (-40°C to +125°C).
Features
♦400kHz, +6V Tolerant I2C Serial Interface
♦+1.71V to +5.5V Operating Voltage
♦8 Open-Drain I/O Ports Rated to 20mA Sink Current
♦I/O Ports Are Overvoltage Protected to +6V
♦Any Port Can Be a Logic Input or an Open-Drain
Output
♦Selectable I/O Port Power-Up Default Logic Levels
♦Transient Changes Are Latched, Allowing Detection
Between Read Operations
♦INT Output Alerts Change on Inputs
♦AD0 and AD2 Inputs Select from 16 Slave
Addresses
♦Low 0.6µA (typ), 1.5µA (max) Standby Current
♦-40°C to +125°C Operating Temperature
MAX7321
I2C Port Expander with 8 Open-Drain I/Os
________________________________________________________________ Maxim Integrated Products 1
19-3738; Rev 0; 7/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Ordering Information
PART TEMP
RANGE
PIN-
PACKAGE
TOP
MARK
PKG
CODE
MAX7321AEE
-40°C to
+125°C
16 QSOP —
E16-4
MAX7321ATE
-40°C to
+125°C
16 TQFN
3mm x 3mm
x 0.8mm
ADC
T1633-4
MAX7321ASE*
-40°C to
+125°C
16 SO — —
MAX7321AUP*
-40°C to
+125°C
20 TSSOP — —
MAX7321AAP*
-40°C to
+125°C
20 SSOP — —
*Purchase of I2C components from Maxim Integrated Products,
Inc., or one of its sublicensed Associated Companies, conveys
a license under the Philips I2C Patent Rights to use these com-
ponents in an I2C system, provided that the system conforms
to the I2C Standard Specification as defined by Philips.
Pin Configurations, Typical Application Circuit, and
Functional Diagram appear at end of data sheet.
Selector Guide
PART
INPUTS
INTERRUPT
MASK
OPEN-
DRAIN
OUTPUTS
PUSH-PULL
OUTPUTS
MAX7319
8Yes — —
MAX7320
—— — 8
MAX7321
Up to 8
—
Up to 8
—
MAX7322
4Yes — 4
MAX7323
Up to 4
—
Up to 4
4
MAX7328
Up to 8
—
Up to 8
—
MAX7329
Up to 8
—
Up to 8
—
*Future product—contact factory for availability.
Cell Phones
SAN/NAS
Servers
Notebooks
Satellite Radio
Automotive
Applications
MAX7321
I2C Port Expander with 8 Open-Drain I/Os
2_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
All Voltages Referenced to GND
Supply Voltage V+....................................................-0.3V to +6V
SCL, SDA, AD0, AD2, RST, INT, P0–P7 ...................-0.3V to +6V
P0–P7 Sink Current ............................................................ 25mA
SDA Sink Current ............................................................... 10mA
INT Sink Current..................................................................10mA
Total V+ Current..................................................................50mA
Total GND Current ...........................................................100mA
Continuous Power Dissipation (TA= +70°C)
16-Pin QSOP (derate 8.3mW/°C above +70°C)...........667mW
16-Pin TQFN (derate 15.6mW/°C above +70°C) .......1250mW
Operating Temperature Range .........................-40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
ELECTRICAL CHARACTERISTICS
(V+ = +1.71V to +5.5V, TA= -40°C to +125°C, unless otherwise noted. Typical values are at V+ = +3.3V, TA= +25°C.) (Note 1)
SYMBOL
MIN
TYP
MAX
UNITS
SCL and SDA and other digital inputs at V+ 0.6
23
0.8 x V+
SDA, SCL, AD0, AD2, RST, P0–P7
0.7 x V+
0.2 x V+
SDA, SCL, AD0, AD2, RST, P0–P7
0.3 x V+
SDA, SCL, AD0, AD2, RST, P0–P7
+0.2
SDA, SCL, AD0, AD2, RST, P0–P7
10
90
110
130
140
VOLSDA
VOLINT
130
40
MAX7321
I2C Port Expander with 8 Open-Drain I/Os
_______________________________________________________________________________________ 3
PORT AND INTERRUPT INT TIMING CHARACTERISTICS
(V+ = +1.71V to +5.5V, TA= -40°C to +125°C, unless otherwise noted. Typical values are at V+ = +3.3V, TA= +25°C.) (Note 1)
SYMBOL
MIN TYP MAX
UNITS
INT Reset Delay Time from STOP
TIMING CHARACTERISTICS
(V+ = +1.71V to +5.5V, TA= -40°C to +125°C, unless otherwise noted. Typical values are at V+ = +3.3V, TA= +25°C.) (Note 1)
SYMBOL
TYP MAX
UNITS
tHD
,
STA
tSU
,
STA
tSU
,
STO
tHD
,
DAT
tSU
,
DAT
0.1Cb
0.1Cb
0.1Cb
Pulse Width of Spike Suppressed
50
Note 1: All parameters tested at TA= +25°C. Specifications over temperature are guaranteed by design.
Note 2: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
Note 3: Guaranteed by design.
Note 4: Cb= total capacitance of one bus line in pF. tRand tFmeasured between 0.3 x V+ and 0.7 x V+. ISINK ≤6mA.
Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
MAX7321
I2C Port Expander with 8 Open-Drain I/Os
4_______________________________________________________________________________________
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
0
0.4
0.2
1.0
0.8
0.6
1.2
1.4
1.8
1.6
2.0
-40 -10 5-25 20 35 50 65 80 95 110 125
STANDBY CURRENT vs. TEMPERATURE
MAX7321 toc01
TEMPERATURE (°C)
STANDBY CURRENT (µA)
V+ = +3.3V
V+ = +2.5V
V+ = +5.0V
V+ = +1.71V
fSCL = 0kHz
0
20
10
40
30
50
60
-40 -10 5 20-25 35 50 65 80 95 110 125
SUPPLY CURRENT vs. TEMPERATURE
MAX7321 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
V+ = +3.3V
V+ = +5.0V
V+ = +1.71V
V+ = +2.5V
fSCL = 400kHz
OUTPUT VOLTAGE LOW
vs. TEMPERATURE
TEMPERATURE (°C)
OUTPUT VOLTAGE LOW (V)
MAX7321 toc03
-40 -25 -10 5 20 35 50 65 80 95 110 125
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
V+ = +5.0V
ISINK = 20mA
V+ = +2.5V
ISINK = 10mA
V+ = +1.71V
ISINK = 5mA
V+ = +3.3V
ISINK = 15mA
Pin Description
QSOP
TSSOP/
SSOP
NAME
4–7, 9–12
2–5, 7–10
19, 20
P0–P7
GND
SDA
N.C.
Detailed Description
MAX7319–MAX7329 Family Comparison
The MAX7319–MAX7323 family consists of five pin-
compatible, eight-port expanders. Each version is opti-
mized for different applications. The MAX7328 and
MAX7329 are second sources to the PCF8574 and
PCF8574A.
The MAX7324–MAX7327 family consists of four pin-
compatible, 16-port expanders that integrate the func-
tions of the MAX7320 and one of either the MAX7319,
MAX7321, MAX7322, or MAX7323.
Functional Overview
The MAX7321 is a general-purpose port expander
operating from a +1.71V to +5.5V supply that provides
eight open-drain I/O ports. Each open-drain output is
rated to sink 20mA, and the entire device is rated to
sink 100mA into all ports combined. The outputs drive
loads connected to supplies up to +6V, independent of
the MAX7321’s supply voltage.
The MAX7321 is set to one of 16 I2C slave addresses
(0x60 to 0x6F) using the address select inputs AD0 and
AD2, and is accessed over an I2C serial interface up to
400kHz. The RST input clears the serial interface in
MAX7321
I2C Port Expander with 8 Open-Drain I/Os
_______________________________________________________________________________________ 5
PART
ADDRESS
INPUTS
OUTPUTS
OUTPUTS
MAX7319 110xxxx
MAX7320 101xxxx
MAX7321 110xxxx Up to 8
MAX7322 110xxxx
Table 1. MAX7321–MAX7329 Family Comparison
MAX7321
case of a hung bus, terminating any serial transaction
to or from the MAX7321.
Any port can be configured as a logic input by setting
the port output logic high (logic high for an open-drain
output is high impedance). When the MAX7321 is read
through the serial interface, the actual logic levels at
the ports are read back.
The open-drain ports offer latching transition detection
when used as inputs. All input ports are continuously
monitored for changes. An input change sets 1 of 8 flag
bits that identify changed input(s). All flags are cleared
upon a subsequent read or write transaction to the
MAX7321.
A latching interrupt output, INT, is programmed to flag
logic changes on ports used as inputs. Data changes
on any input port forces INT to a logic low. Changing
the I/O port level through the serial interface does not
cause an interrupt. The interrupt output INT is cleared
when the MAX7321 is next accessed through the serial
interface.
Internal pullup resistors to V+ are selected by the
address select inputs, AD0 and AD2. Pullups are
enabled on the input ports in groups of four (see Table 3).
Use the slave address selection to ensure that I/O ports
used as inputs are high on power-up. To simplify I/O
port and slave address configuration, I/O ports with
internal pullups enabled also default with their open-
drain outputs logic high (high impedance). I/O ports
with internal pullups disabled default with open-drain
outputs logic low. Output port power-up logic levels are
selected by the address select inputs AD0 and AD2.
Ports default to logic high or logic low on power-up in
groups of four (see Table 3).
Initial Power-Up
On power-up, the transition detection logic is reset, and
INT is released to a high-impedance state. The transi-
tion flags are cleared to indicate no data changes. The
power-up default states of the eight I/O ports are set
according to the I2C slave address selection inputs,
AD0 and AD2 (Table 3). For I/O ports used as inputs,
ensure that the default states are logic high so that
the I/O ports power up in the high-impedance state.
All I/O ports configured with pullups enabled also
have a logic-high power-up state.
RST Input
The RST input voids any I2C transaction involving the
MAX7321, forcing the MAX7321 into the I2C STOP con-
dition. A reset does not affect the interrupt output (INT)
or change the contents of the interrupt mask register.
RST is overvoltage tolerant to +6V.
I2C Port Expander with 8 Open-Drain I/Os
6_______________________________________________________________________________________
PART
ADDRESS
INPUTS
OUTPUTS
OUTPUTS
MAX7323
110xxxx Up to 4
MAX7328
MAX7329
0100xxx
0111xxx Up to 8
MAX7324
Software equivalent to a MAX7320 plus a MAX7321.
MAX7325
Up to 8
Software equivalent to a MAX7320 plus a MAX7319.
MAX7326
Software equivalent to a MAX7320 plus a MAX7322.
MAX7327
101xxxx
110xxxx
Up to 4
Software equivalent to a MAX7320 plus a MAX7323.
Table 1. MAX7321–MAX7329 Family Comparison (continued)
Standby Mode
When the serial interface is idle, the MAX7321 automat-
ically enters standby mode, drawing minimal supply
current.
Slave Address, Power-Up Default Logic
Levels, and Input Pullup Selection
Address inputs AD0 and AD2 determine the MAX7321
slave address, set the power-up I/O state for the ports,
and select which inputs have pullup resistors. Internal
pullups and power-up default states are set in groups
of four (Table 3). The MAX7319, MAX7321, MAX7322,
and MAX7323 use a different range of slave addresses
(110xxxx) than the MAX7320 (101xxxx) (Table 2).
The MAX7321 slave address is determined on each I2C
transmission, regardless of whether the transmission is
actually addressing the MAX7321. The MAX7321 distin-
guishes whether address inputs AD2 and AD0 are con-
nected to SDA or SCL instead of fixed logic levels V+ or
GND during this transmission. This means that the
MAX7321 slave address can be configured dynamical-
ly in the application without cycling the device supply.
On initial power-up, the MAX7321 cannot decode
address inputs AD0 and AD2 fully until the first I2C
transmission, and AD0 and AD2 initially appear to be
connected to V+ or GND. This is important because the
address selection is used to determine the power-up
logic level (output low or input/output high), and
whether pullups are applied. However, at power-up, the
I2C SDA and SCL bus interface lines are high imped-
ance at the pins of every device (master or slave) con-
nected to the bus, including the MAX7321. This is
guaranteed as part of the I2C specification. Therefore,
address inputs AD2 and AD0 that are connected to
SDA or SCL normally appear at power-up to be con-
nected to V+. The power-up logic uses AD0 to select
the power-up state and whether pullups are enabled for
ports P3–P0, and AD2 for ports P7–P4. The rule is that
a logic high, SDA, or SCL connection selects the
pullups (and sets the default port condition to input or
logic-high output), while a logic low deselects the
pullups (and sets the default port condition to logic-low
output) (Table 3). The port configuration is correct on
power-up for a standard I2C configuration, where SDA
or SCL are pulled up to V+ by the external I2C pullup
resistors.
There are circumstances where the assumption that
SDA = SCL = V+ on power-up is not true—for example,
in true hot-swap applications in which there is legiti-
MAX7321
I2C Port Expander with 8 Open-Drain I/Os
_______________________________________________________________________________________ 7
I2C SLAVE
ADDRESS INPUTS
OUTPUTS
OUTPUTS
I2C DATA WRITE
MAX7319
110xxxx
MAX7320
101xxxx
MAX7321
110xxxx Up to 8
MAX7322
110xxxx
MAX7323
110xxxx Up to 4
MAX7328
0100xxx Up to 8
MAX7329
0111xxx Up to 8
Table 2. Read and Write Access to Eight-Port Expander Family
MAX7321
mate bus activity during power-up. Also, if SDA and
SCL are terminated with pullup resistors to a different
supply voltage than the MAX7321’s supply voltage, and
if that pullup supply rises later than the MAX7321’s sup-
ply, then SDA or SCL may appear at power-up to be
connected to GND. In such applications, use the four
address combinations that are selected by connecting
address inputs AD2 and AD0 to V+ or GND (shown in
bold in Table 3). These selections are guaranteed to be
correct at power-up, independent of SDA and SCL
behavior. If one of the other 12 address combinations is
used, be aware that an unexpected combination of
pullups might be asserted until the first I2C transmis-
sion (to any device, not necessarily the MAX7321) is
put on the bus, and an unexpected combination of
ports may initialize as logic-low outputs instead of
inputs or logic-high outputs.
Port Inputs
I/O port inputs switch at the CMOS-logic levels as
determined by the expander’s supply voltage, and are
overvoltage tolerant to +6V, independent of the
expander’s supply voltage.
I/O Port Input Transition Detection
All I/O ports configured as inputs are monitored for
changes since the expander was last accessed
through the serial interface. The state of the input ports
is stored in an internal “snapshot” register for transition
monitoring. The snapshot is continuously compared
with the actual input conditions, and if a change is
detected for any port, INT signals a state change by
going logic low. An internal transition flag is set for that
port. The input is sampled (internally latched into the
snapshot register) and the old transition flags cleared
during the I2C acknowledge of every MAX7321 read
and write access. The previous port transition flags are
read through the serial interface as the second byte of
a 2-byte read sequence.
I2C Port Expander with 8 Open-Drain I/Os
8_______________________________________________________________________________________
CONNECTION
40kΩ INPUT PULLUPS ENABLED
AD2
AD0 A6 A5 A4 A3 A2 A1 A0 P7 P6 P5 P4 P3 P2 P1 P0 P7 P6 P5 P4 P3 P2 P1
P0
SCL
GND 1 100000 1 1 1 10 0 0 0YYYY———
—
SCL
1100001 1 1 1 11 1 1 1YYYYYYY
Y
SCL
SCL 1 100010 1 1 1 11 1 1 1YYYYYYY
Y
SCL
SDA 1 100011 1 1 1 11 1 1 1YYYYYYY
Y
SDA
GND 1 100100 1 1 1 10 0 0 0YYYY———
—
SDA
1100101 1 1 1 11 1 1 1YYYYYYY
Y
SDA
SCL 1 100110 1 1 1 11 1 1 1YYYYYYY
Y
SDA
SDA 1 100111 1 1 1 11 1 1 1YYYYYYY
Y
GND
GND 1101000 0 0000000———————
—
GND
110100100001111————YYY
Y
GND
SCL 1 101010 0 0 0 01 1 1 1————YYY
Y
GND
SDA 1 101011 0 0 0 01 1 1 1————YYY
Y
V+
GND 110110011110000YYYY———
—
V+
110110111111111YYYYYYY
Y
V+
SCL 1 101110 1 1 1 11 1 1 1YYYYYYY
Y
V+
SDA 1 101111 1 1 1 11 1 1 1YYYYYYY
Y
Table 3. MAX7321 Address Map
Serial Interface
Serial Addressing
The MAX7321 operates as a slave that sends and
receives data through an I2C interface. The interface
uses a serial data line (SDA) and a serial clock line (SCL)
to achieve bidirectional communication between mas-
ter(s) and slave(s). The master initiates all data transfers
to and from the MAX7321 and generates the SCL clock
that synchronizes the data transfer (Figure 1).
SDA operates as both an input and an open-drain out-
put. A pullup resistor, typically 4.7kΩ, is required on
SDA. SCL operates only as an input. A pullup resistor,
typically 4.7kΩ, is required on SCL if there are multiple
masters on the 2-wire interface, or if the master in a sin-
gle-master system has an open-drain SCL output.
Each transmission consists of a START condition sent
by a master, followed by the MAX7321’s 7-bit slave
address plus R/Wbit, and then optionally 1 or more
data bytes, and finally a STOP condition (Figure 2).
START and STOP Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, the master
issues a STOP (P) condition by transitioning SDA from
low to high while SCL is high. The bus is then free for
another transmission (Figure 2).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 3).
Acknowledge
The acknowledge bit is a clocked 9th bit the recipient
uses to handshake receipt of each byte of data (Figure
4). Each byte transferred effectively requires 9 bits. The
master generates the 9th clock pulse, and the recipient
pulls down SDA during the acknowledge clock pulse,
such that the SDA line is stable low during the high
period of the clock pulse. When the master is transmit-
ting to the MAX7321, the MAX7321 generates the
acknowledge bit because the device is the recipient.
When the MAX7321 is transmitting to the master, the
master generates the acknowledge bit because the
master is the recipient.
Slave Address
The MAX7321 has a 7-bit-long slave address (Figure
5). The eighth bit following the 7-bit slave address is
the R/Wbit. It is low for a write command, and high for
a read command.
The first (A6), second (A5), and third (A4) bits of the
MAX7321 slave address are always 1, 1, and 0.
Connect AD2 and AD0 to GND, V+,SDA, or SCL to
select slave address bits A3, A2, A1, and A0. The
MAX7321 has 16 possible slave addresses (Table 3),
allowing up to 16 MAX7321 devices on an I2C bus.
MAX7321
I2C Port Expander with 8 Open-Drain I/Os
_______________________________________________________________________________________ 9
SCL
SDA
tRtF
tBUF
START
CONDITION
STOP
CONDITION
REPEATED START CONDITION
START CONDITION
tSU,STO
tHD,STA
tSU,STA
tHD,DAT
tSU,DAT
tLOW
tHIGH
tHD,STA
Figure 1. 2-Wire Serial Interface Timing Details
SDA
SCL
START
CONDITION
STOP
CONDITION
SP
Figure 2. START and STOP Conditions
MAX7321
Accessing the MAX7321
I2C interface access to the MAX7321 is summarized as
follows (Table 2).
A single-byte read from the MAX7321 returns the sta-
tus of the eight I/O ports, and clears both the internal
transition flags and the INT output when the master
acknowledges the slave address byte.
A 2-byte read returns first the status of the eight I/O
ports (as for a single-byte read), followed by the transi-
tion flags. Again, the internal transition flags and the
INT output are cleared automatically when the master
acknowledges the slave address byte (but the previous
transition flag data is sent as the second byte).
A multibyte (more than 2 bytes before the I2C STOP
bit) read repeatedly returns the port data, followed by
the transition flags. As the port data is resampled for
each transmission, and the transition flags are reset
each time, a multibyte read continuously returns the
current data and identifies any changing input ports.
If a port input data change occurs during the read
sequence, then INT is reasserted during the I2C STOP
bit. The MAX7321 does not generate another interrupt
during a single-byte or multibyte read.
Input port data is sampled during the preceding I2C
acknowledge bit (the acknowledge bit for the I2C slave
address in the case of a single-byte or 2-byte read).
A single-byte write to the MAX7321 sets the logic state
of all eight I/O ports.
A multibyte write to the MAX7321 repeatedly sets the
logic state of all eight I/O ports.
Reading the MAX7321
A read from the MAX7321 starts with the master trans-
mitting the MAX7321’s slave address with the R/Wbit
set high. The MAX7321 acknowledges the slave
address, and samples the input ports (takes a snap-
shot) during the acknowledge bit. INT goes high (high
impedance if an external pullup resistor is not fitted)
during the slave address acknowledge. The master can
then issue a STOP condition after the acknowledge
(Figure 6). The snapshot is not taken, and INT status
remains unchanged if the master terminates the serial
transaction with a no acknowledge.
Typically, the master reads 1 or 2 bytes from the
MAX7321, each byte being acknowledged by the mas-
ter upon reception.
The master can read 1 byte from the MAX7321 and
then issue a STOP condition (Figure 7). In this case, the
MAX7321 transmits the current port data, clears the
change flags, and resets the transition detection. INT
goes high (high impedance if an external pullup resis-
tor is not fitted) during the slave address acknowledge.
The new snapshot data is the current port data trans-
mitted to the master; therefore, port changes ocurring
during the transmission are detected. INT remains high
until the STOP condition.
The master can read 2 bytes from the MAX7321 and
then issue a STOP condition (Figure 8). In this case, the
MAX7321 transmits the current port data, followed by
the change flags. The change flags are then cleared,
and transition detection resets. INT goes high (high
impedance if an external pullup resistor is not fitted)
during the slave address acknowledge. The new snap-
shot data is the current port data transmitted to the
master; therefore, port changes occurring during the
transmission are detected. INT remains high until the
STOP condition.
I2C Port Expander with 8 Open-Drain I/Os
10 ______________________________________________________________________________________
SDA
SCL
DATA LINE STABLE;
DATA VALID
CHANGE OF DATA
ALLOWED
Figure 3. Bit Transfer
SCL
SDA BY
TRANSMITTER
CLOCK PULSE
FOR ACKNOWLEDGMENT
START
CONDITION
SDA BY
RECEIVER
12 89
S
Figure 4. Acknowledge
MAX7321
I2C Port Expander with 8 Open-Drain I/Os
______________________________________________________________________________________ 11
SDA
SCL
.
11 A3 A2 A1 A0
0R/W
MSB LSB
ACK
Figure 5. Slave Address
SCL
MAX7321 SLAVE ADDRESS
SA
P
1
PORT I/O
INT OUTPUT
R/W
ACKNOWLEDGE FROM MAX7321
PORT SNAPSHOT
tIV
tPH
tIR
tIV
Figure 6. Reading the MAX7321 (No Data)
SCL
MAX7321 SLAVE ADDRESS
SA P
1
PORT I/O
INT OUTPUT
R/W
ACKNOWLEDGE FROM MAX7321
PORT SNAPSHOT
tIV
tPH
tIR
A
P6 P0
PI1
P2P3P4P5P7
D0D1D2D3D4D5D6
DATA DATA
DATA
D7
PORT SNAPSHOT
tPS tIP
INT REMAINS HIGH UNTIL STOP CONDITION
PORT I/O
Figure 7. Reading the MAX7321 (1 Data Byte)
MAX7321
Writing the MAX7321
A write to the MAX7321 starts with the master transmit-
ting the MAX7321’s slave address with the R/Wbit set
low. The MAX7321 acknowledges the slave address,
and samples the ports (takes a snapshot) during
acknowledge. INT goes high (high impedance if an
external pullup resistor is not fitted) during the slave
address acknowledge. The master can then issue a
STOP condition after the acknowledge (Figure 6), but
typically the master proceeds to transmit 1 or more
bytes of data. The MAX7321 acknowledges these sub-
sequent bytes of data and updates the I/O ports with
each new byte until the master issues a STOP condition
(Figure 9).
Applications Information
Port Input and I2C Interface Level
Translation from Higher or Lower
Logic Voltages
The MAX7321’s I2C interface (SDA, SCL, AD0, AD2),
reset input RST, interrupt output INT, and the eight I/O
ports P0–P7 are overvoltage protected to +6V indepen-
dent of V+. This allows the MAX7321 to operate from a
lower supply voltage, such as +3.3V, while the I2C inter-
face and/or any of the eight I/O ports are driven as inputs
driven from a higher logic level, such as +5V.
The MAX7321 can operate from a higher supply volt-
age, such as +3V, while the I2C interface and/or some
of the I/O ports P0–P7 are driven from a lower logic
level, such as +2.5V. Apply a minimum voltage of 0.7 x
I2C Port Expander with 8 Open-Drain I/Os
12 ______________________________________________________________________________________
SCL
MAX7321 SLAVE ADDRESSSA P1
PORT INPUT DATA 1 DATA 2 DATA 3
DATA 1 DATA 1 TRANSITION
DATA 4
INT OUTPUT
R/W
ACKNOWLEDGE FROM MAX7321
PORT SNAPSHOT
tIV
tPH
tIR
A
P0
P1
P2P3P4P5
P6
P7
D0D1D2D3D4D5D6D7
PORT SNAPSHOT
tPS tIP
F0
F1
F2F3F4F5
F6
F7
D7 D6 D5 D4 D3 D2 D1 D0 A
PORT SNAPSHOT
INT REMAINS HIGH UNTIL STOP CONDITION
PORT I/O INTERRUPT FLAGS
Figure 8. Reading the MAX7321 (2 Data Bytes)
SCL
SDA
START CONDITION R/WACKNOWLEDGE
FROM SLAVE
SLAVE ADDRESS
S0
12345678
AAA
tPV
DATA 1 DATA 2
DATA 2 VALIDDATA 1 VALID
WRITE
TO PORT
DATA OUT
FROM PORT
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
tPV
DATA TO PORT DATA TO PORT
Figure 9. Writing the MAX7321
V+ to assert a logic high on any I/O port. For example,
a MAX7321 operating from a +5V supply may not rec-
ognize a +3.3V nominal logic high. One solution for
input-level translation is to drive MAX7321 I/Os from
open-drain outputs. Use a pullup resistor to V+ or a
higher supply to ensure a high logic voltage of greater
than 0.7 x V+.
Port-Output Port-Level Translation
The open-drain output architecture allows for level
translation to higher or lower voltages than the
MAX7321’s supply. Use an external pullup resistor on
any output to convert the high-impedance logic-high
condition to a positive voltage level. The resistor can be
connected to any voltage up to +6V, and the resistor
value chosen to ensure no more than 20mA is sunk in
the logic-low condition. For interfacing CMOS inputs, a
pullup resistor value of 220kΩis a good starting point.
Use a lower resistance to improve noise immunity, in
applications where power consumption is less critical,
or where a faster rise time is needed for a given capac-
itive load.
Hot Insertion
RST, SCL, SDA, AD0, and AD2 and the P0–P7 I/Os
remain high impedance with up to +6V asserted on
them when the MAX7321 is powered down (V+ = 0).
The MAX7321 can therefore be used in hot-swap appli-
cations.
Each of the I/O P0–P7 has a protection diode to GND
(Figure 10). When a port is driven to a voltage lower
than GND, the protection diode clamps the voltage to a
diode drop below GND.
MAX7321
I2C Port Expander with 8 Open-Drain I/Os
______________________________________________________________________________________ 13
D
S
G
S
D
G
PORT
PULLUP
ENABLE
INPUT
OUTPUT
40kΩ
MAX7321
V+ V+
Figure 10. MAX7321 Input Port Structure
I2C
CONTROL P0
P3
P2
P1
P4
P5
P6
P7
INT
I/O
PORTS
GND
POWER-
ON RESET
INPUT
FILTER
V+
RST
SDA
SCL
AD2
AD0
MAX7321
Functional Diagram
MAX7321
Each of the I/O ports P0–P7 also has a 40kΩ(typ)
pullup resistor that can be enabled or disabled. When a
port driven to a voltage higher than V+,the body diode of
the pullup enable switch conducts and the 40kΩpullup
resistor is enabled. When the MAX7321 is powered down
(V+ = 0), each I/O port appears as a 40kΩresistor in
series with a diode connected to zero. I/O ports are pro-
tected to +6V under any of these circumstances (Figure
10).
Driving LED Loads
When driving LEDs, a resistor must be fitted in series
with the LED to limit the LED current to no more than
20mA. Connect the LED cathode to the MAX7321 port,
and the LED anode to V+ through the series current-
limiting resistor, RLED. Set the port output low to illumi-
nate the LED. Choose the resistor value according to
the following formula:
RLED = (VSUPPLY - VLED - VOL) / ILED
where:
RLED is the resistance of the resistor in series with the
LED (Ω).
VSUPPLY is the supply voltage used to drive the LED (V).
VLED is the forward voltage of the LED (V).
VOL is the output-low voltage of the MAX7321 when
sinking ILED (V).
ILED is the desired operating current of the LED (A).
For example, to operate a 2.2V red LED at 10mA from a
+5V supply:
RLED = (5 - 2.2 - 0.07) / 0.010 = 270Ω
Driving Load Currents Higher than 20mA
The MAX7321 can be used to drive loads, such as relays,
that draw more than 20mA by paralleling outputs. Use at
least one output per 20mA of load current; for example, a
5V, 330mW relay draws 66mA and therefore requires four
paralleled outputs. Any combination of outputs can be
used as part of a load-sharing design because any com-
bination of ports can be set or cleared at the same time
by writing the MAX7321. Do not exceed a total sink cur-
rent of 100mA for the device.
The MAX7321 must be protected from the negative volt-
age transient generated when switching off inductive
loads (such as relays), by connecting a reverse-biased
diode across the inductive load. Choose the peak current
for the diode to be greater than the inductive load’s oper-
ating current.
Power-Supply Considerations
The MAX7321 operates with a supply voltage of +1.71V
to +5.5V over the -40°C to +125°C temperature range.
Bypass the supply to GND with a ceramic capacitor of at
least 0.047µF as close to the device as possible. For the
TQFN version, additionally connect the exposed pad to
GND.
Compatibility with MAX6965, MAX7315, and
MAX7316
The MAX7321 is subset pin compatible with the
MAX6965, MAX7315, and MAX7316. The pin differences
are shown in Table 4. The MAX7321 is not software com-
patible with the MAX6965, MAX7315, or MAX7316. In
many cases, it is possible to design a PC board to work
with all these port expanders, providing design flexibility.
I2C Port Expander with 8 Open-Drain I/Os
14 ______________________________________________________________________________________
PIN-PACKAGE
PIN FUNCTION
16
QSOP
16
TQFN MAX7321 MAX7315
MAX6965 AND
MAX7316
115AD0 AD0 BLINK
216RST AD1 RST
31AD2 AD2 AD0
Table 4. MAX7321, MAX6965, MAX7315,
and MAX7316 Pin Compatibility
MAX7321
P2
P7
P6
P5
P4
V+
+3.3V +5V
µC
SCL
SDA
SCL
AD0
P1
P0
SDA
P3
GND
I/O
I/O
AD2 I/O
I/O
RST RST
INT INT
0.047µF
Typical Application Circuit
MAX7321
I2C Port Expander with 8 Open-Drain I/Os
______________________________________________________________________________________ 15
Pin Configurations
Chip Information
PROCESS: BiCMOS
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
AD0 V+
SDA
SCL
INT
P7
P6
P5
P4
MAX7321
SO/QSOP
RST
AD2
P2
P0
P1
P3
GND
20
19
18
17
16
15
14
1
2
3
4
5
6
7
13
8
12
9
11
10
INT P6
P5
N.C.
P5
P4
GND
P3
N.C.
P2
P1
MAX7321
SSOP/TSSOP
SCL
N.C.
AD0
SDA
V+
RST
N.C.
AD2
P0
15
16
14
13
5
6
7
P1
P2
8
AD2
P7
P6
SCL
13
V+
4
12 10 9
AD0
RST
P5
P4
GND
P3
MAX7321
P0 INT
2
11
SDA
TQFN
3mm x 3mm x 0.8mm
TOP VIEW
*EP
*EXPOSED PADDLE CONNECTED TO GND
MAX7321
I2C Port Expander with 8 Open-Drain I/Os
16 ______________________________________________________________________________________
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
12x16L QFN THIN.EPS
0.10 C0.08 C
0.10 M C A B
D
D/2
E/2
E
A1
A2
A
E2
E2/2
L
k
e
(ND - 1) X e
(NE - 1) X e
D2
D2/2
b
L
e
L
C
L
e
C
L
L
C
L
C
PACKAGE OUTLINE
21-0136
2
1
F
12, 16L THIN QFN, 3x3x0.8mm
MARKING
AAAA
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
EXPOSED PAD VARIATIONS
1.10T1633-1 0.95
CODES
PKG.
T1233-1
MIN.
0.95
NOM.
1.10
D2
1.251.100.951.25
NOM.
1.10
MAX.
1.25
MIN.
0.95
MAX.
1.25
E2
12
N
k
A2
0.25
NE
A1
ND
0
0.20 REF
--
3
0.02
3
0.05
L
e
E
0.45
2.90
b
D
A
0.20
2.90
0.70
0.50 BSC.
0.55
3.00
0.65
3.10
0.25
3.00
0.75
0.30
3.10
0.80
16
0.20 REF
0.25 -
0
4
0.02
4
-
0.05
0.50 BSC.
0.30
2.90
0.40
3.00
0.20
2.90
0.70
0.25
3.00
0.75
3.10
0.50
0.80
3.10
0.30
PKG
REF. MIN.
12L 3x3
NOM. MAX. NOM.
16L 3x3
MIN. MAX.
0.35 x 45°
PIN ID JEDEC
WEED-1
0.35 x 45° WEED-2
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO
JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED
WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220 REVISION C.
NOTES:
T1233-3 1.10 1.25 0.95 1.10 0.35 x 45°1.25 WEED-10.95
T1633F-3 0.65
T1633-4 0.95
0.80 0.95 0.65 0.80
1.10 1.25 0.95 1.10
0.225 x 45°
0.95 WEED-2
0.35 x 45°
1.25 WEED-2
T1633-2 0.95 1.10 1.25 0.95 1.10 0.35 x 45°
1.25 WEED-2
NO
DOWN
BONDS
ALLOWED
YES
NO
YES
N/A
NO
PACKAGE OUTLINE
21-0136
2
2
F
12, 16L THIN QFN, 3x3x0.8
YESWEED-11.251.100.95 0.35 x 45°1.251.100.95T1233-4
T1633FH-3 0.65 0.80 0.95 0.225 x 45°0.65 0.80 0.95 WEED-2 N/A
10. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY
11. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY
MAX7321
I2C Port Expander with 8 Open-Drain I/Os
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17
©2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
QSOP.EPS
E
1
1
21-0055
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH