WCFS4008V1C
4
AC Switching Characteristics[3] Over the Operating Range
WCFS4008V1C 10ns WCFS4008V1C 12ns
Parameter Description Min. Max. Min. Max. Unit
READ CYCLE
tpower[4] VCC(typical) to the first access 1 1 ns
tRC Read Cycle Time 10 12 ns
tAA Address to Data Valid 10 12 ns
tOHA Data Hold from Address Change 3 3 ns
tACE CE LOW to Data Valid 10 12 ns
tDOE OE LOW to Data Valid 5 6 ns
tLZOE OE LOW to Low Z 0 0 ns
tHZOE OE HIGH to High Z[5, 6] 56ns
tLZCE CE LOW to Low Z[6] 33ns
tHZCE CE HIGH to High Z[5, 6] 56ns
tPU CE LOW to Power-Up 0 0 ns
tPD CE HIGH to Power-Down 10 12 ns
WRITE CYCLE[7, 8]
tWC Write Cycle Time 10 12 ns
tSCE CE LOW to Write End 7 8 ns
tAW Address Set-Up to Write End 7 8 ns
tHA Address Hold from Write End 0 0 ns
tSA Address Set-Up to Write Start 0 0 ns
tPWE WE Pulse Width 7 8 ns
tSD Data Set-Up to Write End 5 6 ns
tHD Data Hold from Write End 0 0 ns
tLZWE WE HIGH to Low Z[6] 33ns
tHZWE WE LOW to High Z[5, 6] 56ns
Notes:
3. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
4. tPOWER gives the minimum amount of time that the power supply should be at stable, typical Vcc values until the first memory access can be performed.
5. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.