100324QI - FAIRCHILD SEMICONDUCTOR

July 1988

Revised March 2001

100324 Low Power Hex TTL-to-ECL Translator

100324

Low Power Hex TTL-to-ECL Translator

General Description

The 100324 is a hex translator, designed to convert TTL

logic levels to 100K ECL logic levels. T he inputs are com-

patible with standard or Schottky TTL. A common Enable

(E), when LOW, holds all inverting outputs HIGH and holds

all true outputs LOW. The differential outputs allow each

circuit to be used as an inverting/non-inverting translator, or

as a differential line driver. The output levels are voltage

compensated over the full −4.2V to −5.7V range.

When the circuit is used in the differential mode, the

100324, due to its high common mode rejection, over-

comes voltage gradients between the TTL and ECL ground

systems. The VEE and VTTL power may be applied in either

order.

The 100324 is pin and function compatible with the 100124

with similar AC performance, but features power dissipa-

tion roughly half of the 100124 to ease system cooling

requirements.

Features

■Pin/function compatible with 100124

■Meets 100124 AC specifications

■50% power reduction of the 100124

■Differential outputs

■2000V ESD protection

■−4.2V to −5.7V operating range

■Available to MIL-STD-883

■Available to industrial grade temperature range

(PLCC pack age only )

Ordering Code:

Devices also available in Tape and R eel. Speci fy by append ing the suffix let t er “X” to the o rdering c ode.

Connection Diagrams

24-Pin DIP/SOIC 28-Pin PLCC

Order Number Package Number Package Description

100324SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

100324PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

100324QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

100324QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Industrial Temperature Range (−40°C to +85°C)

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100324

Pin Descriptions Truth Table

H = HIGH Voltage Lev el

L = LOW Voltage Level

Logic Diagram

Pin Names Description

D0–D5Data Inputs

E Enable Input

Q0–Q5Data Outputs

Q0–Q5Complementary

Data Outputs

Inputs Outputs

DnEQnQn

XLLH

LHLH

HHHL

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100324

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: The “A bsolute Maximum Ratings” are thos e values bey ond which

the saf ety of the device cannot be gu aranteed. Th e device shou ld not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the absolute maximum rating.

The “R ecomm ended Ope rating Co ndition s” table will define the condit ions

for actu al device operation.

Note 2: ESD testing conforms to MIL-STD-883, Method 3015.

Commercial Versio n

DC Electrical Characteristics (Note 3)

VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C, VTTL = +4.5V to +5.5V

Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional

noise immunity an d gu ardband ing c an be achi eved by d ecre asin g the al l owable syste m operating ranges. Condit i ons fo r t estin g sho w n in the tables are cho-

sen to guarante e operation under “worst case” conditions.

DIP AC Electric Characteristics

VEE = −4.2V to −5.7V, VCC = VCCA = GND, VTTL = +4.5V to +5.5V

Storage Temperature (TSTG)−65°C to +150°C

Maximum Junction Temperature (TJ)+150°C

VEE Pin Potential to Ground Pin −7.0V to +0.5V

VTTL Pin Potential to Ground Pin −0.5V to +6.0V

Input Voltage (DC) −0.5V to +6.0V

Output Current (DC Output HIGH) −50 mA

ESD (Note 2) ≥2000V

Case Temperature (TC)

Commercial 0°C to +85°C

Industrial −40°C to +85°C

Supply Voltage (VEE)−5.7V to −4.2V

Symbol Parameter Min Typ Max Units Conditions

VOH Output HIGH Voltage −1025 −955 −870 mV VIN =VIH (Max) Loading with

VOL Output LOW Voltage −1830 −1705 −1620 or VIL (Min) 50Ω to −2.0V

VOHC Output HIGH Voltage −1035 mV VIN = VIH(Min) Loading with

VOLC Output LOW Voltage −1610 or VIL (Max) 50Ω to −2.0V

VIH Input HIGH Voltage 2.0 5.0 V Guaranteed HIGH

Signal for All Inputs

VIL Input LOW Voltage 0 0.8 V Guaranteed LOW

Signal for All Inputs

VCD Input Clamp Diode Voltage −1.2 V IIN = −18 mA

IIH Input HIGH Current VIN = +2.4V,

Data 20 µA All Other Inputs VIN = GND

Enable 120

Input HIGH Current 1.0 mA VIN = +5.5V,

Breakdown Test, All Inputs All Other Inputs = GND

IIL Input LOW Current VIN = +0.4V,

Data −0.9 mA All Other Inputs VIN = VIH

Enable −5.4

IEE VEE Power Su pply Current −70 −45 −22 mA All Inputs VIN = +4.0V

ITTL VTTL Power Supply Current 25 38 mA All Inputs VIN = GND

Symbol Parameter TC = 0°CT

C = +25°CT

C = +85°CUnits Conditions

MinMaxMinMaxMinMax

tPLH Propagation Delay 0.50 3.00 0.50 2.90 0.50 3.00 ns

tPHL Data and Enable to Output Figures 1, 2

tTLH Transition Time 0.45 1.80 0.45 1.80 0.45 1.80 ns

tTHL 20% to 80%, 80% to 20%

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100324

Commercial Version (Continued)

SOIC and PLCC AC Electrical Characteristics

VEE = −4.2V to −5.7V, VCC = VCCA = GND, VTTL = +4.5V to +5.5V

Note 4: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack-

aged d evice . The sp ecificatio ns appl y to an y output s swit ching in th e sam e direc tion eithe r HIGH- to-LOW (tOSHL), or LOW-to-H IGH (tOSLH), or in opp osite

direc ti ons both H L and LH (tOST). Parameters tOST and tPS guaranteed by design.

Symbol Parameter TC = 0°CT

C = +25°CT

C = +85°CUnits Conditions

Min Max Min Max Min Max

tPLH Propagation Delay 0.50 2.80 0.50 2.70 0.50 2.80 ns

tPHL Data and Enable to Output Figures 1, 2

tTLH Transition Time 0.45 1.70 0.45 1.70 0.45 1.70 ns

tTHL 20% to 80%, 80% to 20%

tOSHL Maximum Skew Common Edge PLCC Only

Output-to-Output Variation 0.95 0.95 0.95 ns (Note 4)

Data to Output Path

tOSLH Maximum Skew Common Edge PLCC Only

Output-to-Output Variation 0.70 0.70 0.70 ns (Note 4)

Data to Output Path

tOST Maximum Skew Opposite Edge PLCC Only

Output-to-Output Variation 1.60 1.60 1.60 ns (Note 4)

Data to Output Path

tPS Maximum Skew PLCC Only

Pin (Signal) Transition Variation 1.20 1.20 1.20 ns (Note 4)

Data to Output Path

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100324

Industri a l Version

DC Electrical Characteristics (Note 5)

VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −40°C to +85°C, VTTL = +4.5V to +5.5V

Note 5: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional

noise immunity an d gu ardband ing c an be achi eved by d ecre asin g the al l owable syste m operating ranges. Condit i ons fo r t estin g sho w n in the tables are cho-

sen to guarante e operation under “worst case” conditions.

AC Electrical Characteristics

VEE = −4.2V to −5.7V, VCC = VCCA = GND, VTTL = +4.5V to +5.5V

Symbol Parameter TC = −40°CT

C = 0°C to +85°CUnits Conditions

Min Max Min Max

VOH Output HIGH Voltage −1085 −870 −1025 −870 mV VIN =VIH (Max) Loading with

VOL Output LOW Voltage −1830 −1575 −1830 −1620 or VIL (Min) 50Ω to −2.0V

VOHC Output HIGH Voltage −1095 −1035 mV VIN = VIH(Min) Loading with

VOLC Output LOW Voltage −1565 −1610 or VIL (Max) 50Ω to −2.0V

VIH Input HIGH Voltage 2.0 5.0 2.0 5.0 V Guaranteed HIGH

Signal for All Inputs

VIL Input LOW Voltage 0 0.8 0 0.8 V Guaranteed LOW

Signal for All Inputs

VCD Input Clamp Diode Voltage −1.2 −1.2 V IIN = −18 mA

IIH Input HIGH Current VIN = +2.4V,

Data 20 20 µA All Other Inputs VIN = GND

Enable 120 120

Input HIGH Current 1.0 1.0 mA VIN = +5.5V,

Breakdown Test, All Inputs All Other Inputs = GND

IIL Input LOW Current VIN = +0.4V,

Data −0.9 −0.9 mA All Other Inputs VIN = VIH

Enable −5.4 −5.4

IEE VEE Power Su pply Current −70 −22 −70 −22 mA All Inputs VIN = +4.0V

ITTL VTTL Power Supply Current 38 38 mA All Inputs VIN = GND

Symbol Parameter TC = −40°CT

C = +25°CT

C = +85°CUnits Conditions

Min Max Min Max Min Max

tPLH Propagation Delay 0.50 2.80 0.50 2.70 0.50 2.80 ns Figures 1, 2

tPHL Data and Enable to Output

tTLH Transition Times 0.35 1.80 0.45 1.70 0.45 1.70 ns Figures 1, 2

tTHL 20% to 80%, 80% to 20%

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100324

Test Circuit

Note:

•VCC, VCCA = 0V, VEE = −4.5V, VTTL = +5.0V, VIH = +3.0V

•L1, L2 and L3 = equal length 50Ω impe dance lines

•RT = 50Ω terminator internal to scope

•Decoupling 0. 1 µF from GND to VCC, VEE and VTTL

•All unused outputs are loaded with 50Ω to −2V or w it h equiva lent ECL term inator network

•CL = Fixture and stray capacitance ≤ 3 pF

FIGURE 1. AC Test Circuit

Switching Waveform

FIGURE 2. Propagation Delay and Transition Times

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100324

Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M24B

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

Package Number N24E

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100324 Low Power Hex TTL-to-ECL Translator

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Package Number V28A

Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syste ms are devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical compon ent i n any compon ent of a lif e supp ort

device or system whose failure to perform can be rea-

sonabl y ex pect ed to ca use the fa ilu re of the li fe su pp ort

device or system, or to affect its safety or effectiveness.