CYW20737L Bluetooth Low Energy System in Package (SiP) Module The Cypress CYW20737L is a compact, highly integrated Bluetooth Low Energy (BLE) system-in-package (SiP) module. The device includes an embedded BLE antenna, 24 MHz clock, and 512 Kb EEPROM, so a minimal set of external components is needed to create a standalone BLE device. The CYW20737L accelerates time to market. The Bluetooth stack and several application profiles are built into the module, allowing customers to focus on their core applications. To further reduce application development time, the CYW20737L includes integrated software support, with one-click installation of the complete environment and a one-click compile/build/link/load cycle. Coupled with an ultrasmall form factor and support for a wide voltage range, the CYW20737L is ideal for any BT Smart application. Cypress Part Numbering Scheme Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion, there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides Cypress ordering part number that matches an existing IoT part number. Table 1. Mapping Table for Part Number between Broadcom and Cypress Broadcom Part Number Cypress Part Number BCM20737L CYW20737L Features Applications ARM Cortex-M3 microcontroller unit (MCU) Profiles supported in ROM: Embedded 512 Kb EEPROM Battery status Broadcom Serial Control (BSC), SPI, and UART interfaces Blood pressure monitor FCC and CE compliant Find me RoHS compliant, certified lead- and halogen-free Heart rate monitor Moisture Sensitivity Level (MSL) 3 compliant Proximity 6.5 mm x 6.5 mm x 1.2 mm Land Grid Array (LGA) 48-pin package Thermometer and Weight scale Requires external 1.2V DC-DC for low power in sleep and active modes. Time Blood glucose monitor Support for RSA security library Support for LE Audio Support for pairing using NFC tags Additional profiles supported in RAM: Cypress Semiconductor Corporation Document Number: 002-14886 Rev. *C * Blood glucose monitor Temperature alarm Location Other custom profiles 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised May 24, 2017 CYW20737L Figure 1. CYW20737L BLE SiP Block Diagram VBAT/VDDIO VDD1V2 CYW20737L BCM20737L Antenna Bandpass Filter UART BCM20737L CYW20737L 24 MHz XTAL Bluetooth Low Energy System-on-Chip with ARM (R) CortexTM M3-based Microprocessor Core SPI/I2C Infrared ADC GPIOs PWM EEPROM 512 Kb I2C 32.768 kHz Oscillator (optional) IoT Resources Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for your design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software updates. Customers can acquire technical documentation and software from the Cypress Support Community website (http://community.cypress.com/). Document Number: 002-14886 Rev. *C Page 2 of 24 CYW20737L Contents 1. Functional Description ................................................. 4 1.1 External Reset....................................................... 4 1.2 32.768 kHz Oscillator ............................................ 4 1.3 External DC-DC Switcher Characteristics ............. 4 2. Pin Map and Signal Descriptions ................................ 5 3. Electrical Specifications ............................................ 10 4. RF Specifications ....................................................... 11 5. ADC Specifications .................................................... 12 6. Timing and AC Characteristics ................................. 13 6.1 SPI Timing........................................................... 13 6.2 BSC Interface Timing .......................................... 14 Document Number: 002-14886 Rev. *C 6.3 UART Timing....................................................... 15 7. PCB Design and Manufacturing Recommendations 16 7.1 Pad and Solder Mask Opening Dimensions........ 16 7.2 PCB Layout Recommendations .......................... 16 7.3 PCB Stencil ......................................................... 17 7.4 Solder Reflow ...................................................... 17 8. Packaging and Storage Information ......................... 18 9. Mechanical Information ............................................. 20 10. Ordering Information ................................................ 22 Document History .......................................................... 23 Page 3 of 24 CYW20737L 1. Functional Description 1.1 External Reset External reset timing for the CYW20737L is illustrated in Figure 2. Figure 2. External Reset Timing Pulse width >20 s RESET_N Crystal warmup delay: ~ 5 ms Baseband Reset Start reading EEPROM and firmware boot Crystal Enable 1.2 32.768 kHz Oscillator The CYW20737L includes a standard Pierce oscillator. The oscillator circuit includes a comparator with hysteresis on the output to create a single-ended digital output. The hysteresis eliminates chatter when the input is near the comparator threshold (~100 mV). The oscillator circuit can is designed for a 32 kHz or 32.768 kHz crystal oscillator, and can also be driven by an external clock input with a similar frequency. Characteristics for a 32 kHz oscillator are defined in Table 2. Table 2. 32 kHz Crystal Oscillator Characteristics Parameter Output frequency Frequency tolerance Start-up time Symbol Foscout Ftol Tstartup Conditions - Crystal-dependent - Min. Typ. Max. Unit - 32.768 - kHz - 100 - ppm - - 500 s - W Pdrv For crystal selection 0.5 - Crystal series resistance Rseries For crystal selection - - 70 k Crystal shunt capacitance Cshunt For crystal selection - - 1.3 pF Crystal drive level 1.3 External DC-DC Switcher Characteristics The CYW20737L requires an external 1.2V DC switcher to operate its internal digital and RF circuits. A suitable low-power, low-noise switcher must be supplied for proper circuit operation. Digital and analog I/Os, as well as the internal EEPROM operation from the VBAT/VDDIO, can be from 1.62V to 3.63V. The recommended setting is 3V nominal voltage. The following switcher, from Torex Semiconductor LTD, has been qualified and is recommended for all designs. XC9265B/D (see http://www.torexsemi.com/products/detail.php?id=623) Document Number: 002-14886 Rev. *C Page 4 of 24 CYW20737L 2. Pin Map and Signal Descriptions The CYW20737L pin map is shown in Figure 3. Figure 3. CYW20737L (TOP View) The signal name, type, and description of each pin in the CYW20737L is listed in Table 3 on page 6. The symbols shown under I/O Type indicate pin directions (I/O = bidirectional, I = input, O = output) and the internal pull-up/pull-down characteristics (PU = weak internal pull-up resistor and PD = weak internal pull-down resistor), if any. Document Number: 002-14886 Rev. *C Page 5 of 24 CYW20737L Table 3. Pin Descriptions Pin Name I/O Type 1 GPIO: P27 PWM1 I 2 GND GND 3 VBAT I 4 GND GND GND 5 GND GND GND 6 GND GND GND 7 GND GND GND 8 GND GND GND 9 GND GND GND 10 Reserved - 11 GND GND GND 12 GND GND GND 13 GND GND GND 14 GND GND GND 15 GND GND GND 16 VDDC I 17 GND GND 18 UART_RX I 19 UART_TX O, PU UART_TX 20 GND GND GND 21 SCL I/O, PU SCL I/O, PU clock signal for an external I2C device 22 SDA I/O, PU SDA I/O, PU data signal for an external I2C device 23 GND GND GND 24 GND GND GND 25 GPIO: P1 I Default direction: Input. After POR state: Input floating. This pin is tied to the WP pin of the embedded EEPROM. Requires an external 10K pull-up 26 TMC I Test mode control. Pull this pin high to invoke test mode; leave it floating if not used. This pin is connected to GND through an internal 10 k resistor. 27 RESET_N I/O PU Document Number: 002-14886 Rev. *C Description Default direction: Input. After POR state: Input floating. Drain current: 16 mA Alternate function: MOSI (master and slave) for SPI_2 GND Battery supply input. Leave floating Connects to the 1.2V DC-DC step down switcher input. Note: The HIDOFF/Deep Sleep function is not available when the external DC-DC is used. GND UART_RX. This pin is pulled low through an internal 10 k resistor. Active-low system reset with open-drain output Page 6 of 24 CYW20737L Table 3. Pin Descriptions (Cont.) Pin Name I/O Type Description Default direction: Input. After POR state: Input floating. Alternate functions: 28 29 30 GPIO: P0 GND GPIO: P3 I GND I A/D converter input Peripheral UART TX (PUART_TX) MOSI (master and slave) for SPI_2 IR_RX 60Hz_main GND Default direction: Input. After POR state: Input floating. Alternate functions: Peripheral UART CTS (PUART_CTS) SPI_CLK (master and slave) for SPI_2 Default direction: Input. After POR state: Input floating. Alternate functions: 31 GPIO: P2 I Peripheral UART RX (PUART_RX) SPI_CS (slave only) for SPI_2 SPI_MOSI (master only) for SPI_2 Default direction: Input. After POR state: Input floating. Alternate functions: 32 33 GPIO: P4 GPIO: P8 I I Peripheral UART RX (PUART_RX) MOSI (master and slave) for SPI_2. IR_TX Default direction: Input. After POR state: Input floating. Alternate functions: A/D converter input. Default direction: Input. After POR state: Input floating. Alternate functions: 34 GPIO: P33 I Document Number: 002-14886 Rev. *C A/D converter input MOSI (slave only) for SPI_2 Auxiliary clock output (ACLK1) Peripheral UART RX (PUART_RX) Page 7 of 24 CYW20737L Table 3. Pin Descriptions (Cont.) Pin Name I/O Type Description Default direction: Input. After POR state: Input floating. Alternate functions: 35 36 37 38 GPIO: P32 GPIO: P25 GPIO: P24 I I I NC NC GPIO: P13 PWM3 I 39 GPIO: P28 PWM2 GPIO: P14 PWM2 I I A/D converter input SPI_CS (slave only) for SPI_2. Auxiliary clock output (ACLK0) Peripheral UART TX (PUART_TX) Default direction: Input. After POR state: Input floating. Alternate functions: MISO (master and slave) for SPI_2 Peripheral UART RX (PUART_RX) Default direction: Input. After POR state: Input floating. Alternate functions: SPI_CLK (master and slave) for SPI_2 Peripheral UART TX (PUART_TX) No Connection (N/C). Default Direction: Input After POR State: Input Floating Drain current: 16 mA Alternate function: A/D converter input Default direction: Input. After POR state: Input floating. Drain current: 16 mA Alternate functions: A/D converter input LED1 IR_TX Default direction: Input. After POR state: Input floating. Alternate function: A/D converter input Default direction: Input. After POR state: Input floating. Alternate functions: 40 GPIO: P38 I A/D converter input MOSI (master and slave) for SPI_2 IR_TX Default direction: Input. After POR state: Input floating. Alternate functions: 41 GPIO: P15 I Document Number: 002-14886 Rev. *C A/D converter input IR_RX 60 Hz_main Page 8 of 24 CYW20737L Table 3. Pin Descriptions (Cont.) Pin Name 42 GPIO: P26 PWM0 GPIO: P12 I/O Type I I 43 XTALO32K GPIO: P11 O I 44 Description Default direction: Input. After POR state: Input floating. Drain current: 16 mA Alternate function: SPI_CS (slave only) for SPI_2 Default direction: Input. After POR state: Input floating. Alternate functions: A/D converter input XTALO32K Low-power oscillator (LPO) output. Alternate functions: P12 P26 Default direction: Input. After POR state: Input floating. Alternate functions: A/D converter input XTALI32K Low-power oscillator (LPO) input. Alternate functions: XTALI32K I P11 P27 45 GND GND GND 46 GND GND GND 47 GND GND GND 48 GND GND GND Document Number: 002-14886 Rev. *C Page 9 of 24 CYW20737L 3. Electrical Specifications Absolute maximum ratings are defined in Table 4. Table 4. Absolute Maximum Ratings Min. Max. Unit Supply power Parameter NA 1.32 V Storage temperature -40 125 C 0 2 % 1.62 3.63 V Voltage ripple Power supply (VBAT absolute maximum rating) Power for the CYW20737L module is provided by the system through the power pins. Table 5. Voltage Symbol VBAT Parameter Battery voltage Min. Typ. Max. Unit 1.62 - 3.63 V Table 6. Current Consumption Nominal Maximum Unit Receive Operating Mode Receiver and baseband are both operating, 100% Condition 11.5 12.4 mA Transmit Transmitter and baseband are both operating, 100% 9.0 9.8 mA Sleep Wake in < 5 ms 29.0 35.0 A Note: All measurements taken at 25C Document Number: 002-14886 Rev. *C Page 10 of 24 CYW20737L 4. RF Specifications CYW20737L receiver specifications are defined in Table 7. Table 7. Receiver Specifications Parameter Mode and Conditions Min. Typ. Max. Unit - 2402 - 2480 MHz - -94 - dBm -10 - - dBm Frequency range RX sensitivity (standard) Packets: 200 Payload: PRBS 9 Length: 37 Bytes Dirty Transmitter: off. PER: 30.8% Maximum input - Note: All measurements taken at 25C RF transmitter specifications are defined in Table 8. Table 8. Transmitter Specifications Parameter Min. Typ. Max. Unit Transmitter a Frequency range 2402 - 2480 MHz Output power adjustment range -20 - 4 dBm Output power - 2 - dBm Output power variation - 2.5 - dB - - 150 kHz - - 50 kHz - - 20 kHz/50 s Average deviation in payload (sequence: 00001111) 225 - 275 kHz Average deviation in payload (sequence: 10101010) 185 - - kHz - 2 - MHz LO Performance Initial carrier frequency tolerance Frequency Drift Frequency drift Drift rate Frequency Deviation Channel spacing a. This parameter is taken from the Bluetooth 4.0 specification. Document Number: 002-14886 Rev. *C Page 11 of 24 CYW20737L 5. ADC Specifications CYW20737L ADC specifications are defined in Table 9. Table 9. ADC Specifications Parameter Symbol Conditions Min. Typ. Max. Unit Number of input channels - - - 9 - - Channel switching rate fch - - - 133.33 Kch/s Input signal range Reference settling time - Vinp - Charging refsel Effective, single-ended 0 - 3.63 V 7.5 - - s - 500 - k 5 pF Input resistance Rinp Input capacitance Cinp - - - Conversion rate Fc - 5.859 - 187 kHz Conversion time Tc - 5.35 - 170.7 s Resolution R - Absolute voltage measurement error - Using on-chip ADC firmware driver - 2 - % Current I Iavdd1p2 + Iavdd3p3 - - 1 mA Power P - 1.5 - mW - - 100 nA - - 200 s Leakage Current Ileakage Power-up time Tpowerup - T = 25C - 16 Bits Integral nonlinearity INL In the guaranteed performance range -1 - 1 LSBa Differential nonlinearity DNL In the guaranteed performance range -1 - 1 LSBa a. LSBs are expressed at the 10-bit level. Document Number: 002-14886 Rev. *C Page 12 of 24 CYW20737L 6. Timing and AC Characteristics 6.1 SPI Timing SPI interface timing is illustrated in Figure 4 and Figure 5 and defined in Table 10 on page 14. Figure 4. SPI Timing--Modes 0 and 2 6 SPI_CSN SPI_CLK (Mode 0) 1 SPI_CLK (Mode 2) 2 SPI_MOSI First Bit 3 Second Bit 4 SPI_MISO Not Driven First Bit Last bit Last bit Not Driven 5 Second Bit Figure 5. SPI Timing--Modes 1 and 3 6 SPI_CSN SPI_CLK (Mode 1) 1 SPI_CLK (Mode 3) 2 SPI_MOSI Invalid bit 3 First bit 4 SPI_MISO Not Driven Invalid bit Document Number: 002-14886 Rev. *C First bit Last bit Last bit Not Driven 5 Page 13 of 24 CYW20737L Table 10. SPI Interface Timing Specifications Reference Characteristics Min. Typ. Max. 1 SCK 100 1/2SCK - 1 Time from CSN asserted to first clock edge 2 Master setup time - 3 Master hold time 1/2SCK - - 4 Slave setup time - 1/2 SCK - 5 Slave hold time 1/2 SCK - - 6 Time from last clock edge to CSN deasserted SCK 10 SCK 100 6.2 BSC Interface Timing BSC interface timing is illustrated in Figure 6 and is defined in Table 11. Figure 6. BSC Interface Timing Table 11. BSC Interface Timing Specifications Reference Characteristics Min. Max. Unit - 100, 400, 800, 1000 kHz 1 Clock frequency 2 START condition setup time 650 - ns 3 START condition hold time 280 - ns 4 Clock low time 650 - ns 5 Clock high time 280 - ns 6 Data input hold time 0 - ns 7 Data input setup time 100 - ns 8 STOP condition setup time 280 - ns 9 Output valid from clock - 400 ns 10 Bus free time 650 - ns Document Number: 002-14886 Rev. *C Page 14 of 24 CYW20737L 6.3 UART Timing UART timing is illustrated in Figure 7 and defined in Table 12. Figure 7. UART Timing Table 12. UART Timing Specifications Reference Characteristics Min. Max. Unit 1 Delay time, UART_CTS_N low to UART_TXD valid - 24 Baudout cycles 2 Setup time, UART_CTS_N high before midpoint of stop bit - 10 ns 3 Delay time, midpoint of stop bit to UART_RTS_N high - 2 Baudout cycles Document Number: 002-14886 Rev. *C Page 15 of 24 CYW20737L 7. PCB Design and Manufacturing Recommendations 7.1 Pad and Solder Mask Opening Dimensions CYW20737L pad and solder mask opening dimensions are defined in Table 13. Table 13. Pad and Solder Mask Dimensions Pad Type Pad Dimensions Solder Mask Opening Dimensions Type A 0.6 x 0.25 0.7 x 0.35 Type B 0.55 x 0.3 0.65 x 0.4 Type C 0.4 x 0.4 0.5 x 0.5 Unit mm 7.2 PCB Layout Recommendations The following layout recommendations are referenced to Figure 8 on page 16. Connect to system ground from side D of the module (pins 13-22). The L-shaped ground plane is required for the embedded BLE antenna. Keep the GND continuous. Do not cut off the GND shape to accommodate trace routes. An L-shaped ground plane is required. If the L-shaped GND plane is located on the top layer of the PCB, do not place components on the ground plane. If this cannot be avoided, move the L-shaped ground plane to another layer. Antenna efficiency of 31-41% can be achieved based on the layout in Figure 8 on page 16 and the dimensions listed below. Following these layout recommendations is expected to yield 50+ meters of usable range; deviating from these recommendations may reduce the range of the antenna. D: 4.5 mm (typical) G, H, S: 3 mm (typical) L: 3 mm (minimum) W: 0.4 mm (typical) Route signal traces out of the module from side C (between pins 27 and 30) or side D (between pins 16 and 19) of the module. Traces can be overlapped to avoid routing through the keep-out area. Do not route traces from side A or side B. Figure 8. PCB Layout Example Document Number: 002-14886 Rev. *C Page 16 of 24 CYW20737L 7.3 PCB Stencil The recommended PCB stencil is shown in Figure 9 (all measurements in mm). Use an unsolder mask to set the module footprint. Figure 9. CYW20737L Stencil (Bottom View) 7.4 Solder Reflow The recommended solder reflow profile for the CYW20737L is defined in Figure 10. Figure 10. Solder Reflow Profile 245C Temperature 217C 200C 150C PreHeating: 90~120 sec. Soldering: 60~90 sec. Ti Document Number: 002-14886 Rev. *C Page 17 of 24 CYW20737L 8. Packaging and Storage Information The CYW20737L is available in a tape and reel package and is shipped in an ESD-protected moisture-resistant (MSL-3) bag as shown in Figure 11. The storage temperature range is -40C to +125C. Figure 11. CYW20737L ESD/Moisture Packaging The moisture sensitivity label on the CYW20737L shipping bag is shown in Figure 12 on page 19. Document Number: 002-14886 Rev. *C Page 18 of 24 CYW20737L Figure 12. CYW20737L Moisture Sensitivity Label Figure 13 shows the location of pin 1 on the CYW20737L relative to its orientation on the tape packaging. Figure 13. CYW20737L Tape and Reel Pin 1 Location Document Number: 002-14886 Rev. *C Page 19 of 24 CYW20737L 9. Mechanical Information Package dimensions for the CYW20737L are shown in Figure 14. Figure 14. CYW20737L Package Dimensions Document Number: 002-14886 Rev. *C Page 20 of 24 CYW20737L Additional CYW20737L package dimensions are shown in Figure 15. Figure 15. CYW20737L Pin Dimensions (Bottom View) Document Number: 002-14886 Rev. *C Page 21 of 24 CYW20737L 10. Ordering Information Table 14. Ordering Information Part Number CYW20737L Document Number: 002-14886 Rev. *C Package Operating Temperature Humidity 48-pin LGA -40C to +85C 95% max., noncondensing Page 22 of 24 CYW20737L Document History Document Title: CYW20737L Bluetooth Low Energy System in Package (SiP) Module Document Number: 002-14886 Revision ** ECN Orig. of Change - - Submission Date 03/01/2016 Description of Change 20737L-DS100-R: Initial release 20737L-DS101-R: *A - *B 5445313 *C 5746161 UTSV 03/24/2016 UTSV 09/23/2016 AESATP12 05/24/2017 Document Number: 002-14886 Rev. *C Updated: * Table 4 on page 10 * Table 6 on page 10 Updated to Cypress template Updated logo and copyright. Page 23 of 24 CYW20737L Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC(R)Solutions Products ARM(R) Cortex(R) Microcontrollers Automotive Clocks & Buffers Interface Internet of Things Lighting & Power Control Memory PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/arm cypress.com/automotive cypress.com/clocks cypress.com/interface cypress.com/iot cypress.com/powerpsoc cypress.com/memory PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 Cypress Developer Community Forums | WICED IoT Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/psoc cypress.com/touch cypress.com/usb cypress.com/wireless 24 (c) Cypress Semiconductor Corporation, 2016-2017. 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Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Revised May 24, 2017 Page 24 of 24