1. DATE NOTICE OF REVISION (NOR) (YYMMOD) Form Approved THIS REVISION DESCRIBED BELOW HAS BEEN AUTHORIZED FOR THE DOCUMENT LISTED. 95-12-18 OMB No, 0704-0188 ic report for this collection is est averag including the ti lewing instruct ing exist 2. PROCURING garenng and thaintaining the data needed. and compicine ard feviewing mie colecacn of ornakor Send eke eS pearing existing dala sources. ACTIVITY NO aspect of this collechon of information, inclucing suggestions for reducing this burden, to Department of Defense, Washingtion Headquarters Services, Directorate . for information Operations and Reports. 1215 Jefferson Davis Highway, Suite 1204, Arington, VA 22202-4302, and to the Office of Management and Budget, papswers Reduction Project OZ 188), Washington, OC 20503. 3, DODAAG PLEASE 00 NOT RETURN YOUR COMPLETED FORM TO EITHER OF THESE ADDRESSED. RETURN COMPLETED FORM TO THE GOVERNMENT ISSUING CONTRACTING OFFICER FOR THE CONTRACT/ PROCURING ACTIVITY NUMBER LISTED IN ITEM 2 OF THIS FORM. b. ADDRESS (Street, City, State, Zip Code) . CAGE CODE 6. NOR NO, 4. ORIGINATOR Defense Electronics Supply Center 67268 962-R019-96 - = 1507 Wilmington Pike a. TYPED NAME (First, Middle Initial, Dayton, OH 35444-5765 7.CAGE CODE =| 8. DOCUMENT NO. Last) 67268 5962-93148 9. TITLE OF DOCUMENT 11. ECP NO. MICROCIRCUIT, DIGITAL, ADVANCED BIPOLAR CMOS, OCTAL 10. REVISION LETTER EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLOCK ENABLE, N/A TTL COMPATIBLE INPUTS, MONOLITHIC SILICON a. CURRENT b. NEW A 12, CONFIGURATION ITEM (OR SYSTEM) TO WHICH ECP APPLIES All 13. DESCRIPTION OF REVISION t L? for subgroup 9 and from "2.0 ns" to nyts Revision level block; add "A". ns" for subgroups 10 and 11, Change maximum limit from Sheet 1: Revisions {tr cotum; add "A". Revisions description column; add "Changes in accordance with NOR 5962-R019-96". Revisions date column; add "95-12-18". Revision level block; add "A". Rev status of sheets; for sheets 1, 6, 7, and 8, add "A", Sheet 6: Table I, input current high, Tyys change maximum Limit from "+1.0 wA" to "+2.0 pa". Table I, input current low, tips change maximum Limit from "-1.0 pa" to "-2.0 wA". Revision level block; add "A". Sheet 7: Table I, quiescent supply current delta, TTL input levels, Alec: change maximum limit from "1.5 ma" to "2.5 ma", Table I, low level ground bounce noise, Voip? change maximum Limit from "S00 mv" to "700 mv". Revision level block; add "A". Sheet 8: Table 1, propagation delay time, CLK to na, tp yi change minimum Limits from "2.2 ns" to "1.0 ns for subgroup 9 and from "2.2 ns" to yo ns" for subgroups 10 and 11. "7.0 ns" to "7.5 ns" for subgroups 10 and 11. Table I, propagation delay time, CLK to na, ; change minimum limits from "3.1 ns" to 1.5 ns" 14. THIS SECTION FOR GOVERNMENT USE ONLY a. (X one) Xx (1) Existing document supplemented by the NOR may be used in manufacture. (2) Revised document must be received before manufacturer may incorporate this change. (3) Custodian of master document shall make above revision and furnish revised document. o. ACTIVITY AUTHORIZED TO APPROVE CHANGE FOR GOVERNMENT c. TYPED NAME (First. Middle initial. Last) DESC-ELDC Monica L. Poelking a. TITLE e. SIGNATURE f. DATE SIGNED (YYMMDD) Chief. Custom Microelectronics Monica L. Poelking 95-12-18 15a, ACTIVITY ACCOMPLISHING REVISION b. REVISION COMPLETED (Signature) c. DATE SIGNED (YYMMDD) DESC-ELDC Joseph A. Kerby 95-12-18 OO Form 1695, APR 92 Previous eaitions are obsoleteREVISIONS LTR DESCRIPTION DATE (yR-Mo-0A) APPROVED REV SHEET REV SHEET 18 16 17 | 18 REV STATUS REV OF SHEETS SHEET 1 2 3 4 5 6 7 8 10 11 12 13 14 PREPARED BY PMIC N/A Joseph A. Kerby DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHTO 45444 STANDARDIZED CHECKED BY MILITARY Thanh . Nguyen DRAWING MICROCIRCUIT, DIGITAL, ADVANCED THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMEN? OF DEFENSE AMSC N/A APPROVED BY Monica L. Poelking DRAWING APPROVAL DATE 94-05-23 BIPOLAR CMOS, OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLOCK ENABLE, TTL COMPATIBLE INPUTS, MONOLITHIC REVISIONLEVEL SILICON SIZE CAGE CODE 5962-93148 A 67268 SHEET 4 OF 18 DESC FORM 193 JUL 91 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. 5962-E425-931. SCOPE 1.1 Scope. This drawing forms a part of a one part - one part number documentation system (see 6.6 herein). Two product assurance classes consisting of military high reliability (device classes Q and M) and space application (device class V), and a choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). Device class M microcircuits represent non-JAN class B microcircuits in accordance with 1.2.1 of MIL-STD-883, Provisions for the use of MIL-ST0-883 in conjunction with compliant non-JAN devices". When available, a choice of Radiation Hardness Assurance (RHA) Levels are reflected in the PIN. 1.2 PIN. The PIN shall be as shown in the following example: 5962 = 93148 OT 2 RL x | | | | | | | | | | | | LL L | __lL ae Federal RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) \ / (see 1.2.3) V/ Drawing number 1.2.1 RHA designator. Device class M RHA marked devices shall meet the MIL-1-38535 appendix A specified RHA levels and shall be marked with the appropriate RHA designator. Device classes Q and V RHA marked devices shatl meet the MIL-1-38535 specified RHA levels and shall be marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) shall identify the circuit function as follows: Device type Generic number Circuit function 01 54ABT377 Octal edge-triggered D-type flip-flop with clock enable, TTL compatible inputs 1.2.3 Device class designator. The device class designator shall be a single letter identifying the product assurance level as follows: Device class Device requirements documentation 4 Vendor self-certification to the requirements for non-JAN class 8 microcircuits in accordance with 1.2.1 of MIL-STD-883 Qorv Certification and qualification to MIL~I-38535 1.2.4 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style R GDIP1-T20 or CDIP2-T20 20 Dual-in-Line Ss GDFP2-F20 or COFP3-F20 20 Flat pack 2 cacci-N20 20 Square chip carrier 1.2.5 Lead finish. The lead finish shalt be as specified in MIL-STD-883 (see 3.1 herein) for class M or MIL-1-38535 for classes @ and V. Finish letter "X" shall not be marked on the microcircuit or its packaging. The "xX" designation is for use in specifications when lead finishes A, B, and C are considered acceptable and interchangeable without preference. STANDARDIZED SIZE 5962-93148 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET 2 DESC FORM 193A JUL 911.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (V..) - ----+------- 2-6 -0.5 V de to +7.0 V de OC input voltage range 5 ert tte ce eee eee 0.5 Vde to+7.0 Vdc 4/ DC output voltage range gy 1? tet et tee eee ee -0.5 Vde to +5.5 Vde 4/ DC input clamp current (1 3 Wv N O0.0V) -~+--- -18 mA OC output clamp current tf wh <0.0v)-+----- -50 mA OC output current Clo ) (pee output) ee tr ee ee ee +96 mA Storage temperature range (T...) ------------ -65C to +150C Lead temperature (soldering, 1g) seconds) - ------- +300C Thermal resistance, junction-to-case {e, --co tte See MIL-STD-1835 Junction temperature (T,) -------+-+-+--+-+-- 475C Maximum power dissipation (Pp) eee ee ee ee eee 500 mW 1.4 Recommended operating conditions. 2/ 3/ Supply voltage range (Vv. ~-- eee ee ee eee eee 44.5 V de to +5.5 V de Input voltaye range (V cg ~+ ee eee ee ee ee ee +0.0 V de to V Output voltage range a - oo et ee er tee +0.0 V de to Veg Maximum low Level input OUT age Wo) - 2 eee ee ee 0.8 Vv Minimum high level input voltage re wee ee ree 2.0 Vv Case operating temperature range (T y --s-+-+ cote ~55C to +125C Maximum input rise and fall rate cat/av) ~s etter ee 5 ns/V Maximum high level output current (1...) -------- 24 mA Maximum low Level output current (Ip)? 777 ee eee 48 mA 1.5 Digital logic testing for device classes Q and V. Fault coverage measurement of manufacturing logic tests (MIL-STD-883, test method 5012) --- - - XX percent 5/ VV Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise noted, all voltages are referenced to GND. 3/ The Limits for the parameters specified herein shall apply over the full specified Ve c range and case temperature range of -55C to +125C. / The input and output negative voltage ratings may be exceeded provided that the input and output clamp current ratings are observed. 3/ Values will be added when they become available. STANDARDIZED SIZE 5962-93148 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET 3 DESC FORM 193A JUL 912. APPLICABLE DOCUMENTS 2.1 Government_specification, standards, bulletin, and handbook. Unless otherwise specified, the following specification, standards, bulletin, and handbook of the issue Listed in that issue of the Department of Defense Index of Specifications and Standards specified in the solicitation, form a part of this drawing to the extent specified herein. SPECIFICATION MILITARY ; MIL-1-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS MILITARY MIL-ST0-883 Test Methods and Procedures for Microelectronics. MIL-STD-973 - Configuration Management. MIL~-STD-1835 Microcircuit Case Outlines. BULLETIN MILITARY MIL-BUL-103 List of Standardized Military Drawings (SMD's). HANDBOOK MILITARY MIL-HDBK-780 Standardized Military Drawings. (Copies of the specification, standards, bulletin, and handbook required by manufacturers in connection with specific acquisition functions should be obtained from the contracting activity or as directed by the contracting activity.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing shall take precedence. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device class M shall be in accordance with 1.2.1 of MIL-STD-883, "Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices" and as specified herein. The individual item requirements for device classes Q and V shall be in accordance with MIL-I-38535, the device manufacturer's Quality Management (QM) plan, and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-STD-883 (see 3.1 herein) for device class M and MIL-1-38535 for device classes @ and V and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logie diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Ground bounce load circuit and waveforms. The ground bounce load circuit and waveforms shall be as specified on figure 4. 3.2.6 Switching wavetorms and test circuit. The switching waveforms and test circuit shall be as specified on figure 5. STANDARDIZED SIZE 5962-93148 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL | SHEET 4 DESC FORM 193A JUL 91+. 3.3 Electrical performance characteristics and postirradiation parameter limits. Untess otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table 1 and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shail be the subgroups specified in table 11. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN Listed in 1.2 herein. Marking for device class M shall be in accordance with MIL-STD-883 (see 3.1 herein). In addition, the manufacturer's PIN may also be marked as Listed in MIL-BUL-103. Marking for device classes Q and V shall be in accordance with MIL-I-38535. 3.5.1 Certification/compliance mark. The compliance mark for device class M shall be a C" as required in MIL-STD~883 (see 3.1 herein). The certification mark for device classes Q@ and V shall be a "QML" or "Q" as required in MIL-I-38535. 3.6 Certificate of compliance. For device class M, a certificate of compliance shall be required from a manufacturer in order to be Listed as an approved source of supply in MIL-BUL-103 (see 6.7.2 herein). For device classes Q and V, a certificate of compliance shali be required from a QML-38535 Listed manufacturer in order to supply to the requirements of this drawing (see 6.7.7 herein). The certificate of compliance submitted to DESC-EC prior to listing as an approved source of supply for this drawing shall affirm that the manufacturer's product meets, for device class M, the requirements of MIL-STD-883 (see 3.1 herein), or for device classes Q@ and V, the requirements of MIL-1-38535 and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required for device class M in MIL-STD-883 (see 3.1 herein) or for device classes @ and V in MIL-1-38535 shall be provided with each lot of microcircuits delivered to this drawing. 5.8 Notification of change for device class M. for device class M, notification to DESC-EC of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change as defined in MIL-STD-973. 3.9 Verification and review for device class M. For device class M, DESC, DESC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shail be in microcircuit group number 127 (see MIL-1-38535, appendix A). 4. QUALITY ASSURANCE PROVISIONS 4.1 Sampling and inspection. For device class M, sampling and inspection procedures shall be in accordance with MIL-STD-883 (see 3.1 herein). For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-1-38535 and the device manufacturer's QM plan. 4.2 Screening. for device class M, screening shall be in accordance with method 5004 of HIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. For device classes Q@ and V, screening shall be in accordance with MIL-1-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. 4.2.1 Additional criteria for device class M. a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015. (2) T, = +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table Il herein, except that interim electrical tests prior to burn in are optional at the discretion of the manufacturer for device class M. STANDARDIZED SIZE 5962-93148 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET 5 DESC FORM 193A JUL 91TABLE I. Electrical performance characteristics. | | Test conditions 2/ | Device | Group A | | Unit Test and Symbol | 55C s T. 5 +#125C | type Vee | subgroups | Limits 3/ | MIL-STD-883 test | | 4.5 VsVi.5 5.5 Vv | | | { { method 1/ | | unless otherwise specified | | | { | | | | | { Min [Max | | | | | | | | High level | Vout | For all inputs affecting , all 44.5 v { 1,2,3 | 2.5 | |v output voltage =| ] output under test | | { | | | 3006 | | Viy = 2.0 Vor 0.8 V | | | | | | | | Igy = -3 aA | | | | | | | | | L | i J | | | | | | | | | | Vou2 | For all inputs affecting j All [S.0v | 1,2,3 | 3.0 | | | output under test | | ( | | | | | Vyy 22-0 V or 0.8 V | | { | | | | | low = -3 mA | | I | | | | | | L | | | | | | | | | | | | | Voyz3 | For all inputs affecting J} atl {45 v | 1,2,3 | 2.0 | | | output under test | | i | { | { | Vyy =2.0 V or 0.8 V \ | | { { | || Tayi -26 ma | r | | | | | | | | } | | l | | | | | | | | Low Level | Vo. | For all inputs affecting J} atk {4.5 Vv | 1,2,3 | |} 0.55 | Vv output voltage | | output under test | | { | { | 3007 | | Vy = 2.0 V or 0.8 V | { | | { | | | Ty, 48 ma ! ; | | | | | | | { { { | | | | f | | Off-state leakage | Inge | For input or output under test {| all [0.0 Vv | 1 | | #100 pA current | | Vin or = 4.5 V { | | | { | | AlLvother pins at 0.0 V | | | | | | [ { | | i { | | | | | | | | High-state leakage | logy | For output under test | alt {8.5 Vv | 1,2,3 | {| 50 uA current { | Voyy = 5-5 V | | | | | | { outputs at high logic state | | | | | | | I | | { l | | | | | | | | | | Negative input | Vice | For input under test, I, = -18 mA f ALL {4.5 v | 1,2,3 | j -1.2 | Vv clamp voltage | | | | | | | | 3022 I | | | i | i | | | | | | | | | Input current high | I, | For input under test } alt jS.5v | 4,2,3 | | +7.0 | yA 3010 | Vin = Yee | | | | | | | | | { | | | | | | | | | | | { | | Input current low | 1,, | For input under test |} alt {$.5v | 1,2,3 | j -1.0 [ yA 3009 | | Vay = GND | | | | | | | | | | | | | | | | { | | | | | | | i | | | | Output current | Ip | Voyy = 2-5 -V J} att [5.5 V | 1,2,3 | -50 |-180 | ma 3011 | | | | | { | [4/ | | | | | | | | 4 L \ | | See footnotes at end of table. STANDARDIZED SIZE 5962-93148 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET 6 DESC FORM 193A JUL 91TABLE I. Electrical performance characteristics - Continued. | { Test conditions 2/ | Device | | Group A | | unit Test and |Symbot | 55C s T. 3 #125C | type | Veg | subgroups | Limits 3/ MIL-STD-883 test | | 45VsV.55.5V | { | | | method 1/ | | unless otherwise specified | | | | | | | | { | | Min Hax_ 7 | | | | | | Quiescent supply | Ale | for input under test J att [5.5 Vv }] 1,2,3 | | 1.5 | mA current delta, | 5/ | Vi =3.4V | | | | | TIL input levels | } for all other inputs | | | | | | 3005 | | Vin = Veg oF GND | | | | | | | | | | | | | | H+} ++ I | | Quiescent supply | I | Via = Ve. or GND { abl [5.5 Vv |} 1,2,3 | | 250 | yA current outputs | CCH | lout = 6s { | | | | | high | | | | | | | | w_|_ }}- ++ Quiescent supply | I | Vig = V-. or GND ALL ss {5.5 Vf 1,2,3 | | 30 | ma current outputs { cel | ur = 6s | | | | { low | | | | | | { 3005 ! | | | | | | | | Input capacitance | Cin | See 4.4.1b { AlL {5.0 Vv | 4 | | 10.5 | pF 3at2 | uN | ty = 425% | t | | | | | | | | | | | | +++ + | | Output | Cour | See 4.4.1b | all |5.0V a | | 17.0 | pF capacitance | | T. = 25C | | | | | 3012 { | | | | | | | | ! ! | | | | | Low level |v LP | Viy 7 3-0V J all [5.0 4 | | 500 | mw ground bounce | 6? Vip = 0-0. { | | | | | noise T, = +25 C | { | : } | See figure 4 | | { | Low Level | Nouv | See 4.4.1 J} ALL [5.0 V | 4 | |-1200 mv ground bounce [6 | | { noise | | t \ | | | | | | | | High level | Youp | J all [5.0V f 4 | | 1450 | mv Veg bounce 6f | | | | { | noise | | | | | | | | | | High level 1 Vouy | f alls sfS.0v | 4 | {| -700 | av Vee bounce rey | | | | | | noise L { L | | | ! | | | | | | Functional test =| 7/ | V,, = 0.8 V J Alles [4S] 7,8 | bo | Hf som | j Vig = 2.0 V | || | | | | Verify output Yo | | | | | { | | See 4.4.1d l | | | | | | | | | | | | | Vip = 0.8 V j AL [5.5 v | 7,8 | bL {| 4H | | | Viy 2 2-09 | | | | | | | | Verify output V, i | | | | | | | See 4.4.14 { il | | i See footnotes at end of table. STANDARDIZED SIZE 5962-93148 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET 7 DESC FORM 193A JUL 91TABLE I. Electrical performance characteristics - Continued. | | Test conditions 2/ Device | | Group A | J Unit Test and [Symbol | -55C s T. = +125C type | Voc | subgroups | Limits 3/ | MIL-STD-883 test | | 4.5VsV.55.5V | | | | method 1/ | | unless otheruise specified | | | | | | | 1 ! Lo Min | Max | | | { i i | | Clock frequency | F etock! ie SO pF minimum, Jj ALL {5.0V | 9 | Oo | 150 | MHz | | RB, = 5009, { | | | | | | 8/ | Se figure 5 | |4.5 Vv. | | | | | | | {| and { 10,11 | o f| 150 | | | | i5.5 Vv | | { | | | | | | | { | Pulse duration, | ty | C, = 50 pF minimum, J att |[5.0v | 9 3.3 | ns CLK high or low | | R, = 500a, | | | | {| 8/ | Se figure 5 | |4.5 VV | | | | | | and | 10,11 | 3.3 | I | L jp.s vi | | | { | | | | | | | | Setup time, | toy | C, = 50 pF minimum, {| atk |[5.0Vv | 9 2.0 | ns high or low, | | R= 500a, | | | | nd to CLK | 8/ | Se figure 5 | j4.5 Vv | } { | | | Jand | 10,127 [| 2.5 | | | | [5.5 v_ | | | | | | | | | | | | Setup time, | too | C, = 50 pF minimum, [| atl {5.0Vv | 9 } 3.0 | high or Low, | | Rv = 00a, | | { | | CLKEN to CLK | 8/ | Se figure 5 | 14.5 | | j [ | | | | and | 10,17 | 3.0 | | | | L [5.5 Vv | | { | | | | | | | | | Hold time, | th | &, = 50 pF minimum, | AL {5.0v | 9 | 1.8 | | ns high or Low, | | R, = 500a, | | | } l nD from CLK { 8/ | Se figure 5 { [4.5 | | } | | | and | 10,11 [| 1.8 | | I | | [5.5 v_] | | | | | | | | | | | Hold time, | tho | , = 50 pF minimum, {| AUL |5.0V | 9 | 1.8 | | ns high or low, | {| Ry = 500n, | | | | i | CLKEN from CLK | 8/ | See figure 5 | 14.5 v | | | | | | | f and | 10,11 | 1.8 | | | | | [5.5 v1 { | | | | | | | | i Maximum operating | fy,, | C, = 50 pF minimum, { all |[S.OV | 9 {| 150 { | MHz frequency | | R= 5009, | | | | i | { | See figure 5 | j4.5 Vv | | | | | | | and | 10,11 | 150 | | { I [5.5 Vv | | { | | | | | | { | Propagation delay | tou | c= SO pF minimum, J alt |S.aVv | 9 | 2.2 | 6.0 | ns time, CLK to n@ | | R- = 500a, { | | L | | 3003 | 9/ | Se figure 5 | {4.5 | | | | | | | j and | 10,11 | 2.2 [| 7.0 | | | | is.5v_ | |! | | | | | | | | | Propagation delay | toy | C, = 50 pF minimum, J} alt |5.0Vv ] 9 {| 3.7 | 6.8 | ns time, CLK to nq | | R, = 5002, | | | | { | 3003 | o | Se figure 5 | j4.5 Vv | | | | | | | | and {| 10,11 | 2.0 | 7.6 | | t I 15.5 V_] | | | See footnotes on next sheet. STANDARDIZED SIZE 5962-93148 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET 8 DESC FORM 193A JUL 91TABLE I. Electrical _ performance characteristics - Continued. 1/ For tests not Listed in the referenced MIL-STD-883 (e.g. Ale , utilize the general test procedure of 883 under the conditions listed herein. 2/ Each input/output, as applicable, shall be tested at the specified temperature, for the specified Limits, to the tests in table I herein. Output terminals not designated shall be high level logic, low level logic, or open, except for all I_, and 41. tests, where the output terminal shall be open. When performing these tests, the current meter shsCt be placed in the circuit such that all current flows through the meter. For input terminals not designated, V,.. = GNDor Vv. = 3.0 Vv. IN IN 3/ For negative and positive voltage and current values, the sign designates the potential difference in reference to GND and the direction of current flow, respectively; and the absolute value of the magnitude, not the sign, is relative to the minimum and maximum Limits, as applicable, Listed herein. ALL devices shall meet or exceed the Limits specified in table I at 4.5 Vs Vee s 5.5 Vv. 4/ Not wore than one output should be tested at one time, and the duration of the test condition should not exceed one second. S/ This test may be performed either one input at a time (preferred method) or with all input pins simultaneously at Vow =v c -2.1 V (alternate method). Classes Q and V shall use the preferred method. When the test is performed using the alternate test method, the maximum Limit is equal to the number of inputs at a high TTL input level times 1.5 mA; and the preferred method and Limits are guaranteed. 6/ This test is for qualification only. Ground and V.. bounce tests are performed on a non-switching (quiescent) output and are used to measure the magnitude of indGced noise caused by other simultaneously switching outputs. The test is performed on a low noise bench test fixture. For the device under test, all outputs shail be loaded with 5002 of load resistance and a minimum of 50 pF of load capacitance (see figure 4). Only chip capacitors and resistors shall be used. The output load components shall be located as close as possible to the device outputs. It is suggested, that whenever possible, this distance be kept to less than 0.25 inches. Decoupling capacitors shall be placed in parallel from V.. to ground. The values of these decoupling capacitors shall be determined by the device manufacturer. The low and high level ground and V.. bounce noise is measured at the quiet output using a 1 GHz minimum bandwidth oscilloscope with a 50q input impedance. The device inputs shall be conditioned such that all outputs are at a high nominal V level. The device inputs shall then be conditioned such that they switch Stultaneous\y and the output under fest remains at Vas all other outputs possible are switched from V. to Yo and V oup are then measured from the nominal You level to the largest negative and positive peaks, H cope tive! Ysee figure 4). This is then repeated with the? Home outputs not under test switching from Yo. to Vou: The device inputs shall be conditioned such that all outputs are at a low nominal V, level. The device inputs shall then be conditioned such that they switch simultaneously and the output under Test remains at Vo. 25 all other outputs possible are switched from Vv. to V a L and Vv are then measured from the nominat Vo level to the largest positive and negative peaks, respectively (see figure 4). This is then repeated with the Same Outputs not under test switching from Vou to Vor: 7/ Tests shall be performed in sequence, attributes data only. Functional tests shall include the truth table and other logic patterns used for fault detection. The test vectors used to verify the truth table shall, at a minimum, test all functions of each input and output. ALL possible input to output logic patterns per function shalt be guaranteed, if not tested, to the truth table in figure 2, herein. functional tests shall be performed in sequence as approved by the qualifying activity on qualified devices. After incorporating allowable tolerances per MIL-STD-883, Vi = 0.4 V and Vins 2.4 V. For outputs, t s 0.8 V, H 2 2.0 V. loo ~ This parameter is guaranteed, if not tested, to the Limit specified in table I herein. 9/ For propagation delay tests, all paths must be tested. STANDARDIZED SIZE 5962-93148 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET 9 DESC FORM 193A JUL 91TD | Device type a1 | | Case outlines | R, S, 2 | | Terminal | |Terminal number| symbol | | | | | | | | | | | | | | | | | | | | | | | OOANAUW EW oO | | | | | | | | | | | | | | | | | | | | | | J CLK | | | | | | | | | | | | | | | | | | | | | ed Pin descriptions Terminal symbol Description nd (n = 1 to 8) Data inputs CLK Clock input (active rising edge) CLKEN Clock enable input (active low) n@ (n = 1 to 8) Data outputs FIGURE 1. Terminal connections. STANDARDIZED SIZE 5962-93148 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISLON LEVEL SHEET 10 DESC FORM 193A JUL 91(each flip-flop) f t | Inputs | Outputs t | CLKEN CLK nd [| na | L 4 | | x x | Q fou t H | HI f ob t bof ko | X Horlk xX | s High voltage level Low voltage level Irrelevant Low-to-high clock transition = The Level of Q before the indicated steady- state input conditions were established. ao FIGURE 2. Truth table. INS CLK > CLKEN q> eo 1D 1D 3 oo 1 er Ci XK _/ TO 7 OTHER CHANNELS FIGURE 3. Logic diagram. STANDARDIZED SIZE 962-93148 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET ll DESC FORM 193A JUL 91ete | bts 30V SWITCHING sv a7 INPUT 0.3V OV ee / F (ye J IN-PHASE [NPUTS QUT-OF-PHASE INPUTS 3.0V 3.0V [NPUT SKEW LSV t \- LV mn 0.00 | 0.0V t ste gov t t 20V LSV __ LV 0.0V - 0.0V v ACTIVE oH CL SRL OUTPUTS V ow OUTPUT Lt DUT <n QUTPUTS) CL SRL H- w OUTPUT 2 _ OLP _ CHP ome . Quiet i a a OUTPUT VoL Von = : UNDER TEST - * LVyy Ly - * . Tv" en QUTPUT n NOTES: 1. includes a 47 pf chip capacitor (-0 percent, +20 percent) and at least 3 pF of equivalent capacitance from C tke test jig and probe. 2. R, 2 4502 1 percent, chip resistor in series with a 509 termination. For monitored outputs, the 50a termination shall be the 50q characteristic impedance of the coaxiat connector to the oscilloscope. 3. Input signal to the device under test: a. Von = 0.0 V to 3.0 V; duty cycle = 50 percent; f,, = 1 MHz. b. tl, t, = 3.ns #1.0 ns. for input signal generators incapable of maintaining these values of t. and Te, the 3.0 ns limit may be increased up to 10 ns, as needed, maintaining the 1.0 ns tolerance and guaranteeing the resuits at 3.0 ns #1.0 ns; skew between any two switching inputs signals (tes = 250 ps. FIGURE 4. Ground bounce load circuit and waveforms. STANDARDIZED SIZE 5962-93148 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET 12 DESC FORM 193A JUL 91a = . TIMING INPUT LSV ---~------ 0.0V | [ae 5 mle $1, | | | \ 3.0V DATA INPUT isvK isvK 0.0V INPUT PULSE WtOTH HIGH AND LOW Fax CLOCK INPUT FREQUENCY 0.0V FIGURE 5. Switching waveforms and test circuit. STANDARDIZED SIZE 5962-93148 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET 13 DESC FORM 193A JUL 91TIMING INPUT OuTPUT TO Vee oR REQU! REO PULSE GENERATOR NOTES: 1. c. = 2. Ry = 500a or equivalent 3. R. = 50a or equivalent 0.3 V, respectively. 4. Input signal from pulse generator: duty cycle = 50 percent. The measurement points for th and t 3.0V OTHER INPUTS TIED GNO AS ViN o.Qv bP Vv ou Vee DEVICE Your UNOER >> TEST fa V.,, = 0.0 V to 3.0 V; PRR s 10 MHz; t shall be from 0.3 V to 2.7 V, and from 2.7 V to f 50 pF minimum or equivalent (includes test jig and probe capacitance) ,* 2.5 ns; t, 5 2.5 ns; 5S. Timing parameters shall be tested at a minimum input frequency of 1 MHz. 6. The outputs are measured one at a time with one transition per measurement. DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 FIGURE 5. Switching waveforms and test circuit - Continued STANDARDIZED SIZE 5962-93148 MILITARY DRAWING A REVISION LEVEL SHEET 14 DESC FORM 193A JUL 914.2.2 Additional criteria for device classes Q and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shalt be as specified in the device manufacturer's QM plan in accordance with MIL-1-38535. The burn-in test circuit shall be maintained under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MIL-I-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015. b. Interim and final electrical test parameters shatl be as specified in table I1 herein. c. Additional screening for device class V beyond the requirements of device class @ shall be as specified in appendix 8 of MIL-I-38535. 4.3 Qualification inspection for device classes @ and V. Qualification inspection for device classes Q and V shall be in accordance with MIL-1-38535. Inspections to be performed shall be those specified in MIL-I-38535 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4 Conformance inspection. Quality conformance inspection for device class M shall be in accordance with MIL-STD-883 (see 3.1 herein) and as specified herein. Inspections to be performed for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). Technology conformance inspection for classes @ and V shall be in accordance with MIL~-1-38535 including groups A, B, C, D, and inspections and as specified herein except where option 2 of MIL-1-38535 permits alternate in-line control testing. 4.4.1 Group A inspection. a. Tests shall be as specified in table II herein. C,., and shall be measured only for initial qualification and after process or design changes which may affect capacitance. C,,. and fo 1 shall be measured between the designated terminal and GND at a frequency of 1 MHz. This test may be performed at 10 MHz and guaranteed, if not tested, at 1 MHz. The DC bias for the pin under test (V )=s2.5Vor3.0V. for C,, and C..., test all applicable pins on five devices : . BIAS IN OUT with zero failures. b. For Cy and C.._, a device manufacturer may qualify devices by functional groups. A specific functional group shail be composed of function types, that by design, will yield the same capacitance values when tested in accordance with table I, herein. The device manufacturer shali set a function group Limit for the C,,, and C 7 tests. The device manufacturer may then test one device functional group to the Limits and conditions specified herein. ALL other device functions in that particular functional group shall be guaranteed, if not tested, to the limits and test conditions specified in table I, herein. The device manufacturer shall submit to DESC-EC the device functions Listed in each functional group and the test results for each device tested. . Ground and ve bounce tests are required for all device classes. These tests shall be performed only for initial qual {Fieation, after process or design changes which may affect the performance of the device, and any changes to the test fixture. V Lp Youve Voups and V shalt be measured for the worst case outputs of the device. All other outputs shal? be guaranted, if not Yested, to the Limits established for the worst case outputs. The worst case outputs tested are to be determined by the manufacturer. Test 5 devices assembled in the worst case package type supplied to this document. All other package types shall be guaranteed, if not tested, to the limits established for the worst case package. The package type to be tested shall be determined by the manufacturer. The device manufacturer will submit to OESC-EC data that shall include all measured peak values for each device tested and detailed ascilloscope plots for each Voip? v v and V from one sample part per function. The plot shall contain the waveforms of both a OLY, .OHP suitching output gy the output under test. STANDARDIZED SIZE 962-93148 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET 15 DESC FORM 1934 JUL 91Each device manufacturer shall test product on the fixtures they currently use. When a new fixture is used, the device manufacturer shall inform DESC-EC of this change and test the 5 devices on both the new and old test fixtures. The device manufacturer shail then submit to DESC-EC data from testing on both fixtures that shall include all measured peak values for each device tested and detailed oscilloscope plots for each Vorpe Vary. onp- and Vo), from one sample part per function. The plot shall contain the waveforms of both a suitching output guy the output under test. For Voups Youy: oi p- and V.., a device manufacturer may qualify devices by functional groups, A specific functional group shall be composed of function types, that by design, will yield the same test values when tested in accordance with table I, herein. The device manufacturer shall set a functional group timit for the Voup- Von: V LP and Vo v tests. The device manufacturer may then test one device function from a functional group to the Limvks and conditions specified herein. ALt other device functions in that particular functional group shall be guaranteed, if not tested, to the Limits and conditions specified in table 1, herein. The device manufacturer shall submit to DESC-EC the device functions listed in each functional group and test results, along with the oscilloscope plots, for each device tested. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table in figure 2 herein. The test vectors used to verify the truth table shall, at a minimum, test all functions of each input and output. ALL possible input to output logic patterns per function shall be guaranteed, if not tested, to the truth table in figure 2, herein. For device classes @ and V, subgroups 7 and & shall include verifying the functionality of the device; these tests shall have been fault graded in accordance with MIL-STD-883, test method 5012 (see 1.5 herein). TABLE II. Electrical test requirements. Test requirements Subgroups Subgroups Cin accordance with Cin accordance with MIL-STD-883, MIL-1-38535, table III) T5005, table I) Device Device Device class M class Q class V Interim electrical ~~ - 4 parameters (see 4.2) 2/1, 2, 3, 7, 8, 9, 10, 14 | { | | { | | { { { | | | Final electrical | 1/ 1, 2, 3, 7, 1/1, 2, 3, 7, parameters (see 4,2) | 8, 9, 10, 11 8, 9, 10, 11 | | | | I | | | | | | | | | | l 1, 2, 3, 4, ?, 8, 9, 10, 11 Group A test requirements (see 4.4) 8, 9, 10, 11 8, 9, 10, 11 1, 2, 3, 4, 7, 8, 9, 10, 11 Group C end-point electrical parameters (see 4.4) Group 0 end-point electrical 1, 2, 3 parameters (see 4.4) Group end-point electrical 1, 7,9 | | | | | | | { | | | | 1, 2, 3, 4, 7, | 1, 2, 3, 4, q, | | | | | | | | | | { | parameters (see 4.4) | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1 | | | | | | | | 1/ PDA applies to subgroup 1. 2/ PDA applies to subgroups 7 and 7. DEFENSE ELECTRONICS SUPPLY CENTER STANDARDIZED SIZE 5962-93148 MILITARY DRAWING A DAYTON, OHIO 45444 REVISION LEVEL SHEET 16 DESC FORM 193A JUL 91