Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LMP2011, LMP2012 SNOSA71L - OCTOBER 2004 - REVISED SEPTEMBER 2015 LMP2011 Single/LMP2012 Dual High Precision, Rail-to-Rail Output Operational Amplifier 1 Features 3 Description (For VS = 5 V, Typical Unless Otherwise Noted) 1 * * * * * * * * * * Low Ensured VOS Over Temperature 60 V Low Noise with No 1/f 35nV/Hz High CMRR 130 dB High PSRR 120 dB High AVOL 130 dB Wide Gain-Bandwidth Product 3 MHz High Slew Rate 4 V/s Low Supply Current 930 A Rail-to-Rail Output 30 mV No External Capacitors Required 2 Applications * * * Precision Instrumentation Amplifiers Thermocouple Amplifiers Strain Gauge Bridge Amplifier The LMP201x series are the first members of TI's new LMPTM precision amplifier family. The LMP201x series offers unprecedented accuracy and stability in space-saving miniature packaging, offered at an affordable price. This device utilizes patented autozero techniques to measure and continually correct the input offset error voltage. The result is an amplifier which is ultra-stable over time and temperature. It has excellent CMRR and PSRR ratings, and does not exhibit the familiar 1/f voltage and current noise increase that plagues traditional amplifiers. The combination of the LMP201x characteristics makes it a good choice for transducer amplifiers, high gain configurations, ADC buffer amplifiers, DAC I-V conversion, and any other 2.7-V to 5-V application requiring precision and long term stability. Other useful benefits of the LMP201x are rail-to-rail output, a low supply current of 930 A, and wide gain-bandwidth product of 3 MHz. These versatile features found in the LMP201x provide high performance and ease of use. Device Information(1) PART NUMBER LMP2011 LMP2012 PACKAGE BODY SIZE (NOM) SOIC (8) 4.90 mm x 3.91 mm SOT-23 (5) 2.90 mm x 1.60 mm SOIC (8) 4.90 mm x 3.91 mm VSSOP (8) 3.00 mm x 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Bridge Amplifier Offset Voltage vs Common Mode Voltage 5V + VOUT + R1 R2 R2 R1 10k, 0.1% 2k, 1% 2k, 1% 10k, 0.1% R3 20: 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMP2011, LMP2012 SNOSA71L - OCTOBER 2004 - REVISED SEPTEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 4 4 4 4 5 5 6 7 8 9 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information: LMP2011 ................................ Thermal Information: LMP2012 ................................ 2.7-V DC Electrical Characteristics........................... 2.7-V AC Electrical Characteristics ........................... 5-V DC Electrical Characteristics.............................. 5-V AC Electrical Characteristics .............................. Typical Characteristics ............................................ Detailed Description ............................................ 14 7.1 Overview ................................................................. 14 7.2 Functional Block Diagram ....................................... 14 7.3 Feature Description................................................. 14 7.4 Device Functional Modes........................................ 15 8 Application and Implementation ........................ 17 8.1 Application Information............................................ 17 8.2 Typical Applications ................................................ 17 9 Power Supply Recommendations...................... 20 10 Layout................................................................... 20 10.1 Layout Guidelines ................................................. 20 10.2 Layout Example .................................................... 21 11 Device and Documentation Support ................. 22 11.1 11.2 11.3 11.4 11.5 11.6 11.7 Device Support .................................................... Documentation Support ........................................ Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 22 22 22 22 22 22 23 12 Mechanical, Packaging, and Orderable Information ........................................................... 23 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision K (March 2013) to Revision L * Page Added Pin Configuration and Functions section, Storage Conditions table, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................................................................................ 1 Changes from Revision J (March 2013) to Revision K * 2 Page Changed layout of National Data Sheet to TI format ........................................................................................................... 19 Submit Documentation Feedback Copyright (c) 2004-2015, Texas Instruments Incorporated Product Folder Links: LMP2011 LMP2012 LMP2011, LMP2012 www.ti.com SNOSA71L - OCTOBER 2004 - REVISED SEPTEMBER 2015 5 Pin Configuration and Functions DBV Package 5-Pin SOT-23 Single Top View D Package 8-Pin Single SOIC Top View N/C - 2 + 3 - 4 VIN VIN 1 V 8 - 7 + 6 5 N/C + V VOUT N/C Pin Functions: LMP2011 PIN NO. NAME I/O DESCRIPTION DBV D -IN 4 3 O Inverting input +IN 3 2 I Non-Inverting input N/C - 1 - No Internal Connection N/C - 5 - No Internal Connection N/C - 8 - No Internal Connection OUT 1 6 I Output V- 2 4 P Negative (lowest) power supply V+ 5 7 P Positive (highest) power supply D or DGK Package 8-Pin Dual SOIC and VSSOP Top View Pin Functions: LMP2012 PIN NAME NO. I/O DESCRIPTION D, DGK -IN A 2 I Inverting input, channel A +IN A 3 I Non-Inverting input, channel A -IN B 6 I Inverting input, channel B +IN B 5 I Non-Inverting input, channel B OUT A 1 O Output, channel A OUT B 7 O Output, channel B V- 4 P Negative (lowest) power supply V+ 8 P Positive (highest) power supply Copyright (c) 2004-2015, Texas Instruments Incorporated Product Folder Links: LMP2011 LMP2012 Submit Documentation Feedback 3 LMP2011, LMP2012 SNOSA71L - OCTOBER 2004 - REVISED SEPTEMBER 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) (2) See MIN MAX UNIT 5.8 V Supply Voltage - Common-Mode Input Voltage (V ) - 0.3 Lead Temperature (soldering 10 sec.) + (V ) + 0.3 V 300 C Differential Input Voltage Supply Voltage Current at Input Pin 30 30 mA Current at Output Pin 30 30 mA Current at Power Supply Pin 50 30 mA Storage Temperature -65 150 C (1) (2) Absolute Maximum Ratings indicate limits beyond which damage may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. 6.2 ESD Ratings VALUE V(ESD) (1) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2000 Machine model 200 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions MIN MAX Supply Voltage 2.7 5.25 UNIT V Operating Temperature Range -40 125 C 6.4 Thermal Information: LMP2011 LMP2011 THERMAL METRIC (1) D (SOIC) DBV (SOT-23) UNIT 8 PINS 5 PINS RJA Junction-to-ambient thermal resistance 119 164 C/W RJC(top) Junction-to-case (top) thermal resistance 66 116 C/W RJB Junction-to-board thermal resistance 60 28 C/W JT Junction-to-top characterization parameter 17 13 C/W JB Junction-to-board characterization parameter 59 27 C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright (c) 2004-2015, Texas Instruments Incorporated Product Folder Links: LMP2011 LMP2012 LMP2011, LMP2012 www.ti.com SNOSA71L - OCTOBER 2004 - REVISED SEPTEMBER 2015 6.5 Thermal Information: LMP2012 LMP2012 THERMAL METRIC (1) D (SOIC) DGK (VSSOP) 8 PINS 8 PINS UNIT RJA Junction-to-ambient thermal resistance 110 157 C/W RJC(top) Junction-to-case (top) thermal resistance 50 51 C/W RJB Junction-to-board thermal resistance 52 77 C/W JT Junction-to-top characterization parameter 8 5 C/W JB Junction-to-board characterization parameter 51 75 C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.6 2.7-V DC Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25C, V+ = 2.7 V, V- = 0 V, V CM = 1.35 V, VO = 1.35 V, and RL > 1 M. PARAMETER VOS Input Offset Voltage (LMP2011 only) TJ = 25C Input Offset Voltage (LMP2012 only) TJ = 25C Offset Calibration Time TCVOS TEST CONDITIONS MIN (1) TYP (2) MAX (1) 0.8 25 The temperature extremes 60 0.8 The temperature extremes 36 UNIT V 60 TJ = 25C 0.5 The temperature extremes 10 12 ms Input Offset Voltage 0.015 V/C Long-Term Offset Drift 0.006 V/month Lifetime VOS Drift 2.5 V IIN Input Current -3 pA IOS Input Offset Current 6 pA RIND Input Differential Resistance 9 CMRR Common Mode Rejection Ratio -0.3 VCM 0.9 V, 0 VCM 0.9 V PSRR Power Supply Rejection Ratio TJ = 25C 95 The temperature extremes 90 RL = 10 k AVOL Open Loop Voltage Gain RL = 2 k (1) (2) TJ = 25C 95 The temperature extremes 90 TJ = 25C 95 The temperature extremes 90 TJ = 25C 90 The temperature extremes 85 M 130 dB 120 dB 130 124 dB Limits are 100% production tested at 25C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method. Typical values represent the most likely parametric norm. Copyright (c) 2004-2015, Texas Instruments Incorporated Product Folder Links: LMP2011 LMP2012 Submit Documentation Feedback 5 LMP2011, LMP2012 SNOSA71L - OCTOBER 2004 - REVISED SEPTEMBER 2015 www.ti.com 2.7-V DC Electrical Characteristics (continued) Unless otherwise specified, all limits ensured for TJ = 25C, V+ = 2.7 V, V- = 0 V, V CM = 1.35 V, VO = 1.35 V, and RL > 1 M. PARAMETER MIN (1) TYP (2) TJ = 25C 2.665 2.68 The temperature extremes 2.655 TEST CONDITIONS RL = 10 k to 1.35 V, VIN(diff) = 0.5 V TJ = 25C MAX (1) 0.033 RL = 2 k to 1.35 V, VIN(diff) = 0.5 V 0.075 TJ = 25C 2.630 The temperature extremes 2.615 TJ = 25C 2.65 0.061 RL = 10 k to 1.35 V, VIN(diff) = 0.5 V 0.105 TJ = 25C 2.64 The temperature extremes 2.63 TJ = 25C 2.68 0.033 0.075 TJ = 25C RL = 2 k to 1.35 V, VIN(diff) = 0.5 V 2.615 The temperature extremes 2.65 2.6 TJ = 25C 0.061 IO Output Current VIN(diff) = 0.5 V, Sinking, VO = 5 V Supply Current per Channel IS V 0.085 The temperature extremes Sourcing, VO = 0 V, VIN(diff) = 0.5 V V 0.060 The temperature extremes Output Swing (LMP2012 only) V 0.085 The temperature extremes VO V 0.060 The temperature extremes Output Swing (LMP2011 only) UNIT 0.105 TJ = 25C 5 The temperature extremes 3 TJ = 25C 5 The temperature extremes 3 TJ = 25C 12 mA 18 0.919 1.20 The temperature extremes 1.50 mA 6.7 2.7-V AC Electrical Characteristics TJ = 25C, V+ = 2.7 V, V- = 0 V, VCM = 1.35 V, VO = 1.35 V, and RL > 1 M. PARAMETER GBW Gain-Bandwidth Product SR Slew Rate m Phase Margin Gm Gain Margin en Input-Referred Voltage Noise enp-p Input-Referred Voltage Noise trec Input Overload Recovery Time (1) (2) 6 MIN (1) TEST CONDITIONS RS = 100 , DC to 10 Hz TYP (2) MAX (1) UNIT 3 MHz 4 V/s 60 Deg -14 dB 35 nV/Hz 850 nVpp 50 ms Limits are 100% production tested at 25C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method. Typical values represent the most likely parametric norm. Submit Documentation Feedback Copyright (c) 2004-2015, Texas Instruments Incorporated Product Folder Links: LMP2011 LMP2012 LMP2011, LMP2012 www.ti.com SNOSA71L - OCTOBER 2004 - REVISED SEPTEMBER 2015 6.8 5-V DC Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25C, V+ = 5 V, V- = 0 V, V CM = 2.5 V, VO = 2.5 V, and RL > 1M. PARAMETER VOS Input Offset Voltage (LMP2011 only) TJ = 25C Input Offset Voltage (LMP2012 only) TJ = 25C Offset Calibration Time TCVOS TEST CONDITIONS MIN (1) TYP (2) MAX (1) 0.12 25 The temperature extremes 60 0.12 The temperature extremes TJ = 25C 0.5 The temperature extremes 0.015 V/C Long-Term Offset Drift 0.006 V/month 2.5 V -3 pA pA IOS Input Offset Current 6 RIND Input Differential Resistance 9 CMRR Common Mode Rejection Ratio PSRR Power Supply Rejection TJ = 25C Ratio The temperature extremes AVOL Open Loop Voltage Gain -0.3 VCM 3.2, 0 VCM 3.2 RL = 10 k RL = 2 k RL = 10 k to 2.5 V, VIN(diff) = 0.5 V TJ = 25C The temperature extremes 100 RL = 2 k to 2.5 V, VIN(diff) = 0.5 V RL = 10 k to 2.5 V, VIN(diff) = 0.5 V 95 120 RL = 2 k to 2.5 V, VIN(diff) = 0.5 V TJ = 25C 105 The temperature extremes 100 TJ = 25C 95 The temperature extremes 90 TJ = 25C 4.96 The temperature extremes 4.95 TJ = 25C 130 Supply Current per Channel 4.978 0.040 4.895 The temperature extremes 4.875 TJ = 25C V 4.919 0.091 0.115 V 0.140 TJ = 25C 4.92 The temperature extremes 4.91 TJ = 25C 4.978 0.040 0.080 V 0.095 TJ = 25C 4.875 The temperature extremes 4.855 TJ = 25C 4.919 0.0.91 0.125 V 0.150 Sourcing, VO = 0 V, VIN(diff) = 0.5 V TJ = 25C 8 The temperature extremes 6 Sinking, VO = 5 V, VIN(diff) = 0.5 V TJ = 25C 8 The temperature extremes 6 15 mA 17 0.930 The temperature extremes 0.070 0.085 TJ = 25C TJ = 25C dB 132 The temperature extremes Output Current dB 90 The temperature extremes Output Swing (LMP2012 only) dB 90 The temperature extremes VO M 130 The temperature extremes Output Swing (LMP2011 only) (2) ms Input Offset Voltage Input Current (1) 10 12 IIN IS V 36 60 Lifetime VOS Drift IO UNIT 1.20 1.50 mA Limits are 100% production tested at 25C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method. Typical values represent the most likely parametric norm. Copyright (c) 2004-2015, Texas Instruments Incorporated Product Folder Links: LMP2011 LMP2012 Submit Documentation Feedback 7 LMP2011, LMP2012 SNOSA71L - OCTOBER 2004 - REVISED SEPTEMBER 2015 www.ti.com 6.9 5-V AC Electrical Characteristics TJ = 25C, V+ = 5 V, V- = 0 V, VCM = 2.5 V, VO = 2.5 V, and RL > 1M. PARAMETER MIN (1) TEST CONDITIONS TYP (2) MAX (1) UNIT GBW Gain-Bandwidth Product 3 MHz SR Slew Rate 4 V/s m Phase Margin 60 deg Gm Gain Margin -15 dB en Input-Referred Voltage Noise enp-p Input-Referred Voltage Noise trec Input Overload Recovery Time (1) (2) 8 RS = 100 , DC to 10 Hz 35 nV/Hz 850 nVpp 50 ms Limits are 100% production tested at 25C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method. Typical values represent the most likely parametric norm. Submit Documentation Feedback Copyright (c) 2004-2015, Texas Instruments Incorporated Product Folder Links: LMP2011 LMP2012 LMP2011, LMP2012 www.ti.com SNOSA71L - OCTOBER 2004 - REVISED SEPTEMBER 2015 6.10 Typical Characteristics TA=25C, VS= 5 V unless otherwise specified. Figure 1. Supply Current vs Supply Voltage Figure 2. Offset Voltage vs Supply Voltage Figure 3. Offset Voltage vs Common Mode Figure 4. Offset Voltage vs Common Mode 500 10000 VS = 5V 400 300 BIAS CURRENT (pA) VOLTAGE NOISE (nV/ Hz) VS = 5V 1000 100 200 100 0 -100 -200 -300 -400 10 0.1 1 10 100 1k 10k 100k 1M -500 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VCM (V) FREQUENCY (Hz) Figure 5. Voltage Noise vs Frequency Figure 6. Input Bias Current vs Common Mode Copyright (c) 2004-2015, Texas Instruments Incorporated Product Folder Links: LMP2011 LMP2012 Submit Documentation Feedback 9 LMP2011, LMP2012 SNOSA71L - OCTOBER 2004 - REVISED SEPTEMBER 2015 www.ti.com Typical Characteristics (continued) TA=25C, VS= 5 V unless otherwise specified. 120 120 VS = 2.7V 80 VCM = 2.5V 100 80 NEGATIVE PSRR (dB) PSRR (dB) VS = 5V VCM = 1V 100 60 40 NEGATIVE 60 40 POSITIVE POSITIVE 20 20 0 0 10 10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 7. PSRR vs Frequency Figure 8. PSRR vs Frequency Figure 9. Output Sourcing at 2.7 V Figure 10. Output Sourcing at 5 V Figure 11. Output Sinking at 2.7 V Figure 12. Output Sinking at 5 V Submit Documentation Feedback Copyright (c) 2004-2015, Texas Instruments Incorporated Product Folder Links: LMP2011 LMP2012 LMP2011, LMP2012 www.ti.com SNOSA71L - OCTOBER 2004 - REVISED SEPTEMBER 2015 Typical Characteristics (continued) TA=25C, VS= 5 V unless otherwise specified. Figure 13. Maximum Output Swing vs Supply Voltage Figure 14. Maximum Output Swing vs Supply Voltage Figure 15. Minimum Output Swing vs Supply Voltage Figure 16. Minimum Output Swing vs Supply Voltage 100 140 150.0 VS = 5V VS = 5V 120 80 120.0 PHASE 80 60 90.0 60.0 40 GAIN 30.0 20 40 PHASE () VS = 5V 60 GAIN (dB) CMRR (dB) 100 RL = 1M 0 20 0.0 VS = 2.7V CL = < 20pF VS = 2.7V OR 5V -20 0 10 100 100k 1k FREQUENCY (Hz) Figure 17. CMRR vs Frequency 100k 100 1k 10k 100k 1M -30.0 10M FREQUENCY (Hz) Figure 18. Open Loop Gain and Phase vs Supply Voltage Copyright (c) 2004-2015, Texas Instruments Incorporated Product Folder Links: LMP2011 LMP2012 Submit Documentation Feedback 11 LMP2011, LMP2012 SNOSA71L - OCTOBER 2004 - REVISED SEPTEMBER 2015 www.ti.com Typical Characteristics (continued) TA=25C, VS= 5 V unless otherwise specified. 100 150.0 100 120.0 80 150.0 RL = >1M 80 120.0 PHASE PHASE 60.0 40 30.0 20 VS = 5V VS = 2.7V 0.0 CL = < 20 pF RL = >1M & 2k -30.0 10M 1M 100 100k 10k 1k Figure 19. Open Loop Gain and Phase vs RL at 2.7 V Figure 20. Open Loop Gain and Phase vs RL at 5 V 150.0 100 150.0 10pF 10pF 80 120.0 80 120.0 PHASE PHASE 60.0 40 GAIN 30.0 20 CL = 10,50,200 & 500pF 100k 10k 1k FREQUENCY (Hz) 0.0 VS = 5V, RL = >1M 500pF 113 100 90 80 113 PHASE PHASE -40C -40C 90 -40C -40C 68 45 85C 20 VS = 2.7V 0 RL = >1M 85C 23 VOUT = 200 mVPP 0 GAIN (dB) GAIN 25C 10k GAIN 40 85C 20 VS = 5V VOUT = 200 mVPP 0 RL = >1M 23 0 CL = < 20pF 100k 1M -23 10M -20 1k 10k FREQUENCY (Hz) Submit Documentation Feedback 100k 1M -23 10M FREQUENCY (Hz) Figure 23. Open Loop Gain and Phase vs Temperature at 2.7 V 12 45 25C 85C CL = < 20 pF -20 1k 68 60 PHASE () GAIN (dB) 60 40 -30.0 10M Figure 22. Open Loop Gain and Phase vs CL at 5 V Figure 21. Open Loop Gain and Phase vs CL at 2.7 V 100 30.0 CL = 10,50,200 & 500pF -20 100 1M 1k 10k 100k FREQUENCY (Hz) -30.0 10M 1M GAIN 0 500pF -20 60.0 500pF 20 0.0 VS = 2.7V, RL = >1M 40 90.0 PHASE () 500pF 10pF 60 90.0 GAIN (dB) 10pF PHASE () GAIN (dB) 60 80 1M FREQUENCY (Hz) 100 100 -30.0 10M -20 FREQUENCY (Hz) 0 0.0 RL = >1M & 2k 100k 10k 1k RL = 2k CL = < 20 pF RL = 2k -20 100 0 PHASE () 0 60.0 RL = >1M GAIN 30.0 20 90.0 RL = >1M PHASE () RL = >1M GAIN (dB) GAIN (dB) GAIN 40 60 90.0 PHASE () RL = 2k 60 Figure 24. Open Loop Gain and Phase vs Temperature at 5 V Copyright (c) 2004-2015, Texas Instruments Incorporated Product Folder Links: LMP2011 LMP2012 LMP2011, LMP2012 www.ti.com SNOSA71L - OCTOBER 2004 - REVISED SEPTEMBER 2015 Typical Characteristics (continued) TA=25C, VS= 5 V unless otherwise specified. 10 10 MEAS FREQ = 1 KHz MEAS BW = 22 KHz VOUT = 2 VPP MEAS BW = 500 kHz RL = 10k RL = 10k 1 1 AV = +10 THD+N (%) THD+N (%) AV = +10 VS = 2.7V 0.1 VS = 2.7V VS = 5V 0.1 VS = 5V VS = 5V VS = 2.7V 0.01 1 10 100 10 1k 10k OUTPUT VOLTAGE (VPP) FREQUENCY (Hz) Figure 25. THD+N vs AMPL Figure 26. THD+N vs Frequency 100k NOISE (200 nV/DIV) 0.01 0.1 1 sec/DIV Figure 27. 0.1 Hz - 10 Hz Noise vs Time Copyright (c) 2004-2015, Texas Instruments Incorporated Product Folder Links: LMP2011 LMP2012 Submit Documentation Feedback 13 LMP2011, LMP2012 SNOSA71L - OCTOBER 2004 - REVISED SEPTEMBER 2015 www.ti.com 7 Detailed Description 7.1 Overview The LMP201x series offers unprecedented accuracy and stability in space-saving miniature packaging while also being offered at an affordable price. This device utilizes patented techniques to measure and continually correct the input offset error voltage. The result is an amplifier which is ultra stable over time and temperature. 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 How the LMP201x Works The LMP201x uses new, patented auto-zero techniques to achieve the high DC accuracy traditionally associated with chopper-stabilized amplifiers without the major drawbacks produced by chopping. The LMP201x continuously monitors the input offset and corrects this error. The conventional low-frequency chopping process produces many mixing products, both sums and differences, between the chopping frequency and the incoming signal frequency. This mixing causes large amounts of distortion, particularly when the signal frequency approaches the chopping frequency. Even without an incoming signal, the chopper harmonics mix with each other to produce even more trash. If this sounds unlikely or difficult to understand, look at the plot (Figure 28), of the output of a typical (MAX432) chopper-stabilized op amp. This is the output when there is no incoming signal, just the amplifier in a gain of -10 with the input grounded. The chopper is operating at about 150 Hz; the rest is mixing products. Add an input signal and the noise gets much worse. Compare this plot with Figure 29 of the LMP201x. This data was taken under the exact same conditions. The auto-zero action is visible at about 30 kHz but note the absence of mixing products at other frequencies. As a result, the LMP201x has very low distortion of 0.02% and very low mixing products. 10000 VOLTAGE NOISE (nV/ Hz) VS = 5V 1000 100 10 0.1 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 28. The Output of a Chopper Stabilized Op Amp (MAX432) 14 Submit Documentation Feedback Figure 29. The Output of the LMP2011/LMP2012 Copyright (c) 2004-2015, Texas Instruments Incorporated Product Folder Links: LMP2011 LMP2012 LMP2011, LMP2012 www.ti.com SNOSA71L - OCTOBER 2004 - REVISED SEPTEMBER 2015 Feature Description (continued) 7.3.2 The Benefits of LMP201x: No 1/F Noise Using patented methods, the LMP201x eliminates the 1/f noise present in other amplifiers. This noise, which increases as frequency decreases, is a major source of measurement error in all DC-coupled measurements. Low-frequency noise appears as a constantly-changing signal in series with any measurement being made. As a result, even when the measurement is made rapidly, this constantly-changing noise signal will corrupt the result. The value of this noise signal can be surprisingly large. For example: If a conventional amplifier has a flat-band noise level of 10 nV/Hz and a noise corner of 10 Hz, the RMS noise at 0.001 Hz is 1 V/Hz. This is equivalent to a 0.50-V peak-to-peak error, in the frequency range 0.001 Hz to 1.0 Hz. In a circuit with a gain of 1000, this produces a 0.50-mV peak-to-peak output error. This number of 0.001 Hz might appear unreasonably low, but when a data acquisition system is operating for 17 minutes, it has been on long enough to include this error. In this same time, the LMP201x will only have a 0.21-mV output error. This is smaller by 2.4x. This 1/f error gets even larger at lower frequencies. At the extreme, many people try to reduce this error by integrating or taking several samples of the same signal. This is also doomed to failure because the 1/f nature of this noise means that taking longer samples just moves the measurement into lower frequencies where the noise level is even higher. The LMP201x eliminates this source of error. The noise level is constant with frequency so that reducing the bandwidth reduces the errors caused by noise. 7.3.3 No External Capacitors Required The LMP201x does not need external capacitors. This eliminates the problems caused by capacitor leakage and dielectric absorption, which can cause delays of several seconds from turn-on until the amplifier's error has settled. 7.3.4 Copper Leadframe Another source of error that is rarely mentioned is the error voltage caused by the inadvertent thermocouples created when the common Kovar type IC package lead materials are soldered to a copper printed circuit board. These steel-based leadframe materials can produce over 35 V/C when soldered onto a copper trace. This can result in thermocouple noise that is equal to the LMP201x noise when there is a temperature difference of only 0.0014C between the lead and the board! For this reason, the lead-frame of the LMP201x is made of copper. This results in equal and opposite junctions which cancel this effect. The extremely small size of the SOT-23 package results in the leads being very close together. This further reduces the probability of temperature differences and hence decreases thermal noise. 7.3.5 More Benefits The LMP201x offers the benefits mentioned above and more. It has a rail-to-rail output and consumes only 950 A of supply current while providing excellent DC and AC electrical performance. In DC performance, the LMP201x achieves 130 dB of CMRR, 120 dB of PSRR, and 130 dB of open loop gain. In AC performance, the LMP201x provides 3 MHz of gain-bandwidth product and 4 V/s of slew rate. 7.4 Device Functional Modes 7.4.1 Input Currents The LMP201x input currents are different than standard bipolar or CMOS input currents. Due to the auto-zero action of the input stage, the input current appears as a pulsating current at the chopping frequency (35 kHz) flowing in one input and out the other. Under most operating conditions, these currents are in the picoamp level and will have little or no effect in most circuits. These currents tend to increase slightly when the common-mode voltage is near the minus supply. (See the Typical Characteristics.) At high temperatures such as 85C, the input currents become larger, 0.5 nA typical, and are both positive except when the VCM is near V-. If operation is expected at low common-mode voltages and high temperature, do not add resistance in series with the inputs to balance the impedances. Doing this can cause an increase in offset voltage. A small resistance such as 1 k can provide some protection against very large transients or overloads, and will not increase the offset significantly. Copyright (c) 2004-2015, Texas Instruments Incorporated Product Folder Links: LMP2011 LMP2012 Submit Documentation Feedback 15 LMP2011, LMP2012 SNOSA71L - OCTOBER 2004 - REVISED SEPTEMBER 2015 www.ti.com Device Functional Modes (continued) Because of these issues, the LMV201x is not recommended for source impedances over 1M. 7.4.2 Overload Recovery The LMP201x recovers from input overload much faster than most chopper-stabilized op amps. Recovery from driving the amplifier to 2X the full scale output, only requires about 40 ms. Many chopper-stabilized amplifiers will take from 250 ms to several seconds to recover from this same overload. This is because large capacitors are used to store the unadjusted offset voltage. Figure 30. Overload Recovery Test Circuit The wide bandwidth of the LMP201x enhances performance when it is used as an amplifier to drive loads that inject transients back into the output. ADCs (Analog-to-Digital Converters) and multiplexers are examples of this type of load. To simulate this type of load, a pulse generator producing a 1-V peak square wave was connected to the output through a 10-pF capacitor. (Figure 30) The typical time for the output to recover to 1% of the applied pulse is 80 ns. To recover to 0.1% requires 860 ns. This rapid recovery is due to the wide bandwidth of the output stage and large total GBW. 16 Submit Documentation Feedback Copyright (c) 2004-2015, Texas Instruments Incorporated Product Folder Links: LMP2011 LMP2012 LMP2011, LMP2012 www.ti.com SNOSA71L - OCTOBER 2004 - REVISED SEPTEMBER 2015 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LMV201x family offers excellent dc precision and ac performance. These devices offer true rail-to-rail output, ultralow offset voltage and offset voltage drift over the entire -40 to 125C temperature range, as well as 3-MHz bandwidth and no 1/f noise. These features make the LMV201x a robust, high performance operational amplifier ideal for industrial applications. 8.2 Typical Applications 8.2.1 Extending Supply Voltages and Output Swing with a Composite Amplifier C2 R2 R7, 3.9k R1 2 7 LMP201X 3 U1 + 4 Input (-0.7V) C5 0.01 PF Figure 31. Inverting Composite Amplifier +15V 1N4731A (4.3V) D1 C4 0.01 PF 3 6 -15V R6 10k +15V R3 20k D2 R4 1N4148 3.9k 7 + LM6171 2 U2 4 6 Output (+2.5V) R5, 1M C3 0.01 PF Figure 32. Non-Inverting Composite Amplifier 8.2.1.1 Design Requirements In cases where substantially higher output swing is required with higher supply voltages, arrangements like the ones shown in Figure 31 and Figure 32 could be used. These configurations utilize the excellent DC performance of the LMP201x while at the same time allow the superior voltage and frequency capabilities of the LM6171 to set the dynamic performance of the overall amplifier. For example, it is possible to achieve 12-V output swing with 300 MHz of overall GBW (AV = 100) while keeping the worst case output shift due to VOS less than 4 mV. 8.2.1.2 Detailed Design Procedure The LMP201x output voltage is kept at about mid-point of its overall supply voltage, and its input common mode voltage range allows the V- terminal to be grounded in one case (Figure 31, inverting operation) and tied to a small non-critical negative bias in another (Figure 32, non-inverting operation). Higher closed-loop gains are also possible with a corresponding reduction in realizable bandwidth. Table 1 shows some other closed loop gain possibilities along with the measured performance in each case. In terms of the measured output peak-to-peak noise, the following relationship holds between output noise voltage, en p-p, for different closed-loop gain, AV, settings, where -3 dB Bandwidth is BW: Copyright (c) 2004-2015, Texas Instruments Incorporated Product Folder Links: LMP2011 LMP2012 Submit Documentation Feedback 17 LMP2011, LMP2012 SNOSA71L - OCTOBER 2004 - REVISED SEPTEMBER 2015 www.ti.com Typical Applications (continued) enpp1 enpp2 = BW1 A V 1 * BW2 A V 2 (1) It should be kept in mind that in order to minimize the output noise voltage for a given closed-loop gain setting, one could minimize the overall bandwidth. As can be seen from Equation 1 above, the output noise has a square-root relationship to the Bandwidth. In the case of the inverting configuration, it is also possible to increase the input impedance of the overall amplifier, by raising the value of R1, without having to increase the feed-back resistor, R2, to impractical values, by utilizing a "Tee" network as feedback. See the LMC6442 data sheet (Application Notes section) for more details on this. 8.2.1.3 Application Results Table 1 shows the results using various gains and compensation values. Table 1. Composite Amplifier Measured Performance AV R1 () R2 () C2 (pF) BW (MHz) SR (V/s) en p-p (mVPP) 50 200 10k 8 3.3 178 37 100 100 10k 10 2.5 174 70 100 1k 100k 0.67 3.1 170 70 500 200 100k 1.75 1.4 96 250 1000 100 100k 2.2 0.98 64 400 8.2.2 Precision Strain-gauge Amplifier 5V + VOUT + R1 R2 10k, 0.1% 2k, 1% R3 R2 R1 2k, 1% 10k, 0.1% 20: Figure 33. Precision Strain Gauge Amplifier This Strain-Gauge amplifier (Figure 33) provides high gain (1006 or ~60 dB) with very low offset and drift. Using the resistors' tolerances as shown, the worst case CMRR will be greater than 108 dB. The CMRR is directly related to the resistor mismatch. The rejection of common-mode error, at the output, is independent of the differential gain, which is set by R3. The CMRR is further improved, if the resistor ratio matching is improved, by specifying tighter-tolerance resistors, or by trimming. 18 Submit Documentation Feedback Copyright (c) 2004-2015, Texas Instruments Incorporated Product Folder Links: LMP2011 LMP2012 LMP2011, LMP2012 www.ti.com SNOSA71L - OCTOBER 2004 - REVISED SEPTEMBER 2015 8.2.3 ADC Input Amplifier Figure 34. DC Coupled ADC Driver The LMP201x is a great choice for an amplifier stage immediately before the input of an ADC (Analog-to-Digital Converter). See Figure 34. This is because of the following important characteristics: * Very low offset voltage and offset voltage drift over time and temperature allow a high closed-loop gain setting without introducing any short-term or long-term errors. For example, when set to a closed-loop gain of 100 as the analog input amplifier for a 12-bit A/D converter, the overall conversion error over full operation temperature and 30 years life of the part (operating at 50C) would be less than 5 LSBs. * Fast large-signal settling time to 0.01% of final value (1.4 s) allows 12 bit accuracy at 100 KHZ or more sampling rate * No flicker (1/f) noise means unsurpassed data accuracy over any measurement period of time, no matter how long. Consider the following op amp performance, based on a typical low-noise, high-performance commercially-available device, for comparison: - Op amp flatband noise = 8 nV/Hz - 1/f corner frequency = 100 Hz - AV = 2000 - Measurement time = 100 sec - Bandwidth = 2 Hz * This example will result in about 2.2 mVPP (1.9 LSB) of output noise contribution due to the op amp alone, compared to about 594 VPP (less than 0.5 LSB) when that op amp is replaced with the LMP201x which has no 1/f contribution. If the measurement time is increased from 100 seconds to 1 hour, the improvement realized by using the LMP201x would be a factor of about 4.8 times (2.86 mVPP compared to 596 V when LMP201x is used) mainly because the LMP201x accuracy is not compromised by increasing the observation time. * Copper leadframe construction minimizes any thermocouple effects which would degrade low level/high gain data conversion application accuracy (see discussion under The Benefits of the LMP201X section above). * Rail-to-Rail output swing maximizes the ADC dynamic range in 5-Volt single-supply converter applications. Below is a typical block diagram showing the LMP201x used as an ADC amplifier (Figure 34). Copyright (c) 2004-2015, Texas Instruments Incorporated Product Folder Links: LMP2011 LMP2012 Submit Documentation Feedback 19 LMP2011, LMP2012 SNOSA71L - OCTOBER 2004 - REVISED SEPTEMBER 2015 www.ti.com 9 Power Supply Recommendations The LMP201x is specified for operation from 2.7 V to 5.25 V (1.35 V to 2.625 V) over a -40C to +125C temperature range. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in the Typical Characteristics. For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines, TI recommends that 10-nF capacitors be placed as close as possible to the op amp power supply pins. For single supply, place a capacitor between V+ and V- supply leads. For dual supplies, place one capacitor between V+ and ground, and one capacitor between V- and ground. CAUTION Supply voltages larger than 6 V can permanently damage the device. 10 Layout 10.1 Layout Guidelines For best operational performance of the device, use good printed circuit board (PCB) layout practices, including: * Connect low-ESR, 0.1-F ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single supply applications. * Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. * Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds paying attention to the flow of the ground current. For more detailed information refer to SLOA089, Circuit Board Layout Techniques. * In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace. * Place the external components as close to the device as possible. As shown in Layout Example, keeping RF and RG close to the inverting input minimizes parasitic capacitance. * Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit. 20 Submit Documentation Feedback Copyright (c) 2004-2015, Texas Instruments Incorporated Product Folder Links: LMP2011 LMP2012 LMP2011, LMP2012 www.ti.com SNOSA71L - OCTOBER 2004 - REVISED SEPTEMBER 2015 10.2 Layout Example Figure 35. Single Non-Inverting Amplifier Example Layout Copyright (c) 2004-2015, Texas Instruments Incorporated Product Folder Links: LMP2011 LMP2012 Submit Documentation Feedback 21 LMP2011, LMP2012 SNOSA71L - OCTOBER 2004 - REVISED SEPTEMBER 2015 www.ti.com 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support LMP2011/12 PSPICE Model, SNOM113 TINA-TI SPICE-Based Analog Simulation Program, http://www.ti.com/tool/tina-ti TI Filterpro Software, http://www.ti.com/tool/filterpro DIP Adapter Evaluation Module, http://www.ti.com/tool/dip-adapter-evm TI Universal Operational Amplifier Evaluation Module, http://www.ti.com/tool/opampevm Manual for LMH730268 Evaluation board 551012922-001 11.2 Documentation Support 11.2.1 Related Documentation For related documentation, see the following: * SBOA015 (AB-028), Feedback Plots Define Op Amp AC Performance * SLOA089, Circuit Board Layout Techniques * SLOD006, Op Amps for Everyone * TIPD128, Capacitive Load Drive Solution using an Isolation Resistor * SBOA092, Handbook of Operational Amplifier Applications 11.3 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 2. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY LMP2011 Click here Click here Click here Click here Click here LMP2012 Click here Click here Click here Click here Click here 11.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.5 Trademarks LMP, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 11.6 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 22 Submit Documentation Feedback Copyright (c) 2004-2015, Texas Instruments Incorporated Product Folder Links: LMP2011 LMP2012 LMP2011, LMP2012 www.ti.com SNOSA71L - OCTOBER 2004 - REVISED SEPTEMBER 2015 11.7 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright (c) 2004-2015, Texas Instruments Incorporated Product Folder Links: LMP2011 LMP2012 Submit Documentation Feedback 23 PACKAGE OPTION ADDENDUM www.ti.com 23-Aug-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LMP2011MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMP20 11MA LMP2011MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMP20 11MA LMP2011MF NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 125 AN1A LMP2011MF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AN1A LMP2011MFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AN1A LMP2012MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMP20 12MA LMP2012MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMP20 12MA LMP2012MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AP1A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 23-Aug-2017 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMP2011MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMP2011MF SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMP2011MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMP2011MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMP2012MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMP2012MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMP2011MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMP2011MF SOT-23 DBV 5 1000 210.0 185.0 35.0 LMP2011MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMP2011MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LMP2012MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMP2012MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 MAX 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/C 04/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 MAX 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/C 04/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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