Standard Products UT8R256K16 256K x 16 SRAM Advanced Data Sheet October 9, 2002 FEATURES q 15ns maximum access time q Asynchronous operation, functionally compatible with industry-standard 256K x 16 SRAMs q CMOS compatible inputs and output levels, three-state bidirectional data bus - I/O Voltage 2.5 to 3.3 volts, 1.8 volt core q Radiation performance - Intrinsic total-dose: 100K rad(Si) INTRODUCTION The UT8R256K16 is a high-performance CMOS static RAM organized as 262,144 words by 16 bits. Easy memory expansion is provided by active LOW and HIGH chip enables ( E1, E2), an active LOW output enable (G), and three-state drivers. This device has a power-down feature that reduces power consumption by more than 90% when deselected. T EN PM The 16 input/output pins (DQ0 through DQ15) are placed in a high impedance state when the device is deselected (E1 HIGH or E2 LOW), the outputs are disabled (G HIGH), or during a write operation (E1 LOW, E2 HIGH and W LOW). EL O - SEL Immune >100 MeV-cm2 /mg - Onset LET > 24 MeV-cm2 /mg - Memory Cell Saturated Cross Section, 1.0 x 10-8 cm2/bit - 1.0E x 10-10 errors/bit-day, Adams to 90% geosynchronous heavy ion - Neutron Fluence: 3.0E14n/cm 2 - Dose Rate (estimated) - Upset 1.0E9 rad(Si)/sec - Latchup >1.0E11 rad(Si)/sec q Packaging options: - TBD q Standard Microcircuit Drawing pending - QML compliant part Writing to the device is accomplished by taking chip enable one (E1) input LOW, chip enable two (E2) HIGH and write enable (W) input LOW. Data on the 16 I/O pins (DQ0 through DQ15) is then written into the location specified on the address pins (A0 through A17). Reading from the device is accomplished by taking chip enable one (E1) and output enable (G) LOW while forcing write enable (W) and chip enable two (E2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. A0 A1 W E1 Pre-Charge Circuit A2 E2 EV A3 BHE Memory Array 256K x 16 BLE Row Select A4 A5 D A6 IN G DQ(7) to DQ(0) * * * DQ(15) to DQ(8) * * * A7 I/O Circuit A8 A9 Low Byte Read Circuit Column Select Data Control Data Control A10 A11 A12 A13A14 A15 A16 A17 High Byte Read Circuit Figure 1. UT8R256K16 SRAM Block Diagram 1 DEVICE OPERATION 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC A17 A16 A15 /G /BHE /BLE DQ15 DQ14 DQ13 DQ12 VSS VDD2 DQ11 DQ10 DQ9 DQ8 E2 A14 A13 A12 A11 A10 VDD1 The UT8R256K16 has four control inputs called Enable 1 ( E1), Enable 2 (E2), Write Enable (W), Half-word Enables (BLE/ BHE) and Output Enable (G); 18 address inputs, A(17:0); and 16 bidirectional data lines, DQ(15:0). E1 and E2 device enables control device selection, active, and standby modes. Asserting E1 and E2 enables the device, causes I DD to rise to its active value, and decodes the 18 address inputs to select one of 262,144 words in the memory. W controls read and write operations. During a read cycle, G must be asserted to enable the outputs. Table 1. Device Operation Truth Table Figure 2. 15ns SRAM Pinout G W E2 E1 BLE BHE X X X H X X DQ(15:8) 3-State DQ(7:0) 3-State Standby X X L X X X DQ(15:8) 3-State DQ(7:0) 3-State Standby L H H L T 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 H DQ(15:8) 3-State DQ(7:0) Data Out Low Byte Read L H A(17:0) Address Input W Write Enable G Output Enable DQ(15:0) Data Input/Output Enable (Active Low) V DD1 Power (1.8V) E2 Enable (Active High) V DD2 Power (2.5V) VSS D Mode H L DQ(15:8) Data Out DQ(7:0) 3-State High Byte Read L H H L L L DQ(15:8) Data Out DQ(7:0) Data Out Word Read X L H L L L DQ(15:8) Data In DQ(7:0) Data In Word Write X L H L L H DQ(15:8) 3-State DQ(7:0) Data In Low Byte Write X L H L H L DQ(15:8) Data In DQ(7:0) 3-State High Byte Write H H H L X X DQ(15:8) DQ(7:0) All 3-State 3-State X X H L H H DQ(15:8) DQ(7:0) All 3-State 3-State Notes: 1. "X" is defined as a "don't care" condition. 2. Device active; outputs disabled. 2 I/O Mode L Ground EV Low and high byte enable IN BHE and BLE EL O E1 H PM PIN NAMES L EN VDD1 A0 A1 A2 A3 A4 /E1 DQ0 DQ1 DQ2 DQ3 VDD2 VSS DQ4 DQ5 DQ6 DQ7 /W A5 A6 A7 A8 A9 NC READ CYCLE high-impedance state by G, the user must wait tWLQZ before applying data to the sixteen bidirectional pins DQ(15:0) to avoid bus contention. A combination of W and E2 greater than VIH (min) and E1 less than VIL (max) defines a read cycle. Read access time is measured from the latter of device enable, output enable, or valid address to valid data output. BYTE ENABLES Separate byte enable controls (BLE and BHE) allow individual bytes to be accessed. BLE controls the lower bits DQ(7:0). BHE controls the upper bits DQ(15:8). Writing to the device is performed by asserting E1, E2 and the byte enables. Reading the device is performed by asserting E1, E2, G, and the byte enables while W is held inactive (HIGH). BLE OPERATION 0 0 16-bit read or write cycle 0 1 8-bit high byte read or write cycle (low byte bi-direction pins DQ(7:0) are in 3 -state) 1 0 8-bit low byte read or write cycle (high byte bi-direction pins DQ(15:8) are in 3 -state) PM EN SRAM Read Cycle 2, the Chip Enable-controlled Access in Figure 3b, is initiated by the latter of E1 and E2 going active while G remains asserted, W remains deasserted, and the addresses remain stable for the entire cycle. After the specified tETQV is satisfied, the 16-bit word addressed by A(17:0) is accessed and appears at the data outputs DQ(15:0). BHE T SRAM Read Cycle 1, the Address Access in Figure 3a, is initiated by a change in address inputs while the chip is enabled with G asserted and W deasserted. Valid data appears on data outputs DQ(15:0) after the specified tAVQV is satisfied. Outputs remain active throughout the entire cycle. As long as device enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle time (tAVAV ). SRAM Read Cycle 3, the Output Enable-controlled Access in Figure 3c, is initiated by G going active while E1 and E2 are asserted, W is deasserted, and the addresses are stable. Read access time is tGLQV unless t AVQV or tETQV have not been satisfied. 1 1 High and Low byte bi-directional pins remain in 3-state, write function disabled RADIATION HARDNESS Write Cycle The UT8R256K16 SRAM incorporates special design, layout, and process features which allows operation in a limited radiation environment. EL O A combination of W and E1 less than V IL (max) and E2 greater than VIH (min) defines a write cycle. The state of G is a "don't care" for a write cycle. The outputs are placed in the high-impedance state when eitherG is greater than V IH(min), or when W is less than VIL(max). EV Table 2. Radiation Hardness Design Specifications 1 Write Cycle 1, the Write Enable-controlled Access in Figure 4a, is defined by a write terminated by W going high, with E1 and E2 still active. The write pulse width is defined by tWLWH when the write is initiated by W, and by t ETWH when the write is initiated by E1 or E2. Unless the outputs have been previously placed in the high-impedance state byG, the user must wait user must wait tWLQZ before applying data to the 16 bidirectional pins DQ(15:0) to avoid bus contention. Total Dose 100K rad(Si) Heavy Ion Error Rate2 1.0E-10 Errors/Bit-Day D Notes: 1. The SRAM is immune to latchup to particles of 128MeV-cm 2/mg. 2. 10% worst case particle environment, Geosynchronous orbit, 0.025 mils of Aluminum. IN Supply Sequencing No supply voltage sequencing is required between V DD1 and V DD2 . Write Cycle 2, the Chip Enable-controlled Access in Figure 4b, is defined by a write terminated by the latter of E1 or E2 going inactive. The write pulse width is defined by tWLEF when the write is initiated byW, and by t ETEF when the write is initiated by either E1or E2 going active. For the W initiated write, unless the outputs have been previously placed in the 3 ABSOLUTE MAXIMUM RATINGS1 (Referenced to VSS ) SYMBOL PARAMETER LIMITS V DD1 DC supply voltage -0.3 to 2.0V V DD2 DC supply voltage -0.3 to 3.8V V I/O Voltage on any pin -0.3 to 3.8V TSTG Storage temperature -65 to +150C PD Maximum power dissipation TJ Maximum junction temperature +150C Thermal resistance, junction-to-case2 5C/W DC input current 5 mA JC II 1.2W RECOMMENDED OPERATING CONDITIONS SYMBOL PM EN T Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 3. Test per MIL-STD-883, Method 1012. PARAMETER Positive supply voltage V DD2 Positive supply voltage TC Case temperature range VIN DC input voltage 1.7 to 1.9V 2.25 to 3.6V IN D EV EL O V DD1 LIMITS 4 -55 to +125C 0V to V DD2 DC ELECTRICAL CHARACTERISTICS (Pre and Post-Radiation)* (-55C to +125C) SYMBOL PARAMETER CONDITION MIN MAX .7*VDD2 UNIT V IH High-level input voltage V V IL Low-level input voltage V OL1 Low-level output voltage IOL = 8mA,V DD2 =VDD2 (min) VOH1 High-level output voltage IOH = -4mA,VDD2 =V DD2 (min) CIN 1 Input capacitance = 1MHz @ 0V 7 pF CIO 1 Bidirectional I/O capacitance = 1MHz @ 0V 7 pF IIN Input leakage current VIN = V DD2 and VSS -2 2 A I OZ Three-state output leakage current VO = VDD2 and V SS -2 2 A -100 +100 mA 1 mA 55 mA TBD mA TBD mA 50 mA 55 mA .3*VDD2 V .2*VDD2 V .8*VDD2 V VDD2 = VDD2 (max), G = VDD2 (max) Short-circuit output current VDD2 = VDD2 (max), V O = VDD2 IDD1 (OP1 ) Supply current operating @ 1MHz PM EN VDD2 = VDD2 (max), V O = VSS T IOS 2, 3 Inputs : VIL = V SS + 0.2V, VIH = V DD2 + 0.2V , I OUT = 0 VDD1 = V DD1 (max), V DD2 = VDD2 (max) IDD1 (OP2 ) Supply current operating @100MHz, Inputs : VIL = V SS + 0.2V, VIH = V DD2 + 0.2V, IOUT = 0 IDD2 (OP1 ) Supply current operating @ 1MHz EL O VDD1 = V DD1 (max), V DD2 = VDD2 (max) Inputs : VIL = V SS + 0.2V, VIH = V DD2 + 0.2V , I OUT = 0 VDD1 = V DD1 (max), V DD2 = VDD2 (max) Supply current operating @100MHz, Inputs : VIL = V SS + 0.2V, EV IDD2 (OP2 ) VIH = V DD2 + 0.2V, IOUT = 0 VDD1 = V DD1 (max), V DD2 = VDD2 (max) IDD(SB)4 D Supply current standby @0Hz IN IDD(SB)4 Total Supply current standby A(17:0) @ 10MHz CMOS inputs , IOUT = 0 E1 = V DD2 , E2 = GND VDD1 = V DD1 (max), V DD2 = VDD2 (max) CMOS inputs , IOUT = 0 E1 = V DD2 - 0.5, E2 = GND, VDD1 = V DD1 (max), V DD2 = VDD2 (max) Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019 at 1.0E5 rad(Si). 1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance. 2. Supplied as a design limit but not guaranteed or tested. 3. Not more than one output may be shorted at a time for maximum duration of one second. 4. VIH = V DD2 (max), VIL = 0V. 5 AC CHARACTERISTICS READ CYCLE (Pre and Post-Radiation)* (-55C to +125C, VDD1 = V DD1 (min), V DD2 = V DD2 (min)) SYMBOL PARAMETER UNIT 8R256K16-15 MIN MAX tAVAV1 Read cycle time tAVQV Read access time tAXQX2 Output hold time 5 ns tGLQX 2 G-controlled output enable time 0 ns tGLQV G-controlled output enable time tGHQZ 2 G-controlled output three-state time 0 E-controlled output enable time 5 15 E-controlled access time tEFQZ4 E-controlled output three-state time2 0 tBLZ BLE, BHE Enable to Output in Low-Z 0 tBHZ BLE, BHE Enable to Output in High-Z BLE, BHE Access Time IN D EV EL O Notes: * Post-radiation performance guaranteed at 25 C per MIL-STD-883 Method 1019. 1. Guaranteed but not tested. 2. Three-state is defined as a 200mV change from steady-state output voltage. 3. The ET (enable true) notation refers to the latter falling edge of E1 or rising edge of E2. 4. The EF (enable false) notation refers to the latter rising edge of E1 or falling edge of E2. 6 ns 7 ns 7 ns ns PM EN tETQV 3 tBA ns T tETQX 2,3 15 15 ns 7 ns ns 7 ns 7 ns tAVAV A(17:0) DQ(15:0) Previous Valid Data Valid Data tAVQV Assumptions: 1 . E1 and G < V IL (max) and E2 and W > VIH (min) tAXQX Figure 3a. SRAM Read Cycle 1: Address Access t ETQV tETQX DQ(15:0) t EFQZ PM EN Latter of E1 low and E2 high T A(17:0) DATA VALID Assumptions: 1. G, BHE, BLE < V IL (max) and W > V IH (min) EL O Figure 3b. SRAM Read Cycle 2: Chip Enable Access tAVQV A(17:0) EV t BA G D BLE/BHE t BHZ tBLZ t GHQZ DQ(15:0) IN t GLQX Assumptions: 1 . E1 < V IL (max) , E2 and W > V IH (min) DATA VALID tGLQV Figure 3c. SRAM Read Cycle 3: Output Enable Access 7 AC CHARACTERISTICS WRITE CYCLE (Pre and Post-Radiation)* (-55C to +125C, VDD1 = V DD1 (min), V DD2 = V DD2 (min)) SYMBOL PARAMETER UNIT 8R256K16-15 MIN MAX tAVAV 1 Write cycle time 15 ns tETWH Device enable to end of write 10 ns tAVET Address setup time for write (E1/E2- controlled) 0 ns tAVWL Address setup time for write (W - controlled) 0 ns tWLWH Write pulse width 10 ns tWHAX Address hold time for write (W - controlled) 0 ns tEFAX Address hold time for device enable (E1/E2- controlled) 0 ns tWLQZ 2 W - controlled three-state time 0 tWHQX2 W - controlled output enable time 4 tETEF Device enable pulse width (E1/E2 - controlled) 10 tDVWH Data setup time tWHDX Data hold time tWLEF 7 ns PM EN T ns ns ns 0 ns Device enable controlled write pulse width 10 ns tDVEF Data setup time 7 ns tEFDX Data hold time 0 ns tAVWH Address valid to end of write 10 ns tWHWL Write disable time 4 ns tBLWH BLE, BHE low to write high 10 ns tBLEF BLE, BHE low to enable high 10 ns EV EL O 7 IN D Notes : * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019. 1. Guaranteed but not tested (G high). 2. Three-state is defined as 200mV change from steady-state output voltage. 8 A(17:0) tAVAV 2 E1 tAVWH E2 tETWH tWHW BLE/BHE tBLWH W tAVWL tWLWH tWHAX Q(15:0) D(15:0) APPLIED DATA tWHDX PM EN tDVWH T tWHQX tWLQZ EL O Assumptions: 1. G < VIL (max). If G > VIH (min) then Q(15:0) will be in three-state for the entire cycle. 2. G high for t AVAV cycle. IN D EV Figure 4a. SRAM Write Cycle 1: W - Controlled Access 9 tAVAV 3 A(17:0) t ETEF tAVET t EFAX E1 E2 or tEFAX tAVET E1 E2 t BLEF BLE / BHE PM EN W T t WLEF APPLIED DATA D(15:0) t WLQZ Q(15:0) t DVEF tEFDX Assumptions & Notes: 1. G < V IL (max). If G > V IH (min) then Q(15:0) will be in three-state for the entire cycle. EL O 2. Either E1 scenario above can occur. 3. G high for t AVAV cycle. IN D EV Figure 4b. SRAM Write Cycle 2: Enable - Controlled Access 10 DATA RETENTION CHARACTERISTICS (Pre and Post-Radiation) (TC = 25C, VDD2 = V DD2 (min), 1 Sec DR Pulse) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT V DR VDD1 for data retention 1.0 -- V I DDR 1 Data retention current -- 10 A tEFR 1,2 Chip deselect to data retention time 0 ns tAVAV ns tR1,2 Operation recovery time DATA RETENTION MODE VDR > 1.0V VIN >0.7VD D 2 CMOS 1.7V tR t EFR E2 VSS E1 VDD2 VIN <0.3VD D 2 CMOS T 1.7V PM EN VDD1 EL O Figure 5. Low V DD Data Retention Waveform CMOS 188 ohms 90% V DD2 -0.05V EV 1.5V 10% < 2ns < 2ns Input Pulses D 50pF 0.0V IN Notes: 1. 50pF including scope probe and test socket. 2. Measurement of data output occurs at the low to high or high to low transition mid-point (i.e., CMOS input = V DD2 /2). Figure 6. AC Test Loads and Input Waveforms 11 PACKAGING IN D EV EL O PM EN T TBD 12 ORDERING INFORMATION 256K x 16 SRAM UT **** * - * * * * * Lead (A) (C) (X) Finish: = Hot solder dipped = Gold = Factory option (gold or solder) Screening: (C) = Military Temperature Range flow (P) = Prototype flow Package Type: (TBD) Access Time: (15) = 15ns access time EL O PM EN T Device Type: (8R256K16) =256K x 16 SRAM IN D EV Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an "X" is specified when ordering, then the part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3. Prototype flow per UTMC Manufacturing Flows Document. Tested at 25 C only. Lead finish is GOLD ONLY. Radiation neither tested nor guaranteed. 4. Military Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at -55 C, room temp, and 125C. Radiation neither tested nor guaranteed. 13 256K x 16 SRAM: SMD 5962 - **TBD** ** * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory Option (gold or solder) Case Outline: (TBD) Class Designator: (Q) = QML Class Q (V) = QML Class V Device Type (01) = 15ns access time, CMOS I/O Drawing Number: TBD PM EN T Total Dose: (R) = 100K rad(Si) Federal Stock Class Designator: No options IN D EV EL O Notes: 1.Lead finish (A,C, or X) must be specified. 2.If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3.Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. 14