5962R-TBD01QTBDA - Aeroflex UTMC - Datasheet.Directory

IN DEVELOPMENT

Figure 1. UT8R256K16 SRAM Block Diagram

Memory Array

256K x 16

Pre-Charge Circuit

Column Select

Row Select

Data Control

I/O Circuit

Data Control

A10 A11 A12 A13A14A15

DQ(7) to DQ(0)

DQ(15) to DQ(8)

BHE

BLE

•

A16A17

Low Byte

Read Circuit

High Byte

Read Circuit

FEATURES

q15ns maximum access time

qAsynchronous operation, functionally compatible with

industry-standard 256K x 16 SRAMs

qCMOS compatible inputs and output levels, three-state

bidirectional data bus

- I/O Voltage 2.5 to 3.3 volts, 1.8 volt core

qRadiation performance

- Intrinsic total-dose: 100K rad(Si)

- SEL Immune >100 MeV-cm2/mg

- Onset LET > 24 MeV-cm2/mg

- Memory Cell Saturated Cross Section, 1.0 x 10-8cm2/bit

- 1.0E x 10-10 errors/bit-day, Adams to 90%

geosynchronous heavy ion

- Neutron Fluence: 3.0E14n/cm2

- Dose Rate (estimated)

- Upset 1.0E9 rad(Si)/sec

- Latchup >1.0E11 rad(Si)/sec

qPackaging options:

- TBD

qStandard Microcircuit Drawing pending

- QML compliant part

INTRODUCTION

The UT8R256K16 is a high-performance CMOS static RAM

organized as 262,144 words by 16 bits. Easy memory expansion

is provided by active LOW and HIGH chip enables (E1, E2), an

active LOW output enable (G), and three-state drivers. This

device has a power-down feature that reduces power

consumption by more than 90% when deselected.

Writing to the device is accomplished by taking chip enable one

(E1) input LOW, chip enable two (E2) HIGH and write enable

(W) input LOW. Data on the 16 I/O pins (DQ0 through DQ15)

is then written into the location specified on the address pins

(A0 through A17). Reading from the device is accomplished by

taking chip enable one (E1) and output enable (G) LOW while

forcing write enable (W) and chip enable two (E2) HIGH. Under

these conditions, the contents of the memory location specified

by the address pins will appear on the I/O pins.

The 16 input/output pins (DQ0 through DQ15) are placed in a

high impedance state when the device is deselected (E1 HIGH

or E2 LOW), the outputs are disabled (G HIGH), or during a

write operation (E1 LOW, E2 HIGH and W LOW).

Standard Products

UT8R256K16 256K x 16 SRAM

Advanced Data Sheet

October 9, 2002

IN DEVELOPMENT

PIN NAMES

DEVICE OPERATION

The UT8R256K16 has four control inputs called Enable 1 (E1),

Enable 2 (E2), Write Enable (W), Half-word Enables (BLE/

BHE) and Output Enable (G); 18 address inputs, A(17:0); and

16 bidirectional data lines, DQ(15:0). E1 and E2 device enables

control device selection, active, and standby modes. Asserting

E1 and E2 enables the device, causes IDD to rise to its active

value, and decodes the 18 address inputs to select one of 262,144

words in the memory. W controls read and write operations.

During a read cycle, G must be asserted to enable the outputs.

Table 1. Device Operation Truth Table

Notes:

1. “X” is defined as a “don’t care” condition.

2. Device active; outputs disabled.

A(17:0) Address Input WWrite Enable

DQ(15:0) Data Input/Output GOutput Enable

E1 Enable (Active Low) VDD1 Power (1.8V)

E2 Enable (Active High) VDD2 Power (2.5V)

BHE and

BLE Low and high byte

enable VSS Ground

Figure 2. 15ns SRAM Pinout

VDD1 148 NC

A0 247 A17

A1 346 A16

A2 445 A15

A3 544 /G

A4 643 /BHE

/E1 742 /BLE

DQ0 841 DQ15

DQ1 940 DQ14

DQ2 10 39 DQ13

DQ3 11 38 DQ12

VDD2 12 37 VSS

VSS 13 36 VDD2

DQ4 14 35 DQ11

DQ5 15 34 DQ10

DQ6 16 33 DQ9

DQ7 17 32 DQ8

/W 18 31 E2

A5 19 30 A14

A6 20 29 A13

A7 21 28 A12

A8 22 27 A11

A9 23 26 A10

NC 24 25 VDD1

GWE2 E1 BLE BHE I/O Mode Mode

X X X H X X DQ(15:8)

3-State

DQ(7:0)

3-State

Standby

X X LX X X DQ(15:8)

3-State

DQ(7:0)

3-State

Standby

LH H L L HDQ(15:8)

3-State

DQ(7:0)

Data Out

Low Byte Read

LH H LHLDQ(15:8)

Data Out

DQ(7:0)

3-State

High Byte Read

LH H L L L DQ(15:8)

Data Out

DQ(7:0)

Data Out

Word Read

XLHL L L DQ(15:8)

Data In

DQ(7:0)

Data In

Word Write

XLHL L HDQ(15:8)

3-State

DQ(7:0)

Data In

Low Byte Write

XLHLHLDQ(15:8)

Data In

DQ(7:0)

3-State

High Byte Write

H H H LX X DQ(15:8)

DQ(7:0)

All 3-State

3-State

X X H LH H DQ(15:8)

DQ(7:0)

All 3-State

3-State

IN DEVELOPMENT

READ CYCLE

A combination of W and E2 greater than VIH (min) and E1

less than VIL (max) defines a read cycle. Read access time is

measured from the latter of device enable, output enable, or

valid address to valid data output.

SRAM Read Cycle 1, the Address Access in Figure 3a, is

initiated by a change in address inputs while the chip is

enabled with G asserted and W deasserted. Valid data appears

on data outputs DQ(15:0) after the specified tAVQV is

satisfied. Outputs remain active throughout the entire cycle.

As long as device enable and output enable are active, the

address inputs may change at a rate equal to the minimum

read cycle time (tAVAV).

SRAM Read Cycle 2, the Chip Enable-controlled Access in

Figure 3b, is initiated by the latter of E1 and E2 going active

while G remains asserted, W remains deasserted, and the

addresses remain stable for the entire cycle. After the

specified tETQV is satisfied, the 16-bit word addressed by

A(17:0) is accessed and appears at the data outputs DQ(15:0).

SRAM Read Cycle 3, the Output Enable-controlled Access

in Figure 3c, is initiated by G going active while E1 and E2

are asserted, W is deasserted, and the addresses are stable.

Read access time is tGLQV unless tAVQV or tETQV have not

been satisfied.

Write Cycle

A combination of W and E1 less than VIL(max) and E2

greater than VIH(min) defines a write cycle. The state of G is

a “don’t care” for a write cycle. The outputs are placed in the

high-impedance state when either G is greater than VIH(min),

or when W is less than VIL(max).

Write Cycle 1, the Write Enable-controlled Access in Figure

4a, is defined by a write terminated by W going high, with

E1 and E2 still active. The write pulse width is defined by

tWLWH when the write is initiated by W, and by tETWH when

the write is initiated by E1 or E2. Unless the outputs have

been previously placed in the high-impedance state by G, the

user must wait user must wait tWLQZ before applying data to

the 16 bidirectional pins DQ(15:0) to avoid bus contention.

Write Cycle 2, the Chip Enable-controlled Access in Figure

4b, is defined by a write terminated by the latter of E1 or E2

going inactive. The write pulse width is defined by tWLEF

when the write is initiated by W, and by tETEF when the write

is initiated by either E1or E2 going active. For the W initiated

write, unless the outputs have been previously placed in the

high-impedance state by G, the user must wait tWLQZ before

applying data to the sixteen bidirectional pins DQ(15:0) to

avoid bus contention.

BYTE ENABLES

Separate byte enable controls (BLE and BHE) allow

individual bytes to be accessed. BLE controls the lower bits

DQ(7:0). BHE controls the upper bits DQ(15:8). Writing to

the device is performed by asserting E1, E2 and the byte

enables. Reading the device is performed by asserting E1, E2,

G, and the byte enables while W is held inactive (HIGH).

RADIATION HARDNESS

The UT8R256K16 SRAM incorporates special design,

layout, and process features which allows operation in a

limited radiation environment.

Table 2. Radiation Hardness Design Specifications1

Notes:

1. The SRAM is immune to latchup to particles of 128MeV-cm2/mg.

2. 10% worst case particle environment, Geosynchronous orbit, 0.025 mils

of Aluminum.

Supply Sequencing

No supply voltage sequencing is required between VDD1 and

VDD2.

BHE BLE OPERATION

0 0 16-bit read or write cycle

0 1 8-bit high byte read or write cycle

(low byte bi-direction pins DQ(7:0)

are in 3 -state)

1 0 8-bit low byte read or write cycle

(high byte bi-direction pins

DQ(15:8) are in 3 -state)

1 1 High and Low byte bi-directional

pins remain in 3-state, write function

disabled

Total Dose 100K rad(Si)

Heavy Ion

Error Rate21.0E-10 Errors/Bit-Day

IN DEVELOPMENT

ABSOLUTE MAXIMUM RATINGS1

(Referenced to VSS)

Notes:

1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device

at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability and performance.

3. Test per MIL-STD-883, Method 1012.

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS

VDD1 DC supply voltage -0.3 to 2.0V

VDD2 DC supply voltage -0.3 to 3.8V

VI/O Voltage on any pin -0.3 to 3.8V

TSTG Storage temperature -65 to +150°C

PDMaximum power dissipation 1.2W

TJMaximum junction temperature +150°C

ΘJC Thermal resistance, junction-to-case25°C/W

IIDC input current ±5 mA

SYMBOL PARAMETER LIMITS

VDD1 Positive supply voltage 1.7 to 1.9V

VDD2 Positive supply voltage 2.25 to 3.6V

TCCase temperature range -55 to +125°C

VIN DC input voltage 0V to VDD2

IN DEVELOPMENT

DC ELECTRICAL CHARACTERISTICS (Pre and Post-Radiation)*

(-55°C to +125°C)

Notes:

* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1.0E5 rad(Si).

1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.

2. Supplied as a design limit but not guaranteed or tested.

3. Not more than one output may be shorted at a time for maximum duration of one second.

4. VIH = VDD2 (max), VIL = 0V.

SYMBOL PARAMETER CONDITION MIN MAX UNIT

VIH High-level input voltage .7*VDD2 V

VIL Low-level input voltage .3*VDD2 V

VOL1 Low-level output voltage IOL = 8mA,VDD2 =VDD2 (min) .2*VDD2 V

VOH1 High-level output voltage IOH = -4mA,VDD2

=VDD2 (min) .8*VDD2 V

CIN1Input capacitance ƒ = 1MHz @ 0V 7pF

CIO1Bidirectional I/O capacitance ƒ = 1MHz @ 0V 7pF

IIN Input leakage current VIN = VDD2 and VSS -2 2µA

IOZ Three-state output leakage current VO = VDD2

and VSS

VDD2 = VDD2

(max), G = VDD2

(max)

-2 2µA

IOS2, 3 Short-circuit output current VDD2 = VDD2

(max), VO = VDD2

VDD2 = VDD2

(max), VO = VSS

-100 +100 mA

IDD1(OP1)Supply current operating

@ 1MHz Inputs : VIL = VSS + 0.2V,

VIH = VDD2 + 0.2V , IOUT = 0