© Semiconductor Components Industries, LLC, 2000
July, 2019 − Rev. 2
1Publication Order Number:
NC7SZ58/D
NC7SZ57, NC7SZ58
TinyLogic UHS Universal
Configurable Two-Input
Logic Gates
Description
The NC7SZ57 and NC7SZ58 are universal configurable two−input
logic gates. Each device is capable of being configured for 1 of 5
unique two−input logic functions. Any possible two−input
combinatorial logic function can be implemented, as shown in the
Function Selection Table. Device functionality is selected by how the
device is wired at the board level. Figures 4 through 13 illustrate how
to connect the NC7SZ57 and NC7SZ58, respectively, for the desired
logic function. All inputs have been implemented with hysteresis.
The device is fabricated with advanced CMOS technology to
achieve ultra high speed with high output drive while maintaining low
static power dissipation over a broad VCC operating range. The device
is specified to operate over the 1.65 V to 5.5 V VCC operating range.
The input and output are high impedance when VCC is 0 V. Inputs
tolerate voltages up to 5.5 V independent of VCC operating range.
Features
•Ultra High−Speed
•Capable of Implementing any Two−Input Logic Functions
•Typical Usage Replaces Two (2) TinyLogic Gate Devices
•Reduces Part Counts in Inventory
•Broad VCC Operating Range: 1.65 V to 5.5 V
•Power Down High Impednce Input / Output
•Over−Voltage Tolerant Inputs Facilitate 5 V to 3 V Translation
•Proprietary Noise / EMI Reduction Circuitry Implemented
•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
See detailed ordering, marking and shipping information in the
package dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAMS
www.onsemi.com
SC−88
(SC−70 6 Lead)
1.25x2
CASE 419AD−01
SIP6 1.45x1.0
CASE 127EB
UDFN6
1.0X1.0, 0.35P
CASE 517DP
XXKK
XYZ
XXKK
XYZ
XX, XXX = Specific Device Code
KK = 2−Digit Lot Run Traceability Code
XY = 2−Digit Date Code Format
Z = Assembly Plant Code
= Year Coding Scheme
= Plant Code Identifier
T = Die Run Code
= Eight−Week Datacoding Scheme
XXXT
Pin 1
Pin 1
NC7SZ57, NC7SZ58
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2
Pin Configurations
Figure 1. SC70 (Top View)
(Top View) AAA
Pin One
I1 1 6 I2
GND 2 5 VCC
I0 3 4 Y
I1I2
GND VCC
I0Y
1
2
3
6
5
4
Figure 2. Pin 1 Orientation
Figure 3. MicroPakt (Top Through View)
NOTES:
1. AAA represents product code top mark (see Ordering Information).
2. Orientation of top mark determines pin one location.
3. Reading the top mark left to right, pin one is the lower left pin.
PIN DEFINITIONS
Pin # SC70 Pin # MicroPak Name Description
1 1 I1 Data Input
2 2 GND Ground
3 3 I0 Data Input
4 4 Y Output
5 5 VCC Supply Voltage
6 6 I2 Data Input
FUNCTION TABLE
Inputs NC7SZ57 NC7SZ58
I2I1I0Y = (I0) · (I2) + (I1) · (I2)Y = (I0) · (I2) + (I1) · (I2)
L L L H L
L L H L H
L H L H L
L H H L H
H L L L H
H L H L H
H H L H L
H H H H L
H = HIGH Logic Level
L = LOW Logic Level
NC7SZ57, NC7SZ58
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FUNCTION SELECTION TABLE
2−Input Logic Function Device Selection Connection Configuration
2−Input AND NC7SZ57 Figure 4
2−Input AND with Inverted Input NC7SZ58 Figure 10, Figure 11
2−Input AND with Both Inputs Inverted NC7SZ57 Figure 7
2−Input NAND NC7SZ58 Figure 9
2−Input NAND with Inverted Input NC7SZ57 Figure 5, Figure 6
2−Input NAND with Both Inputs Inverted NC7SZ58 Figure 12
2−Input OR NC7SZ58 Figure 12
2−Input OR with Inverted Input NC7SZ57 Figure 5, Figure 6
2−Input OR with Both Inputs Inverted NC7SZ58 Figure 9
2−Input NOR NC7SZ57 Figure 7
2−Input NOR with Inverted Input NC7SZ58 Figure 9, Figure 10
2−Input NOR with Both Inputs Inverted NC7SZ57 Figure 4
2−Input XOR NC7SZ58 Figure 13
2−Input XNOR NC7SZ57 Figure 8
NC7SZ57, NC7SZ58
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4
NC7SZ57 Logic Configurations
Figure 4 through Figure 8 show the logical functions that
can be implemented using the NC7SZ57. The diagrams
show the DeMorgan’s equivalent logic duals for a given
two−input function. The logical implementation is next to
the board−level physical implementation of how the pins of
the function should be connected.
Figure 4. 2−Input AND Gate Figure 5. 2−Input NAND with Inverted A Input
Figure 6. 2−Input NAND with Inverted B Input Figure 7. 2−Input NOR Gate
Figure 8. 2−Input XNOR Gate
NC7SZ57, NC7SZ58
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5
NC7SZ58 Logic Configurations
Figure 9 through Figure 13 show the logical functions that
can be implemented using the NC7SZ58. The diagrams
show the DeMorgan’s equivalent logic duals for a given
two−input function. The logical implementation is next to
the board−level physical implementation of how the pins of
the function should be connected.
Figure 9. 2−Input NAND Gate Figure 10. 2−Input AND with Inverted A Input
Figure 11. 2−Input AND with Inverted B Input Figure 12. 2−Input OR Gate
Figure 13. 2−Input XOR Gate
NC7SZ57, NC7SZ58
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6
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Min Max Unit
VCC Supply Voltage −0.5 6.5 V
VIN DC Input Voltage −0.5 6.5 V
VOUT DC Output Voltage −0.5 6.5 V
IIK DC Input Diode Current VIN < 0.5 V − −50 mA
IOK DC Output Diode Current VOUT < −0.5 V − −50 mA
IOUT DC Output Source / Sink Current −±50 mA
ICC or IGND DC VCC or Ground Current −±50 mA
TSTG Storage Temperature Range −65 +150 °C
TJMaximum Junction Temperature under Bias −+150 °C
TLLead Temperature, Soldering, 10 Seconds −+260 °C
PDPower Dissipation at +85°CSC70−6−190 mW
MicroPak−6−327
MicroPak2t−6−327
ESD Human Body Model, JEDEC: JESD22−A114 −4000 V
Charge Device Model, JEDEC: JESD22−C101 −2000
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Conditions Min Max Unit
VCC Supply Voltage Operating 1.65 5.5 V
Supply Voltage Data Retention 1.5 5.5
VIN Input Voltage 0 5.5 V
VOUT Output Voltage 0 VCC V
TAOperating Temperature −40 +85 °C
qJA Thermal Resistance SC70−6−659 °C/W
MicroPak−6−382
MicroPak2−6−382 °C/W
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
NC7SZ57, NC7SZ58
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7
DC ELECTICAL CHARACTERISTICS
Symbol Parameter VCC (V) Conditions
TA = +25°C TA = −40 to +85°C
Unit
Min Typ Max Min Max
VP Positive Threshold
Voltage
1.65 −0.99 1.40 −1.40 V
2.30 −1.39 1.80 −1.80
3.00 −1.77 2.20 −2.20
4.50 −2.49 3.10 −3.10
5.50 −2.95 3.60 −3.60
VN Negative Threshold
Voltage
1.65 0.20 0.50 −0.20 −V
2.30 0.40 0.75 −0.40 −
3.00 0.60 0.99 −0.60 −
4.50 1.00 1.43 −1.00 −
5.50 1.20 1.70 −1.20 −
VH Hysteresis Voltage 1.65 0.15 0.48 0.90 0.15 0.90 V
2.30 0.25 0.64 1.10 0.25 1.10
3.00 0.40 0.78 1.20 0.40 1.20
4.50 0.60 1.06 1.50 0.60 1.50
5.50 0.70 1.25 1.70 0.70 1.70
VOH HIGH Level Output
Voltage
1.65 VIN = VIH or VIL
IOH = −100 mA
1.55 1.65 −1.55 −V
2.30 2.20 2.30 −2.20 −
3.00 2.90 3.00 −2.90 −
4.50 4.40 4.50 −4.40 −
1.65 VIN = VIH
or VIL
IOH = −4 mA 1.29 1.52 −1.29 −
2.30 IOH = −8 mA 1.90 2.15 −1.90 −
3.00 IOH = −16 mA 2.40 2.80 −2.40 −
3.00 IOH = −24 mA 2.30 2.68 −2.30 −
4.50 IOH = −32 mA 3.80 4.20 −3.80 −
VOL LOW Level Output
Voltage
1.65 VIN = VIH or VIL
IOL = 100 mA
− − 0.10 −0.10 V
2.30 − − 0.10 −0.10
3.00 − − 0.10 −0.10
4.50 − − 0.10 −0.10
1.65 VIN = VIH
or VIL
IOL = 4 mA −0.08 0.24 −0.24
2.30 IOL = 8 mA −0.10 0.30 −0.30
3.00 IOL = 16 mA −0.15 0.40 −0.40
3.00 IOL = 24 mA −0.22 0.55 −0.55
4.50 IOL = 32 mA −0.22 0.55 −0.55
IIN Input Leakage Current 1.65 to 5.50 VIN = 5.5 V, GND − − ±0.1 −±1.0 mA
IOFF Power Off Leakage
Current
0 VIN or VOUT = 5.5 V − − 1−10 mA
ICC Quiescent Supply
Current
1.65 to 5.5 VIN = 5.5 V, GND − − 1−10 mA
NC7SZ57, NC7SZ58
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8
AC ELECTRICAL CHARACTERISTICS
Symbol Parameter VCC (V) Conditions
TA = +25°C TA = −40 to +85°C
Unit
Min Typ Max Min Max
tPLH, tPHL Propagation Delay In to Y
(Figure 14, 16)
1.8 ±0.15 CL = 15 pF,
RL = 1 MW
−8.0 14.0 −14.5 ns
2.5 ±0.2 −4.9 8.0 −8.5
3.3 ±0.3 −3.7 5.3 −5.7
5.0 ±0.5 −2.8 4.3 −4.6
3.3 ±0.3 CL = 50 pF,
RL = 500 W
−4.2 6.0 −6.5 ns
5.0 ±0.5 −3.4 4.9 −5.3
CIN Input Capacitance 0−2−−−pF
CPD Power Dissipation Capacitance
(Figure 15)
3.3 (Note 4) −14 −−−pF
5.0 −17 −−−
4. CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (ICCD) at
no output loading and operating at 50% duty cycle. (See Figure 12) CPD is related to ICCD dynamic operating current by the expression:
ICCD = (CPD) (VCC) (fIN) + (ICCstatic).
AC Loading and Waveforms
NOTE:
5. CL includes load and stray capacitance.
6. Input PRR = 1.0 MHz, tW = 500 ns.
Figure 14. AC Test Circuit
NOTE:
7. Input = AC Waveforms.
8. PRR = Variable; Duty Cycle = 50%.
A
INPUT
VCC
Figure 15. ICCD Test Circuit
VCC
CLRL
INPUT OUTPUT
DUT
DUT INPUT
tr = 3 ns
50%
50%
50%
90%
10%
90%
10%
INPUT
Out of Phase
OUTPUT
In Phase
OUTPUT
tf = 3 ns
VCC
GND
VOH
VOL
VOH
VOL
50%
50%
50%
tPHL tPLH
tPLH tPHL
tW
Figure 16. AC Waveforms
NC7SZ57, NC7SZ58
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9
ORDERING INFORMATION
Device Top Mark Package Shipping†
NC7SZ57P6X Z57 6−Lead SC70, EIAJ SC−88a, 1.25 mm Wide 3000 / Tape & Reel
NC7SZ57L6X KK 6−Lead Micropak, 1.0 mm Wide 5000 / Tape & Reel
NC7SZ57FHX KK 6−Lead, MicroPak2, 1x1 mm Body, .35 mm Pitch 5000 / Tape & Reel
NC7SZ58P6X Z58 6−Lead SC70, EIAJ SC−88a, 1.25 mm Wide 3000 / Tape & Reel
NC7SZ58L6X LL 6−Lead Micropak, 1.0 mm Wide 5000 / Tape & Reel
NC7SZ58FHX LL 6−Lead, MicroPak2 , 1x1 mm Body, .35 mm Pitch 5000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MicroPak and MicroPak2 are trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other
countries.
SIP6 1.45X1.0
CASE 127EB
ISSUE O
DATE 31 AUG 2016
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON13590G
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
SIP6 1.45X1.0
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
SC−88 (SC−70 6 Lead), 1.25x2
CASE 419AD−01
ISSUE A
DATE 07 JUL 2010
E1
D
A
L
L1 L2
ee
bA1
A2
c
TOP VIEW
SIDE VIEW END VIEW
q1
q1
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-203.
E
q
SYMBOL MIN NOM MAX
θ
A
A1
b
c
D
E
E1
e
L
0º 8º
L2
0.00
0.15
0.10
0.26
1.80
1.80
1.15
0.65 BSC
0.15 BSC
1.10
0.10
0.30
0.18
0.46
2.20
2.40
1.35
L1
0.80
θ1 4º 10º
A2 0.80 1.00
0.42 REF
0.36
2.00
2.10
1.25
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON34266E
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
SC−88 (SC−70 6 LEAD), 1.25X2
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
UDFN6 1.0X1.0, 0.35P
CASE 517DP
ISSUE O
DATE 31 AUG 2016
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON13593G
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
UDFN6 1.0X1.0, 0.35P
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
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