KAF-4320 IMAGE SENSOR 2084 (H) X 2085 (V) FULL FRAME CCD IMAGE SENSOR JULY 20, 2012 DEVICE PERFORMANCE SPECIFICATION REVISION 1.0 PS-0034 KAF-4320 Image Sensor TABLE OF CONTENTS Summary Specification ......................................................................................................................................................................................... 4 Description .................................................................................................................................................................................................... 4 Features ......................................................................................................................................................................................................... 4 Applications .................................................................................................................................................................................................. 4 Ordering Information ............................................................................................................................................................................................ 5 Device Description ................................................................................................................................................................................................. 6 Architecture .................................................................................................................................................................................................. 6 Image Acquisition ........................................................................................................................................................................................ 7 Charge Transport ......................................................................................................................................................................................... 7 Output Structure ..................................................................................................................................................................................... 7 Dark Reference Pixels ............................................................................................................................................................................ 8 Dummy Pixels ........................................................................................................................................................................................... 8 Physical Description .................................................................................................................................................................................... 9 Pin Description and Device Orientation ............................................................................................................................................ 9 Imaging Performance .......................................................................................................................................................................................... 11 Electro Optical Specifications ........................................................................................................................................................... 11 Specifications............................................................................................................................................................................................. 11 Typical Performance Curves ............................................................................................................................................................................ 12 Linearity ...................................................................................................................................................................................................... 14 CCD Output ................................................................................................................................................................................................ 15 Noise ............................................................................................................................................................................................................ 16 CCD amplifier ........................................................................................................................................................................................ 16 System noise .......................................................................................................................................................................................... 16 Temperature dependence of the noise floor ................................................................................................................................ 16 Noise Versus Frequency ..................................................................................................................................................................... 17 Performance Versus Temperature .................................................................................................................................................. 17 Defect Definitions ................................................................................................................................................................................................ 19 Operating Conditions .............................................................................................................................................................................. 19 Specifications............................................................................................................................................................................................. 19 Operation .................................................................................................................................................................................................................. 20 Absolute Maximum Ratings ................................................................................................................................................................... 20 Equivalent Input Circuits......................................................................................................................................................................... 20 DC Bias Operating Conditions ............................................................................................................................................................... 21 AC Operating Conditions ........................................................................................................................................................................ 22 AC Timing Conditions .............................................................................................................................................................................. 23 Pixel rate clock waveforms ................................................................................................................................................................ 24 Timing ......................................................................................................................................................................................................................... 25 Normal Read Out .................................................................................................................................................................................. 25 Power Dissipation..................................................................................................................................................................................... 26 Amplifier power .................................................................................................................................................................................... 26 Total Power ............................................................................................................................................................................................ 26 CCD Surface Flatness ........................................................................................................................................................................... 27 Storage and Handling .......................................................................................................................................................................................... 29 Storage Conditions................................................................................................................................................................................... 29 ESD ............................................................................................................................................................................................................... 29 Cover Glass Care and Cleanliness ......................................................................................................................................................... 29 Environmental Exposure ........................................................................................................................................................................ 29 Soldering Recommendations ................................................................................................................................................................ 29 www.truesenseimaging.com Revision 1.0 PS-0034 Pg. 2 KAF-4320 Image Sensor Mechanical Drawings ........................................................................................................................................................................................... 30 Completed Assembly ............................................................................................................................................................................... 30 Quality Assurance and Reliability .................................................................................................................................................................. 32 Quality and Reliability ............................................................................................................................................................................. 32 Replacement .............................................................................................................................................................................................. 32 Liability of the Supplier ........................................................................................................................................................................... 32 Liability of the Customer ........................................................................................................................................................................ 32 Test Data Retention ................................................................................................................................................................................. 32 Mechanical.................................................................................................................................................................................................. 32 Life Support Applications Policy .................................................................................................................................................................... 32 Revision Changes................................................................................................................................................................................................... 33 MTD/PS-0677 ............................................................................................................................................................................................. 33 PS-0034 ....................................................................................................................................................................................................... 33 TABLE OF FIGURES Figure 1: Block Diagram ................................................................................................................................................................................ 6 Figure 2: Horizontal Seam Cross-Section .................................................................................................................................................. 7 Figure 3: Output Architecture ..................................................................................................................................................................... 8 Figure 4: Pinout Diagram .............................................................................................................................................................................. 9 Figure 5: Typical Spectral Response .........................................................................................................................................................12 Figure 6: Dark Current Temperature Dependence ..............................................................................................................................13 Figure 7: Linearity .........................................................................................................................................................................................14 Figure 8: Output: Small Signal ...................................................................................................................................................................15 Figure 9: CCD Output Large Signal ...........................................................................................................................................................15 Figure 10: Noise Versus Pixel Rate ...........................................................................................................................................................17 Figure 11: Noise Versus Temperature - 3 MHz Pixel Rate .................................................................................................................17 Figure 12: Noise Versus Temperature - 1 MHz Pixel Rate .................................................................................................................18 Figure 13: Example Output Structure Load Diagram ..........................................................................................................................21 Figure 14: Clock Example ............................................................................................................................................................................24 Figure 15: Timing Diagrams ........................................................................................................................................................................25 Figure 16: Die Flatness Data ......................................................................................................................................................................27 Figure 17: Die Flatness Data ......................................................................................................................................................................28 Figure 18: Die Flatness Data ......................................................................................................................................................................28 Figure 19: Completed Assembly (1 of 2) .................................................................................................................................................30 Figure 20: Completed Assembly (2 of 2) .................................................................................................................................................31 www.truesenseimaging.com Revision 1.0 PS-0034 Pg. 3 KAF-4320 Image Sensor Summary Specification KAF-4320 Image Sensor DESCRIPTION The KAF-4320 Image Sensor is a high performance monochrome area CCD (charge-coupled device) image sensor designed for a wide range of image sensing applications. The sensor incorporates true two-phase CCD technology, simplifying the support circuits required to drive the sensor as well as reducing dark current without compromising charge capacity. The sensor also utilizes the TRUESENSE Transparent Gate Electrode to improve sensitivity compared to the use of a standard front side illuminated polysilicon electrode. The full imaging array is read out of four outputs, each of which is driven by a low impedance two stage source follower that provides a high conversion gain. This combination enables low noise at a net readout rate of 12 MHz (3 MHz per output). FEATURES Parameter Typical Value Architecture Full-Frame CCD Total Number of Pixels 2092 (H) x 2093 (V) Number of Active Pixels 2084 (H) x 2085 (V) = approx. 4.3 M Pixel Size 24 m (H) x 24 m (V) Imager Size 50.02 mm (H) x 50.02 mm (V) Die Size 52.3 mm (H) x 52.7 mm (V) Output Sensitivity 10 V/e- Saturation Signal 500,000 electrons Readout Noise 20 electrons (3 MHz) Outputs 4 Dark Current (T = 25 C) < 15 pA/cm2 Dark Current Doubling Temperature 6.4 C True Two Phase Full Frame Architecture Dynamic Range 20,000 : 1 Blooming Suppression None TRUESENSE Transparent Gate Electrode for high sensitivity Maximum Data Rate 3 MHz Package PGA Package APPLICATIONS Medical Imaging Scientific Imaging www.truesenseimaging.com Cover Glass Clear Parameters above are specified at T = 25 C unless otherwise noted. Revision 1.0 PS-0034 Pg. 4 KAF-4320 Image Sensor Ordering Information Catalog Number Product Name Description 4H0476 KAF- 4320-AAA-JP-B1 Monochrome, No Microlens, PGA Package, Taped Clear Cover Glass, no coatings, Grade 1 4H0477 KAF- 4320-AAA-JP-B2 Monochrome, No Microlens, PGA Package, Taped Clear Cover Glass, no coatings, Grade 2 4H0478 KAF- 4320-AAA-JP-AE Monochrome, No Microlens, PGA Package, Taped Clear Cover Glass, no coatings, Engineering Sample 4H0475 KEK-4H0475-KAF-4320-16-3 Evaluation Board (Complete Kit) Marking Code KAF- 4320-AAA (Lot Number) N/A See Application Note Product Naming Convention for a full description of the naming convention used for Truesense Imaging image sensors. For reference documentation, including information on evaluation kits, please visit our web site at www.truesenseimaging.com. Please address all inquiries and purchase orders to: Truesense Imaging, Inc. 1964 Lake Avenue Rochester, New York 14615 Phone: (585) 784-5500 E-mail: info@truesenseimaging.com Truesense Imaging reserves the right to change any information contained herein without notice. All information furnished by Truesense Imaging is believed to be accurate. www.truesenseimaging.com Revision 1.0 PS-0034 Pg. 5 KAF-4320 Image Sensor Device Description ARCHITECTURE 1 4 4 H1 H2 H2 H1 RD R VDD VOUT4 VLG GND OG H1L 1042 1042 4 4 1 4 V1 V2 V1 V2 GUARD V1 V2 V1 V2 KAF-4320 2084H x 2085V* 24 m X 24 m Pixels 4 4 V2 V1 V2 V1 GUARD V2 V1 V2 V1 4 Dark 1 4 4 1042 (Last VCCD Phase = TF2 H1) 1042 H1 H2 H2 H1 RD R VDD VOUT1 VLG VSUB OG H1L RD R VDD VOUT3 VLG VSUB OG H1L 4 4 1 RD R VDD VOUT2 VLG VSUB OG H1L * Note: The center row is predominately a 24um x 25um polysilicon pixel that splits evenly into each half of the array. Thus, each quadrant will consist of 1046 H x 1047 V rows where the last row will contain roughly half the signal. Figure 1: Block Diagram www.truesenseimaging.com Revision 1.0 PS-0034 Pg. 6 24m 24m 10m 14m Poly ITO +++++ ++ ++ 25m +++++ Top Half ++++ Row 1045 Row 1046 1/2 Row 1047 1/2 Row 1047 Row 1046 Row 1045 KAF-4320 Image Sensor 24m +++++ 24m ++ +++++ ++ Bottom Half Pixel optical boundary Figure 2: Horizontal Seam Cross-Section IMAGE ACQUISITION An electronic representation of an image is formed when incident photons falling on the sensor plane create electronhole pairs within the sensor. These photon induced electrons are collected locally by the formation of potential wells at each photogate or pixel site. The number of electrons collected is linearly dependent on light level and exposure time and non-linearly dependent on wavelength. When the pixel's capacity is reached, excess electrons will leak into the adjacent pixels within the same column. This is termed blooming. During the integration period, the V1 and V2 register clocks are held at a constant (low) level. See Figure 15. CHARGE TRANSPORT Referring again to Figure 15, the integrated charge from each photogate is transported to the output using a two-step process. Each line (row) of charge is first transported from the vertical CCD to the horizontal CCD register using the V1 and V2 register clocks. The horizontal CCD is presented a new line on the falling edge of V2 while H1 is held high. The horizontal CCD then transports each line, pixel by pixel, to the output structure by alternately clocking the H1 and H2 pins in a complementary fashion. On each falling edge of H1L a new charge packet is transferred onto a floating diffusion and sensed by the output amplifier. Output Structure Charge presented to the floating diffusion is converted into a voltage and current amplified in order to drive off-chip loads. The resulting voltage change seen at the output is linearly related to the amount of charge placed on the floating diffusion. Once the signal has been sampled by the system electronics, the reset gate (R) is clocked to remove the signal and the floating diffusion is reset to the potential applied by Vrd. (See Figure 3). More signal at the floating diffusion reduces the voltage seen at the output pin. In order to activate the output structure, an off-chip load must be added to the Vout pin of the device such as shown in Figure 5. If charge binning is desired, the charge can be combined at the output node or it can be combined in the H1L gate and then presented to the output node. www.truesenseimaging.com Revision 1.0 PS-0034 Pg. 7 KAF-4320 Image Sensor Dark Reference Pixels There are 4 light shielded pixels at the beginning of each line. There are 4 dark lines at the start of every frame and 4 dark lines at the end of each frame. Since there are outputs at each of the four corners, the light shield will affect the beginning of each line from each output, and for the first four lines from each of the outputs. Under normal circumstances, these pixels do not respond to light. However, dark reference pixels in close proximity to an active pixel can scavenge signal depending on light intensity and wavelength and therefore will not represent the true dark signal. Dummy Pixels Within the horizontal shift register are 4-1/2 leading pixels that are not associated with a column of pixels within the vertical register. These pixels contain only horizontal shift register dark current signal and do not respond to light. A few leading dummy pixels may scavenge false signal depending on operating conditions. H2 H1 H2 HCCD Charge Transfer VDD H1L Vog R Vrd Floating Diffusion Vout Vlg Source Follower #1 Source Follower #2 Figure 3: Output Architecture www.truesenseimaging.com Revision 1.0 PS-0034 Pg. 8 KAF-4320 Image Sensor PHYSICAL DESCRIPTION Gnd oR OG oH2 oH1 oH1L 52 51 50 49 48 47 46 45 44 61 60 59 58 57 56 55 54 53 Vrd Vlg Vss Gnd Gnd Gnd Gnd Gnd Gnd Gnd oH1L oH1 oH2 OG Gnd oR Pin Description and Device Orientation 43 42 41 40 62 63 64 65 71 39 Vout3 38 Vdd 37 oV2 36 oV1 35 Gnd 34 oV1 72 33 Vout4 66 Vdd 67 oV2 68 oV1 69 Gnd 70 oV1 oV2 oV2 32 Guard 31 oV2 Guard 73 oV2 74 oV1 30 75 oV1 77 29 Gnd 28 oV1 78 27 Gnd 76 oV1 oV2 Vrd Vlg Vss Gnd oV2 Vdd 79 Vout1 80 26 Vdd 25 Vout2 Gnd 81 Vss 82 Vlg 83 24 Gnd 23 Vss 22 Vlg 21 Vrd Pin 1 Gnd oR OG oH2 oH1 oH1L Gnd Gnd Gnd 11 12 13 14 15 16 17 18 19 20 N/C 9 10 N/C 7 8 Gnd oH1L oH1 oH2 OG Gnd oR 1 2 3 4 5 6 Gnd 84 Gnd Vrd Figure 4: Pinout Diagram www.truesenseimaging.com Revision 1.0 PS-0034 Pg. 9 KAF-4320 Image Sensor Pin Name Description Pin Name Description 1 GND Substrate (ground) 43 VRD Reset Drain 2 R Reset Clock 44 GND Substrate (ground) 3 VOG Output gate bias 45 R Reset Clock 4 H1L Horizontal CCD Clock - Last phase 46 VOG Output gate bias 5 H1 Horizontal CCD Clock - Phase 1 47 H1L Horizontal CCD Clock - Last phase 6 H2 Horizontal CCD Clock - Phase 2 48 H1 Horizontal CCD Clock - Phase 1 7 GND Substrate (ground) 49 H2 Horizontal CCD Clock - Phase 2 8 GND Substrate (ground) 50 GND Substrate (ground) 9 GND Substrate (ground) 51 GND Substrate (ground) 10 N/C No connect 52 GND Substrate (ground) 11 N/C No connect 53 GND Substrate (ground) 12 GND Substrate (ground) 54 GND Substrate (ground) 13 GND Substrate (ground) 55 GND Substrate (ground) 14 GND Substrate (ground) 56 H2 Horizontal CCD Clock - Phase 2 15 H2 Horizontal CCD Clock - Phase 2 57 H1 Horizontal CCD Clock - Phase 1 16 H1 Horizontal CCD Clock - Phase 1 58 H1L Horizontal CCD Clock - Last phase 17 H1L Horizontal CCD Clock - Last phase 59 VOG Output gate bias 18 VOG Output gate bias 60 R Reset Clock 19 R Reset Clock 61 GND Substrate (ground) 20 GND Substrate (ground) 62 VRD Reset Drain 21 VRD Reset Drain 63 VLG Amplifier Supply Return 22 VLG Amplifier Supply Return 64 VSS Source follower load gate bias 23 VSS Source follower load gate bias 65 GND Substrate (ground) 24 GND Substrate (ground) 66 Vout4 Amplifier output 25 Vout2 Amplifier output 67 VDD Amplifier Supply 26 VDD Amplifier Supply 68 V2 Vertical CCD Clock - Phase 2 27 V2 Vertical CCD Clock - Phase 2 69 V1 Vertical CCD Clock - Phase 1 28 V1 Vertical CCD Clock - Phase 1 70 GND Substrate (ground) 29 GND Substrate (ground) 71 V1 Vertical CCD Clock - Phase 1 30 V1 Vertical CCD Clock - Phase 1 72 V2 Vertical CCD Clock - Phase 2 31 V2 Vertical CCD Clock - Phase 73 Guard Guard Ring 32 Guard Guard Ring 74 V2 Vertical CCD Clock - Phase 33 V2 Vertical CCD Clock - Phase 75 V1 Vertical CCD Clock - Phase 1 34 V1 Vertical CCD Clock - Phase 1 76 GND Substrate (ground) 35 GND Substrate (ground) 77 V1 Vertical CCD Clock - Phase 1 36 V1 Vertical CCD Clock - Phase 1 78 V2 Vertical CCD Clock - Phase 2 37 V2 Vertical CCD Clock - Phase 2 79 VDD Amplifier Supply 38 VDD Amplifier Supply 80 Vout1 Amplifier output 39 Vout3 Amplifier output 81 GND Substrate (ground) 40 GND Substrate (ground) 82 VSS Source follower load gate bias 41 VSS Source follower load gate bias 83 VLG Source follower load gate bias 42 VLG Amplifier Supply Return 84 VRD Reset Drain Notes: 1. Like named pins (e.g. Vss) should be connected to the same supply. www.truesenseimaging.com Revision 1.0 PS-0034 Pg. 10 KAF-4320 Image Sensor Imaging Performance Electro Optical Specifications All values measured at 25 C, and nominal operating conditions. These parameters exclude defective pixels. SPECIFICATIONS Description Saturation Signal Vertical CCD capacity Horizontal CCD capacity Output Node capacity Symbol Min. Nom. 500000 650000 850000 550000 Nsat Max. Units Notes Verification Plan design10 electrons/pixel 1 design10 Quantum Efficiency (see Figure 5) Photoresponse Non-Linearity PRNL < 1.0 2.0 % 2 design10 Photoresponse Non-Uniformity PRNU 0.8 2.0 % 3 design10 G 0.2 5 % 8 die9 Jdark 2507 54015 electrons/pixel/sec 4 die9 6.3 7 C 300 540 electrons/pixel/sec 5 die9 dB 6 design10 Channel to channel Gain Difference Dark Signal Dark Signal Doubling Temperature Dark Signal Non-Uniformity Dynamic Range Output Amplifier DC Offset Output Amplifier Sensitivity Output Amplifier output Impedance Noise Floor DSNU DR Vodc - Vout/Ne Zout - ne 86 87.5 Vrd-4 Vrd -3 9 10 Vrd -2 11 150 17 24 design10 die9 V - V/e design10 Ohms die9 electrons 7 design10 Notes: 1. The maximum output video amplitude limits the charge capacity and dynamic range. The maximum charge capacity is determined from a photon transfer measurement and is defined as the point where the mean-variance fails to demonstrate the theoretical behavior. 2. Worst case deviation from straight line fit, between 0.1% and 95% of Vsat. 3. One Sigma deviation of a 1042 x 1042 sample (data from one output) when the CCD is illuminated uniformly at half of saturation, excluding defective pixels. [100 * (std deviation/average)] 4. Average of all pixels with no illumination at 25 C. 5. Average dark signal of any of 16 x 16 blocks within the sensor (each block is 130 x 130 pixels). 6. The dynamic range limited by the noise of the output amplifier (i.e. at temperatures less than -10 C), pixel frequency = 3MHz, and bandwidth = 10 MHz. 7. Noise floor of the CCD amplifier assuming correlated double sampling, pixel frequency = 3MHz, and bandwidth = 10MHz. 8. G = abs (100 * (1 - [response of a channel]/ [average response of all four channels])). The specified gain difference is the combination of all the gain errors on the CCD sensor and the analog signal processing in the test system. 9. A parameter that is measured on every sensor during production testing. 10. A parameter that is quantified during the design verification activity. www.truesenseimaging.com Revision 1.0 PS-0034 Pg. 11 KAF-4320 Image Sensor Typical Performance Curves KAF-4320 Absolute Quantum Efficiency 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 300 400 500 600 700 800 900 1000 1100 1200 Wavelength (nm) Figure 5: Typical Spectral Response www.truesenseimaging.com Revision 1.0 PS-0034 Pg. 12 KAF-4320 Image Sensor KAF-4320 Dark Current 1000 el/pix/sec 100 measured Tdbl=6.4 C 10 1 -20 -10 0 10 20 30 Temperature (C) Figure 6: Dark Current Temperature Dependence www.truesenseimaging.com Revision 1.0 PS-0034 Pg. 13 KAF-4320 Image Sensor LINEARITY Figure 7 shows a typical result from measuring the signal response as a function of integration time, while the illumination level is constant. The data is fit in log space to give equal weighting between low and high signal levels. A perfectly linear system would have a slope of 1.00 in log space. The slope in the fit is allowed to deviate from the ideal by a small amount. Typical values of the slope are between 1.00 and 1.02. The deviation from linear is defined as: %dev = abs (100 * [measured value-fit value]/ fit value). KAF-4320 Linearity 1000000 Signal (electrons/pixel) 100000 10000 1000 measured fit % dev from fit 100 10 1 0.1 0.01 1 10 100 1000 10000 100000 Time (msec) Figure 7: Linearity www.truesenseimaging.com Revision 1.0 PS-0034 Pg. 14 KAF-4320 Image Sensor CCD OUTPUT The following figures show typical CCD video at the output of the CCD and at the input of the analog to digital converter (A/D) in the test system. Bandwidth limiting is applied at the A/D input to minimize the noise floor. Figure 8: Output: Small Signal Figure 9: CCD Output Large Signal www.truesenseimaging.com Revision 1.0 PS-0034 Pg. 15 KAF-4320 Image Sensor NOISE The CCD amplifier noise floor, the CCD dark current during readout, and other system components such as the analogdigital converter dictate the total system noise. CCD amplifier The noise contributed by the output amplifier is determined from the amplifier's noise power spectrum, the system bandwidth, and any other analog processing. Correlated double sampling is a standard analog processing technique used with CCDs and it is assumed that it is used for all of the rest of the calculations and results in this document. System noise The total noise will be the combination of the CCD noise and the noise contributed by other components in the processing circuitry. The total noise, dominated by the CCD and the A/D converter is also shown in Figure 10. The measured vales were obtained using a system that employed Datel 16 bit analog to digital converters, the ADS 931 and ADS933. The system noise obtained matched the Datel specifications exactly and was similar and slightly lower than the CCD noise contribution. The table below shows the results and good agreement between the expected and measured results for the CCD alone and the CCD in the system at 1 MHz and 3 MHz. The values in the table are in electrons referred to the CCD amplifier input. CCD Measured Noise CCD + System Datel ADS93x Measured 1.00E+06 12 16.2 3.00E+06 17.3 22.6 Frequency Temperature dependence of the noise floor The temperature dependence of the noise floor is dictated primarily by the dark current generated during the readout time for the CCD. Figure 11 and Figure 12 show the expected dynamic range as a function of temperature for two pixel rates, 3 MHz and 1 MHz. The dynamic range was calculated using the measured amplifier and system noise values, the expected dark current performance, and the saturation signal. At 25 C, the dark current shot noise can contribute from 12 to 50 electrons and dominate the noise floor. The maximum dynamic range can be achieved at temperatures < -10 C for these read out frequencies. www.truesenseimaging.com Revision 1.0 PS-0034 Pg. 16 KAF-4320 Image Sensor Noise Versus Frequency Pixel Rate Dependency of Noise Noise (electrons) 25 20 15 10 5 0 0.0E+00 1.0E+06 2.0E+06 3.0E+06 4.0E+06 Pixel rate (MHz) CCD noise - calculated CCD noise measured CCD+system - measured Figure 10: Noise Versus Pixel Rate Performance Versus Temperature KAF-4320 System Dynamic Range total system CCD 16 Dynamic Range (Bits) 15.5 15 14.5 14 13.5 13 12.5 12 -50 -40 -30 -20 -10 0 10 20 30 Temperature (C) total system noise: CCD readout dark current + CCD amplifier + A/D converter (Datel 933 16 bit converter) Figure 11: Noise Versus Temperature - 3 MHz Pixel Rate www.truesenseimaging.com Revision 1.0 PS-0034 Pg. 17 KAF-4320 Image Sensor KAF-4320 System Dynamic Range total system CCD 16 Dynamic Range (Bits) 15.5 15 14.5 14 13.5 13 12.5 12 -50 -40 -30 -20 -10 0 10 20 30 Temperature (C) total system noise: CCD readout dark current + CCD amplifier + A/D converter (Datel 931 16 bit converter) Figure 12: Noise Versus Temperature - 1 MHz Pixel Rate www.truesenseimaging.com Revision 1.0 PS-0034 Pg. 18 KAF-4320 Image Sensor Defect Definitions OPERATING CONDITIONS Cosmetic tests performed at T = 25 C SPECIFICATIONS Grade Point Defects Cluster Defects C1 <50 C2 <100 Point Defects Columns Double Column <20 0 0 <20 <4 0 Dark: A pixel, which deviates by more than 6% from neighboring pixels when illuminated to 70% of saturation -- OR -- Bright: A Pixel with dark current >5,000 e /pixel/sec at 25 C Cluster Defect A grouping of not more than 5 adjacent point defects Column Defect A grouping of >5 contiguous point defects along a single column -- OR -- A column containing a pixel with dark current > 100,000 e /pixel/sec (bright column) -- OR -A column that does not meet the minimum vertical CCD charge capacity (low charge capacity column) -- OR -- - A column which loses more than 3500 e under 2 ke illumination (trap defect) Neighboring Pixels The surrounding 128 x 128 pixels or 64 columns/rows Defect Separation Column and cluster defects are separated by no less than two (2) pixels in any direction (excluding single pixel defects) Cluster defects are separated by no less than 2 pixels from other column and cluster defects. Column defects are separated by no less than 5 pixels from other column defects. www.truesenseimaging.com Revision 1.0 PS-0034 Pg. 19 KAF-4320 Image Sensor Operation ABSOLUTE MAXIMUM RATINGS Description Symbol Min. Max. Units Notes Diode Pin Voltages Vdiode 0 25 V 1, 2 Gate Pin Voltages -Type 1 Vgate1 -17 17 V 1, 3, 6 Gate Pin Voltages -Type 2 Vgate2 0 17 V 1, 4, 6 Iout -10 mA 5 Cload 15 pF 5 Output Bias Current Output Load Capacitance Notes: 1. 2. 3. 4. 5. 6. Referenced to pin Vsub or between each pin in this group. Includes pins: Vrd, Vdd, Vss, Vout. Includes pins: V1, V2, H1, H2, H1L, Includes pins: Vog, Vlg. R. Avoid shorting output pins to ground or any low impedance source during operation. This sensor contains gate protection circuits to provide protection against ESD events. The circuits will turn on when greater than 18 volts appears between any two gate pins. Permanent damage can result if excessive current is allowed to flow under these conditions. EQUIVALENT INPUT CIRCUITS Many of the pins contain a form of gate protection to prevent damage from electrostatic discharge. These take the form of zener diodes that prevent the voltage differences between gates from becoming large enough to damage the sensor. Isolated gates such as oR and Vlg require only protection between the gate and the sensor substrate. www.truesenseimaging.com oH1 oH2 oH1L oV1 oV2 Vog Sub oR Sub Sub Vlg Sub Revision 1.0 PS-0034 Pg. 20 KAF-4320 Image Sensor DC BIAS OPERATING CONDITIONS Description Units Max DC Current (mA) Notes Vrd 18.5 V 0.01 2 Output Amplifier Return Vss 2.0 V 1 3 Output Amplifier Supply Vdd 21 V Iout 2 Substrate GND 0 V Output Gate Vog 3 Output amplifier load gate Vlg Reset Drain Guard ring Amplifier Output Current Notes: 1. 2. 3. Symbol Min. Nom. Max 0 Vss Vss+1.0 Vguard 10 Iout -5 V 0.01 Vss+1.2 V 0.01 -10 mA V 3 - 1 An output load sink must be applied to Vout to provide a constant current source and activate the output amplifier - see Figure 13. Voltage tolerance is 2% (actual voltage should be nominal +/- tolerance). Voltage tolerance is 5% (actual voltage should be nominal +/- tolerance). Vdd 0.1uF ~5ma Vout 2N3904 or equivalent Buffered Output 140 1k Figure 13: Example Output Structure Load Diagram www.truesenseimaging.com Revision 1.0 PS-0034 Pg. 21 KAF-4320 Image Sensor AC OPERATING CONDITIONS Description Symbol Vertical CCD Clock - Phase 1 V1 Vertical CCD Clock - Phase 2 V2 Horizontal CCD Clock - Phase 1 H1 Horizontal CCD Clock -Last Gate H1L Horizontal CCD Clock - Phase 2 H2 Reset Clock Notes: 1. 2. 3. 4. 5. 6. 7. R Level Nom. Units Effective Capacitance Notes Low Level -8.0 8.0 V V 75 nF (each of V1 pins 30, 34, 71, 75) 4, 5 -8.0 8 V V 75 nF (each of V2 pins 31, 33, 72, 74) 4, 5 0 10.0 V V 150 pF (each of H1 pins 5, 16, 48, 57) 3, 6 -3.0 10.0 V V 10 pF 3 -3.0 10.0 V V 100 pF (each of H2 pins 6, 15, 49, 56) 3, 7 2.0 12.0 V V 5 pF 3 Clock Amplitude Low Level Clock Amplitude Low Level Clock Amplitude Low Level Clock Amplitude Low Level Clock Amplitude Low Level Clock Amplitude All pins draw less than 10 A DC current. Capacitance values relative to VSUB. Voltage tolerance is 2% (actual voltage should be nominal +/- tolerance). Voltage tolerance is 5% (actual voltage should be nominal +/- tolerance). Total clock capacitance is 4 * 75 nF = 300 nF. Total clock capacitance is 4 * 150 pF = 600 pF. Total clock capacitance is 4 * 100 pF = 400 pF. www.truesenseimaging.com Revision 1.0 PS-0034 Pg. 22 KAF-4320 Image Sensor AC TIMING CONDITIONS Description H1, H2 Clock Frequency Symbol Min. fH Nom. Max. Units Notes 3 3 MHz 1, 2, 3 Pixel Period (1 Count) te 333 333 ns H1, H2 Setup Time tHS 10 10 s V1, V2 Clock Pulse Width tV 30 30 s 2 Reset Clock Pulse Width tR 20 ns 4 470.3 470.3 ms 5 449.6 449.6 s Readout Time treadout Integration Time tint Line Time tline Notes: 1. 2. 3. 4. 5. 6. 7. 8. 6 7 50% duty cycle values. CTE will degrade above the nominal frequency. Rise and fall times (10 / 90% levels) should be limited to 5 - 10% of clock period. Crossover of register clocks should be between 40 - 60% of amplitude. R should be clocked continuously. treadout = ( 1046* tline ) Integration time is user specified. Longer integration times will degrade noise performance due to dark signal fixed pattern and shot noise. tline = ( 3* tV ) + tHS + ( 1050* te) When combining the image from the upper half of the device with that from the lower half, line 1047 from each must be added together and gained (approx. 1.2X) to match the other 1046 lines. www.truesenseimaging.com Revision 1.0 PS-0034 Pg. 23 KAF-4320 Image Sensor Pixel rate clock waveforms For best performance, the horizontal clocks should be damped, similar to those shown in Figure 14. The clocks in this figure were generated using a 50 Ohm output impedance clock driver. Excessively fast clocks can result in a higher noise floor. Figure 14: Clock Example www.truesenseimaging.com Revision 1.0 PS-0034 Pg. 24 KAF-4320 Image Sensor Timing Normal Read Out Frame Timing - per quadrant ( each output contains one half of the lines) tint tReadout 1 Frame = 1046 Lines V1 Line V2 1 2 1045 1046 H1, H1L H2 Line Timing Detail Pixel Timing Detail tV V1 tV R H1, H1L V2 tHS H1, H1L tR te H2 te 1 count Vpix H2 Vout 1050 counts Vsat R Vodc Vsub Line Content - per quadrant (each output contains one half of a line) 1-4 Vdark 5-8 Photoactive Pixels 9-1050 Dummy Pixels Vsat Saturated pixel video output signal Vdark Video output signal in no light situation, not zero due to Jdark Vpix Pixel video output signal level, more electrons =more negative* Vodc Video level offset with respect to vsub Vsub Analog Ground * See Image Aquisition section (page 4) Dark Reference Pixels Figure 15: Timing Diagrams For binning, please call Truesense Imaging, Inc. www.truesenseimaging.com Revision 1.0 PS-0034 Pg. 25 KAF-4320 Image Sensor POWER DISSIPATION The power dissipated by the CCD clocks is calculated using the formula: 2 Power = CV f Where C is the capacitance in farads, V is the clock amplitude in volts, and f is the frequency in Hz. Amplifier power The power dissipated by amplifiers is calculated by Power = I*V where I is the current and V is the voltage drop on the CCD. The sensor contains two stage source followers. The first stage draws approximately 250 micro amps and the voltage drop is Vdd - Vss. The second stage sources much more current, approximately 5 mA while the voltage drop on the sensor is much smaller, Vdd - Vout where Vout ~ Vrd. Total Power The table below shows the power dissipated at three different pixel frequencies. For each of these cases the amplifier operating conditions are held constant so its contribution is not frequency dependent. The time for the vertical clock transfers is also held constant (90 microseconds per line) but the line time changes depending on the pixel rate. Contributor Pixel rate Notes 500 kHz 1 MHz 3 MHz Pixel rate Amplifiers 120 mW 120 mW 120 mW Total of 4 outputs Hccd 60 mW 120 mW 360 mW Vccd 62 mW 121 mW 297 mW Total 241 mW 361 mW 776 mW www.truesenseimaging.com Revision 1.0 PS-0034 Pg. 26 KAF-4320 Image Sensor CCD Surface Flatness The flatness of the die is defined as a peak-to-peak distortion in the image sensor surface. The parallelism between the image sensor surface and any of the package components is not specified or guaranteed. The non-parallelism is removed when measuring the distortion in the image sensor surface. Min. Die Flatness Peak to peak distortion Nom. Max. Units 8.8 12.0 microns Some examples of profiles of some typical image sensors surfaces are shown below. Figure 16: Die Flatness Data www.truesenseimaging.com Revision 1.0 PS-0034 Pg. 27 KAF-4320 Image Sensor Figure 17: Die Flatness Data Figure 18: Die Flatness Data www.truesenseimaging.com Revision 1.0 PS-0034 Pg. 28 KAF-4320 Image Sensor 3. Improper cleaning of the cover glass may damage these devices. Refer to Application Note Image Sensor Handling Best Practices. Storage and Handling STORAGE CONDITIONS Description Symbol Minimum Storage Temperature TST -100 Operating Temperature TOP -70 Notes: 1. Maximum Units Notes +80 C At Device +50 C At Device Image sensors with temporary cover glass should be stored at room temperature (nominally 25 C.) in dry nitrogen ESD 1. This device contains limited protection against Electrostatic Discharge (ESD). ESD events may cause irreparable damage to a CCD image sensor either immediately or well after the ESD event occurred. Failure to protect the sensor from electrostatic discharge may affect device performance and reliability. 2. Devices should be handled in accordance with strict ESD procedures for Class 0 (<250 V per JESD22 Human Body Model test), or Class A (<200 V JESD22 Machine Model test) devices. Devices are shipped in static-safe containers and should only be handled at static-safe workstations. 3. See Application Note Image Sensor Handling Best Practices for proper handling and grounding procedures. This application note also contains workplace recommendations to minimize electrostatic discharge. 4. Store devices in containers made of electroconductive materials. COVER GLASS CARE AND CLEANLINESS 1. The cover glass is highly susceptible to particles and other contamination. Perform all assembly operations in a clean environment. 2. Touching the cover glass must be avoided. www.truesenseimaging.com ENVIRONMENTAL EXPOSURE 1. Extremely bright light can potentially harm CCD image sensors. Do not expose to strong sunlight for long periods of time, as the color filters and/or microlenses may become discolored. In addition, long time exposures to a static high contrast scene should be avoided. Localized changes in response may occur from color filter/microlens aging. For Interline devices, refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible lighting Conditions. 2. Exposure to temperatures exceeding maximum specified levels should be avoided for storage and operation, as device performance and reliability may be affected. 3. Avoid sudden temperature changes. 4. Exposure to excessive humidity may affect device characteristics and may alter device performance and reliability, and therefore should be avoided. 5. Avoid storage of the product in the presence of dust or corrosive agents or gases, as deterioration of lead solderability may occur. It is advised that the solderability of the device leads be assessed after an extended period of storage, over one year. SOLDERING RECOMMENDATIONS 1. The soldering iron tip temperature is not to exceed 370 C. Higher temperatures may alter device performance and reliability. 2. Flow soldering method is not recommended. Solder dipping can cause damage to the glass and harm the imaging capability of the device. Recommended method is by partial heating using a grounded 30 W soldering iron. Heat each pin for less than 2 seconds duration. Revision 1.0 PS-0034 Pg. 29 KAF-4320 Image Sensor Mechanical Drawings COMPLETED ASSEMBLY Figure 19: Completed Assembly (1 of 2) www.truesenseimaging.com Revision 1.0 PS-0034 Pg. 30 KAF-4320 Image Sensor Figure 20: Completed Assembly (2 of 2) www.truesenseimaging.com Revision 1.0 PS-0034 Pg. 31 KAF-4320 Image Sensor Quality Assurance and Reliability QUALITY AND RELIABILITY All image sensors conform to the specifications stated in this document. This is accomplished through a combination of statistical process control and visual inspection and electrical testing at key points of the manufacturing process, using industry standard methods. Information concerning the quality assurance and reliability testing procedures and results are available from Truesense Imaging upon request. For further information refer to Application Note Quality and Reliability. REPLACEMENT All devices are warranted against failure in accordance with the Terms of Sale. Devices that fail due to mechanical and electrical damage caused by the customer will not be replaced. LIABILITY OF THE SUPPLIER A reject is defined as an image sensor that does not meet all of the specifications in this document upon receipt by the customer. Product liability is limited to the cost of the defective item, as defined in the Terms of Sale. LIABILITY OF THE CUSTOMER Damage from mishandling (scratches or breakage), electrostatic discharge (ESD), or other electrical misuse of the device beyond the stated operating or storage limits, which occurred after receipt of the sensor by the customer, shall be the responsibility of the customer. TEST DATA RETENTION Image sensors shall have an identifying number traceable to a test data file. Test data shall be kept for a period of 2 years after date of delivery. MECHANICAL The device assembly drawing is provided as a reference. Truesense Imaging reserves the right to change any information contained herein without notice. All information furnished by Truesense Imaging is believed to be accurate. Life Support Applications Policy Truesense Imaging image sensors are not authorized for and should not be used within Life Support Systems without the specific written consent of Truesense Imaging, Inc. www.truesenseimaging.com Revision 1.0 PS-0034 Pg. 32 KAF-4320 Image Sensor Revision Changes MTD/PS-0677 Revision Number Description of Changes 1.0 First formal release. 2.0 Updated format. Add completed assembly drawing. Updated part designations. Changed column definition to >100,000 e-. Updated diagrams of chip architecture to show 1047 vertical lines. Corrected "Image Performance" table. Deleted section on binning per ECO 1046. Changed column definition number "4" to "A column which loses more than 3500 e- under 2 ke- illumination (trap defect)". Corrected titles for Linearity chart and System Dynamic Range chart per ECO 1060. Corrected total number of pixels. 3.0 4.0 p. 31-32 Corrected Completed Assembly Drawing 4.1 p. 21 Removed the temperature and humidity from the table of Absolute Maximum Ratings and removed Note 6. Renumbered notes. p. 23 Separated Levels column into two rows, Low Level and Clock Amplitude p. 30 Corrected Storage and Operating Temperatures. p.9 Corrected labels for Vss and Vlg p.10 Corrected labels for Vss and Vlg and added a note stating like named pins should be connected to the same supply p.11 Updated expected values for the amplifier DC offset. Removed incorrect units from the dark current specification p.22 Updated DC bias operating conditions ECO 1137 PS-0034 Revision Number 1.0 Description of Changes Initial release with new document number, updated branding and document template Updated Storage and Handling and Quality Assurance and Reliability sections www.truesenseimaging.com (c)Truesense Imaging Inc., 2012. TRUESENSE is a registered trademark of Truesense Imaging, Inc. Revision 1.0 PS-0034 Pg. 33