2.5V CMOS Static RAM 1 Meg (64K x 16-Bit) IDT71T016SA Features Description The IDT71T016 is a 1,048,576-bit high-speed Static RAM organized as 64K x 16. It is fabricated using IDT's high-performance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for highspeed memory needs. The IDT71T016 has an output enable pin which operates as fast as 5ns, with address access times as fast as 10ns. All bidirectional inputs and outputs of the IDT71T016 are LVTTL-compatible and operation is from a single 2.5V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71T016 is packaged in a JEDEC standard a 44-pin Plastic SOJ, 44-pin TSOP Type II, and a 48-ball plastic 7 x 7 mm FBGA. 64K x 16 advanced high-speed CMOS Static RAM Equal access and cycle times -- Commercial: 10/12/15/20ns -- Industrial: 12/15/20ns One Chip Select plus one Output Enable pin Bidirectional data inputs and outputs directly LVTTL-compatible Low power consumption via chip deselect Upper and Lower Byte Enable Pins Single 2.5V power supply Available in 44-pin Plastic SOJ, 44-pin TSOP, and 48-Ball Plastic FBGA packages Functional Block Diagram JULY 2008 1 (c) 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-5326/02 IDT71T016SA, 2.5V CMOS Static RAM 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges Pin Configurations 1 2 3 4 5 6 A BLE OE A0 A1 A2 NC B I/O8 BHE A3 A4 CS I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D VSS I/O11 NC A7 I/O3 VDD E VDD I/O12 NC NC I/O4 VSS F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H NC A8 A9 A10 A11 NC 5326 tbl 02a FBGA (BF48-1) Top View Pin Description TSOP Top View A0 - A15 Address Inputs Input CS Chip Select Input WE Write Enable Input OE Output Enable Input BHE High Byte Enable Input BLE Low Byte Enable Input I/O0 - I/O15 Data Input/Output I/O VDD 2.5V Power VSS Ground Power Gnd Truth Table(1) 5326 tbl 01 CS OE WE BLE BHE I/O0-I/O7 I/O8-I/O15 H X X X X High-Z High-Z Deselected - Standby L L H L H DATAOUT High-Z Low Byte Read L L H H L High-Z DATA OUT High Byte Read L L H L L DATAOUT DATA OUT Word Read L X L L L DATAIN DATAIN Word Write L X L L H DATAIN High-Z Low Byte Write L X L H L High-Z DATAIN High Byte Write L H H X X High-Z High-Z Outputs Disabled L X X H H High-Z High-Z Outputs Disabled Function 5326 tbl 02 NOTE: 1. H = VIH, L = VIL, X = Don't care. 6.42 2 IDT71T016SA, 2.5V CMOS Static RAM 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges Absolute Maximum Ratings(1) Symbol Rating Value Unit VDD Supply Voltage Relative to VSS -0.3 to +3.6 V VIN, VOUT Terminal Voltage Relative to VSS -0.3 to VDD+0.3 V TBIAS Temperature Under Bias -55 to +125 o C TSTG Storage Temperature -55 to +125 o C PT Power Dissipation 1.25 W IOUT DC Output Current 50 mA Recommended Operating Temperature and Supply Voltage Grade Temperature VSS VDD Commercial 0C to +70C 0V See Below Industrial -40C to +85C 0V See Below 5326 tbl 04 Recommended DC Operating Conditions Symbol 5326 tbl 03 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Capacitance Parameter(1) CIN Input Capacitance CI/O I/O Capacitance VDD Supply Voltage Vss Ground VIH VIL Input High Voltage Min. Typ. Max. Unit 2.375 2.5 2.625 V 0 0 0 1.7 ____ (2) Input Low Voltage -0.3 V (1) VDD+0.3 ____ V 0.7 V 5326 tbl 05 NOTES: 1. VIH (max) = VDD + 1.0V a.c. (pulse width less than tCYC/2) for I < 20 mA, once per cycle. 2. VIL (min) = -1.0V a.c. (pulse width less than tCYC/2) for I < 20 mA, once per cycle. (TA = +25C, f = 1.0MHz) Symbol Parameter Conditions Max. Unit V IN = 3dV 6 pF V OUT = 3dV 7 pF 5326 tbl 06 NOTE: 1. This parameter is guaranteed by device characterization, but not production tested. DC Electrical Characteristics (VDD = Min. to Max., Commercial and Industrial Temperature Ranges) IDT71T016SA Symbol |ILI| |ILO| Parameter Test Condition Min. Max. Unit Input Leakage Current VDD = Max., V IN = V SS to VDD ___ 5 A Output Leakage Current VDD = Max., CS = VIH, VOUT = VSS to VDD ___ 5 A 0.7 V ___ V VOL Output Low Voltage IOL = 2.0mA, V DD = Min. ___ V OH Output High Voltage IOH = 2.0mA, VDD = Min. 1.7 DC Electrical Characteristics(1,2) 5326 tbl 07 (VDD = Min. to Max., VLC = 0.2V, VHC = VDD - 0.2V) 71T016SA10 71T016SA12 71T016SA15 71T016SA20 Parameter Symbol ICC Dynamic Operating Current CS < VLC, Outputs Open, VDD = Max., f = fMAX(3) Com'l Com'l Ind Com'l Ind Com'l Ind Max. 160 150 160 130 130 120 120 Typ.(4) 90 85 ____ 80 ____ 80 ____ Unit mA ISB Dynamic Standby Power Supply Current CS > VHC, Outputs Open, VDD = Max., f = fMAX(3) 45 40 45 35 35 30 30 mA ISB1 Full Standby Power Supply Current (static) CS > VHC, Outputs Open, VDD = Max., f = 0(3) 10 15 15 15 15 15 15 mA NOTES: 5326 tbl 8 1. All values are maximum guaranteed values. 2. All inputs switch between 0.2V (Low) and VDD - 0.2V (High). 3. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing . 4. Typical values are measured at 2.5V, 25C and with equal read and write cycles. This parameter is guaranteed by device characterization but is not production tested. 6.42 3 IDT71T016SA, 2.5V CMOS Static RAM 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges AC Test Conditions Input Pulse Levels 0V to 2.5V Input Rise/Fall Times 1.5ns Input Timing Reference Levels (VDD/2) Output Reference Levels (VDD/2) AC Test Load See Figure 1, 2 and 3 5326 tbl 09 AC Test Loads +1.25V 50 I/O Z0 = 50 30pF 5326 drw 03 *Including jig and scope capacitance. Figure 1. AC Test Load Figure 2. AC Test Load (for t CLZ, tOLZ, tCHZ, tOHZ , tOW, and tWHZ) Figure 3. Output Capacitive Derating 6.42 4 IDT71T016SA, 2.5V CMOS Static RAM 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges AC Electrical Characteristics (VDD = Min. to Max., Commercial and Industrial Temperature Ranges) 71T016SA10(2) Symbol Parameter 71T016SA12 71T016SA15 71T016SA20 Min. Max. Min. Max. Min. Max. Min. Max. Unit Read Cycle Time 10 ____ 12 ____ 15 ____ 20 ____ ns tAA Address Access Time ____ 10 ____ 12 ____ 15 ____ 20 ns tACS Chip Select Access Time ____ 10 ____ 12 ____ 15 ____ 20 ns tCLZ(1) Chip Select Low to Output in Low-Z 4 ____ 4 ____ 5 ____ 5 ____ ns tCHZ(1) Chip Select Hig h to Output in High-Z ____ 5 ____ 6 ____ 6 ____ 8 ns tOE Output Enable Low to Output Valid ____ 5 ____ 6 ____ 7 ____ 8 ns tOLZ(1) Output Enable Low to Output in Low-Z 0 ____ 0 ____ 0 ____ 0 ____ ns tOHZ(1) Output Enable High to Output in High-Z ____ 5 ____ 6 ____ 6 ____ 8 ns tOH Output Hold from Address Change 4 -- 4 -- 4 -- 4 -- ns tBE Byte Enable Low to Output Valid -- 5 -- 6 -- 7 ____ 8 ns tBLZ(1) Byte Enable Low to Output in Low-Z 0 ____ 0 ____ 0 ____ 0 ____ ns tBHZ(1) Byte Enable High to Output in High-Z ____ 5 ____ 6 ____ 6 ____ 8 ns READ CYCLE tRC WRITE CYCLE tWC Write Cycle Time 10 ____ 12 ____ 15 ____ 20 ____ ns tAW Address Valid to End of Write 7 ____ 8 ____ 10 ____ 12 ____ ns tCW Chip Select Low to End of Write 7 ____ 8 ____ 10 ____ 12 ____ ns 8 ____ 10 ____ 12 ____ ns tBW Byte Enable Low to End of Write 7 ____ tAS Address Set-up Time 0 ____ 0 ____ 0 ____ 0 ____ ns tWR Address Ho ld from End of Write 0 ____ 0 ____ 0 ____ 0 ____ ns 7 ____ 8 ____ 10 ____ 12 ____ ns 6 ____ 7 ____ 9 ____ ns 0 ____ 0 ____ 0 ____ ns 3 ____ 3 ____ ns ____ 6 ____ 8 ns Write Pulse Width tWP tDW Data Valid to End of Write 5 ____ tDH Data Hold Time 0 ____ 3 ____ ____ 6 (1) tOW Write Enable High to Output in Low-Z 3 ____ tWHZ(1) Write Enable Low to Output in High-Z ____ 5 NOTES: 1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested. 2. 00C to +700C temperature range only. Timing Waveform of Read Cycle No. 1(1,2,3) NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. OE, BHE, and BLE are LOW. 6.42 5 5326 tbl 10 IDT71T016SA, 2.5V CMOS Static RAM 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges Timing Waveform of Read Cycle No. 2(1) NOTES: 1. WE is HIGH for Read Cycle. 2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter. 3. Transition is measured 200mV from steady state. Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4) NOTES: 1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE. 2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + t DW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured 200mV from steady state. 6.42 6 IDT71T016SA, 2.5V CMOS Static RAM 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4) Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing)(1,4) NOTES: 1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE. 2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + t DW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured 200mV from steady state. 6.42 7 IDT71T016SA, 2.5V CMOS Static RAM 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges Ordering Information 6.42 8 IDT71T016SA, 2.5V CMOS Static RAM 1 Meg (64K x 16-bit) Commercial and Industrial Temperature Ranges Datasheet Document History Rev 0 1 Date 08/23/01 04/16/04 Page 2 07/14/08 p. 1,2,6,7 p. 1-8 p. 3 Description Created new datasheet Updated datasheet to full release version. Updated overshoot and undershoot specifications and typical DC electrical characteristics. Corrected pin labels output enable, chip select, write enable, high and low byte enables to be OE, CS, WE, BHE, BLE to reflect active low nature. CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 9 for Tech Support: ipchelp@idt.com 800-345-7015