PRELIMINARY
100-MHz Pentium® II Clock Synthesizer/Driver with
Spread Spectrum for Mobile or Desktop PCs
CY2280
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Decemb er 24
,
1998
Features
• Mixed 2.5V and 3.3V operat ion
• Clock solution for Pentium® II, and other similar pro-
cessor-based motherboards
—Four 2.5V CPU cloc ks up to 100 MHz
—Eight 3.3V synch. PCI clocks, one free-running
—Two 3.3 V 48-MHz USB clocks
—Th ree 3.3V Ref. clocks at 14.318 MHz
— Two 2.5V A P I C clock s at 14 .3 18 M Hz or P CI/2
• EMI control
—Spread spectrum cl ocking
—F actory-EPR O M programmab le spr ead spectrum
margin
—Factory-EPROM programmable output drive and
sl ew ra te
• Fa ctory-EPROM pr ogrammab le CPU cloc k frequenci es
for custom confi gurations
• Available in spac e-saving 48-pin SSOP pac kage
Functional Descripti on
The CY2280 i s a Spread Spect rum clo ck synthesi zer/driver for
a Pentium II, or other similar processor-based PC requiring
100-MHz support. Al l o f the requi re d system cloc ks are pro vid-
ed in a space sa ving 48-pin SSOP package. The CY2280 can
be used with the CY231x for a total solution for systems wi th
SDRAM.
The CY2280 provides the opti on of spread spectrum clocking
on the CPU and PCI clocks for reduced EMI. A downspread
percentage is introduced when the SEL_SS input is asserted .
The device can be run without spread spectrum when the
SEL_SS input is deasserted. The percentage of spreading is
EPROM-programmable to optimize EMI-reduction.
The CY2280 has power-down, CPU stop, and PCI stop pins
for powe r m anagement contr ol. The signals are synchronized
on-chip, and ensure glitch-free transitions on the outputs.
When the CPU_STOP input is asser ted, the CPU clock out-
puts are driven LOW. When the PCI_STOP input is asser ted,
the PCI clock outputs (except the free-r unning PCI clock) are
driven LOW. When the PWR_DWN pin is asserted, the refer-
ence oscillator and PLLs are shut down, and all outputs are
driven LOW.
CY2280 Selector Guide CY2280 Configuration Options
Clock Outputs -1 -11S -12S -13S -21S - 31S
CPU (66.6, 100 MHz) 4 4 4 4 4 4
PCI (CPU/2, CPU/3) 888888
USB (48 MHz) 222222
APIC (14.318 MHz) 2 2 2 2 -- 2
APIC (PCI/2) --------2--
Reference (1 4.318 MHz) 3 3 3 3 3 3
CPU-PCI del ay 1.5−4.0 ns 1.5−4.0 ns 1.5−4.0 ns 1.5−4.0 ns 1. 5−4.0 ns 0 ns
CPU-APIC delay -- -- -- -- 2.0- 4.5 ns --
Spread Spectrum
(Downspread) N/A −0.6% −1.0% −1.5% −0.6% −0.6%
Pentium is a registered trademark of Intel Corporation.
Logic Bloc k Diagram
EPROM
XTALOUT
XTALIN
APIC [0:1]
14.318
MHz
OSC.
SEL0
V
DDAPIC
CPU
PLL
SEL100
Delay
REF [0-2]
CPUCLK [0-3]
V
DDCPU
PCI [1-7]
PCICLK_F
STOP
STOP
LOGIC
LOGIC
SEL1
USBCLK [0:1]
SYS PLL
CPU_STOP
PWR_DWN
Divider
PCI_STOP V
DDPCI
V
DDPCI
V
DDREF
V
DDUSB
-1
-2
SEL_SS
2
CY2280
Pin Summary
Name Pins Description
VDDPCI 15, 9 3.3V Digit al voltage supply f or PCI clocks
VDDUSB 21 3.3V Digital voltage supply f or USB cl ocks
VDDREF 48 3.3V Digital voltage supply f or REF cl ocks
VDDAPIC 46 2.5V Digit al voltage suppl y for APIC clocks
VDDCPU 41, 37 2.5V Di git al voltage supply for CPU cl ocks
AVDD 33, 19 Analog voltage supply, 3.3V
VSS 3, 6, 12, 18, 20, 24, 32, 34, 38 , 4 3 Ground
XTALIN[1] 4Ref erence crystal in put
XTALOUT[1] 5Referen ce crystal feedbac k
PCI_STOP 31 Acti ve LOW control input to stop PCI cl ocks
CPU_STOP 30 Active LO W control input to stop CPU clocks
PWR_DWN 29 Active LO W control input to power down device
SEL_SS 28 Spread spect rum select input (-11S, -12S, -1 3S, -21S, -31S opti ons)
N/C 28 Spread spectrum select input (-1 option)
SEL0 27 CPU frequency select i nput, bit 0 (see Funct ion Table)
SEL1 26 CPU frequency select i nput, bit 1 (see Function Tab le)
SEL100 25 CPU frequency select i nput, selects bet ween 100 MHz and 66.6 MHz
(s e e Fu nc t io n Table)
CPUCLK[0:3] 40, 39, 36, 35 CPU clock outputs
PCICLK[1:7] 8, 10, 11, 13, 14, 16, 17 PCI clock outputs, at one-half or one-third the CPU frequency of 66.6 MHz
or 100 M Hz respectively
PCICLK_F 7Free-running PCI clock output
APIC[0:1] 45, 44 APIC cl ock output s
REF[0:2] 1, 2, 47 3.3V Reference clock outputs
USBCLK[0:1] 22, 23 USB clock outputs
RESERVED 42 Reserved
Note:
1. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF.
Pin Configurations 1
2
3
4
5
6
7
8
9
10
11
12
33
32
31
30
29
25
26
27
28
36
35
REF0
34
13
14
15
16
17
18
19
20
21
22
23
24
45
44
43
42
41
37
38
39
40
48
47
46
REF1
VSS
XTALIN
XTALOUT
PCICLK_F
VSS
PCICLK1
PCICLK2
VDDPCI
PCICLK3
VSS
PCICLK4
VDDPCI
PCICLK5
PCICLK7
VSS
AVDD
VSS
VDDUSB
USBCLK0
USBCLK1
VSS
VDDREF
REF2
VDDAPIC
APIC0
APIC1
VSS
RESERVED
VDDCPU
CPUCLK0
CPUCLK1
VSS
VDDCPU
CPUCLK2
CPUCLK3
VSS
AVDD
PCI_STOP
PWR_DWN
N/C
SEL0
SEL1
SEL100
CPU_STOP
VSS
PCICLK6
1
2
3
4
5
6
7
8
9
10
11
12
33
32
31
30
29
25
26
27
28
36
35
REF0
34
13
14
15
16
17
18
19
20
21
22
23
24
45
44
43
42
41
37
38
39
40
48
47
46
REF1
VSS
XTALIN
XTALOUT
PCICLK_F
VSS
PCICLK1
PCICLK2
VDDPCI
PCICLK3
VSS
PCICLK4
VDDPCI
PCICLK5
PCICLK7
VSS
AVDD
VSS
VDDUSB
USBCLK0
USBCLK1
VSS
VDDREF
REF2
VDDAPIC
APIC0
APIC1
VSS
RESERVED
VDDCPU
CPUCLK0
CPUCLK1
VSS
VDDCPU
CPUCLK2
CPUCLK3
VSS
AVDD
PCI_STOP
PWR_DWN
SEL_SS
SEL0
SEL1
SEL100
CPU_STOP
VSS
PCICLK6
CY2280-1
CY2280-11S
CY2280-12S
CY2280-13S
CY2280-21S
CY2280-31S
48-pin SSOP (Top View)
48-pin SSOP (Top View)
3
CY2280
Function Table (-11S, -12 S, -13S, -3 1S Options)
SEL100 SEL1 SEL0 SEL_SS[2] CPU/PCI
Ratio CPUCLK PCICLK_F
PCICLK REF APIC USBCLK
0 0 0 N/A 2 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
0 0 1 N /A 2 Reserv ed Reserved 14.318 MH z 14.318 MH z 48 MHz
0 1 0 N /A 2 Reserv ed Reserved 14.318 MH z 14.318 MH z 48 MHz
0 1 1 0 (downspread) 2 66.66 MHz 33. 33 MHz 14.318 MH z 14.318 MH z 48 MHz
0 1 1 1 (no spread) 2 66.66 MHz 33. 33 MHz 14.318 MH z 14.318 MH z 48 MHz
1 0 0 N/A 3 TCLK/2 TCLK/6 TCLK[3] TCLK[3] TCLK/2
1 0 1 N /A 3 Reserv ed Reserved 14.318 MH z 14.318 MH z 48 MHz
1 1 0 N /A 3 Reserv ed Reserved 14.318 MH z 14.318 MH z 48 MHz
1 1 1 0 (downspread) 3 100 MH z 33.33 MHz 14.318 MHz 14.318 MHz 48 MHz
Function Table (-21S Option)
SEL100 SEL1 SEL0 SEL_SS[2] CPU/PCI
Ratio CPUCLK PCICLK_F
PCICLK REF APIC USBCLK
0 0 0 N/A 2 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
0 0 1 N /A 2 Reserv ed Reserved 14.318 MH z Reserved 48 MHz
0 1 0 N /A 2 Reserv ed Reserved 14.318 MH z Reserved 48 MHz
0 1 1 0 (downspread) 2 66.66 MHz 33. 33 MHz 14.318 MH z 16.67 MHz 48 MHz
0 1 1 1 (no spread) 2 66.66 MHz 33. 33 MHz 14.318 MH z 16.67 MHz 48 MHz
1 0 0 N/A 3 TCLK/2 TCLK/6 TCLK[3] TCLK/12[3] TCLK/2
1 0 1 N /A 3 Reserv ed Reserved 14.318 MH z Reserved 48 MHz
1 1 0 N /A 3 Reserv ed Reserved 14.318 MH z Reserved 48 MHz
1 1 1 0 (downspread) 3 100 MH z 33.33 MHz 14.318 MHz 16.67 MHz 48 MHz
Actual Clock Frequenc y Values
Clock Output Target Frequency
(MHz) Actual Frequency
(MHz) PPM
CPUCLK 66.67 66.654 –195
CPUCLK 100 99.77 –2346
USBCLK 48.0 48.008 167
Power Management Logic
CPU_STOP PCI_STOP PWR_DWN CPUCLK PCICLK PCICLK_F Other
Clocks Osc. PLLs
X X 0 Low Low Low Low Off Off
0 0 1 Low Low Running Running Running Running
0 1 1 Low Running Running Running Running Running
1 0 1 Running Low Running Running Running Running
1 1 1 Running Running Running Running Running Running
Notes:
2. Target frequency is modulated by percentage shown (max.) when SEL_SS = 0.
3. TCLK supplied on the XTALIN pin in Test Mode.
4
CY2280
Maximum Ratings
(Above whi ch the useful lif e m ay be impaired. For user guide-
li nes, not tested.)
Supply Voltage..................................................–0.5 to +7.0V
Input Voltage................. .... ............. .. ..........–0.5V to VDD+0.5
Storage Temperature (Non-Condensing) ... –65°C to +150°C
Max. Soldering Temperature (10 sec) ...................... +260°C
Junction Temperature............................................... +150°C
Package Pow er Dissipation .............................................. 1W
Static Discharge Voltage ... .. .......... .. .......... ........ .... ....>2000V
(per MIL- STD-883, Method 3015, like VDD pi ns tied together)
Operating Conditions[4]
Parameter Description Min. Max. Unit
AVDD, VDDPCI,
VDDUSB, VDDREF Analog and Digit al Supply Voltage 3.135 3.465 V
VDDCPU CPU Supply Voltage 2.375 2.625 V
VDDAPIC APIC Supply Voltage 2.375 2.625 V
TAOper ating Temperature, Ambien t 0 70 °C
CLMax. Capacitive Load on
CPUCLK
PCICLK
APIC, REF
USB
20
30
20
20
pF
f(REF) Reference Frequency, Oscillator Nominal Value 14.318 14. 318 MHz
Electrica l Characte ristics Over the Operating Range
Parameter Description Test Conditions Min. Max. Unit
VIH High-level Input Voltage Except Cr ystal Inputs[5] 2.0 V
VIL Low-level Input Voltage Except Crystal Inputs[5] 0.8 V
VOH High- level Output Voltage[6] VDDCPU = VDDAPIC = 2.3 75V IOH = 12 mA CPUCLK 2.0 V
IOH = 18 mA API C
VOL Low-level Output Voltage[6] VDDCPU = V DDAPIC = 2.375V IOL = 12 mA CPUCLK 0. 4 V
IOL = 18 mA APIC
VOH High- level Output Voltage[6] VDDPCI, AV DD, V DDREF
, VDDUSB = 3 .135V IOH = 14.5 mA PCICLK 2.4 V
IOH = 16 mA USBCLK
IOH = 16 mA REF
VOL Low-level Output Voltage[6] VDDPCI, AVDD, V DDREF
, VDDUSB= 3.135V I OL = 9.4 mA PCICLK 0.4V V
IOL = 9 mA USBCLK
IOL = 9 mA REF
IIH Input High Current VIH = VDD –10 +10 µA
IIL Input Low Current VIL = 0V 10 µA
IOZ Output Leakage Current Three-state –10 +10 µA
IDD25 Power Supply Current for
2.5V Clocks[6] VDDCPU = 2.625V, VIN = 0 o r VDD, Loaded Output s, CPU = 66.6 MHz 70 mA
IDD25 Power Supply Current for
2.5V Clocks[6] VDDCPU = 2.6 25V, VIN = 0 or VDD, Loaded Output s , CPU = 100 MHz 100 mA
IDD33 Power Supply Current for
3.3V Clocks[6] VDD = 3.465V, VIN = 0 o r VDD, Loaded Outputs 170 mA
IDDS P ower-down Current [6] Current draw in powerdown state 500 µA
Notes:
4. Electrical parameters are guaranteed with these operating conditions.
5. Crystal Inputs have CMOS thresholds.
6. Parameter is guaranteed by design and characterization. Not 100% tested in production.
5
CY2280
Swi tch ing C h aracteri sti cs[6, 7]
Parameter Output Description Test Conditions Min. Typ. Max. Unit
t1All Output Duty Cycle[8] t1 = t1A ÷ t1B 45 50 55 %
t2CPUCLK,
APIC CPU and APIC Clock
Risi ng and Falli ng Edge
Rate
Between 0.4V and 2.0V -1,-11S,
-12S,-13S,
-21S only
1.0 4.0 V/ns
-31S only 0.8 4.0 V/ns
t2PCICLK PCI Clock Risi ng and
Falling Edge Rate Between 0.4V and 2.4V -1,-11S,
-12S,-13S,
-21S only
1.0 4.0 V/ns
-31S only 0.9 4.0 V/ns
t2USBCLK,
REF USB , REF Risi ng and
Falling Edge Rate Between 0.4V and 2.4V 0.5 2.0 V/ns
t3CPUCLK CPU Clock Ris e Time Between 0. 4V and 2.0V -1,-11S,
-12S,-13S,
-21S only
0.4 1.6 ns
-31S only 0.4 2.0 ns
t4CPUCLK CPU Clock F al l Time Between 2.0V and 0.4V -1,-11S,
-12S,-13S,
-21S only
0.4 1.6 ns
-31S only 0.4 2.0 ns
t5CPUCLK CPU-CPU Clock Skew Measur ed at 1.25V 100 175 ps
t6CPUCLK,
PCICLK CPU-PCI Clock Ske w[9] Measur ed at 1.25V for 2.5V
clocks, and at 1.5V for 3.3V
clocks
-1,-11S,
-12S,-13S,
-21S only
1.5 4.0 ns
-31S only –1 1ns
t7PCICLK,
PCICLK PCI-PCI Clo ck Ske w Measur ed at 1.5V 250 ps
t8CPUCLK,
APIC CPU-APIC Clock
Skew[10] Measured at 1.25V for 2. 5V
clocks -21S only 2.0 4.5 ns
t9APIC APIC-APIC Cloc k Skew Measured at 1. 25V 100 175 ps
t10 CPUCLK Cycle-Cycle Clock Jitter Measur ed at 1.25V -1,-11S,
-12S,-13S,
-21S only
200 250 ps
-31S only 250 350 ps
t11 PCICLK Cycle-Cycle Clock Jitt er Measured at 1.5V 250 500 ps
t12 CPUCLK,
PCICLK Power -up Time CPU, PCI clock stabil ization from
power-up 3ms
Notes:
7. All parameters specified with loaded outputs.
8. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V.
9. PCI lags CPU for -11S, -12S, -13S, -14S, -21S options.
10. APIC lags CPU for -21S option.
6
CY2280
Swi tch ing Waveforms
Duty Cycle Timing
t1A t1B
OUTPUT
All Outp uts Ri se/Fall Time
OUTPUT
t2
t3
VDD
0V
t2
t4
CPU-CPU Clock Skew
t5
CPUCLK
CPUCLK
CPU-PCI Cl ock Skew
t6
CPUCLK
PCICLK
t7
PCICLK
PCICLK
PCI-PCI Clock Skew
t8
CPUCLK
APIC
CPU-APIC Cl ock Skew (-21S only )
7
CY2280
Swi tch ing Waveforms (conti nued)
t9
APIC
APIC
APIC-APIC Clock Skew
CPU_STOP
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
(Free-Running)
CPU_STOP
CPUCLK
(External)
PCI_STOP
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
PCI_STOP
PCICLK
(External)
(Free-Running)
PWR_DOWN
CPUCLK
(Internal)
PCICLK
(Internal)
PWR_DWN
PCICLK
CPUCLK
(External)
(External)
VCO
Crystal
Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.
8
CY2280
Frequency (MHz)
Amplitude (dB)
Spread Spectrum Enabled
Spread Spectrum Disabled
SPREAD SPECTRUM CLOCKING
Description Max. Unit
Outputs Min.
Down Spread Margin at the Fundamental F requency −0.6 %
Modulation Frequency
CPU, PCI
30.0 33.0 kHz
0.0
Configuration
All (except - 1)
Down Spread Margin at the Fundamental Frequency
Down Spread Margin at the Fundamental Frequency
Down Spread Margin at the Fundamental Frequency
CPU, PCI
CPU, PCI
CPU, PCI, APIC
−1.0 %
0.0
−1.5 %
0.0
−0.6 %
0.0
-11S, -31S
-12S
-13S
-21S
9
CY2280
Application Informa tion
Clock traces must be terminated with either seri es or par allel termination, as they are normally done.
Application Circ uit
Summary
• A parall el-resonant crystal should be used as the reference t o the clock generator. The operating frequency and CLOAD of
this crystal shou ld be as specif ied in the data sheet . Optional trimming capa citor s may be needed if a cryst al with a di ff eren t
CLOAD is used. Footprints must be laid out f or flexibility.
• S urfa ce mo unt, lo w-ESR, cera mic capacitors should be used for filtering. Typically, these capacitors have a v alue of 0.1 µF.
In som e cases, smaller val ue capacitors may be required.
• The value of the series terminat ing resistor satisfi es the follo w ing equation, where Rtrace is the loaded characteristic imp ed-
ance of t he tr ace , Rout is the out put imped ance o f the cloc k genera tor (speci fied in the d ata sheet ) , and Rseri es is t he series
terminating resistor.
Rseries > Rtrace – Rout
• Footprints must be laid out for optional EMI-r educing capacitors , which should be placed as c lose to the termi nating resistor
as is physicall y possib le. Typical values of these capaci tors range from 4.7 pF to 22 pF.
• A Ferrite Bead may be used to i solate the Board VDD from the clock gener ator VDD island. Ens ure that the Ferrit e Bead
offers greater than 50Ω impedance at the clock fr equency, under loaded DC conditi ons. Please refer to the appl ication note
“Layout and Termination Techniques for Cyp ress Clock Generators” for more det ails.
• If a Ferrite Bead is used, a 10 µF–22 µF tantal um by pass capacitor sho uld be plac ed close to the F errite Bead. Thi s capacitor
prevents power supply droop during current surges.
10
CY2280
Document #: 38-00694-C
Test Circuit
3, 6, 12, 18, 20, 24, 32, 34, 38, 43
9, 15, 19, 21, 33, 48
VDDPCI, VDDCORE,
CLOAD
OUTPUTS
0.1 µF
0.1µF
VDDCPU, VDDAPIC
Notes:
CY2280
37, 41, 46
Each supply pin must have an individual decoupling capac it or
All capacitors must be placed as close to the pins as is possible.
VDDUSB, V DDREF
Orde ring Information
Ordering Code Package Name Packag e Type Operating Range
CY2280PVC-1 O48 48-Pin SSOP Commercial
CY2280PVC-11S O48 48-Pin SSOP Commercial
CY2280PVC-12S O48 48-Pin SSOP Commercial
CY2280PVC-13S O48 48-Pin SSOP Commercial
CY2280PVC-14S O48 48-Pin SSOP Commercial
CY2280PVC-21S O48 48-Pin SSOP Commercial
CY2280PVC-31S O48 48-Pin SSOP Commercial
CY2280
© Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circui try other than circuitry embodied in a Cypress Semicon ductor pr oduct. Nor does it conv ey or imply any l icense under patent or oth er rights. C ypress Semi conductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Diagram
48-Lead Shrunk Small Outline Package O48
51-85061-B
