ADC161S626CIMMX/NOPB - National Semiconductor

ADC161S626

May 14, 2009

16-Bit, 50 to 250 kSPS, Differential Input, MicroPower ADC

General Description

The ADC161S626 is a 16-bit successive-approximation reg-

ister (SAR) Analog-to-Digital converter (ADC) with a maxi-

mum sampling rate of 250 kSPS. The ADC161S626 has a

minimum signal span accuracy of ± 0.003% over the temper-

ate range of −40°C to +85°C. The converter features a differ-

ential analog input with an excellent common-mode signal

rejection ratio of 85 dB, making the ADC161S626 suitable for

noisy environments.

The ADC161S626 operates with a single analog supply (VA)

and a separate digital input/output (VIO) supply. VA can range

from +4.5V to +5.5V and VIO can range from +2.7V to +5.5V.

This allows a system designer to maximize performance and

minimize power consumption by operating the analog portion

of the ADC at a VA of +5V while interfacing with a +3.3V con-

troller. The serial data output is binary 2's complement and is

SPI™ compatible.

The performance of the ADC161S626 is guaranteed over

temperature at clock rates of 1 MHz to 5 MHz and reference

voltages of +2.5V to +5.5V. The ADC161S626 is available in

a small 10-lead MSOP package. The high accuracy, differ-

ential input, low power consumption, and small size make the

ADC161S626 ideal for direct connection to bridge sensors

and transducers in battery operated systems or remote data

acquisition applications.

Applications

■Direct Sensor Interface

■I/O Modules

■Data Acquisition

■Portable Systems

■Motor Control

■Medical Instruments

■Instrumentation and Control Systems

Features

■16-bit resolution with no missing codes

■Guaranteed performance from 50 to 250 kSPS

■±0.003% signal span accuracy

■Separate Digital Input/Output Supply

■True differential input

■External voltage reference range of +0.5V to VA

■Zero-Power Track Mode with 0 µsec wake-up delay

■Wide input common-mode voltage range of 0V to VA

■SPI™/QSPI™/MICROWIRE™ compatible Serial

Interface

■Operating temperature range of −40°C to +85°C

■Small MSOP-10 package

Key Specifications

■Conversion Rate 50 kSPS to 250 kSPS

■DNL + 0.8 / − 0.5 LSB

■INL ± 0.8 LSB

■Offset Error Temp Drift 2.5 µV/°C

■Gain Error Temp Drift 0.3 ppm/°C

■SNR 93.2 dBc

■THD − 104 dBc

■Power Consumption

■— 10 kSPS, 5V 0.24 mW

— 200 kSPS, 5V 5.3 mW

— 250 kSPS, 5V 5.8 mW

— Power-Down, 5V 10 µW

Typical Application

30073482

TRI-STATE® is a trademark of National Semiconductor Corporation.

MICROWIRE™ is a trademark of National Semiconductor Corporation.

QSPI™ and SPI™ are trademarks of Motorola, Inc.

ADC161S626 16-Bit, 50 to 250 kSPS, Differential Input, MicroPower ADC

Ordering Information

Order Code Temperature Range Description Top Mark

ADC161S626CIMM −40°C to +85°C 10-Lead MSOP Package, 1000 Units Tape & Reel X98C

ADC161S626CIMMX −40°C to +85°C 10-Lead MSOP Package, 3500 Units Tape & Reel X98C

ADC161S626CIMME −40°C to +85°C 10-Lead MSOP Package, 250 Units Tape & Reel X98C

ADC161S626EB Evaluation Board

Block Diagram

30073402

Connection Diagram

30073405

Pin Descriptions

Pin No. Symbol Description

1VREF

Voltage Reference

+0.5V < VREF < VA

2 +IN Non-Inverting Input

3 −IN Inverting Input

4 GND Ground

5 GND Ground

6 CS Chip Select Bar

7DOUT Serial Data Output

8 SCLK Serial Clock

9VIO

Digital Input/Output Power

+2.7V < VREF < +5.5V

10 VA

Analog Power

+4.5V < VREF < +5.5V

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ADC161S626

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Analog Supply Voltage VA−0.3V to 6.5V

Digital I/O Supply Voltage VIO −0.3V to 6.5V

Voltage on Any Analog Input Pin to

GND −0.3V to (VA + 0.3V)

Voltage on Any Digital Input Pin to

GND −0.3V to (VIO + 0.3V)

Input Current at Any Pin (Note 3) ±10 mA

Package Input Current (Note 3) ±50 mA

Power Consumption at TA = 25°C See (Note 4)

ESD Susceptibility (Note 5)

Human Body Model

Machine Model

Charge Device Model

2500V

250V

1250V

Junction Temperature +150°C

Storage Temperature −65°C to +150°C

Operating Ratings (Notes 1, 2)

Operating Temperature Range −40°C ≤ TA ≤ +85°C

Supply Voltage, VA+4.5V to +5.5V

Supply Voltage, VIO +2.7V to +5.5V

Reference Voltage, VREF +0.5V to VA

Analog Input Pins Voltage Range 0V to VA

Differential Analog Input Voltage −VREF to +VREF

Input Common-Mode Voltage, VCM See Figure 10 (Sect 2.3)

Digital Input Pins Voltage Range 0V to VIO

Clock Frequency 1 MHz to 5 MHz

Package Thermal Resistance

Package θJA

10-lead MSOP 240°C / W

Soldering process must comply with National

Semiconductor's Reflow Temperature Profile specifications.

Refer to www.national.com/packaging. (Note 6)

ADC161S626 Converter Electrical Characteristics (Note 7)

The following specifications apply for VA = 4.5V to 5.5V, VIO = 2.7V to 5.5V, and VREF = 2.5V to 5.5V for fSCLK = 1 MHz to 4 MHz

or VREF = 4.5V to 5.5V for fSCLK = 1 MHz to 5 MHz; fIN = 20 kHz, and CL = 25 pF, unless otherwise noted. Maximum and minimum

values apply for TA = TMIN to TMAX; the typical values are tested at TA = 25°C.

Symbol Parameter Conditions Min Typ Max Units

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes 16 Bits

DNL Differential Non-Linearity −1 -0.5/+0.8 +2 LSB

INL Integral Non-Linearity −2 ±0.8 +2 LSB

OE Offset Error VREF = 2.5V −1 −0.1 +1 mV

VREF = 5V −0.4 mV

OEDRIFT Offset Error Temperature Drift VREF = 2.5V 3.7 µV/°C

VREF = 5V 2.5 µV/°C

FSE Positive Full-Scale Error −0.003 ±0.03 %FS

Negative Full-Scale Error −0.002 ±0.03 %FS

GE Positive Gain Error −0.002 ±0.02 %FS

Negative Gain Error −0.0001 ±0.02 %FS

GEDRIFT Gain Error Temperature Drift 0.3 ppm/°

DYNAMIC CONVERTER CHARACTERISTICS

SINAD Signal-to-Noise Plus Distortion Ratio VREF = 2.5V 85 88 dBc

VREF = 4.5V to 5.5V 89 93.0 dBc

SNR Signal-to-Noise Ratio VREF = 2.5V 85 88 dBc

VREF = 4.5V to 5.5V 89 93.2 dBc

THD Total Harmonic Distortion VREF = 2.5V −104 dBc

VREF = 4.5V to 5.5V −106 dBc

SFDR Spurious-Free Dynamic Range VREF = 2.5V 108 dBc

VREF = 4.5V to 5.5V 111 dBc

ENOB Effective Number of Bits VREF = 2.5V 13.8 14.3 bits

VREF = 4.5V to 5.5V 14.5 15.2 bits

FPBW −3 dB Full Power Bandwidth Output at 70.7%FS with FS

Differential Input 26 MHz

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ADC161S626

Symbol Parameter Conditions Min Typ Max Units

ANALOG INPUT CHARACTERISTICS

VIN Differential Input Range −VREF +VREF V

IINA Analog Input Current

CS high ±1 µA

VREF = 5V, VIN = 0V, fS = 50 kSPS 3.2 nA

VREF = 5V, VIN = 0V, fS = 200 kSPS 10.3 nA

CINA Input Capacitance (+IN or −IN) In Acquisition Mode 20 pF

In Conversion Mode 4 pF

CMRR Common Mode Rejection Ratio See the Specification Definitions for

the test condition 85 dB

DIGITAL INPUT CHARACTERISTICS

VIH Input High Voltage fIN = 0 Hz 0.7 x VIO 1.9 V

VIL Input Low Voltage fIN = 0 Hz 1.7 0.3 x VIO V

IIND Digital Input Current ±1 µA

CIND Input Capacitance 4 pF

DIGITAL OUTPUT CHARACTERISTICS

VOH Output High Voltage ISOURCE = 200 µA VIO − 0.2 VIO − 0.03 V

ISOURCE = 1 mA VIO − 0.09 V

VOL Output Low Voltage ISOURCE = 200 µA 0.01 0.4 V

ISOURCE = 1 mA 0.07 V

IOZH, IOZL TRI-STATE Leakage Current Force 0V or VA ±1 µA

COUT TRI-STATE Output Capacitance Force 0V or VA 4 pF

Output Coding Binary 2'S Complement

POWER SUPPLY CHARACTERISTICS

VAAnalog Supply Voltage Range 4.5 5 5.5 V

VIO

Digital Input/Output Supply Voltage

Range (Note 9) 2.7 3 5.5 V

VREF Reference Voltage Range 0.5 5 VAV

IVA (Conv) Analog Supply Current, Conversion

Mode

VA = 5V, fSCLK = 4 MHz,

fS = 200 kSPS 1060 µA

VA = 5V, fSCLK = 5 MHz,

fS = 250 kSPS 1160 1340 µA

IVIO

(Conv)

Digital I/O Supply Current, Conversion

Mode

VIO = 3V, fSCLK = 4 MHz,

fS = 200 kSPS 80 µA

VIO = 3V, fSCLK = 5 MHz,

fS = 250 kSPS 100 µA

IVREF

(Conv) Reference Current, Conversion Mode

VA = 5V, fSCLK = 4 MHz,

fS = 200 kSPS 80 µA

VA = 5V, fSCLK = 5 MHz,

fS = 250 kSPS 100 170 µA

IVA (PD) Analog Supply Current, Power Down

Mode (CS high)

fSCLK = 5 MHz, VA = 5V 7 µA

fSCLK = 0 Hz, VA = 5V (Note 8) 2 3 µA

IVIO (PD) Digital I/O Supply Current, Power Down

Mode (CS high)

fSCLK = 5 MHz, VIO = 3V 1 µA

fSCLK = 0 Hz, VIO = 3V (Note 8) 0.3 0.5 µA

IVREF (PD) Reference Current, Power Down Mode

(CS high)

fSCLK = 5 MHz, VREF = 5V 0.5 µA

fSCLK = 0 Hz, VREF = 5V (Note 8) 0.5 0.7 µA

PWR

(Conv) Power Consumption, Conversion Mode

VA = 5V, fSCLK = 4 MHz, fS = 200

kSPS, and fIN = 20 kHz, 5.3 mW

VA = 5V, fSCLK = 5 MHz, fS = 250

kSPS, and fIN = 20 5.8 6.7 mW

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ADC161S626

Symbol Parameter Conditions Min Typ Max Units

PWR (PD) Power Consumption, Power Down

Mode (CS high)

fSCLK = 5 MHz, VA = 5.0V

(Note 8) 35 µW

fSCLK = 0 Hz, VA = 5.0V

(Note 8) 10 15 µW

PSRR Power Supply Rejection Ratio See the Specification Definitions for

the test condition −78 dB

AC ELECTRICAL CHARACTERISTICS

fSCLK Maximum Clock Frequency 1 5 MHz

fSMaximum Sample Rate (Note 10) 50 250 kSPS

tACQ Acquisition/Track Time 600 ns

tCONV Conversion/Hold Time 17 SCLK

cycles

tAD Aperture Delay See the Specification Definitions 6 ns

ADC161S626 Timing Specifications (Note 7)

The following specifications apply for VA = 4.5V to 5.5V, VIO = 2.7V to 5.5V, VREF = 2.5V to 5.5V, fSCLK = 1Mz to 5MHz, and CL =

25 pF, unless otherwise noted. Maximum and minimum values apply for TA = TMIN to TMAX; the typical values are tested at TA =

25°C.

Symbol Parameter Min Typ Max Units

tCSS CS Setup Time prior to an SCLK rising edge 8 3 ns

tCSH CS Hold Time after an SCLK rising edge 8 3

tDH DOUT Hold Time after an SCLK falling edge 6 11 ns

tDA DOUT Access Time after an SCLK falling edge 18 41 ns

tDIS DOUT Disable Time after the rising edge of CS (Note 11) 20 30 ns

tCS Minimum CS Pulse Width 20 ns

tEN DOUT Enable Time after the 2nd falling edge of SCLK 20 70 ns

tCH SCLK High Time 20 ns

tCL SCLK Low Time 20 ns

trDOUT Rise Time 7 ns

tfDOUT Fall Time 7 ns

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed

specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test

conditions. Operation of the device beyond the maximum Operating Ratings is not recommended.

Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.

Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < GND or VIN > VA), the current at that pin should be limited to 10 mA. The 50

mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to five.

Note 4: The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the

junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA)/θJA. The values

for maximum power dissipation listed above will be reached only when the ADC161S626 is operated in a severe fault condition (e.g. when input or output pins

are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided.

Note 5: Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is a 220 pF capacitor discharged through 0 Ω. Charge

device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged.

Note 6: Reflow temperature profiles are different for lead-free packages.

Note 7: Typical values are at TJ = 25°C and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality

Level).

Note 8: This parameter is guaranteed by design and/or characterization and is not tested in production.

Note 9: The value of VIO is independent of the value of VA. For example, VIO could be operating at 5.5V while VA is operating at 4.5V or VIO could be operating

at 2.7V while VA is operating at 5.5V.

Note 10: While the maximum sample rate is fSCLK / 20, the actual sample rate may be lower than this by having the CS rate slower than fSCLK / 20.

Note 11: tDIS is the time for DOUT to change 10% while being loaded by the Timing Test Circuit.

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ADC161S626

Timing Diagrams

30073401

FIGURE 1. ADC161S626 Single Conversion Timing Diagram

30073408

FIGURE 2. Timing Test Circuit

30073406

FIGURE 3. DOUT Rise and Fall Times

30073411

FIGURE 4. DOUT Hold and Access Times

30073410

FIGURE 5. Valid CS Assertion Times

30073412

FIGURE 6. Voltage Waveform for tDIS

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ADC161S626

Specification Definitions

APERTURE DELAY is the time between the first falling edge

of SCLK and the time when the input signal is sampled for

conversion.

COMMON MODE REJECTION RATIO (CMRR) is a measure

of how well in-phase signals common to both input pins are

rejected.

To calculate CMRR, the change in output offset is measured

while the common mode input voltage is changed from 2V to

3V.

CMRR = 20 LOG ( Δ Common Input / Δ Output Offset)

CONVERSION TIME is the time required, after the input volt-

age is acquired, for the ADC to convert the input voltage to a

digital word.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of

the maximum deviation from the ideal step size of 1 LSB.

DUTY CYCLE is the ratio of the time that a repetitive digital

waveform is high to the total time of one period. The specifi-

cation here refers to the SCLK.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE

BITS) is another method of specifying Signal-to-Noise and

Distortion or SINAD. ENOB is defined as (SINAD − 1.76) /

6.02 and says that the converter is equivalent to a perfect

ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequency

at which the reconstructed output fundamental drops 3 dB

below its low frequency value for a full scale input.

GAIN ERROR is the deviation from the ideal slope of the

transfer function. It is the difference between Positive Full-

Scale Error and Negative Full-Scale Error and can be calcu-

lated as:

Gain Error = Positive Full-Scale Error − Negative Full-Scale

Error

INTEGRAL NON-LINEARITY (INL) is a measure of the de-

viation of each individual code from a line drawn from ½ LSB

below the first code transition through ½ LSB above the last

code transition. The deviation of any given code from this

straight line is measured from the center of that code value.

MISSING CODES are those output codes that will never ap-

pear at the ADC outputs. The ADC161S626 is guaranteed not

to have any missing codes.

NEGATIVE FULL-SCALE ERROR is the difference between

the differential input voltage at which the output code transi-

tions from code 0x8001h to 0x8000h and −VREF + 1 LSB.

NEGATIVE GAIN ERROR is the difference between the neg-

ative full-scale error and the offset error.

OFFSET ERROR is the difference between the differential

input voltage at which the output code transitions from code

0x0000h to 0x0001h and 1 LSB.

POSITIVE FULL-SCALE ERROR is the difference between

the differential input voltage at which the output code transi-

tions from code 0xFFFEh to 0xFFFFh and VREF - 1 LSB.

POSITIVE GAIN ERROR is the difference between the pos-

itive full-scale error and the offset error.

POWER SUPPLY REJECTION RATIO (PSRR) is a measure

of how well a change in the analog supply voltage is rejected.

PSRR is calculated from the ratio of the change in offset error

for a given change in supply voltage, expressed in dB. For the

ADC161S626, VA is changed from 4.5V to 5.5V.

PSRR = 20 LOG (ΔOutput Offset / ΔVA)

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in

dB, of the rms value of the input signal to the rms value of the

sum of all other spectral components below one-half the sam-

pling frequency, not including harmonics or d.c.

SIGNAL TO NOISE PLUS DISTORTION (S/N+D or

SINAD) Is the ratio, expressed in dB, of the rms value of the

input signal to the rms value of all of the other spectral com-

ponents below one-half the sampling frequency, including

harmonics but excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-

ence, expressed in dB, between the desired signal amplitude

to the amplitude of the peak spurious spectral component be-

low one-half the sampling frequency, where a spurious spec-

tral component is any signal present in the output spectrum

that is not present at the input and may or may not be a har-

monic.

TOTAL HARMONIC DISTORTION (THD) is the ratio of the

rms total of the first five harmonic components at the output

to the rms level of the input signal frequency as seen at the

output, expressed in dB. THD is calculated as

where Af1 is the RMS power of the input frequency at the out-

put and Af2 through Af6 are the RMS power in the first 5

harmonic frequencies.

THROUGHPUT TIME is the minimum time required between

the start of two successive conversion.

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ADC161S626

Typical Performance Characteristics VA = VIO = VREF = +5V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA =

+25°C, and fIN = 20 kHz unless otherwise stated.

DNL - 250 kSPS

30073421

INL - 250 kSPS

30073422

DNL vs. VA

30073423

INL vs. VA

30073424

DNL vs. VREF

30073418

INL vs. VREF

30073419

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ADC161S626

Typical Performance Characteristics VA = VIO = VREF = +5V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA =

+25°C, and fIN = 20 kHz unless otherwise stated.

DNL vs. SCLK FREQUENCY

30073425

INL vs. SCLK FREQUENCY

30073426

DNL vs. TEMPERATURE

30073429

INL vs. TEMPERATURE

30073430

SINAD vs. VA

30073433

THD vs. VA

30073432

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ADC161S626

Typical Performance Characteristics VA = VIO = VREF = +5V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA =

+25°C, and fIN = 20 kHz unless otherwise stated.

SINAD vs. VREF

30073437

THD vs. VREF

30073436

SINAD vs. SCLK FREQUENCY

30073441

THD vs. SCLK FREQUENCY

30073440

SINAD vs. INPUT FREQUENCY

30073449

THD vs. INPUT FREQUENCY

30073448

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ADC161S626

Typical Performance Characteristics VA = VIO = VREF = +5V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA =

+25°C, and fIN = 20 kHz unless otherwise stated.

SINAD vs. TEMPERATURE

30073472

THD vs. TEMPERATURE

30073471

VA CURRENT vs. VA

30073435

VA CURRENT vs. SCLK FREQUENCY

30073455

VA CURRENT vs. TEMPERATURE

30073454

VREF CURRENT vs. VREF

30073434

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ADC161S626

Typical Performance Characteristics VA = VIO = VREF = +5V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA =

+25°C, and fIN = 20 kHz unless otherwise stated.

VREF CURRENT vs. SCLK FREQUENCY

30073452

VREF CURRENT vs. TEMPERATURE

30073451

VIO CURRENT vs. VIO

30073444

VIO CURRENT vs. SCLK FREQUENCY

30073442

VIO CURRENT vs. TEMPERATURE

30073443

SPECTRAL RESPONSE - 250 kSPS

30073414

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ADC161S626

Functional Description

The ADC161S626 is a 16-bit, 50 kSPS to 250 kSPS sampling

Analog-to-Digital (A/D) converter. The converter uses a suc-

cessive approximation register (SAR) architecture based up-

on capacitive redistribution containing an inherent sample-

and-hold function. The differential nature of the analog inputs

is maintained from the internal sample-and-hold circuits

throughout the A/D converter to provide excellent common-

mode signal rejection.

The ADC161S626 operates from independent analog and

digital supplies. The analog supply (VA) can range from 4.5V

to 5.5V and the digital input/output supply (VIO) can range

from 2.7V to 5.5V. The ADC161S626 utilizes an external ref-

erence (VREF), which can be any voltage between 0.5V and

VA. The value of VREF determines the range of the analog in-

put, while the reference input current (IREF) depends upon the

conversion rate.

The analog input is presented to two input pins: +IN and –IN.

Upon initiation of a conversion, the differential input at these

pins is sampled on the internal capacitor array. The inputs are

disconnected from the internal circuitry while a conversion is

in progress. The ADC161S626 features a zero-power track

mode (ZPTM) where the ADC is consuming the minimum

amount of power (Power-Down Mode) while the internal sam-

pling capacitor array is tracking the applied analog input

voltage. The converter enters ZPTM at the end of each con-

version window and experiences no delay when the ADC

enters into Conversion Mode. This feature allows the user an

easy means for optimizing system performance based on the

settling capability of the analog source while minimizing pow-

er consumption. ZPTM is exercised by bringing chip select

bar (CS) high or when CS is held low after the conversion is

complete (after the 18th falling edge of the serial clock).

The ADC161S626 communicates with other devices via a

Serial Peripheral Interface (SPI™), a synchronous serial in-

terface that operates using three pins: chip select bar (CS),

serial clock (SCLK), and serial data out (DOUT). The external

SCLK controls data transfer and serves as the conversion

clock. The duty cycle of SCLK is essentially unimportant, pro-

vided the minimum clock high and low times are met. The

minimum SCLK frequency is set by internal capacitor leak-

age. Each conversion requires a minimum of 18 SCLK cycles

to complete. If less than 16 bits of conversion data are re-

quired, CS can be brought high at any point during the con-

version. This procedure of terminating a conversion prior to

completion is commonly referred to as short cycling.

The digital conversion result is clocked out by the SCLK input

and is provided serially, most significant bit (MSB) first, at the

DOUT pin. The digital data that is provided at the DOUT pin is

that of the conversion currently in progress and thus there is

no pipe line delay or latency.

1.0 REFERENCE INPUT (VREF)

The externally supplied reference voltage (VREF) sets the

analog input range. The ADC161S626 will operate with

VREF in the range of 0.5V to VA.

Operation with VREF below 2.5V is possible with slightly di-

minished performance. As VREF is reduced, the range of

acceptable analog input voltages is reduced. Assuming a

proper common-mode input voltage (VCM), the differential

peak-to-peak input range is limited to (2 x VREF). See Section

2.3 for more details.

Reducing VREF also reduces the size of the least significant

bit (LSB). For example, the size of one LSB is equal to [(2 x

VREF) / 2n], which is 152.6 µV where n is 16 bits and VREF is

5V. When the LSB size goes below the noise floor of the

ADC161S626, the noise will span an increasing number of

codes and overall performance will suffer. Dynamic signals

will have their SNR degrade; while, D.C. measurements will

have their code uncertainty increase. Since the noise is Gaus-

sian in nature, the effects of this noise can be reduced by

averaging the results of a number of consecutive conver-

sions.

VREF and analog inputs (+IN and -IN) are connected to the

capacitor array through a switch matrix when the input is

sampled. Hence, IREF, I+IN, and I-IN are a series of transient

spikes that occur at a frequency dependent on the operating

sample rate of the ADC161S626.

IREF changes only slightly with temperature. See the curves,

“Reference Current vs. SCLK Frequency” and “Reference

Current vs. Temperature” in the Typical Performance Curves

section for additional details.

2.0 ANALOG SIGNAL INPUTS

The ADC161S626 has a differential input where the effective

input voltage that is digitized is (+IN) − (−IN).

2.1 Differential Input Operation

The transfer curve of the ADC161S626 for a fully differential

input signal is shown in Figure 7. A positive full scale output

code (0111 1111 1111 1111b or 7FFFh or 32,767d) will be

obtained when (+IN) − (−IN) is greater than or equal to

(VREF − 1 LSB). A negative full scale code (1000 0000 0000

0000b or 8000h or -32,768d) will be obtained when [(+IN) −

(−IN)] is less than or equal to (−VREF + 1 LSB). This ignores

gain, offset and linearity errors, which will affect the exact dif-

ferential input voltage that will determine any given output

code.

30073499

FIGURE 7. ADC Transfer Curve

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ADC161S626

Both inputs should be biased at a common mode voltage

(VCM), which will be thoroughly discussed in Section 2.3. Fig-

ure 8 shows the ADC161S626 being driven by a full-scale

differential source.

30073480

FIGURE 8. Differential Input

2.2 Single-Ended Input Operation

For single-ended operation, the non-inverting input (+IN) of

the ADC161S626 can be driven with a signal that has a peak-

to-peak range that is equal to or less than (2 x VREF). The

inverting input (−IN) should be biased at a stable VCM that is

halfway between these maximum and minimum values. In

order to utilize the entire dynamic range of the

ADC161S626, VREF is limited to (VA / 2). This allows +IN a

maximum swing range of ground to VA. Figure 9 shows the

ADC161S626 being driven by a full-scale single-ended

source.

30073481

FIGURE 9. Single-Ended Input

Since the design of the ADC161S626 is optimized for a dif-

ferential input, the performance degrades slightly when driven

with a single-ended input. Linearity characteristics such as

INL and DNL typically degrade by 0.1 LSB and dynamic char-

acteristics such as SINAD typically degrade by 2 dB. Note that

single-ended operation should only be used if the perfor-

mance degradation (compared with differential operation) is

acceptable.

2.3 Input Common Mode Voltage

The allowable input common mode voltage (VCM) range de-

pends upon VA and VREF used for the ADC161S626. The

ranges of VCM are depicted in Figure 10 and Figure 11. Note

that these figures only apply to a VA of 5V. Equations for cal-

culating the minimum and maximum VCM for differential and

single-ended operations are shown in Table 1.

30073461

FIGURE 10. VCM range for Differential Input operation

30073462

FIGURE 11. VCM range for single-ended operation

TABLE 1. Allowable VCM Range

Input Signal Minimum VCM Maximum VCM

Differential VREF / 2 VA − VREF / 2

Single-Ended VREF VA − VREF

2.4 CMRR

By using this differential input, small signals common to both

inputs are rejected. As shown in Figure 12, noise is immune

at low frequencies where the common-mode rejection ratio

(CMRR) is 90 dB. As the frequency increases to 1 MHz, the

CMRR rolls off to 40 dB . In general, operation with a fully

differential input signal or voltage will provide better perfor-

mance than with a single-ended input. However, if desired,

the ADC161S626 can be presented with a single-ended input.

www.national.com 14

ADC161S626

30073475

FIGURE 12. Analog Input CMRR vs. Frequency

2.5 Noise

The noise floor of the ADC161S626 is very low as shown in

Figure 13 and Figure 14. These figures were created by driv-

ing the ADC input with a low-noise voltage source set near

0V. For Figure 13, the input was adjusted in order to obtain

the code 0x0000h. For Figure 14, the input was increased by

1/2 LSB in order to obtain the transition point between code

0x0000h and 0x0001h. In both instances, 216 (65,534) sam-

ples were collected and plotted in a histogram format.

Ideally the noise histogram at code center would show a sin-

gle output code while the noise histogram at code transition

would show two output codes. Any codes outside of the ideal

output are a result of the internal noise of the ADC161S626

and the input source. Since the ADC161S626 has very low

internal noise, only two codes outside of the center code are

exhibited in the histogram of Figure 13. Similar results are

shown in Figure 14.

30073483

FIGURE 13. Noise Histogram at Code Center

30073484

FIGURE 14. Noise Histogram at Code Transition

2.6 Input Settling

When the ADC161S626 enters acquisition (tACQ) mode at the

end of the conversion window, the internal sampling capacitor

(CSAMPLE) is connected to the ADC input via an internal switch

and a series resistor (RSAMPLE), as shown in Figure 15. Typ-

ical values for CSAMPLE and RSAMPLE are 20 pF and 200 ohms

respectively. If there is not a large external capacitor (CEXT)

at the analog input of the ADC, a voltage spike will be ob-

served at the input pins. This is a result of CSAMPLE and

CEXT being at different voltage potentials. The magnitude and

direction of the voltage spike depend on the difference be-

tween the voltage of CSAMPLE and CEXT. If the voltage at

CSAMPLE is greater than the voltage at CEXT, a positive voltage

spike will occur. If the opposite is true, a negative voltage

spike will occur. It is not critical for the performance of the

ADC161S626 to filter out the voltage spike. Rather, ensure

that the transient of the spike settles out within tACQ; for rec-

ommended solutions, see Section 4.0 in the Application In-

formation.

30073485

FIGURE 15. ADC Input Capacitors

15 www.national.com

ADC161S626

3.0 SERIAL DIGITAL INTERFACE

The ADC161S626 communicates via a synchronous 3-wire

serial interface as shown in Figure 1 or re-shown in Figure

16 for convenience. CS, chip select bar, initiates conversions

and frames the serial data transfers. SCLK (serial clock) con-

trols both the conversion process and the timing of the serial

data. DOUT is the serial data output pin, where a conversion

result is sent as a serial data stream, MSB first.

A serial frame is initiated on the falling edge of CS and ends

on the rising edge of CS. The ADC161S626's DOUT pin is in

a high impedance state when CS is high and for the first clock

period after CS is asserted; DOUT is active for the remainder

of time when CS is asserted.

The ADC161S626 samples the differential input upon the as-

sertion of CS. Assertion is defined as bringing the CS pin to

a logic low state. For the first 17 periods of the SCLK following

the assertion of CS, the ADC161S626 is converting the ana-

log input voltage. On the 18th falling edge of SCLK, the

ADC161S626 enters acquisition (tACQ) mode. For the next

three periods of SCLK, the ADC161S626 is operating in ac-

quisition mode where the ADC input is tracking the analog

input signal applied across +IN and -IN. During acquisition

mode, the ADC161S626 is consuming a minimal amount of

power.

The ADC161S626 can enter conversion mode (tCONV) under

three different conditions. The first condition involves CS go-

ing low (asserted) with SCLK high. In this case, the

ADC161S626 enters conversion mode on the first falling edge

of SCLK after CS is asserted. In the second condition, CS

goes low with SCLK low. Under this condition, the

ADC161S626 automatically enters conversion mode and the

falling edge of CS is seen as the first falling edge of SCLK. In

the third condition, CS and SCLK go low simultaneously and

the ADC161S626 enters conversion mode. While there is no

timing restriction with respect to the falling edges of CS and

SCLK, there are minimum setup and hold time requirements

for the falling edge of CS with respect to the rising edge of

SCLK. See Figure 5 in the Timing Diagram section for more

information.

3.1 CS Input

The CS (chip select bar) input is active low and is CMOS

compatible. The ADC161S626 enters conversion mode when

CS is asserted and the SCLK pin is in a logic low state. When

CS is high, the ADC161S626 is always in acquisition mode

and thus consuming the minimum amount of power. Since

CS must be asserted to begin a conversion, the sample rate

of the ADC161S626 is equal to the assertion rate of CS.

Proper operation requires that the fall of CS not occur simul-

taneously with a rising edge of SCLK. If the fall of CS occurs

during the rising edge of SCLK, the data might be clocked out

one bit early. Whether or not the data is clocked out early

depends upon how close the CS transition is to the SCLK

transition, the device temperature, and the characteristics of

the individual device. To ensure that the MSB is always

clocked out at a given time (the 3rd falling edge of SCLK), it is

essential that the fall of CS always meet the timing require-

ment specified in the Timing Specification table.

3.2 SCLK Input

The SCLK (serial clock) is used as the conversion clock to

shift out the conversion result. SCLK is CMOS compatible.

Internal settling time requirements limit the maximum clock

frequency while internal capacitor leakage limits the minimum

clock frequency. The ADC161S626 offers guaranteed perfor-

mance with the clock rates indicated in the electrical table.

The ADC161S626 enters acquisition mode on the 18th falling

edge of SCLK during a conversion frame. Assuming that the

LSB is clocked into a controller on the 18th rising edge of

SCLK, there is a minimum acquisition time period that must

be met before a new conversion frame can begin. Other than

the 18th rising edge of SCLK that was used to latch the LSB

into a controller, there is no requirement for the SCLK to tran-

sition during acquisition mode. Therefore, it is acceptable to

idle SCLK after the LSB has been latched into the controller.

3.3 Data Output

The data output format of the ADC161S626 is two’s comple-

ment as shown in Figure 7. This figure indicates the ideal

output code for a given input voltage and does not include the

effects of offset, gain error, linearity errors, or noise. Each

data output bit is output on the falling edges of SCLK. DOUT

is in a high impedance state for the 1st falling edge of SCLK

while the 2nd SCLK falling edge clocks out a leading zero. The

3rd to 18th SCLK falling edges clock out the conversion result,

MSB first.

While most receiving systems will capture the digital output

bits on the rising edges of SCLK, the falling edges of SCLK

may be used to capture the conversion result if the minimum

hold time for DOUT is acceptable. See Figure 4 for DOUT hold

(tDH) and access (tDA) times.

DOUT is enabled on the second falling edge of SCLK after the

assertion of CS and is disabled on the rising edge of CS. If

CS is raised prior to the 18th falling edge of SCLK, the current

conversion is aborted and DOUT will go into its high impedance

state. A new conversion will begin when CS is driven LOW.

30073401

FIGURE 16. ADC161S626 Single Conversion Timing Diagram

www.national.com 16

ADC161S626

Applications Information

OPERATING CONDITIONS

We recommend that the following conditions be observed for

operation of the ADC161S626:

−40°C ≤ TA ≤ +85°C

+4.5V ≤ VA ≤ +5.5V

+2.7V ≤ VIO ≤ +5.5V

+0.5V ≤ VREF ≤ +5.5V

1 MHz ≤ fSCLK ≤ 5 MHz

VCM: See Section 2.3

4.0 ANALOG INPUT CONSIDERATIONS

As stated previously in Section 2.6, it is not critical for the

performance of the ADC161S626 to filter out the voltage spike

that occurs when the ADC161S626 enters acquisition (tACQ)

mode at the end of the conversion window. However, it is crit-

ical that a system designer ensures that the transients of the

spike settle out within tACQ. The burden of this task can be

placed on the analog source itself or the burden can be shared

by the source and an external capacitor, CEXT as shown in

Figure 15. The external capacitor acts as a local charge reser-

voir for the internal sampling capacitor and thus reduces the

size of the voltage spike. For low frequency analog sources

such as sensors with DC-like output behaviors, CEXT values

greater than 1 nF are recommended. However, some sensors

and signal conditioning circuitry will not be able to maintain

their stability in the presence of the external capacitive load.

In these instances, a series resistor (REXT) is recommended.

The magnitude of REXT is dependent on the output capability

of the analog source and the settling requirement of the ADC.

Independent of the presence of an external capacitor, the

system designer always has the option of lowering the sample

rate of the ADC161S626 which directly controls the amount

of time allowed for the voltage spike to settle. The slower the

sample rate, the longer the tACQ time or settling time. This is

possible with the ADC161S626 since the converter enters

tACQ at the end of the prior conversion and thus is tracking the

analog input source the entire time between conversions.

5.0 POWER CONSUMPTION

The architecture, design, and fabrication process allow the

ADC161S626 to operate at conversion rates up to 250 kSPS

while consuming very little power. The ADC161S626 con-

sumes the least amount of power while operating in acquisi-

tion (power-down) mode. For applications where power

consumption is critical, the ADC161S626 should be operated

in acquisition mode as often as the application will tolerate.

To further reduce power consumption, stop the SCLK while

CS is high.

5.1 Short Cycling

Short cycling refers to the process of halting a conversion af-

ter the last needed bit is outputted. Short cycling can be used

to lower the power consumption in those applications that do

not need a full 16-bit resolution, or where an analog signal is

being monitored until some condition occurs. In some circum-

stances, the conversion could be terminated after the first few

bits. This will lower power consumption in the converter since

the ADC161S626 spends more time in acquisition mode and

less time in conversion mode.

Short cycling is accomplished by pulling CS high after the last

required bit is received from the ADC161S626 output. This is

possible because the ADC161S626 places the latest con-

verted data bit on DOUT as it is generated. If only 10-bits of the

conversion result are needed, for example, the conversion

can be terminated by pulling CS high after the 10th bit has

been clocked out.

5.2 Burst Mode Operation

Normal operation of the ADC161S626 requires the SCLK fre-

quency to be 20 times the sample rate and the CS rate to be

the same as the sample rate. However, in order to minimize

power consumption in applications requiring sample rates be-

low 250 kSPS, the ADC161S626 should be run with an SCLK

frequency of 5 MHz and a CS rate as slow as the system

requires. When this is accomplished, the ADC161S626 is op-

erating in burst mode. The ADC161S626 enters into acquisi-

tion mode at the end of each conversion, minimizing power

consumption. This causes the converter to spend the longest

possible time in acquisition mode. Since power consumption

scales directly with conversion rate, minimizing power con-

sumption requires determining the lowest conversion rate that

will satisfy the requirements of the system.

6.0 PCB LAYOUT AND CIRCUIT CONSIDERATIONS

For best performance, care should be taken with the physical

layout of the printed circuit board. This is especially true with

a low VREF or when the conversion rate is high. At high clock

rates there is less time for settling, so it is important that any

noise settles out before the conversion begins.

6.1 Analog and Digital Power Supplies

Any ADC architecture is sensitive to spikes on the power sup-

ply, reference, and ground pins. These spikes may originate

from switching power supplies, digital logic, high power de-

vices, and other sources. Power to the ADC161S626 should

be clean and well bypassed. A 0.1 µF ceramic bypass ca-

pacitor and a 1 µF to 10 µF capacitor should be used to

bypass the ADC161S626 supply, with the 0.1 µF capacitor

placed as close to the ADC161S626 package as possible.

Since the ADC161S626 has both the VA and VIO pins, the user

has three options on how to connect these pins. The first op-

tion is to tie VA and VIO together and power them with the same

power supply. This is the most cost effective way of powering

the ADC161S626 but is also the least ideal. As stated previ-

ously, noise from VIO can couple into VA and adversely affect

performance. The other two options involve the user powering

VA and VIO with separate supply voltages. These supply volt-

ages can have the same amplitude or they can be different.

VA can be set to any value between +4.5V and +5.5V; while

VIO can be set to any value between +2.7V and +5.5V.

Best performance will typically be achieved with VA operating

at 5V and VIO at 3V. Operating VA at 5V offers the best linearity

and dynamic performance when VREF is also set to 5V; while

operating VIO at 3V reduces the power consumption of the

digital logic. Operating the digital interface at 3V also has the

added benefit of decreasing the noise created by charging

and discharging the capacitance of the digital interface pins.

6.2 Voltage Reference

The reference source must have a low output impedance and

needs to be bypassed with a minimum capacitor value of 0.1

µF. A larger capacitor value of 1 µF to 10 µF placed in parallel

with the 0.1 µF is preferred. While the ADC161S626 draws

very little current from the reference on average, there are

higher instantaneous current spikes at the reference.

VREF of the ADC161S626, like all A/D converters, does not

reject noise or voltage variations. Keep this in mind if VREF is

derived from the power supply. Any noise and/or ripple from

the supply that is not rejected by the external reference cir-

cuitry will appear in the digital results. The use of an active

17 www.national.com

ADC161S626

reference source is recommended. The LM4040 and LM4050

shunt reference families and the LM4120 and LM4140 series

reference families are excellent choices for a reference

source.

6.3 PCB Layout

Capacitive coupling between the noisy digital circuitry and the

sensitive analog circuitry can lead to poor performance. The

solution is to keep the analog circuitry separated from the

digital circuitry and the clock line as short as possible. Digital

circuits create substantial supply and ground current tran-

sients. The logic noise generated could have significant im-

pact upon system noise performance. To avoid performance

degradation of the ADC161S626 due to supply noise, avoid

using the same supply for the VA and VREF of the

ADC161S626 that is used for digital circuitry on the board.

Generally, analog and digital lines should cross each other at

90° to avoid crosstalk. However, to maximize accuracy in high

resolution systems, avoid crossing analog and digital lines al-

together. It is important to keep clock lines as short as possi-

ble and isolated from ALL other lines, including other digital

lines. In addition, the clock line should also be treated as a

transmission line and be properly terminated. The analog in-

put should be isolated from noisy signal traces to avoid cou-

pling of spurious signals into the input. Any external

component (e.g., a filter capacitor) connected between the

converter's input pins and ground or to the reference input pin

and ground should be connected to a very clean point in the

ground plane.

A single, uniform ground plane and the use of split power

planes are recommended. The power planes should be lo-

cated within the same board layer. All analog circuitry (input

amplifiers, filters, reference components, etc.) should be

placed over the analog power plane. All digital circuitry should

be placed over the digital power plane. Furthermore, the GND

pins on the ADC161S626 and all the components in the ref-

erence circuitry and input signal chain that are connected to

ground should be connected to the ground plane at a quiet

point. Avoid connecting these points too close to the ground

point of a microprocessor, microcontroller, digital signal pro-

cessor, or other high power digital device.

7.0 APPLICATION CIRCUITS

The following figures are examples of the ADC161S626 in

typical application circuits. These circuits are basic and will

generally require modification for specific circumstances.

7.1 Data Acquisition

Figure 17 shows a typical connection diagram for the

ADC161S626 operating at VA of +5V. VREF is connected to a

2.5V shunt reference, the LM4020-2.5, to define the analog

input range of the ADC161S626 independent of supply vari-

ation on the +5V supply line. The VREF pin should be de-

coupled to the ground plane by a 0.1 µF ceramic capacitor

and a tantalum capacitor of 10 µF. It is important that the 0.1

µF capacitor be placed as close as possible to the VREF pin

while the placement of the tantalum capacitor is less critical.

It is also recommended that the VA and VIO pins of the

ADC161S626 be de-coupled to ground by a 0.1 µF ceramic

capacitor in parallel with a 10 µF tantalum capacitor.

30073463

FIGURE 17. Low cost, low power Data Acquisition System

7.2 Bridge Sensor Application

Figure 18 and Figure 19 show examples of interfacing bridge

sensors to the ADC161S626. The applications assume that

the bridge sensors require buffering and amplification to fully

utilize the dynamic range of the ADC and thus optimize the

performance of the entire signal path. The amplification

stages consist of the LMP7732 and the LMP7731, dual and

single precision amplifiers, and some gain setting passive

components. The amplification stages offer the benefit of high

input impedance and high amplification capability.

Figure 19, which has the amplification stage configured as an

instrumentation amplifier, has the added benefit of additional

common-mode rejection of common-mode noise or DC-volt-

ages coming from the bridge sensor. Depending on the volt-

age applied at VCM, the ADC161S626 in the single-ended

application will convert the output voltage of a bridge sensor

that contains both a positive and negative component or a

bridge sensor that only outputs a positive voltage. For the

case of a sensor with both positive and negative output ca-

pability, it is recommended that VCM be connected to VREF.

For a sensor that only outputs a positive voltage, VCM would

need to be connected to ground. Both of these scenarios will

allow all the ADC output codes to be potentially utilized.

A separate power supply (VBR) is assumed to be biasing the

bridge sensor but another option for biasing the bridge sensor

would be powering it from the +5V power supply. This option

has the benefit of providing the ideal common-mode input

www.national.com 18

ADC161S626

voltage for the ADC161S626, while keeping design complex-

ity and cost to a minimum. However, any fluctuation in the +5V

supply will still be visible on the differential input to the ampli-

fication stage. The LM4120-4.1, a 4.1V series reference, and

the LM4120-2.5, a 2.5V series reference, are used as the ref-

erence voltages in the respective application drawings. The

application in Figure 19 is limited to a VREF of 2.5V or less

because of the single-ended configuration of the differential

ADC161S626, as discussed in Section 2.2. The

ADC161S626 and the LM4120's are all powered from the

same +5V voltage source.

30073466

FIGURE 18. Differential Application for a Bridge Sensor

30073488

FIGURE 19. Single-Ended Application for a Bridge Sensor

7.3 Current Sensing Application

Figure 20 shows an example of interfacing a current trans-

ducer to the ADC161S626. The current transducer converts

an input current into a voltage that is converted by the ADC.

Since the output voltage of the current transducer is single-

ended and centered around a common-mode voltage (VCM)

of 2.5V, the ADC161S626 is configured with the output of the

transducer driving the non-inverting input and VCM of the

transducer driving the inverting input. The output of the trans-

ducer has an output range of ±2.5V around VCM of 2.5V. As

a result, a series reference voltage of 2.5V is connected to the

ADC161S626. This will allow all of the codes of the

ADC161S626 to be available for the application. This config-

uration of the ADC161S626 is referred to as a single-ended

application of a differential ADC. All of the elements in the

application are conveniently powered by the same +5V power

supply, keeping circuit complexity and cost to a minimum.

19 www.national.com

ADC161S626

30073438

FIGURE 20. Interfacing the ADC161S626 to a Current Transducer

www.national.com 20

ADC161S626

Physical Dimensions inches (millimeters) unless otherwise noted

10-Lead MSOP

Order Number ADC161S626CIMM

NS Package Number MUB10A

21 www.national.com

ADC161S626

Notes

ADC161S626 16-Bit, 50 to 250 kSPS, Differential Input, MicroPower ADC

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