IP5311CX5/LF - NXP Semiconductors

1. Product profile

1.1 General description

IP5311CX5 is a dual-channel RC low-pass filter array which is designed to provide

filtering of undesired RF signals in the 10 MHz to 6000 MHz frequency band. In addition,

IP5311CX5 incorporates diodes to provide protection to downstream components from

ElectroStatic Discharge (ESD) voltages as high as ±15 kV contact according the

IEC 61000-4-2 model, far exceeding standard level 4.

The device is optimized for loudspeaker applications using speakers of 10 Ω impedance

and above.

IP5311CX5 is fabricated using monolithic silicon technology and integrates several

resistors, bidirectional diodes and two high density capacitors in a single Wafer-Level

Chip-Scale Package (WLCSP). These features make the IP5311CX5 ideal for use in

applications requiring the utmost in miniaturization such as mobile phone handsets,

cordless telephones and personal digital devices.

1.2 Features and benefits

Pb-free, RoHS compliant and free of haloge n and antimony (Dark Green compliant)

Dual-channel integrated RC filter network with high density capacitors (2 ×5nF)

Integrated ESD protection withstanding ±15 kV contact discharge, far exceeding

IEC 61000-4-2 level 4

WLCSP with 0.4 mm pitch

1.3 Applications

Cellular and Personal Communi cation System (PCS) mobile handsets

Cordless telephones

Wireless data (WAN/LAN) systems

IP5311CX5

Dual-channel integrated passive filter network with ESD

protection to IEC 61000-4-2 level 4

Rev. 2 — 23 December 2010 Product data sheet

Product data sheet Rev. 2 — 23 December 2010 2 of 14

NXP Semiconductors IP5311CX5

Dual-channel integrated passive filter network

2. Pinning information

2.1 Pinning

2.2 Pin description

3. Ordering information

[1] Lead-free.

[2] Lead-free and sol pearls.

Fig 1. Pin configuration for WLCSP5

008aaa200

transparent top view,

solder balls facing down

bump A1

index area

Table 1. Pinning

Pin Description

A1 filter channel 1 internal 2 kV amplifier connection

A2 filter channel 1 external 15 kV speaker connection

C1 filter channel 2 internal 2 kV amplifier connection

C2 filter channel 2 external 15 kV speaker connection

B1 not connected (missing ball)

B2 ground

Table 2. Ordering information

Type number Package

Name Description Version

IP5311CX5/LF[1] WLCSP5 wafer level chip-size package; 5 bumps; 1.16 ×0.8 ×0.61 mm IP5311CX5/LF

IP5311CX5/LF/P[2] WLCSP5 wafer level chip-size package; 5 bumps; 1.16 ×0.8 ×0.61 mm IP5311CX5/LF/P

Product data sheet Rev. 2 — 23 December 2010 3 of 14

NXP Semiconductors IP5311CX5

Dual-channel integrated passive filter network

4. Functional diagram

5. Limiting values

[1] Device is qualified with 1000 pulses of ±15 kV contact discharges each, according to the IEC 61000-4-2

model and far exceeds the specified level 4 (8 kV contact discharge).

Fig 2. Schematic diagram IP5311CX5

008aaa20

15 Ω

C1 C2

15 Ω

5 nF

Table 3. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VIinput voltage −0.5 +4.5 V

VESD electrostatic discharge

voltage pins A2 and C2 to ground

contact discharge [1] −15 +15 kV

air discharge [1] −15 +15 kV

IEC 61000-4-2 level 4;

pins A2 and C2 to ground

contact discharge −8+8kV

air discharge −15 +15 kV

IEC 61000-4-2 level 1;

pins A1 and C1 to ground

contact discharge −2+2kV

air discharge −2+2kV

Ich channel current (DC) - 92 mA

Pch channel power dissipation continuous power - 100 mW

Ptot total power dissipation continuous power - 200 mW

Tstg storage temperature −55 +150 °C

Treflow(peak) peak reflow temperature 10 s maximum - 260 °C

Tamb ambient temperature −35 +85 °C

Product data sheet Rev. 2 — 23 December 2010 4 of 14

NXP Semiconductors IP5311CX5

Dual-channel integrated passive filter network

6. Characteristics

[1] Guaranteed by design.

Table 4. Channel characteristics

Tamb =25

C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Rs(ch) channel series resistance 13.5 15 16.5 Ω

C1capacitance 1 high density;

Vbias(DC) =0V;

f = 100 kHz

456nF

C2capacitance 2 4 5 6 nF

Cddiode capacitance Vbias(DC) =0V;

f = 100 kHz [1] -14-pF

VBR breakdown voltage positive direction;

Itest =1mA 14 16.5 - V

negative direction;

Itest =−1mA -−16.5 −14 V

ILR reverse leakage current per channel; VI=3.0V - - 60 nA

per channel; VI=−3.0 V −60 - - nA

Product data sheet Rev. 2 — 23 December 2010 5 of 14

NXP Semiconductors IP5311CX5

Dual-channel integrated passive filter network

7. Application information

7.1 Insertion loss

The insertion loss measur ement configuration of a typical 50 Ω NetWork Analyzer (NWA)

system for evaluation of the IP5311CX5 is shown in Figure 3.

The insertion loss of both channels at frequencies up to 6 GHz is displayed in Figure 4.

Fig 3. Frequency response measurement configuratio n

(1) Channel 1 (pins A1 and A2).

(2) Channel 2 (pin s C1 and C2).

Fig 4. Measured insertion loss magnitudes

OUT

001aai75

50 Ω50 Ω

Vgen

DUT

TEST BOARD

001aak630

−30

−20

−40

−10

s21

(dB)

−50

f (MHz)

10−1104

103

110

(1)

(2)

Product data sheet Rev. 2 — 23 December 2010 6 of 14

NXP Semiconductors IP5311CX5

Dual-channel integrated passive filter network

7.2 Crosstalk

The crosstalk measurement configuration of a typical 50 Ω NWA system for evaluation of

the IP5311CX5 is shown in Figure 5.

The measured crosstalk within the IP5311CX5 in a 50 Ω NWA system from one channel

to the other channel is shown in Figure 6. In all cases, unu sed connections are terminat ed

with 50 Ω to ground.

Fig 5. Crosstalk measurement configuration

(1) Channel 1 to channel 2 (pins A1 and C2).

(2) Channel 2 to channel 1 (pins A2 and C1).

Fig 6. Measured crosstalk between adjacen t chan nels

OUT_2

001aai75

50 Ω50 Ω

Vgen

DUT

IN_1

OUT_1IN_2

TEST BOARD

50 Ω50 Ω

001aak631

−60

−40

−80

−20

αct

(dB)

−100

f (MHz)

10−1104

103

110

(2)

(1)

Product data sheet Rev. 2 — 23 December 2010 7 of 14

NXP Semiconductors IP5311CX5

Dual-channel integrated passive filter network

7.3 Voltage dependency of high density capacitors

The high density capacitors integrated in IP5311CX5 show a voltage dependency similar

to some higher value discrete ceramic capacitors.

When used in an average mobile application, the typ ical voltage swing across the

capacitance will be in the range of −0.5 V to +4 V. In this event, the capacitor values

change proportional to the bias voltage as depicted in Figure 7.

The measurement is performed several times, starting at the ‘startin g point’ at 0 V,

increasing to 4 V (arrow 1), decreasing to −0.5 V (following arrow 2) and back to +4 V

(arrow 3).

When measuring the capacitance over voltage for voltage swings of e.g. −20 V to +20 V,

a hysteresis in the capacitance over Vbias(DC) can be observed (see Figure 8), which is

inherent to the integration process for the high density capacitors in this product.

Again, the measurement starts at ‘starting poi nt’, following arrow 1 up to Vbias(DC) =20V,

from there along arrow 2 down to Vbias(DC) =−2 0 V and back via arro w 3 and arrow 4.

Values of C1 and C2 specified in Table 4 are based on measurement s at the star ting point.

Fig 7. Relat ive capacitanc e C/C(0V) of high density

capacitors for −0.5 V ≤Vbias(DC) ≤+4 V Fig 8. Relative capacitance C/C(0V) of high den sity

capacitors for −20 V ≤Vbias(DC) ≤+20 V

Vbias(DC) (V)

−0.5 4.53.51.5 2.50.5

001aak632

0.95

0.85

1.05

1.15

C/C(0V)

0.75

starting

point

Vbias(DC) (V)

−20 2010−10 0

001aak633

0.5

0.75

0.25

1.25

C/C(0V)

starting

point

Product data sheet Rev. 2 — 23 December 2010 8 of 14

NXP Semiconductors IP5311CX5

Dual-channel integrated passive filter network

8. Package outline

Fig 9. Package outline IP5311CX5/LF (WLCSP5)

European

projection

wlcsp5_2x3-b1_po

LCSP5: wafer level chip-size package; 5 bumps (2 x 3 - B1)

detail X

laser

marking

area

bump A1

index area

Product data sheet Rev. 2 — 23 December 2010 9 of 14

NXP Semiconductors IP5311CX5

Dual-channel integrated passive filter network

9. Design and assembly recommendations

9.1 PCB design guidelines

It is recommended, for optimum performance, to use a Non-Solder Mask Defined

(NSMD), also known as a copper-defined design, incorporating laser-drilled micro-vias

connecting the ground p ads to a buried ground-plane layer. This results in the lowest

possible ground inductance and provides the best hi gh frequency and ESD performance.

Refer to Table 6 for the recommended PCB design parameters.

9.2 PCB assembly guidelines for Pb-free soldering

Table 5. Dimensions for Figure 9

Symbol Min Typ Max Unit

A 0.57 0.61 0.65 mm

A10.18 0.20 0.22 mm

A20.39 0.41 0.43 mm

b 0.21 0.26 0.31 mm

D 0.75 0.80 0.85 mm

E 1.11 1.16 1.21 mm

e-0.4-mm

Table 6. Recommended PCB design parameters

Parameter Value or specification

PCB pad diameter 250 μm

Micro-via diameter 100 μm (0.004 inch)

Solder mask aperture diameter 325 μm

Copper thickness 20 μm to 40 μm

Copper finish AuNi

PCB material FR4

Table 7. Assembly recommendations

Parameter Value or specification

Solder screen aperture diameter 325 μm

Solder screen thickness 100 μm (0.004 inch)

Solder paste: Pb-free SnAg (3 % to 4 %); Cu (0.5 % to 0.9 %)

Solder to flux ratio 50 : 50

Solder reflow profile see Figure 10

Product data sheet Rev. 2 — 23 December 2010 10 of 14

NXP Semiconductors IP5311CX5

Dual-channel integrated passive filter network

The device is capable of withstanding at least three reflows of this profile.

Fig 10. Pb-free solder reflow profile

Table 8. Characteristics

Symbol Parameter Conditions Min Typ Max Unit

Treflow(peak) peak reflow temperature 230 - 260 °C

t1time 1 soak time 60 - 180 s

t2time 2 time during T ≥250 °C--30s

t3time 3 time during T ≥230 °C10-50s

t4time 4 time during T > 217 °C30-150s

t5time 5 - - 540 s

dT/dt rate of change of

temperature cooling rate - - −6°C/s

preheat 2.5 - 4.0 °C/s

001aai94

reflow(peak)

250

230

217

(°C)

cooling rate

preheat

t (s)

Product data sheet Rev. 2 — 23 December 2010 11 of 14

NXP Semiconductors IP5311CX5

Dual-channel integrated passive filter network

10. Abbreviations

11. Revision history

Table 9. Abbreviations

Acronym Description

DUT Device Under Test

ESD ElectroStatic Discharge

FR4 Flame Retard 4

LAN Local Area Network

NSMD Non-Solder Mask Defined

NWA NetWork Analyzer

PCB Printed-Circuit Board

PCS Personal Communication System

RF Radio Frequency

RoHS Restriction of Hazardous Substances

WAN Wide Area Network

WLCSP Wafer-Level Chip-Scale Package

Table 10. Revision history

Document ID Release date Data sheet status Change notice Supersedes

IP5311CX5 v.2 20101223 Product data sheet - IP5311CX5 v.1

Modifications: •Figure 1: changed

•Figure 9: changed

IP5311CX5 v.1 20091130 Product data sheet - -

Product data sheet Rev. 2 — 23 December 2010 12 of 14

NXP Semiconductors IP5311CX5

Dual-channel integrated passive filter network

12. Legal information

12.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

12.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

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full information. For detailed and full information see the relevant full data

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office. In case of any inconsistency or conflict wit h the short data sheet, th e

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Applications — Applications that are described herein for any of these

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representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

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Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

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products are sold subject to the general terms and conditions of commercial

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Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification fo r product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

Product data sheet Rev. 2 — 23 December 2010 13 of 14

NXP Semiconductors IP5311CX5

Dual-channel integrated passive filter network

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for aut omotive use. It i s neither qua lified nor tested

in accordance with automotive testing or application requirements. NXP

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In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standards, custome r

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such au tomotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

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liability, damages or failed product claims resulting f rom customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

12.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

13. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors IP5311CX5

Dual-channel integrated passive filter network

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 23 December 2010

Document identifier: IP5311CX5

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

14. Contents

1 Product profile. . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 General description . . . . . . . . . . . . . . . . . . . . . 1

1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . 1

1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2

2.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3

5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 4

7 Application information. . . . . . . . . . . . . . . . . . . 5

7.1 Insertion loss . . . . . . . . . . . . . . . . . . . . . . . . . . 5

7.2 Crosstalk. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

7.3 Voltage dependency of high density

capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8

9 Design and assembly recommendations . . . . 9

9.1 PCB design guidelines . . . . . . . . . . . . . . . . . . . 9

9.2 PCB assembly guidelines for Pb-free

soldering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

10 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 11

11 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11

12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12

12.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12

12.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

12.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 12

12.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13

13 Contact information. . . . . . . . . . . . . . . . . . . . . 13

14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14