IP5311CX5 Dual-channel integrated passive filter network with ESD protection to IEC 61000-4-2 level 4 Rev. 2 -- 23 December 2010 Product data sheet 1. Product profile 1.1 General description IP5311CX5 is a dual-channel RC low-pass filter array which is designed to provide filtering of undesired RF signals in the 10 MHz to 6000 MHz frequency band. In addition, IP5311CX5 incorporates diodes to provide protection to downstream components from ElectroStatic Discharge (ESD) voltages as high as 15 kV contact according the IEC 61000-4-2 model, far exceeding standard level 4. The device is optimized for loudspeaker applications using speakers of 10 impedance and above. IP5311CX5 is fabricated using monolithic silicon technology and integrates several resistors, bidirectional diodes and two high density capacitors in a single Wafer-Level Chip-Scale Package (WLCSP). These features make the IP5311CX5 ideal for use in applications requiring the utmost in miniaturization such as mobile phone handsets, cordless telephones and personal digital devices. 1.2 Features and benefits Pb-free, RoHS compliant and free of halogen and antimony (Dark Green compliant) Dual-channel integrated RC filter network with high density capacitors (2 x 5 nF) Integrated ESD protection withstanding 15 kV contact discharge, far exceeding IEC 61000-4-2 level 4 WLCSP with 0.4 mm pitch 1.3 Applications Cellular and Personal Communication System (PCS) mobile handsets Cordless telephones Wireless data (WAN/LAN) systems IP5311CX5 NXP Semiconductors Dual-channel integrated passive filter network 2. Pinning information 2.1 Pinning bump A1 index area 2 1 A B C 008aaa200 transparent top view, solder balls facing down Fig 1. Pin configuration for WLCSP5 2.2 Pin description Table 1. Pinning Pin Description A1 filter channel 1 internal 2 kV amplifier connection A2 filter channel 1 external 15 kV speaker connection C1 filter channel 2 internal 2 kV amplifier connection C2 filter channel 2 external 15 kV speaker connection B1 not connected (missing ball) B2 ground 3. Ordering information Table 2. Ordering information Type number Package Name Description Version IP5311CX5/LF[1] WLCSP5 wafer level chip-size package; 5 bumps; 1.16 x 0.8 x 0.61 mm IP5311CX5/LF IP5311CX5/LF/P[2] WLCSP5 wafer level chip-size package; 5 bumps; 1.16 x 0.8 x 0.61 mm IP5311CX5/LF/P [1] Lead-free. [2] Lead-free and sol pearls. IP5311CX5 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 23 December 2010 (c) NXP B.V. 2010. All rights reserved. 2 of 14 IP5311CX5 NXP Semiconductors Dual-channel integrated passive filter network 4. Functional diagram 15 A1 A2 5 nF B2 5 nF 15 C1 C2 008aaa201 Fig 2. Schematic diagram IP5311CX5 5. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VI input voltage VESD electrostatic discharge voltage Conditions Min Max Unit -0.5 +4.5 V pins A2 and C2 to ground contact discharge [1] -15 +15 kV air discharge [1] -15 +15 kV IEC 61000-4-2 level 4; pins A2 and C2 to ground contact discharge -8 +8 kV air discharge -15 +15 kV IEC 61000-4-2 level 1; pins A1 and C1 to ground +2 kV +2 kV - 92 mA channel current (DC) Pch channel power dissipation continuous power - 100 mW Ptot total power dissipation continuous power - 200 mW Tstg storage temperature -55 +150 C - 260 C -35 +85 C Tamb [1] Product data sheet -2 -2 Ich Treflow(peak) peak reflow temperature IP5311CX5 contact discharge air discharge 10 s maximum ambient temperature Device is qualified with 1000 pulses of 15 kV contact discharges each, according to the IEC 61000-4-2 model and far exceeds the specified level 4 (8 kV contact discharge). All information provided in this document is subject to legal disclaimers. Rev. 2 -- 23 December 2010 (c) NXP B.V. 2010. All rights reserved. 3 of 14 IP5311CX5 NXP Semiconductors Dual-channel integrated passive filter network 6. Characteristics Table 4. Channel characteristics Tamb = 25 C; unless otherwise specified. Symbol Parameter Rs(ch) channel series resistance Product data sheet Max Unit 13.5 15 16.5 5 6 nF 5 6 nF - 14 - pF positive direction; Itest = 1 mA 14 16.5 - V negative direction; Itest = -1 mA - -16.5 -14 V per channel; VI = 3.0 V - - 60 nA per channel; VI = -3.0 V -60 - - nA capacitance 2 Cd diode capacitance Vbias(DC) = 0 V; f = 100 kHz VBR breakdown voltage [1] Typ 4 capacitance 1 reverse leakage current Min 4 C1 C2 ILR IP5311CX5 Conditions high density; Vbias(DC) = 0 V; f = 100 kHz [1] Guaranteed by design. All information provided in this document is subject to legal disclaimers. Rev. 2 -- 23 December 2010 (c) NXP B.V. 2010. All rights reserved. 4 of 14 IP5311CX5 NXP Semiconductors Dual-channel integrated passive filter network 7. Application information 7.1 Insertion loss The insertion loss measurement configuration of a typical 50 NetWork Analyzer (NWA) system for evaluation of the IP5311CX5 is shown in Figure 3. The insertion loss of both channels at frequencies up to 6 GHz is displayed in Figure 4. IN OUT DUT 50 50 TEST BOARD Vgen 001aai755 Fig 3. Frequency response measurement configuration 001aak630 0 s21 (dB) -10 (1) (2) -20 -30 -40 -50 10-1 1 10 102 103 104 f (MHz) (1) Channel 1 (pins A1 and A2). (2) Channel 2 (pins C1 and C2). Fig 4. IP5311CX5 Product data sheet Measured insertion loss magnitudes All information provided in this document is subject to legal disclaimers. Rev. 2 -- 23 December 2010 (c) NXP B.V. 2010. All rights reserved. 5 of 14 IP5311CX5 NXP Semiconductors Dual-channel integrated passive filter network 7.2 Crosstalk The crosstalk measurement configuration of a typical 50 NWA system for evaluation of the IP5311CX5 is shown in Figure 5. The measured crosstalk within the IP5311CX5 in a 50 NWA system from one channel to the other channel is shown in Figure 6. In all cases, unused connections are terminated with 50 to ground. IN_1 OUT_2 DUT IN_2 50 50 OUT_1 TEST BOARD 50 50 Vgen 001aai756 Fig 5. Crosstalk measurement configuration 001aak631 0 ct (dB) -20 -40 -60 -80 -100 10-1 (2) (1) 1 10 102 103 104 f (MHz) (1) Channel 1 to channel 2 (pins A1 and C2). (2) Channel 2 to channel 1 (pins A2 and C1). Fig 6. IP5311CX5 Product data sheet Measured crosstalk between adjacent channels All information provided in this document is subject to legal disclaimers. Rev. 2 -- 23 December 2010 (c) NXP B.V. 2010. All rights reserved. 6 of 14 IP5311CX5 NXP Semiconductors Dual-channel integrated passive filter network 7.3 Voltage dependency of high density capacitors The high density capacitors integrated in IP5311CX5 show a voltage dependency similar to some higher value discrete ceramic capacitors. When used in an average mobile application, the typical voltage swing across the capacitance will be in the range of -0.5 V to +4 V. In this event, the capacitor values change proportional to the bias voltage as depicted in Figure 7. The measurement is performed several times, starting at the `starting point' at 0 V, increasing to 4 V (arrow 1), decreasing to -0.5 V (following arrow 2) and back to +4 V (arrow 3). When measuring the capacitance over voltage for voltage swings of e.g. -20 V to +20 V, a hysteresis in the capacitance over Vbias(DC) can be observed (see Figure 8), which is inherent to the integration process for the high density capacitors in this product. Again, the measurement starts at `starting point', following arrow 1 up to Vbias(DC) = 20 V, from there along arrow 2 down to Vbias(DC) = -20 V and back via arrow 3 and arrow 4. Values of C1 and C2 specified in Table 4 are based on measurements at the starting point. 001aak632 1.15 001aak633 1.25 4 C/C(0V) C/C(0V) 3 1 1.05 0.75 0.95 3 1 starting point starting point 1 0.5 2 0.85 0.25 2 0.75 -0.5 Fig 7. 0.5 1.5 2.5 Relative capacitance C/C(0V) of high density capacitors for -0.5 V Vbias(DC) +4 V IP5311CX5 Product data sheet 0 -20 3.5 4.5 Vbias(DC) (V) Fig 8. -10 0 10 20 Vbias(DC) (V) Relative capacitance C/C(0V) of high density capacitors for -20 V Vbias(DC) +20 V All information provided in this document is subject to legal disclaimers. Rev. 2 -- 23 December 2010 (c) NXP B.V. 2010. All rights reserved. 7 of 14 IP5311CX5 NXP Semiconductors Dual-channel integrated passive filter network 8. Package outline WLCSP5: wafer level chip-size package; 5 bumps (2 x 3 - B1) D bump A1 index area A2 E A A1 laser marking area detail X e b C B A 2 1 European projection X wlcsp5_2x3-b1_po Fig 9. Package outline IP5311CX5/LF (WLCSP5) IP5311CX5 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 23 December 2010 (c) NXP B.V. 2010. All rights reserved. 8 of 14 IP5311CX5 NXP Semiconductors Dual-channel integrated passive filter network Table 5. Dimensions for Figure 9 Symbol Min Typ Max Unit A 0.57 0.61 0.65 mm A1 0.18 0.20 0.22 mm A2 0.39 0.41 0.43 mm b 0.21 0.26 0.31 mm D 0.75 0.80 0.85 mm E 1.11 1.16 1.21 mm e - 0.4 - mm 9. Design and assembly recommendations 9.1 PCB design guidelines It is recommended, for optimum performance, to use a Non-Solder Mask Defined (NSMD), also known as a copper-defined design, incorporating laser-drilled micro-vias connecting the ground pads to a buried ground-plane layer. This results in the lowest possible ground inductance and provides the best high frequency and ESD performance. Refer to Table 6 for the recommended PCB design parameters. Table 6. Recommended PCB design parameters Parameter Value or specification PCB pad diameter 250 m Micro-via diameter 100 m (0.004 inch) Solder mask aperture diameter 325 m Copper thickness 20 m to 40 m Copper finish AuNi PCB material FR4 9.2 PCB assembly guidelines for Pb-free soldering Table 7. IP5311CX5 Product data sheet Assembly recommendations Parameter Value or specification Solder screen aperture diameter 325 m Solder screen thickness 100 m (0.004 inch) Solder paste: Pb-free SnAg (3 % to 4 %); Cu (0.5 % to 0.9 %) Solder to flux ratio 50 : 50 Solder reflow profile see Figure 10 All information provided in this document is subject to legal disclaimers. Rev. 2 -- 23 December 2010 (c) NXP B.V. 2010. All rights reserved. 9 of 14 IP5311CX5 NXP Semiconductors Dual-channel integrated passive filter network T (C) Treflow(peak) 250 230 cooling rate 217 preheat t1 t (s) t2 t3 t4 t5 001aai943 The device is capable of withstanding at least three reflows of this profile. Fig 10. Pb-free solder reflow profile IP5311CX5 Product data sheet Table 8. Characteristics Symbol Parameter Treflow(peak) peak reflow temperature t1 time 1 soak time 60 - 180 s t2 time 2 time during T 250 C - - 30 s t3 time 3 time during T 230 C 10 - 50 s t4 time 4 time during T > 217 C 30 - 150 s - - 540 s cooling rate - - -6 C/s preheat 2.5 - 4.0 C/s t5 time 5 dT/dt rate of change of temperature Conditions All information provided in this document is subject to legal disclaimers. Rev. 2 -- 23 December 2010 Min Typ Max Unit 230 - 260 C (c) NXP B.V. 2010. All rights reserved. 10 of 14 IP5311CX5 NXP Semiconductors Dual-channel integrated passive filter network 10. Abbreviations Table 9. Abbreviations Acronym Description DUT Device Under Test ESD ElectroStatic Discharge FR4 Flame Retard 4 LAN Local Area Network NSMD Non-Solder Mask Defined NWA NetWork Analyzer PCB Printed-Circuit Board PCS Personal Communication System RF Radio Frequency RoHS Restriction of Hazardous Substances WAN Wide Area Network WLCSP Wafer-Level Chip-Scale Package 11. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes IP5311CX5 v.2 20101223 Product data sheet - IP5311CX5 v.1 - - Modifications: IP5311CX5 v.1 IP5311CX5 Product data sheet * * Figure 1: changed Figure 9: changed 20091130 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 23 December 2010 (c) NXP B.V. 2010. All rights reserved. 11 of 14 IP5311CX5 NXP Semiconductors Dual-channel integrated passive filter network 12. Legal information 12.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 12.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. 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Export might require a prior authorization from national authorities. IP5311CX5 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 23 December 2010 (c) NXP B.V. 2010. All rights reserved. 12 of 14 IP5311CX5 NXP Semiconductors Dual-channel integrated passive filter network Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 12.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 13. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com IP5311CX5 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 23 December 2010 (c) NXP B.V. 2010. All rights reserved. 13 of 14 IP5311CX5 NXP Semiconductors Dual-channel integrated passive filter network 14. Contents 1 1.1 1.2 1.3 2 2.1 2.2 3 4 5 6 7 7.1 7.2 7.3 8 9 9.1 9.2 10 11 12 12.1 12.2 12.3 12.4 13 14 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Application information. . . . . . . . . . . . . . . . . . . 5 Insertion loss . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Crosstalk. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Voltage dependency of high density capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 Design and assembly recommendations . . . . 9 PCB design guidelines . . . . . . . . . . . . . . . . . . . 9 PCB assembly guidelines for Pb-free soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact information. . . . . . . . . . . . . . . . . . . . . 13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 23 December 2010 Document identifier: IP5311CX5