Vishay Siliconix
SiP2214
Document Number: 73191
S09-1454-Rev. E, 03-Aug-09
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1
Dual Output Low Dropout Regulator
FEATURES
• 2.25 V to 5.5 V input voltage range
• Two outputs - 150 mA and 300 mA
• Low ground current
• Open drain driver output
• POR
• Current limit
• Thermal shutdown
• MLP33-10 and MLP44-16 PowerPAK® packages
APPLICATIONS
• Cellular phones
• Wireless modems
•PDAs
DESCRIPTION
The SiP2214 is a dual output low dropout regulator capable
of supplying 150 mA from output 1 and 300 mA from output
2. In addition to the LDOs, an open drain output has been
included, which is capable of sinking 150 mA. The SiP2214
offers a low dropout, low ground current and extremely low
noise with the addition of a bypass capacitor.
Protection features include POR with adjustable delay,
undervoltage lockout, output current limit, and thermal
shutdown.
The fixed output version of SiP2214 is available in the
MLP33-10 PowerPAK package and the adjustable version is
available in the MLP44-16 PowerPAK package. Both
packages are specified to operate over the range of - 40 °C
to 85 °C.
TYPICAL APPLICATION CIRCUIT
VOUT1
VOUT2
POR
DRV
VIN
EN
BP
SW
SET
GND
SiP2214
VOUT1
VOUT2
POR
VIN
EN
SW
GND
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Document Number: 73191
S09-1454-Rev. E, 03-Aug-09
Vishay Siliconix
SiP2214
Notes:
a. Device mounted with all leads soldered or welded to PC board.
b. Derate 20 mW/°C above 70 °C.
c. Derate 23.5 mW/°C above 70 °C.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
Parameter Limit Unit
VIN, VEN, to GND - 0.3 to 7 V
Power Dissipation MLP33-10 PowerPAKb1600 mW
MLP44-16 PowerPAKc1880
Storage Temperature - 55 to 150 °C
Thermal Resistance MLP33-10 PowerPAKa50 °C/W
MLP44-16 PowerPAKa43
RECOMMENDED OPERATING RANGE
Parameter Limit Unit
Input Voltage Range 2.25 to 5.5 V
Enable Voltage Range 0 to 5.5
Operating Temperature Range TA- 40 to 85 °C
Operating Temperature Range TJ- 40 to 125
SPECIFICATIONS
Parameter Symbol
Test Conditions Unless Specified
VIN = VOUT + 1 Vf, COUT = 1 µF, IOUT = 100 µA
TA = 25 °C
Temp.a
Limits
Unit Min.b Typ.cMax.b
Regulators
Output Voltage Accuracy From Nominal VOUT Room - 1 1 %
Full - 2 2
Output Voltage
Temperature Coefficient Room 40 ppm/°C
Line RegulationfVIN = VOUT + 1 V to 5.5 V Room - 0.3 0.2 0.3
%
Full - 0.6 0.6
Load Regulation IOUT = 100 µA to 150 mA (LDO 1 and 2) Room 0.2 1.0
IOUT = 100 µA to 300 mA (LDO 2) Room 1.5
Dropout VoltagegVDROP
IOUT = 150 mA (LDO 1 and 2) Room 120 190
mV
Full 250
IOUT = 300 mA (LDO 2) Room 240 340
Full 420
Ground Pin Current IG
IOUT1 = IOUT2 = 0 µA Room 48 65
µA
IOUT1 = IOUT2 = 0 µA Full 80
IOUT1 = 150 mA, IOUT2 = 300 mA Room 60
VEN < 0.4 V Full 2.0
Output Voltage Noise CBP = 0.01 µF 30 µVrms
Ripple Rejection f = 1 kHz, COUT = 1 µF, CBP = 10 nF Room 60 dB
f = 20 kHz, COUT = 1 µF, CBP = 10 nF Room 40
Inputs
EN, SW Input Voltage VIL Logic Low Full 0.6 V
VIH Logic High Full 1.8
EN, SW Input Current IIL VIL < 0.6 V Room - 1 0.01 1 µA
IIH VIH > 1.8 V Room - 1 0.01 1
SET Pin Threshold Voltage VTH(set) POR = High Room 1.25 V
SET Pin Current Source VSET = 0 V Room 0.75 1.25 1.75 µA
Document Number: 73191
S09-1454-Rev. E, 03-Aug-09
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Vishay Siliconix
SiP2214
Notes:
a. Room = 25 °C, Full = - 40 °C to 85 °C.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. Timing is measured from 90 % of LDO #1’s final value to 90 % of LDO #2’s final value.
e. Guaranteed by design.
f. For higher output of the regulator pair.
g. Dropout voltage is defined as the input to output differential voltage at which the output voltage drops 2 % below the output voltage measured
with a 1 V differential, provided that VIN does not drop below 2.25 V. When VOUT(nom) is less than 2.25 V, the output will be in regulation when
2.25 V - VOUT(nom) is greater than the dropout voltage specified.
SPECIFICATIONS
Parameter Symbol
Test Conditions Unless Specified
VIN = VOUT + 1 Vf, COUT = 1 µF, IOUT = 100 µA,
TA = 25 °C
Temp.a
Limits
Unit Min.b Typ.cMax.b
Power On Reset (POR) Output
Threshold VTHL % of Nominal VOUT2
Room 90 %
VTHH Room 96
Output Voltage VOL IL = 250 µA Room 0.02 0.1 V
Leakage Current IPOR POR = High Room - 1 0.01 1 µA
Driver (DRV) Output
Output Voltage VOL IL = 150 mA Full 0.2 0.6 V
Leakage Current IDRV = 0 mA, VDRV = 5.5 V, SW = 0 V Room - 1 0.01 1 µA
Protection
Current Limit IIL
VOUT1 = 0 V Room 150 280 460 mA
VOUT2 = 0 V Room 300 450 700
Thermal Shutdown Temperature Room 165 °C
Thermal Hysteresis Room 25
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Document Number: 73191
S09-1454-Rev. E, 03-Aug-09
Vishay Siliconix
SiP2214
FUNCTIONAL BLOCK DIAGRAM
VIN
EN
BP
SW
VOUT1
VOUT2
POR
DRV
GND
Reference
LDO #2
PORDLY
LDO #1
SWLOGIC
SET
GNDSW
Fixed Voltage Version
VIN
EN1
BP
SW
VOUT1
VOUT2
POR
DRV
GND
Reference
LDO #2
PORDLY
LDO #1
SWLOGIC
SET
GNDSW
Adjustable Voltage Version
ADJ1
EN2ADJ2
Document Number: 73191
S09-1454-Rev. E, 03-Aug-09
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Vishay Siliconix
SiP2214
PIN CONFIGURATIONS AND ORDERING INFORMATION
X: Output 1 voltage code.
Z: Output 2 voltage code.
The exposed pad on both packages must be connected externally to the GND pin.
10
9
8
7
V
IN
EN
BP
SW
V
OUT1
V
OUT2
POR
DRV
Top View
V
IN
EN
1
EN
2
BP
V
OUT1
V
OUT2
ERR
DRV
Bottom View
SET
2
3
4
1
56 SW
GND GND
10
9
8
7
1
2
3
4
65
Exposed Pad
PowerPAK MLP33-10 with Large Pad
DRV EN
2
GND
SW
ADJ
2
ADJ
1
BP
POR EN
1
12
11
10
1
2
3
94
8765
13 14 15 16
Bottom View
D N G
D N G
T E S
W S
V 2 T U O
V 1 T U O
V N I
V N I
PowerPAK MLP44-16
VOLTAGE OPTIONS
Voltage Code (x, z)
Adj A
1.5 F
1.6 W
1.8 G
1.85 D
1.9 Y
2.0 H
2.1 E
2.5 J
2.6 K
2.7 L
2.8 M
2.85 N
2.9 O
3.0 P
3.1 Q
3.2 R
3.3 S
3.4 T
3.5 U
3.6 V
ORDERING INFORMATION
Part Number Temp. Range Package Marking
SiP2214DMP-XZ-T1
- 40 °C to 85 °C
PowerPAK
MLP33-10 14XZ
SiP2214DLP-AA-T1 PowerPAK
MLP44-16 14AA
PIN DESCRIPTION
Pin Number Name Function
MLP33-10 MLP44-16
1 15, 16 VIN Input voltage for the power MOSFETs and their gate drive
2 EN Enables both LDO outputs
1EN
1Enable LDO #1
2EN
2Enable LDO #2
3 3 BP Bypass for noise reduction
4 5 SW Control for open drain output
4ADJ
1Feedback connection for LDO #1
5 6 SET Connection for external capacitor to delay POR
6 7, 8 GND Ground
9GND
SW Ground for the internal N-channel MOSFET switch
10 ADJ2Feedback connection for LDO #2
7 11 DRV Open drain output
8 12 POR Power on reset output
913V
OUT2 Output of LDO #2 - 300 mA
10 14 VOUT1 Output of LDO #1 - 150 mA
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Document Number: 73191
S09-1454-Rev. E, 03-Aug-09
Vishay Siliconix
SiP2214
TYPICAL CHARACTERISTICS
Dropout Characteristics - Output 1
Dropout Voltage - Output 1
Ground Current vs. Supply Voltage
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Supply Voltage (V)
)V( tuptuO
100 µA
150 mA
- 10
10
30
50
70
90
110
130
150
- 40 - 20 0 20 40 60 80 100 120 140
)Vm(
ega
tloV
tuo
po
rD
150 mA Load
Temperature (°C)
0
10
20
30
40
50
60
0123456
Supply Voltage (V)
(µA) tnerruC dnuorG
Output 1 and 2
with 100 µA Load
Dropout Characteristics - Output 2
Dropout Voltage - Output 2
Ground Current vs. Output 1 Current
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
)V( tuptuO
Supply Voltage (V)
100 µA
300 mA
V
t
uopor
D)
Vm( e
gat
l
o
0
50
100
150
200
250
300
350
- 40 - 20 0 20 40 60 80 100 120 140
Temperature (°C)
300 mA Load
0
10
20
30
40
50
60
0 20 40 60 80 100 120 140
Output 1 Load Current (mA)
(µA) tne
r
ru
C
dnu
o
rG
Document Number: 73191
S09-1454-Rev. E, 03-Aug-09
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Vishay Siliconix
SiP2214
TYPICAL CHARACTERISTICS
Ground Current vs. Output 2 Current
Output Voltage vs. Load Current - Output 1
Output Voltage 1 vs. Temperature
0
10
20
30
40
50
60
0 50 100 150 200 250 300
Output 2 Load Current (mA)
(µA) t n e r r u C d n u o r G
2.780
2.785
2.790
2.795
2.800
2.805
2.810
2.815
2.820
0 255075100125150
Output 1 Load Current (mA)
)V( egat
l
oV tuptuO
2.760
2.770
2.780
2.790
2.800
2.810
2.820
2.830
2.840
- 40 - 20 0 20 40 60 80 100 120 140
Temperature (°C)
100 µA Load
)V( egatloV
tupt
u
O
Ground Pin Current
Output Voltage vs. Load Current - Output 2
Output Voltage 2 vs. Temperature
0
10
20
30
40
50
60
- 40 - 20 0 20 40 60 80 100 120 140 160
Load On Both Outputs
Temperature (°C)
(µA) tnerruC niP dnuorG
100 µA
0 µA
1 mA
3.585
3.590
3.595
3.600
3.605
3.610
3.615
0 50 100 150 200 250 300
)V( egatloV tuptuO
Output 2 Load Current (mA)
3.55
3.56
3.57
3.58
3.59
3.60
3.61
3.62
3.63
3.64
3.65
- 40 - 20 0 20 40 60 80 100 120 140
Temperature (°C)
)V( egatloV tuptuO
100 µA Load
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Document Number: 73191
S09-1454-Rev. E, 03-Aug-09
Vishay Siliconix
SiP2214
TYPICAL CHARACTERISTICS
Switch Threshold vs. Supply Voltage
POR Delay
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
2.25 2.75 3.25 3.75 4.25 4.75 5.25
Supply Voltage (V)
)V( dlohserhT gnihctiwS
Drive Current = 1 mA
POR Setting Cap (nF)
) s m (
e
m i
T
C
IN
= 1 µF
C
OUT
= 1 µF
I
LOAD
= 100 µA
100
0.01
0.001 100 1000
0.1
1
10
1010.1 0.01
1000
Enable Voltage Threshold vs. Supply Voltage
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
2.25 2.75 3.25 3.75 4.25 4.75 5.25 5.75
Supply Voltage (V)
)V( dlohserhT elbanE
Document Number: 73191
S09-1454-Rev. E, 03-Aug-09
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Vishay Siliconix
SiP2214
TYPICAL WAVEFORMS
Noise Spectrum Output 1
Enable Sequence
Load Transient Response LDO1
10
0.01
10 Hz 1 MHz
µV Hz
100 µs/div
EN
2 V/div
VOUT2
1 V/div
VOUT1
1 V/div
CIN = 1 µ F
COUT = 1 µ F
CBP = 0.01 µ F
VIN = 5 V
150 mA
IOUT1
100 mA/div
VOUT2
50 mV/div
VOUT1
50 mV/div
5 µs/div
CIN = 1 µ F
COUT = 1 µ F
CBP = 0.01 µ F
VIN = 5 V
Noise Spectrum Output 2
Power-On Reset Sequence
Load Transient Response LDO2
10
0.01
10 Hz 1 MHz
µV Hz
5 ms/div
EN
2 V/div
POR
2 V/div
V
OUT2
1 V/div
V
OUT1
1 V/div
C
IN
= 1 µ F
C
OUT
= 1 µ F
C
BP = 0.01 µ F
C
SET
= 0.01 µF
V
IN
= 5 V
300 mA
IOUT1
200 mA/div
VOUT1
50 mV/div
VOUT2
50 mV/div
5 µs/div
CIN = 1 µ F
COUT = 1 µ F
CBP = 0.01 µ F
VIN = 5 V
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Document Number: 73191
S09-1454-Rev. E, 03-Aug-09
Vishay Siliconix
SiP2214
DETAILED OPERATION
The SiP2214 is a low drop out, low quiescent current
monolithic dual linear regulator, with power-on reset and
open drain driver output features. With output voltage range
from 1.25 V to 5 V the first regulator can source 150 mA and
the second regulator can source 300 mA. The open drain
driver has the capability to drive LED’s for backlighting
applications.
VIN
VIN is the input supply pin for both LDO’s. The bypass
capacitor for this pin is not critical as long as the input supply
has low enough source impedance. For practical circuits, a
1.0 µF or larger ceramic capacitor is recommended. When
the source impedance is not low enough and/or the source is
several inches from the SiP2214, then a larger input bypass
capacitor is needed. When the source impedance, wire and
trace impedance are unknown, it is recommended that an
input bypass capacitor be used of a value that is equal to or
greater than the output capacitor.
VOUT1,2 (LDO Outputs)
The VOUT is the output voltage of the regulator. Connect a
bypass capacitor from VOUTx to ground. The output capacitor
can be any value from 1.0 µF to 10.0 µF. A ceramic capacitor
with X5R or X7R dielectric type is recommended for best
output noise, line transient, and load transient performance.
Enable
The Enable pin controls the turning on and off of both
regulators of the SiP2214. VOUT of both outputs are
guaranteed to be on when the Enable pin voltage is equal or
greater than 1.8 V. VOUT is guaranteed to be off when the
Enable pin voltage equals or is less than 0.6 V. To
automatically turn on VOUT whenever the Input is applied, tie
the Enable pin to VIN.
For the adjustable voltage version of the SiP2214, LDO1 and
LDO2, have separate and independent Enable control pins.
Power-On Reset (POR)
The POR is an open drain output that goes low when VOUT2
is less than 5 % of its nominal value. As with any open drain
output, an external pull up resistor is needed. The POR pin
is disconnected if not used.
SET
When a capacitor is connected from SET to GROUND, the
POR signal transition from low to high is delayed. This
delayed POR signal can be used as the power-on reset
signal for the application system. To set the POR delay time
refer to the POR Delay curve to determine the capacitor
value.
The Set pin should be an open circuit if not used.
OPEN-Drain Driver (DRV)
The SW pin a logic level input put that controls the DRV pin.
The switch pin is an active high input and should not be left
floating. The drive pin is an open drain output able to sink
150 mA of current.
Bypass Capacitor
For low noise application and/or increase in power supply
rejection ration (PSRR) connect a high frequency ceramic
capacitor from BP to ground. A 0.01 µF X5R or X7R ceramic
capacitor is recommended.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?73191.
Document Number: 91000 www.vishay.com
Revision: 18-Jul-08 1
Disclaimer
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Vishay
All product specifications and data are subject to change without notice.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf
(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any
information provided herein to the maximum extent permitted by law. The product specifications do not expand or
otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed
therein, which apply to these products.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this
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The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless
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