Le77D11 Integrated Voice Chip Sets VoiceChipTM Family 770 Series APPLICATIONS ! Short/Medium Loop: approximately 2000 ft. of 26 AWG, and 5 REN loads ! Voice over IP/DSL - Integrated Access Devices, Smart ORDERING INFORMATION An Le78D11 codec/filter must be used with this part. Device Package Le77D112TC 44-pin eTQFP Residential Gateways, Home Gateway/Router ! Cable Telephony - NIU, Set-Top Box, Home Side Box, Cable Modem, Cable PC ! Fiber-Fiber In The Loop (FITL), Fiber to the Home (FTTH) ! Wireless Local Loop, Intelligent PBX, ISDN NT1/TA FEATURES ! Integrated Dual-Channel Chip set ! ! ! ! -- Built-in boost switching power supply tracks line voltage minimizing power dissipation -- Only +3.3 V and +12 V (nominal) required -- Wide range of input voltages (+8 V to +40 V) supported -- Minimum external discrete components -- 44-pin eTQFP package Ringing -- 5REN -- Up to 90 Vpk, Balanced -- Sinusoidal or trapezoidal with programmable DC offset Subscriber Loop Test/Self-Test -- GR-909 compliant drop test capability in both measurements and pass/fail - Hazardous Potential - Foreign Electromotive Force - Resistive Faults - Receive Off-hook - Ringers Test - Loop Length World Wide Programmability: -- Two-wire AC impedance -- Dual Current Limit -- Metering -- Programmable loop closure and ring trip thresholds Six SLIC Device States, including: -- Low power Standby state -- On-hook transmission -- Reverse Polarity RELATED LITERATURE ! 080697 Le78D11 Data Sheet ! 080716 Le77D11/Le78D11 Chip Set User's Guide ! 081013 Layout Considerations for the Le77D11 and DESCRIPTION Legerity's Le77D11 dual-channel SLIC device has enhanced and optimized features to directly address the requirements of voice over broadband applications. Their common goal is to reduce system level costs, space, and power through higher levels of integration, and to reduce the total cost of ownership by offering better quality of service. The Le78D11/Le77D11 is a two-device chip set providing a totally software configurable solution to the BORSCHT functions for two lines. The resulting system is less complex, smaller, and denser, yet cost effective with minimal external components. The Le77D11 device requires only two power supplies: +3.3 VDC and nominally +12 VDC, but can range from +8 to +40 VDC depending on the application. A single TTL-level clock source drives the two switching regulators that generate the required line voltage dynamically on a "per line" basis. Six programmable states are available: Low Power Standby, Disconnect, Normal Active, Reverse Polarity, Ringing and Line Test. Binary fault detection is provided upon application of fault conditions or thermal overload. BLOCK DIAGRAM Le77D11 SLIC Switching Power Supply 2-wire Tip+Ring Interface Ring Tip 2-wire to 4-wire conversion Le78D11 Codec Codec Interface 2-wire to 4-wire conversion 2-wire Tip+Ring Interface Ring Tip Switching Power Supply Le9502 Application Note Docuemnt ID# 080696 Date: Jun 17, 2003 Rev: F Version: 1 Distribution Level: Public Document TABLE OF CONTENTS Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Related Literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Block Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Two-Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Switcher Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Signal Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Fault Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Supply Currents and Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 System Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Device Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Test Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Single Channel Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Application Circuit Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 44-Pin eTQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Revision B1 to C1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Revision C1 to D1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Revision D1 to E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Revision E1 to F1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2 Le77D11 VoiceChipTM Family 770 Series SLIC Data Sheet PRODUCT DESCRIPTION The dual channel Le77D11 SLIC device uses reliable, dielectrically isolated, fully complementary bipolar technology to implement BORSCHT functions for short loop applications. Internal power dissipation is minimized by two independent line voltage tracking, buck-boost switching regulators. Two power supplies are required: 3.3 V and a positive supply (VSW). A TTL-level clock driven by the Le78D11 codec/filter is required for switcher operation. Six programmable states control loop signaling, transmission, and ringing. The Le77D11 device DC current limit (ISC) is programmable from 15 to 45 mA. The following diagram demonstrates a typical application. Figure 1. Typical Le77D11 SLIC Device/Le78D11 Codec/Filter Application in an 8-Port Integrated Access Device in Customer Premises Din 1 Le77D11 Le78D11 Dout Le77D11 PCM I/F Le78D11 DCLK/CS Le77D11 DSP Network Processor Loop/Cable MODEM WLL DSLAM/ HEADEND Le78D11 Din Le77D11 Le78D11 Dout Data Interfaces 8 Ethernet USB HomePNA BLOCK DESCRIPTIONS Figure 2. Le77D11 SLIC Device Block Diagram F1 Fault Detection Signal Transmission A1 (TIP) B1 (RING) 2-Wire Interface Signal Conditioning VREG 1 SD 1 ILS 1 CHS 1 Switcher Controller NPRFILT 1 VIN 1 VOUT 1 VHP 1 CFILT 1 LPF 1 IMT 1 RDC 1 Control Logic C1 1 C2 1 C3 1 Control Logic C1 2 C2 2 C3 2 VSW CHCLK FSET SD 2 ILS 2 CHS 2 VREG 2 A2 (TIP) B2 (RING) Switcher Controller 2-Wire Interface Signal Conditioning IMT 2 RDC 2 Signal Transmission NPRFILT 2 VIN 2 VOUT 2 VHP 2 CFILT 2 LPF 2 Fault Detection F2 BGND 1 BGND 2 AGND VCC VREF Le77D11 VoiceChipTM Family 770 Series SLIC Data Sheet 3 Two-Wire Interface The two-wire interface block provides DC current and sends/receives voice signals to a telephone connected via the Ai (Tip) and Bi (Ring) pins. The Ai (Tip) and Bi (Ring) pins are also used to send the ringing signal to the telephone. The Le77D11 SLIC device can also be programmed in Disconnect state to place the A and B pins at high impedance with the Switching Regulator disabled. DC Feed DC feed control in the Le78D11/Le77D11 chip set is implemented in the Le77D11 SLIC device. The current limit threshold (ILTH) can be programmed via the MPI interface of the Le78D11 codec/filter. The current limit threshold (ILTH) can be programmed up to 30 mA using the recommended RDC value. Referring to Figure 3, the DC feed curve consists of two distinct regions. The first region is a flat anti-sat region that supplies a constant Tip-Ring voltage (VAB open). The second region is a constant current region that begins when the loop current reaches the programmed current limit threshold (ILTH). This region looks like a constant current source with 3.2 k shunt resistor. The short circuit current is nominally 14.4 mA greater than ILTH. A block diagram of the DC feed control circuit is shown in Figure 4. In the anti-sat region, current source CS1 creates a constant reference current, which is limited to sub-voice frequencies by CLPFi. This filtered current is then steered by the Polarity Control, depending on whether the SLIC device mode is Standby, Normal Active, or Reverse Polarity. The steered current then takes one of two paths to the Level Shift block, where it is used to set VA (TIP) and VB (RING). This voltage from the Level Shift block is buffered by the output amplifiers and appears at Ai (TIP) and Bi (RING). When ILOOP/500 becomes greater than ILTH/500, the difference is subtracted from CS1, and again filtered by CLPFi. This reduced current causes a reduced DC feed voltage. In Standby and Normal Active, Ai (TIP) is held constant, while Bi (RING) is changed to reduce the feed voltage. In Reverse Polarity, Ai (TIP) and Bi (RING) are swapped. When (ILOOP-ILTH)/500 = CS1], all of the current from CS1 is subtracted, making the TIP-RING voltage = 0 V. This is the short circuit condition. At least 100 loop and fuse resistance are required to ensure stability of the Ai (TIP) and Bi (RING) output amplifiers. The capacitor CLPFi, in conjunction with an internal 25-k resistor (not shown) is used to create a low pass filter for the DC feed loop. This capacitor should nominally be 4.7 F, setting a 1.4 Hz pole. The purpose of this filter is to separate the operation of the DC feed from voice frequencies, preventing distortion and idle-channel noise. Normal or Reverse Polarity is controlled by the Le78D11 codec/filter through the C3-1 state control pins. Some applications require slew rate control of the transition between these feed states. The capacitor, CNPRi, may be used to increase the transition time and create a quiet polarity change. In the Normal Active state, the NPRFILTi pin is driven up to VCC. When Reverse Polarity is selected, CNPRi is discharged by current INPR, and the transition time is: ( V CC - V REF ) * C NPRi t = --------------------------------------------------------I NPR In the Reverse Polarity state, the NPRFILTi pin is discharged near ground. When Normal Active is selected, CNPRi is charged by V REF * C NPRi current INPR, and the transition time is: t = ----------------------------------I NPR A 100-nF capacitor provides a nominal Normal Active to Reverse Polarity transition time of about 5 ms and a Reverse Polarity to Normal Active transition time of 3 ms. Figure 3. DC Feed Curve VAB ILTH VAB open (48 V) I SC = I LTH + 14.4mA V DC V DC = ---------I LTH = ---------------------R DC K DC 40 14.4 mA 0 ISC ILOOP Notes: 1. VDC is programmable via the Le78D11 codec/filter. (VDC = 0.00 V to 1.20 V relative to VREF.) 2. VREF = 1.4 V nominal. I IMT 3. KDC = Le77D11 SLIC device DC current gain. K DC = -------------- . I LOOP 4. RDC = external resistor 20 k nominal. 5. VAB = VAi - VBi Tip-Ring differential voltage. 6. ISC = Loop short circuit current limit. 7. ILTH = Loop current limit threshold. ILTH should be programmed to 15 mA or less when in the Standby state. 8. 4 These are nominal values for DC feed curve. See the "Device Specifications" table for tolerance values. Le77D11 VoiceChipTM Family 770 Series SLIC Data Sheet Figure 4. DC Feed Block Diagram, Active and Standby Modes VCC ILOOP CS1 K DC VDC SLAC LPF i RDC * A i (TIP) Current Mirrors RS RDC i ILTH CLPFi * IA K DC ILOOP Level Shift NPRFILT i Sum/ Sense/ Fault RL Polarity Control CNPRi * IB RS ILOOP IMT i B i (RING) K DC Fi Note: * denotes external components Ringing Ringing is accomplished by placing the Le77D11 SLIC device into the Ringing state via the Le78D11 codec/filter's MPI interface. Placing the Le77D11 SLIC device into the ringing state automatically enables signal generator A in the Le78D11 codec/filter which puts the ringing signal on the receive signal path (pin VIN). (For information on programming the Le78D11 codec/filter's signal generators, please refer to the Le77D11 /Le78D11 Chip Set User's Guide, document ID# 080716). When the Le77D11 SLIC device is in the ringing state, the gain from the input pin, VIN, to the output is KR, the ringing voltage gain. The output waveform is a quasi-balanced waveform, as shown in Figure 5. On the positive half cycle of the input waveform, when (VIN - VREF) is positive, VAB is positive with VA(TIP) near -4 V and VB(RING) brought negative. When (VIN - VREF) is negative, VB(RING) is held near -4 V and VA(TIP) is brought more negative. The waveform can be either sinusoidal or trapezoidal under the control of the Le78D11 codec/filter. To provide 90-V ringing capability, the application of a PNP bipolar switching transistor is used. For the reference schematic, Zetex part FZT955 in a SOT-223 package is used. Its VCEO rating is 140 V. Due to the switching efficiency and overhead voltage, one can achieve 90 Vpk sinusoidal ringing with a 5 REN load with VSW = 12 V. See Figure 6, on page 7 for external filters recommended for a 90-V peak ringing application. Figure 5. Ringing Waveforms VREF + V PK VREF VREF - V PK A. Voltage Applied to VIN Pin -4 V -(K R * V PK + 4) B. Voltage Output at A (Tip) (dashed line) and B (Ring) (solid line) Pins Le77D11 VoiceChipTM Family 770 Series SLIC Data Sheet 5 Switcher Controller The switcher controller's main function is to provide a negative power supply (VREG) that tracks Tip and Ring voltage for the twowire interface. As Tip and Ring voltage decreases, the switcher will likewise lower VREG. In doing so, the switcher saves power because the device is not forced to maintain static supply voltage in all states. The switching power supply controller uses a discontinuous mode buck-boost voltage converter topology. The frequency of operation is programmed by the Le78D11 codec/filter and is typically 85.3 kHz (256 kHz/3). The Le78D11 codec/filter outputs a clock at its programmed frequency with approximately a 10% duty cycle which is fed into the CHCLK pin of the Le77D11 SLIC device. This clock signal controls the switching supply's operating frequency as well as the switching supply's maximum duty cycle. The Le77D11 SLIC device adjusts the actual duty cycle up to the maximum of 90% depending on the magnitude of the error voltage on the compensation (CHS) pin. The error signal is generated by integrating the difference in control current which is set by the Le77D11 SLIC device, and the feedback current. This error signal will converge to a value which in turn sets the duty cycle of the switching supply to satisfy feedback loop requirements. A control current (See Figure 6, on page 7) is generated on the Le77D11 SLIC device and is set to force VREG to track Tip and Ring line conditions to optimize system power efficiency. In equilibrium, the control current, which is fed into the CHS summing node, is set to provide the required line voltage plus an offset to give headroom for the power amplifiers. The error signal on CHS is compared to an internal ramp signal. The ramp rate of this internal ramp signal is set by a resistor, RRAMP, to analog ground (AGND) on the FSET pin. A 1% resistor should be chosen to give the ramp precise control, and prevent internal nodes from going into saturation. RRAMP is determined by the equation: RRAMP = (24 * 109 -Hz)/(CHCLK Frequency). When the CHCLK signal goes from a logic high to a logic low, it will initiate a cycle by resetting the ramp, resetting a current limit latch, and turning on the external power switch. Then, on a cycle-by-cycle basis, one of three events will shut off the power switch depending on which event occurs first: a) The ramp voltage exceeds the error voltage that is integrated on the CHS node (normal voltage feedback operation). b) The CHCLK goes high (90% duty cycle point is reached). c) The power switch current limit threshold is reached. Cycle-by-cycle current limiting is provided by the current sense ILS pin which senses the external power switch current through the resistor RLIM. If this pin exceeds -0.28 V with respect to VSW, the switching supply will set the current limit latch and shut off the external switch drive until the CHCLK pin goes high to reset the latch. This peak inductor current, and also peak switching converter power output can be controlled on a cycle-by-cycle basis and set by the equation ILIM = |0.28 V|/RLIM. This sensing configuration has the added benefit that if the clock signal is removed for some reason, the power switch cannot be left on indefinitely. A leading edge blanking filter is added at the output of the latch to ignore the first 150 ns of a current limit event. This feature is used to ignore a false current trip that may be caused by the power switch driving the reverse recovery charge (QRR) of the external power rectifier. This circuit has been optimized for operation to supply 20-Hz ringing of 90-V peak with a nominal supply voltage, VSW, of 12 V. The on chip driver is designed to drive an external PNP transistor. Its output drive is clamped between 7-9 V below VSW, and can source or sink approximately 100 mA. The driver has approximately 50 of source resistance. When a PNP transistor is used, additional resistance should be added from the SDi pin to the base of the external power device. For this application, RBD is 180 and capacitor CBD is 27 nF to increase the switching speed and efficiency. This increases the power available during the Ringing state when the converter operates at the highest currents. The capacitors CFL and CVREG use very low ESR film capacitors to minimize ripple and noise on VREG. The capacitance is sized to permit more rapid charging of the capacitors, and hence a faster slew rate. Reduction of switcher noise is accomplished by using lower ESR capacitors and increasing the value of the LVREG inductor in the post filter. The power supply output is able to track the ringing waveform under these conditions. 6 Le77D11 VoiceChipTM Family 770 Series SLIC Data Sheet Figure 6. Switching Power Supply Block Diagram VSW Inside Le77D11 SLIC Device VSW - CSW CSWi * + BGND LATCH I= 48 V 800 K 8V 800 K + LEADING EDGE BLANKING FILTER VCC 0.28 V - RLIMi * + OUTPUT In Active SET - ILSi RESET 100 Vin In Ringing 800 K VREF in Active 15 V I= 800 K CBDi* 1.4 V CLAMP in Ringing DD2* VSW DRIVER - SDi RBDi * QSWi * + CHS i COMPARATOR DSWi * TRIANGLE WAVE CHSi * CFLi * LSWi * FSET RRAMP * BGND BGND CHCLK 800 k 10% High Duty Cycle 85.3 kHz or 256 kHz Selectable via the Le78D11 device LVREGi* VREG i CVREGi* CVREGi* BGND CESRi* BGND Note: * denotes external components Signal Transmission In Normal Active and Reverse Polarity states, the AC line current is sensed across the internal resistors, RS (see Figure 7, on page 8), summed, attenuated and converted to voltage at the CFILT pin. This voltage then goes through a high pass filter (with a nominal 13 Hz corner frequency), implemented using an on-chip 8 k nominal resistor and an external CHP capacitor, is amplified, and sent to the Le78D11 codec/filter at the VOUT pin. The output is proportional to the AC metallic component of the line voltage. Additionally, the signal transmission block receives the analog signal from the Le78D11 codec/filter. The analog signal is amplified and sent to the line.A proportion of the signal at VOUT is also fed back to the line. There are three parameters which define the AC characteristics of the Le77D11 SLIC device. First is the input impedance presented to the line or two-wire side (Z2WIN), second is the gain from the four-wire (VIN) to the two-wire (VAB) side (G42), and third is the gain from the two-wire side to the four-wire (VOUT) side (G24). Input Impedance (Z2WIN) Z2WIN is the impedance presented to the line at the two-wire side, and is defined by: Z 2WIN = 2R F + K V K OUT R IMT where 2 * RF is the total resistance of the external fuse resistors in the circuit, RIMT is the impedance setting resistor, KOUT is the gain from VOUT to VAB, and KV is the voice current gain defined in the Transmission Specifications Table. Note that the equation reveals that Z2WIN is a function of the selectable resistors, RIMT and RF. For example, if RF = 0 and RIMT is 100 k, the terminating impedance is 600 . This is the configuration used in this data sheet for defining the device specifications. However, in a real application, RF = 50 is recommended, producing a total input impedance of 700 which is a good starting point for meeting worldwide requirements using the programmable filters of the Le78D11 codec/filter. Le77D11 VoiceChipTM Family 770 Series SLIC Data Sheet 7 Two-Wire to Four-Wire Gain (G24) The two-wire to four-wire gain is the gain from the phone line to the VOUT output of the Le77D11 SLIC device. To solve for G24, the VIN pin is grounded (see Figure 7). V OUT 1 -------------- = G 24 = ----------------------------------------2R F V AB -------------------- + K OUT KV R IMT or 2R F G 24 = - 20 log K OUT + ------------------ K V R IMT in dB Using the values of RIMT and RF from the application example, G24 for this circuit is -10.9 dB. Four-Wire to Two-Wire Gain (G42) G42 is the gain from the VIN input to the line. This gain is defined as VAB/VIN. RL K IN ------------------------ R L + 2R F V AB ---------- = G 42 = --------------------------------------------------VIN OUT R IMT K V 1 + K --------------------------------- R + 2R L F or G 42 RL - K IN ---------------------- R + L 2R F = - 20 log --------------------------------------------------- R K K OUT IMT V 1 + ---------------------------------- R L + 2R F in dB where KIN is the gain from VIN to VAB. Using the values of RIMT and RF from the application example and RL = 600 , G42 for this circuit is 7.3 dB. Note: Equation derivations can be found in the Legerity Le77D11/Le78D11 Chip Set User's Guide (document ID# 080716). Figure 7. R F* Ai Transmission Block Diagram RS CFILTi VHPi IL Kv C HPi* R IMTi * RS R F* Bi Note: * denotes external components 8 Le77D11 VoiceChipTM Family 770 Series SLIC Data Sheet K in R L* K out Sense VAB VINi VOUTi Fault Detection Each channel of the Le77D11 device has a fault detection pin, F1 or F2. These pins are driven low when a longitudinal current fault or foreign voltage fault occurs (see Figure 4, on page 5). When not in Disconnect state, there are three conditions that will cause the Fi pin to indicate a fault condition: * |IA - IB| > ILONG * In Normal Active and Standby state, a foreign voltage fault occurs in which VA is above ground or VB is close to VREG. * In Reverse Polarity state, a foreign voltage fault occurs in which VB is above ground or VA is close to VREG. In the Disconnect state, fault detection is not supported; however, fault conditions can be monitored by the Le78D11 device. For more details on AC, DC fault detection, loss of power, or clock-failure alarm, please refer to the Legerity Le77D11/Le78D11 Chip Set User's Guide (document ID# 080716). Signal Conditioning The RDCi pin is used to set the DC feed current limit, as described in the DC feed section. The IMTi pin provides KDC times the loop current to the Le78D11 codec/filter. The Le78D11 codec/filter implements all loop supervision and ring trip processing on this signal. IA + IB I IMT = ---------------- * K DC 2 Thermal Overload When the die temperature around the power amplifier of an Le77D11 device channel reaches approximately 160C, the IMT pin of that channel is pulled High. At the same time, all the blocks controlling that channel of the device are shut off, except for the logic interface block. The SLIC channel goes into a state similar to Disconnect, making the line current zero. When the temperature drops below 145C, the SLIC channel returns to its previous state. It is important to recognize that even while a channel experiences thermal overload, the state of the device can be modified. At TSD, the switcher is turned off. Control Logic Each channel of the Le77D11 SLIC device has three input pins from the Le78D11 codec/filter (C3, C2, and C1). The inputs set the operational state of each channel. There are six operational SLIC device states (See Table 1): Low Power Standby, Disconnect, Normal Active, Reverse Polarity, Ringing and Line Test. This leaves two reserved logic states. Table 1. C3 C2 C1 Device Operating States Operating Mode Description 0 0 0 Low Power Standby Voice transmission disabled. Maximum loop current capability and loop current sensing range are reduced. 0 0 1 Disconnect Le77D11 device channel is shut down and switching power supply is shut off.* 0 1 0 Normal Active Le77D11 device channel fully operational. Ai (TIP) is more positive than Bi (RING). Also used for on-hook transmission. 0 1 1 Reverse Polarity Similar to normal active, but DC polarity is reversed so that the Bi (RING) lead is more positive than the Ai (TIP) lead. Also used for on-hook transmission. 1 0 0 Ringing Ringing state with VAB set to KR * VIN. The switching supply maintains minimum headroom for the sourcing and sinking amplifiers in order to maximize power efficiency. 1 0 1 Line Test State Similar to ringing state with reduced bias currents for lower noise. Loop current sensing range is limited. See IMT pin specifications. 1 1 0 Reserved Not used. 1 1 1 Reserved Not used. Note: * When in Disconnect state, the DC-DC converter is disabled and the VREG voltage will decay to 0 V. The Ai and Bi outputs are disabled; however, they still have ESD protection diodes to BGND and VREG which will provide a low impedance clamp to any line voltages > 0.5 V. Le77D11 VoiceChipTM Family 770 Series SLIC Data Sheet 9 VREG 2 B 2 (RING) A 2 (TIP) NPRFILT 2 C1 2 C2 2 C3 2 VIN 2 F2 VOUT 2 VHP 2 CONNECTION DIAGRAM 44 43 42 41 40 39 38 37 36 35 34 CFILT 2 1 33 BGND 2 IMT 2 2 32 CHS 2 LPF 2 3 31 ILS 2 RDC 2 4 30 SD 2 VREF 5 29 CHCLK VCC 6 28 VSW AGND 7 27 SD 1 FSET 8 26 ILS 1 RDC 1 9 25 CHS 1 LPF 1 10 24 BGND 1 IMT 1 11 23 VREG 1 44-pin eTQFP Exposed Pad B 1 (RING) A 1 (TIP) C1 1 NPRFILT 1 C2 1 F1 C3 1 VIN 1 VOUT 1 VHP 1 CFILT 1 12 13 14 15 16 17 18 19 20 21 22 Note: 1. 10 Pin 1 is marked for orientation. Le77D11 VoiceChipTM Family 770 Series SLIC Data Sheet PIN DESCRIPTIONS Pin Name Type Description AGND Ground Analog and digital ground return for VCC circuitry (common to both channels). A1,2 (Tip) Output A (Tip) lead power amplifier outputs for channels 1 and 2. BGND1,2 Ground Supply ground return for power amplifiers on channel 1 and 2. B1,2 (Ring) Output C11, C21, C31 C12, C22, C32 B (Ring) lead power amplifier outputs for channels 1 and 2. Input Logic control inputs to control channel 1 state. Input Logic control inputs to control channel 2 state. CFILT1,2 Output CHCLK Input Switching power supply clock input that sets the frequency and maximum duty cycle of the switcher (common to both channels). CHS1,2 Input Compensation nodes for switching power supply channels 1 and 2. Output Fault detect pins for channels 1 and 2. A low indicates a fault for the respective channel, which can be triggered by large longitudinal current, or ground key. F1,2 AC coupling pins for 4-wire (VOUT) amplifiers of channels 1 and 2. FSET Input Ramp rate control pin for 85.3 kHz operation. IMT1,2 Output ILS1,2 Input LPF1,2 Output A capacitor tied from these pins to AGND stabilizes the DC feed loop, and lowers Idle Channel Noise for channels 1 and 2. NPRFILT1,2 Output An optional capacitor tied from these pins to AGND controls the reverse polarity slew rate of channels 1 and 2. Current output equal to the loop current divided by 500. During thermal overload, IMT is forced High. Voltage sense pins to limit peak current in external switching power supply transistors (channels 1 and 2). Input Resistor connection to programmable VDCi pin of Le78D11 codec/ filter to set DC feed current limit threshold (ILTH) of each channel. SD1,2 Output Base (gate) drive for switching power supply transistor (channels 1 and 2). VCC Supply A nominal 3.3 V power supply for internal VCC circuitry (common to both channels). VHP1,2 Output High pass inverting summing nodes of the VOUT amplifiers driven by the AC current coming from CFILT1 and CFILT2. VOUT1,2 Output Analog (4-wire side) VOUT amplifier output. RDC1,2 VIN1,2 Input Analog (4-wire side) voice or ringing signal inputs. These pins multiplex between 4-wire voice input and ringing input depending on the programmed state of the Le77D11 SLIC device channel. VREF Supply A nominal 1.4 V reference supplied by the Le78D11 codec/filter for internal use (common to both channels). VREG1,2 Supply Negative regulated power supplies generated by the Le77D11 SLIC device Switching Regulators. (Channels 1 and 2). VSW Supply A positive supply used to generate the negative supplies of VREG1, VREG2 (common to both channels). Exposed Pad Isolated Exposed pad on underside of device must be connected to a heat spreading area. The AGND plane is recommended. Le77D11 VoiceChipTM Family 770 Series SLIC Data Sheet 11 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings can cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods can affect device reliability. Storage temperature Ambient temperature, under bias VCC with respect to AGND -55 to +150C -40 to 85C -0.4 to +6.5 V VREG with respect to BGND +0.4 to -115 V -100 to 100 mV BGND with respect to AGND A (Tip) or B (Ring) to BGND: Continuous VREG -1 to BGND +1 10 ms (F = 0.1 Hz) VREG -5 to BGND +5 1 s (F = 0.1 Hz) VREG -10 to BGND +10 VREG -15 to BGND +15 250 ns (F = 0.1 Hz) Current from A (Tip) or B (Ring) C1, C2, C3 to AGND CHCLK VSW 150 mA -0.4 to VCC + 0.4 V AGND to VCC BGND to +44 V VREF AGND to VCC Maximum power dissipation, TA = 85 C (See notes) 1.8 W Thermal Data: In 44-pin eTQFP package Thermal Data: In 44-pin eTQFP package ESD Immunity (Human Body Model) JA 32 C/W JC 9.2 C/W 1.5 kV minimum Notes: Thermal limiting circuitry on chip will shut down the circuit at a junction temperature of about 165C. Continuous operation above 145C junction temperature may degrade device reliability. The thermal performance of a thermally enhanced package is assured through optimized printed circuit board layout. Specified performance requires that the exposed thermal pad be soldered to an equally sized exposed copper surface, which, in turn, conducts heat through 16 0.3 mm diameter vias on a 1.27 mm pitch to a large (> 500 mm2) internal copper plane. (Refer to Legerity application note Layout Considerations for the Le77D112 and Le9502 Devices, document ID# 081013). OPERATING RANGES Legerity guarantees the performance of this device over commercial (0 to 70C) and industrial (-40 to 85C) temperature ranges by conducting electrical characterization over each range, and by conducting a production test with single insertion coupled to periodic sampling. These characterization and test procedures comply with section 4.6.2 of Bellcore TR-TSY-000357 Component Reliability Assurance Requirements for Telecommunications Equipment. Environmental Ranges Ambient Temperature -40 to 85C Electrical Ranges 12 VCC 3.3 V 5% VSW 8 to 40 V VREF 1.40 V 50 mV VREG -7 to -110 V (0 V in Disconnect state) Le77D11 VoiceChipTM Family 770 Series SLIC Data Sheet ELECTRICAL CHARACTERISTICS Unless otherwise noted, test conditions are: VCC = 3.3 V, VSW = 12.0 V, VREF = 1.4 V. For Active, Reverse Polarity, Line Test and Disconnect, VDC = 0.6 V (ILTH = 15 mA); for Standby, VDC = 0.4 V (ILTH = 10 mA). AGND = BGND, there are no fuse resistors, RL = 600 , -40C < TA < 85C, 85.3 kHz CHCLK. Ringing configuration is VIN = 0.7 Vpk 20-Hz sinusoidal. Line Test configuration is VIN = 0.5 Vdc. Please refer to the test circuit on page 18 for all other component values. Supply Currents and Power Dissipation Operation States Standby Disconnect Condition RL = open VIN =0 V RL = open VIN = 0 V RL = open VIN = 0 V Active RL = 900 VIN = 0 V RL = 300 VIN = 0 V RL = open VIN = 0 V Pol Rev RL = 900 VIN = 0 V RL = 300 VIN = 0 V RL = open Ringing VIN = 0.7 Vac RL = 1400 VIN = 0.7 Vac Line Test RL = open VIN = 0.5 Vdc 3.3 V VCC Supply Current (mA) VREG Supply Current (mA) (Note 4) VREG Supply Power (mW) SLIC Device Power (mW) (Note 5) VSW Pin Current (mA) Note Min Typ Max Min Typ Max Min Typ Max Min Typ Max Typ 2 5 7 0.25 0.9 2.2 15 50 105 20 65 110 2.0 1 1 3 5 -- 0.1 -- 0 0.5 3 5 10 15 0.1 1 3 6 9 1 3 4.2 75 160 245 80 165 250 2.5 1 -- 7 -- -- 26 -- -- 820 -- -- 360 -- 4.6 1, 2 4 7 10 26 33 40 500 730 1000 300 430 565 4.1 1 3 6 9 1 3 4.2 75 160 245 80 165 250 2.5 1, 2 -- 7 -- -- 26 -- -- 833 -- -- 360 -- 4.6 1, 2 10 26 33 40 500 730 1000 300 430 565 4.1 1 -- -- 3 -- -- 152 -- -- 180 -- 2.1 1, 2 4 -- 7 6 4 7 9 33 38 42 2000 2500 2900 600 750 900 5.7 1, 3 2 5 8 1 2 5 90 170 280 90 170 280 2.6 1 Notes: 1. 2. 3. Values shown are for one channel only but are tested with both channels in the same state. Not tested in production. Parameter is guaranteed by characterization or correlation to other tests. Production test forces Vin=0.5 Vdc which is equivalent to Vin=0.7 Vac. 4. V REG * I VREG - , where = efficiency. For our recommended circuit, an efficiency of 0.6 can be assumed under heavy loads. I VSW = ---------------------------------- * V SW 5. SLIC device power is defined as the power delivered through the VCC and VREG pins minus the power delivered to the load. It does not include any power associated with the VSW pin and the external switcher. Le77D11 VoiceChipTM Family 770 Series SLIC Data Sheet 13 SPECIFICATIONS System Specifications The performance targets defined in this section are for a system using the Le78D11/Le77D11 chip set. Specifications for the Le78D11 codec/filter are published separately. Item Condition Output Impedance during internal ringing Ringing mode, Le78D11 codec/ filter generating internal ringing Sinusoidal Ringing THD Ringing mode, RL = 1500 generating internal sinusoidal ringing Min Typ Max Unit Note 2 * RF 4. 2 % 4. mA 4. % 3. +20 % 4. Max Unit Note Signaling Performance Limits Hook switch threshold ITH = 10 mA Hook switch hysteresis All ITH settings Internal Ring-trip Accuracy RTSL = 2.2 W (07h) 7 13 10 -20 Device Specifications Specification Condition Min Typ Line Characteristics VA, Active VB, Reverse Polarity RL = open -4 VA Standby, RL = open -1 VAB Active or Reverse Polarity, RL = open 45 48 51 VAB open Standby, RL = open 45 48 51 VREG Active or Reverse Polarity, RL = open -54 -58 -62 VREG Standby, RL = open -49.5 -53 -56.5 Current limit threshold ILTH accuracy Active or Reverse Polarity 13 15 17 Standby 8 10 12 Active or Reverse Polarity, RL = 600 ; ILTH = 15 mA ILTH + 7 ILTH + 11.3 ILTH + 20 Standby RL = 600 ; ILTH = 10 mA ILTH + 7 ILTH + 11.5 ILTH + 20 Active or Reverse Polarity, RL = 100 ; ILTH = 15 mA ILTH + 10 ILTH + 13.5 ILTH + 25 Standby RL = 100 ; ILTH = 10 mA ILTH + 10 ILTH + 13.7 ILTH + 25 Loop Current, IL accuracy Short circuit loop current, ISC LPFi 4. mA 25 k Bias voltage with respect to GND 2.4 V |INPR| 20 50 1. 1. Output impedance Leakage current for capacitor value of 4.7 F 20% NPRFILTi drive capability V 0.1 A 100 A 3. Ringing and Line Test State VA, VB VIN = 0 V, with respect to VREF, RL = 1400 VAB offset VIN = 0 V, with respect to VREF, RL = 1400 Voltage gain, KR V AB RL open, K R = --------V IN Ringing distortion RL = 1400 , VIN = 0.9 Vpk Ringing current limit RL = 100 -4 -2 95 V +2 V 100 105 V/V 0.5 3.5 % 135 180 mApk 3. 1. RL = 1400 , VIN = 0.9 Vpk 14 90 Le77D11 VoiceChipTM Family 770 Series SLIC Data Sheet 4. Specification Condition Min Typ Max Unit Note Switching Power Supply CHCLK kHz 3. Chopper Clock Duty Cycle 7.5 85.3 10 12.5 % 3. ILSi Offset (current limit sense threshold) 0.25 0.28 0.31 V Input impedance ILSi Bias current -1 Output impedance SDi Slew Rate negative 3 Slew Rate positive 25 VOL where VSW 12 V, RBD = 330 VSW - 0.2 V V VSW - 7.2 V VSW - 6.3 V M Line test and Ringing 180 Standby and Active 75 Disconnect 1 Input impedance, tied to VREF A 10 -5 3. VSW - 5.4 V 1 Offset voltage with respect to VREF A V/sec VSW - 0.3 V Input impedance FSET +1 50 VOH where VSW 12 V, RBD = 330 CHSi 7000 +5 mV Power Supply Rejection Ratio at the Two-wire interface VCC to VAB 200 to 4000 Hz 25 45 4 to 20 kHz, 50 mVRMS 25 30 200 to 4000 Hz, 100 mVRMS 25 45 4 to 50 kHz 20 40 4. 50 to 100 kHz 15 30 4. Longitudinal balance RL = 600 , 300 to 3400 Hz, 0 dBm, Active and Reverse Polarity 46 63 T-L balance 1 kHz, 0 dBm 40 50 Longitudinal current per pin A(TIP) or B(RING) 30 Longitudinal impedance A(TIP) or B(RING), 0 to 100 Hz Longitudinal current detect, ILONG Fi Low, RL from B(RING) to GND, Standby, Active, or Reverse Polarity 18 2WRL 300 to 3400 Hz, for 600 26 KDC DC current gain (IMT accuracy) I IMT K DC = -------------- , RL = 600 , I LOOP VREG to VAB dB Longitudinal Capability dB mA 4. 1 5 /pin 4. 27 35 mA Transmission Performance KV Voice Current gain Active, Standby, Reverse Polarity Line Test:, Standby Active or Rev. Pol. Ringing IL < |40 mA| IL < |55 mA| IL < |90 mA| dB 4. 1 - --------525 1 - --------500 1 - --------475 A/A 6. 1 ---------520 1 ---------500 1 ---------480 A/A 4. Le77D11 VoiceChipTM Family 770 Series SLIC Data Sheet 15 Specification Condition VIN to VAB (KIN) RL = open, 0dBm, two-wire VOUT to VAB (KOUT) Min Typ Max 13.7 14 14.3 9.34 9.54 9.74 Unit Note 4. Gain accuracy 4- to 2-Wire 0 dBm, 1 kHz 7.76 7.96 8.16 Gain accuracy 2- to 4-Wire 0 dBm, 1 kHz -9.74 -9.54 -9.34 Gain accuracy 4- to 4-Wire 0 dBm, 1 kHz -1.78 -1.58 -1.38 Gain accuracy over frequency 300 to 3400 Hz, Relative to 1 kHz -0.1 +0.1 Gain tracking at 1kHz, relative to 0 dBm -30 to +3 dBm, 2-Wire -0.1 +0.1 -55 to -30 dBm, 2-Wire -0.1 +0.1 4. Gain tracking, On Hook, relative to 0 dBm 0 to -30 dBm, 2-wire -0.15 +0.15 4., 7. +3 to 0 dBm, 2-wire -0.35 +0.35 4., 7. THD (Total Harmonic Distortion) 0 dBm, 2-wire, 1 kHz -64 -50 +7 dBm, 2-wire, 1 kHz -55 -40 THD, On Hook 0 dBm, 2-wire, 1kHz Overload Level, 2-Wire Active or Reverse Polarity, 1kHz dB -36 2.5 7. Vpk 2. 4. Idle Channel Noise C-message 12 15 dBrnC Idle Channel Noise Psophometric -78 -75 dBmP +150 A Output impedance CFILTi Drive capability, Active State Input impedance VHPi VINi VREF Offset voltage with respect to VREF -20 Offset voltage with respect to VREF -40 mV +40 mV 1 3. A 3. k 3. Input impedance 200 Offset voltage voice -20 +20 Ringing and Line Test -20 +20 0 +200 A 4.44 4.64 dB -55 -40 dB -80 -75 dB RL = 300 , 16.0 kHz 4.24 Frequency = 12 kHz Frequency = 16 kHz +50 3., 5. -50 Bias current Metering distortion, RL = 300 , VAB = 1.5 Vpk +20 Drive capability, RL = 20 k to VREF RL = 300 , 12.0 kHz Metering gain 5 Output impedance VOUTi 8000 -150 mV 3. 3. 4. 4. Crosstalk Between Channels Crosstalk coupling loss F = 200 Hz to 3.4 kHz Logic Interface Inputs (C1, C2, C3, CHCLK) 8. VIL 0.8 VIH 2.0 IIL VIN = 0.4 V -150 +150 IIH VIN = 2.4 V -100 +100 V A Outputs (F) 16 VOH IOUT = -25 A VOL IOUT = 25 A 2.4 2.8 0.2 Le77D11 VoiceChipTM Family 770 Series SLIC Data Sheet 0.4 V Specification Condition Min Typ Max Unit Note M 3. A 3. V 4. IMT Pin Characteristics Output impedance Offset current, RL = open, -2 +2 Ringing -180 +180 Active and Reverse Polarity -110 +110 Standby and Line Test VIMT = VREF IMTi 1 Output Range -80 +80 Line Test |IMT| current limit VIN = 0.7V, RL = 100 with respect to VREF 80 120 VIMT Thermal Shutdown IIMT = 1mA 2.8 Notes: 1. VAB = Voltage between the Ai (Tip) and Bi (Ring) pins. 2. Overload level is defined when THD = 1%. 3. Guaranteed by design. 4. Not tested in production. Parameter is guaranteed by characterization or correlation to other tests. 5. Layout should have less than 10 pF from pin to ground. 6. IIMT = current coming out from IMT pin. 7. When On Hook, RLDC is open circuit, RLAC = 600 . 8. C3 and C2 have pull-downs and C1 has pull-up to set the device state to Disconnect when the pins are floating. Le77D11 VoiceChipTM Family 770 Series SLIC Data Sheet 17 TEST CIRCUIT Per Channel VCC 100 nF 16 V + VCC* ILOOP - VINi RL VOUT i RINGi Bi (RING) 100 k VHPi VSW VSW* CSW + 220 F - U1 Le77D11 180 ESC2 100 nF LSWi 47 H 1.5 F Fi CVREGi ILSi *VREF SDi *CHCLK 85.3 kHz STATE SELECTION C2i VREGi CHSi BGNDi C3i NPRFILT i 4148-SOT VSW * Note: * denotes pins that are common to both channels. i = per channel component. 18 1 F C1i AGND* 1 2 4.7 k IMTi 1 nF To base of QSW on other channel VDC 20 k RDCi BAV99TA FZT955 2.0 F 300 V CFILT i 0.1 27 nF 150 H VREF 280 k FSET* 2.0 F 300 V VIN LPFi Ai (TIP) TIPi 0.1 F Place close to VSW pin VREF 4.7 F Le77D11 VoiceChipTM Family 770 Series SLIC Data Sheet 100 nF 16 V SINGLE CHANNEL APPLICATION CIRCUIT RSA1i RSA2i RSB1i RSB2i 3.3 V 3.3 V PTC1i TIPi RINGi 1 K1 K1 2 G A 3 NC 4 K2 U3 A K2 CLPFi C4 8 + VINi Ai (TIP) 6 Bi (RING) RLIMi CSW1 CSW CVREG1 CESRi CFILTi VSW* Fi + Place close to VSW pin CBDi DSWi CFL1 CFL2 U1 Le77D11 DD2 - LVREGi FSET* QSWi LSWi RBDi CVREGi RDCi DGND1 ILSi *VREF SDi *CHCLK VREGi CHSi AGND* CHSi BGNDi Fi VDCi 1 2 TSCA DRA DXA FS PCLK U2 Le78D11 IMTi VREF CHCLK C1i C1i C2i C2i C3i C3i NPRFILTi CNPRi (optional) VSi IREF MCLK DCLK CSL DIN DOUT INT RS PCM Interface MPI Interface RREF DD1 To base of QSW on other channel C3 DGND2 CHPi IMTi 3.3 V VCCD ROUTi RDCi C2 AGND2 VHPi RRAMP VSW VINi RIMTi PTC2i 3.3 V VCCA2 VOUTi VOUTi 5 C1 AGND1 VBi LPFi VCC* 7 VCCA1 VAi - VSW * RVSi Note: * Denotes pins that are common to both channels. i = per channel component. Protection is voltage tracking device. CESRi is located close to gate on U3. Le77D11 VoiceChipTM Family 770 Series SLIC Data Sheet 19 APPLICATION CIRCUIT PARTS LIST The following list defines the parts and part values required to meet target specification limits for 90 Vpk ringing with VSW = 12 V and CHCLK = 85.3 kHz for channel i of the line card (i = 1, 2). The protection circuit is not included. Item Quantity (see note 1) Type Value Tol. Rating Comments CHSi 2 Capacitor 1 nF 10% 50 V Panasonic / ECJ-1VB1H102K, 0603 CBDi 2 Capacitor 27 nF 10% 16 V Kemet C0603C273K5RAC C1, C2, C3, C4 4 Capacitor 100 nF 10% 16 V Panasonic / ECJ-1VF1C104Z, 0603 CESRi 2 Capacitor 0.1uF 10% 200 V CalChip GMC31X7R104K200NT CNPRi 2 Capacitor 100 nF 10% 16 V Panasonic / ECJ-1VB1C104K (optional) CVREGi 2 Capacitor 100 nF 10% 200 V CalChip GMC31X7R104K200NT CHPi 2 Capacitor 1.5 F 10% 6.3 V Panasonic / ECJ-2YB0J155K,0805 CLPFi 2 Capacitor 4.7 F Tantalum 20% 6.3 V Panasonic ECS-TOJY475R CFL1, CFL2 CVREG1 6 Capacitor 1.0 F, ESR < 40 m 10% 200 V Tecate CMC-300/105KX1825T060 CSW 1 Capacitor 220 F Alum. Elect. 20% 25 V Nichicon / UPW1E221MPH CSW1 1 Capacitor 100 nF 10% 50 V DIGI-KEY / PCC1840CT-ND,0805 DSWi 2 Diode ES2C 2A General Semi. / ES2C DD1 1 Diode 4148-SOT 600 mA Fairchild / MMBD4148CC DD2, DD3 2 Diode BAV99TA 250 mA Zetex / BAV99TA (DIGI-KEY # BAV99ZXTR-ND) LSWi 2 Inductor 47 H 2.95 A Cooper Coiltronics / DR127-470 LVREGi 2 Inductor 150 H 205 mA Coilcraft 1812LS154X_B PTC1i, PTC2i 4 PTC 50 250 V AsiaCom / MZ2L-50R QSWi 2 PNP Transistor FZT955 140 V Zetex / FZT955 RLIMi 2 Resistor 0.1 , 5% 1/4 W Panasonic ERJ-14RSJR10U / DIGI-KEY P10SCT-ND RBDi 2 Resistor 180 1% 1/4 W Panasonic ERJ-6ENF1820V RDCi 2 Resistor 20 K 1% 1/16 W Panasonic / ERJ-3EKF2002V RREF 1 Resistor 69.8 K 1% 1/16 W Panasonic / ERJ-3EKF6982V RIMTi 2 Resistor 100 K 1% 1/16 W Panasonic / ERJ-3EKF1003V RRAMP 1 Resistor 280 K 1% 1/16 W Panasonic / ERJ-3EKF2803V RVSi 2 Resistor 475 K 1% 1/16 W Panasonic / ERJ-3EKF4753V RSA1i, RSB1i, RSA2i, RSB2i 8 Resistor 237 k 1% 1/8 W Panasonic / ERJ-8ENF2373V ROUTi 2 Resistor 10 k 1% 1/16 W Panasonic / ERJ-3KF1002V U3i 2 Protector Bourns / TISP61089BDR Note: 1. 20 Quantities required for a complete two-channel solution. Le77D11 VoiceChipTM Family 770 Series SLIC Data Sheet Note PHYSICAL DIMENSIONS 44-Pin eTQFP Le77D11 VoiceChipTM Family 770 Series SLIC Data Sheet 21 REVISION HISTORY Revision B1 to C1 * In Pin Descriptions, FSET pin, removed reference to 256 kHz operation * In Absolute Maximum Ratings, the following changes were made: - Changed TA from 22.7 to 32C/W - Changed maximum power dissipation from 2.6 to 1.8 W - Added another note describing eTQFP package * In Supply Currents and Power Dissipation, Ringing operation state, removed condition VIN = 0.7 VDC * In System Specifications, first paragraph, removed TA = 0 to 70C * Updated Physical Dimensions drawing Revision C1 to D1 * Made updates pertaining to 90 Vpk throughout document Revision D1 to E1 * In Device Specificaions, ILSi Offset, changed min from .27 to .25 and max from .29 to .31 * Made updates to Application Circuit Parts List, including: - Increased voltage ratings on capacitors CESRi, CVREGi, CFLi and CVREG1 - Changed value of CFLi and CVREG1 to 1 F Revision E1 to F1 * 22 Modified application circuit and BOM to reflect addition of the TISP61089BDR protector Le77D11 VoiceChipTM Family 770 Series SLIC Data Sheet The contents of this document are provided in connection with Legerity, Inc. products. Legerity makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in Legerity's Standard Terms and Conditions of Sale, Legerity assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. Legerity's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of Legerity's product could create a situation where personal injury, death, or severe property or environmental damage may occur. Legerity reserves the right to discontinue or make changes to its products at any time without notice. (c) 2003 Legerity, Inc. All rights reserved. Trademarks Legerity, the Legerity logo and combinations thereof, VoiceChip, and SLAC are trademarks of Legerity, Inc. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 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