HFA3524 TM Data Sheet March 2000 File Number 2.5GHz/600MHz Dual Frequency Synthesizer Features The Intersil 2.4GHz PRISM(R) chip set is a highly integrated six-chip solution for RF modems employing Direct Sequence Spread Spectrum (DSSS) signaling. The HFA3524 600MHz Dual Frequency Synthesizer is one of the six chips in the PRISM chip set (see the Typical Application Diagram). * Low Current Consumption The HFA3524 is a monolithic, integrated dual frequency synthesizer, including prescaler, is to be used as a local oscillator for RF and first IF of a dual conversion transceiver. * Systems Targeting IEEE 802.11 Standard The HFA3524 contains a dual modulus prescaler. A 32/33 or 64/65 prescaler can be selected for the RF synthesizer and a 8/9 or a 16/17 prescaler can be selected for the IF synthesizer. Using a digital phase locked loop technique, the HFA3524 can generate a very stable, low noise signal for the RF and IF local oscillator. Serial data is transferred into the HFA3524 via a three wire interface (Data, Enable, Clock). Supply voltage can range from 2.7V to 5.5V. The HFA3524 features very low current consumption of 13mA at 3V. * TDMA Packet Protocol Radios 4062.8 * 2.7V to 5.5V Operation * Selectable Powerdown Mode ICC = 1A Typical at 3V * Dual Modulus Prescaler, 32/33 or 64/65 * Selectable Charge Pump High Z State Mode Applications * PCMCIA Wireless Transceiver * Wireless Local Area Network Modems * Part 15 Compliant Radio Links * Portable Battery Powered Equipment Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE HFA3524IA -40 to 85 20 Ld TSSOP HFA3524IA96 -40 to 85 Tape and Reel PKG. NO. M20.173 Functional Block Diagram fIN IF IF PRESCALER 15-BIT IF N COUNTER PHASE COMP CHARGE PUMP DO IF IF LD f OUT 15-BIT IF R COUNTER OSCIN LOCK DETECT FASTLOCK MUX OSC 15-BIT RF R COUNTER RF LD CHARGE PUMP fIN RF RF PRESCALER 18-BIT RF N COUNTER CLOCK DATA LE FO/LD DO RF PHASE COMP 22-BIT DATA REGISTER 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright (c) Intersil Corporation 2000 PRISM(R) is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation. HFA3524 Typical Application Diagram HSP3824 HFA3724 (FILE# 4064) TUNE/SELECT HFA3424 (NOTE) RXI (FILE# 4131) A/D DESPREAD RXQ I /2 (FILE# 4066) 0o/90o M M U U X X RSSI A/D A/D CCA TXI SPREAD RFPA VCO HFA3925 VCO 802.11 MAC-PHY INTERFACE CTRL HFA3624 UP/DOWN CONVERTER DPSK DEMOD TXQ Q DATA TO MAC (FILE# 4067) DPSK MOD. (FILE# 4132) QUAD IF MODULATOR DSSS BASEBAND PROCESSOR DUAL SYNTHESIZER PRISM CHIP SET FILE #4063 HFA3524 (FILE# 4062) NOTE: Required for systems targeting 802.11 specifications. TYPICAL TRANSCEIVER APPLICATION CIRCUIT USING THE HFA352 For additional information on the PRISM chip set, see us on the web http://www.intersil.com/prism or call (321) 724-7800 to access Intersil' AnswerFAX system. When prompted, key in the four-digit document number (File #) of the datasheets you wish to receive. 2 The four-digit file numbers are shown in Typical Application Diagram, and correspond to the appropriate circuit. HFA3524 Pinout HFA3524 (TSSOP) TOP VIEW VCC1 1 VP1 2 19 VP2 DO RF 3 18 DO IF GND 4 17 GND 20 VCC2 fIN RF 5 16 fIN IF f IN RF 6 15 f IN IF GND 7 14 GND OSCIN 8 13 LE GND 9 12 DATA FO/LD 10 11 CLOCK Pin Descriptions PIN NUMBER PIN NAME I/O DESCRIPTION 1 VCC1 - Power supply voltage input. Input may range from 2.7V to 5.5V. VCC1 must equal VCC2. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. 2 VP1 - Power Supply for RF charge pump. Must be > VCC. 3 DO RF O Internal charge pump output. For connection to a loop filter for driving the input of an external VCO. 4 GND - Ground. 5 fIN RF I RF prescaler input. Small signal input from the VCO. 6 f IN RF l RF prescaler complimentary input. A bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. Capacitor is optional with some loss of sensitivity. 7 GND - Ground. 8 OSCIN I Oscillator input. The input has a VCC/2 input threshold and can be driven from an external CMOS or TTL logic gate. 9 GND - Ground. 10 FO/LD O Multiplexed output of the RF/lF programmable or reference dividers, RF/lF lock detect signals and Fastlock mode. CMOS output (see Programmable Modes). 11 Clock I High impedance CMOS Clock input. Data for the various counters is clocked in on the rising edge, into the 22-bit shift register. 12 Data l Binary serial data input. Data entered MSB first. The last two bits are the control bits. High impedance CMOS input. 13 LE l Load enable CMOS input. When LE goes HIGH, data stored in the shift registers is loaded into one of the 4 appropriate latches (control bit dependent). 14 GND - Ground. 15 f IN IF I IF prescaler complimentary input. A bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. Capacitor is optional with some loss of sensitivity. 16 fIN IF I IF prescaler input. Small signal input from the VCO. 17 GND - Ground. 18 DO IF O IF charge pump output. For connection to a loop filter for driving the input of an external VCO. 19 VP2 - Power Supply for IF charge pump. Must be >VCC. 20 VCC2 - Power supply voltage input Input may range from 2.7V to 5.5V. VCC2 must equal VCC1. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. 3 HFA3524 Block Diagram VCC1 1 1X 4X RF CHARGE PUMP VP1 RF LOCK DETECT 2 PU DO RF 3 PD GND RF PHASE DETECTOR 1X fOUT/ LOCK DETECT/ FASTLOCK MULTIPLEXER FR 1 FP 1 IF LOCK DETECT FR 2 FP 2 IF PHASE DETECTOR 4X 19 18 GND SWALLOW CONTROL 32/33 OR 64/65 RF PRESCALER 1-BIT RF PWDN DO IF PD SWALLOW CONTROL - VP2 PU 17 + VCC2 IF CHARGE PUMP 4 5 fIN RF 6 f IN RF 20 1-BIT P1 LATCH PROGRAMMABLE 18-BIT (RF) N-COUNTER (RF) 18-BIT N-LATCH PROGRAMMABLE 15-BIT (IF) N-COUNTER (IF) 15-BIT N-LATCH 8/9 OR 16/17 IF PRESCALER 1-BIT P2 LATCH 16 + 15 fIN IF f IN IF 1-BIT IF PWDN 14 GND 7 GND 5-BIT MODE LATCH 15-BIT R1 LATCH LATCH DECODE OSCIN 8 PROGRAMMABLE 15-BIT (R1) REFERENCE COUNTER 9 PROGRAMMABLE 15-BIT (R2) REFERENCE COUNTER GND 5-BIT MODE LATCH 20-BIT SHIFT REGISTER 2-BIT CONTROL LATCH 13 LE 12 DATA 11 CLOCK 15-BIT R2 LATCH 10 FOLD NOTES: 1. VCC1 supplies power to the RF prescaler, N-counter and phase detector. VCC2 supplies power to the IF prescaler, N-counter and phase detector, RF and IF R-counters along with the OSCIN buffer and all digital circuitry. VCC1 and VCC2 are separated by a diode and must be run at the same voltage level. 2. VP1 and VP2 can be run independently as long as VP VCC. 4 HFA3524 Absolute Maximum Ratings Thermal Information Thermal Resistance (Typical, Note 3) JA (oC/W) TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Maximum Storage Temperature Range (TS) . . . . . . -55oC to 150oC Maximum Lead Temperature (Soldering 4s) (TL) . . . . . . . . . .260oC (TSSOP - Lead Tips Only) Power Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V VP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V Voltage on Any Pin with GND = 0V (VI) . . . . . . . . . . . -0.3V to +6.5V Operating Conditions Power Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V VP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VCC to +5.5V Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. JA is measured with the component mounted on an evaluation PC board in free air. VCC = 3.0V, VP = 3.0V, -40oC < TA < 85oC, Unless Otherwise Specified Electrical Specifications HFA3524 PARAMETER SYMBOL Power Supply Current TEST CONDITIONS MIN TYP MAX UNITS ICC RF + IF VCC = 2.7V to 5.5V - 13 - mA RF Only VCC = 2.7V to 5.5V - 10 - mA VCC = 3.0V - 1 25 A - 2.5 GHz Powerdown Current ICC-PWDN Operating Frequency fIN RF 0.5 Operating Frequency fIN IF 45 - 600 MHz Oscillator Frequency fOSC 5 - 44 MHz f 10 - - MHz VCC = 3.0V -15 - +4 dBm VCC = 5.0V -10 - +4 dBm -10 - +4 dBm Maximum Phase Detector Frequency RF Input Sensitivity PfIN RF IF Input Sensitivity PfIN IF VCC = 2.7V to 5.5V Oscillator Sensitivity VOSC OSCIN 0.5 - - VP-P High Level Input Voltage VIH (Note) 0.8VCC - - V Low Level Input Voltage VIL (Note) - - 0.2VCC V High Level Input Current IIH VIH = VCC = 5.5V (Note) -1.0 - 1.0 A -1.0 - 1.0 A - - 100 A -100 - - A VCC -0.4 - - V Low Level Input Current IIL VIL = 0V, VCC = 5.5V (Note) Oscillator Input Current IIH VIH = VCC = 5.5V Oscillator Input Current IIL VIL = 0V, VCC = 5.5V High Level Output Voltage VOH IOH = -500A High Level Output Voltage VOH IOH = -1mA - - - V Low Level Output Voltage VOL IOL = 500A - - 0.4 V Low Level Output Voltage VOL IOL = 1mA - - - V Data to Clock Set Up Time tCS See Data Input Timing 50 - - ns Data to Clock Hold Time tCH See Data Input Timing 10 - - ns Clock Pulse Width High tCWH See Data Input Timing 50 - - ns Clock Pulse Width Low tCWL See Data Input Timing 50 - - ns Clock to Load Enable Set Up Time tES See Data Input Timing 50 - - ns Load Enable Pulse Width tEW See Data Input Timing 50 - - ns NOTE: Clock, Data and LE does not include fIN RF, fIN IF and OSCIN. 5 HFA3524 VCC = 3.0V, VP = 3.0V, -40oC < TA < 85oC, Unless Otherwise Specified Charge Pump Specifications HFA3524 PARAMETER SYMBOL Charge Pump Output Current Charge Pump High Z State Current TEST CONDITIONS TYP MAX UNITS IDO-SOURCE VDO = VP/2, ICPO = HIGH (Note 4) - -5.0 - mA IDO-SINK VDO = VP/2, ICPO = HIGH (Note 4) - 5.0 - mA IDO-SOURCE VDO = VP/2, ICPO = LOW (Note 4) - -1.25 - mA IDO-SINK VDO = VP/2, ICPO = LOW (Note 4) - 1.25 - mA -2.5 - 2.5 nA - 3 10 % 0.5V VDO VP - 0.5, T < 25oC - 10 15 % VDO = VP/2, -40oC < T < 85oC - 10 - % IDO-HIGH Z CP Sink vs Source Mismatch (Note 5) MIN IDO-SINK vs IDO- 0.5V VDO VP - 0.5, -40oC < T < 85oC VDO = VP/2, TA = 25oC SOURCE CP Current vs Voltage (Note 6) IDO vs VDO CP Current vs Temperature (Note 7) IDO vs T NOTES: 4. See Programmable Modes for ICPO description. 5. IDO vs VDO = Charge Pump Output Current magnitude variation vs Voltage = [1/2 *{| I1 | - | I3 |}]/[1/2 * {| I1 | + | I3 |}] * 100% and [1/2 * | I4 | - | I6 |]/[1/2 * {| I4 | + | I6 |}] * 100%. 6. IDO-SINK vs IDO-SOURCE = Charge Pump Output Current Sink vs Source Mismatch = [| I2 | - | I5 |]/[1/2 * {| I2 | + | I5 |}] * 100%. CURRENT (mA) 7. IDO vs TA = Charge Pump Output Current magnitude variation vs Temperature = [| I2 at temp | - | I2 at 25oC |]/ | I2 at 25oC | * 100% and [| I5 at temp | - | I5 at 25oC |]/ | I5 at 25oC | * 100%. I3 I2 I1 VOLTAGE OFFSET V I4 I5 I6 V I1 = CP sink current at VDO = VP - V I2 = CP sink current at VDO = VP/2 I3 = CP sink current at VDO = V VP/2 0 V I4 = CP source current at VDO = VP - V VOLTAGE D O I5 = CP source current at VDO = VP/2 I6 = CP source current at VDO = V FIGURE 1. CHARGE PUMP CURRENT SPECIFICATION DEFINITIONS fIN CLOCK PC 0 100pF DATA PARALLEL PORT VP-V VP 13dB ATTN LE FC FOLD RF 50 VCC 0.01F VP SMHU 835.8011.52 SIGNAL GENERATOR OSCIN 12K 51 IN HP5385A FREQUENCY COUNTER 39K 2.2F 100pF 2.7V 100pF 2.2F 5.0V FIGURE 2. RF SENSITIVITY TEST BLOCK DIAGRAM 6 10MHz EXT REF OUT HFA3524 Typical HFA3524 Performance Curves 1500 15 1250 14 ICC (mA) 13 IDO HIGH Z STATE (pA) T = 85oC 12 T = 40oC 11 T = 25oC 10 9 8 1000 T = 90oC 750 500 T = 70oC 250 0 T = 25oC -250 7 2.5 -500 3.0 3.5 4.0 4.5 5.0 5.5 0 1 2 VCC (V) FIGURE 3. ICC vs VCC 6 1.5 VP = 5.5V VP = 5.5V VP = 2.7V DO CURRENT (mA) DO CURRENT (mA) 5 2.0 4 2 0 VP = 2.7V -2 VP = 5.5V -4 1.0 VP = 2.7V 0.5 0 VP = 2.7V -0.5 VP = 5.5V -1.0 -1.5 -2.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 0.5 1.0 1.5 DO VOLTAGE (V) 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 DO VOLTAGE (V) FIGURE 5. CHARGE PUMP CURRENT vs DO VOLTAGE ICP = HIGH FIGURE 6. CHARGE PUMP CURRENT vs DO VOLTAGE ICP = LOW 25 20 SINK 15 SOURCE 10 MISMATCH (%) 20 VARIATION (%) 4 FIGURE 4. IDO HIGH Z STATE vs DO VOLTAGE 6 -6 3 DO VOLTAGE (V) 15 VP = 3.0V VP = 5.0V 10 VP = 3.0V VP = 5.0V 5 0 -5 -10 -15 5 -20 0 0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 VOLTAGE OFFSET (V) 2.5 -25 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 DO VOLTAGE (V) NOTE: See charge pump current specification definitions. FIGURE 7. CHARGE PUMP CURRENT VARIATION 7 FIGURE 8. SINK vs SOURCE MISMATCH vs DO VOLTAGE 5.0 HFA3524 Typical HFA3524 Performance Curves (Continued) VCC = 2.7V TO 5.5V, fIN = 10MHz TO 1000MHz VCC = 2.7V TO 5.5V, fIN = 0.5GHz TO 3GHz 4 1 4 3 3 2 1 2 Marker 1 = 1GHz, Real = 101, Imaginary = -144 Marker 2 = 2GHz, Real = 37, Imaginary = -54 Marker 3 = 3GHz, Real = 22, Imaginary = -2 Marker 4 = 500MHz, Real = 209, Imaginary = -232 Marker 1 = 100MHz, Real = 589, Imaginary = -209 Marker 2 = 200MHz, Real = 440, Imaginary = -286 Marker 3 = 300MHz, Real = 326, Imaginary = -287 Marker 4 = 500MHz, Real = 202, Imaginary = -234 FIGURE 10. IF INPUT IMPEDANCE -10 -15 -15 -20 -20 SENSITIVITY (dBm) -10 -25 VCC = 5.5V -35 VCC = 2.7V -40 -25 -30 -35 VCC = 5.5V -40 -45 VCC = 2.7V -45 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 -50 0 100 200 FREQUENCY (MHz) 300 FIGURE 11. RF SENSITIVITY vs FREQUENCY 0.200 -10 VCC = 5.5V -20 0.063 -30 0.020 VCC = 2.7V 0.006 0.002 -50 -60 0 10 20 30 40 50 FREQUENCY (MHz) FIGURE 13. OSCILLATOR INPUT SENSITIVITY vs FREQUENCY 8 500 FIGURE 12. IF INPUT SENSITIVITY vs FREQUENCY 0 -40 400 FREQUENCY (MHz) SENSITIVITY (VPP) -30 SENSITIVITY (dBm) SENSITIVITY (dBm) FIGURE 9. RF INPUT IMPEDANCE 600 HFA3524 Functional Description CONTROL BITS The simplified block diagram in Figure 14 shows the 22-bit data register, two 15-bit R Counters and the 15-bit and 18-bit N Counters (intermediate latches are not shown). The data stream is clocked (on the rising edge of Clock) into the DATA input, MSB first. The last two bits are the Control Bus. The DATA is transferred into the counters as follows: IF PRESCALER fIN IF C1 C2 0 0 IR R Counter DATA LOCATION 0 1 RF R Counter 1 0 IF N Counter 1 1 RF N Counter PHASE COMP 15-BIT IF N COUNTER CHARGE PUMP DO IF IF LD f OUT 15-BIT IF R COUNTER OSCIN LOCK DETECT FASTLOCK MUX OSC RF LD 15-BIT RF R COUNTER FO/LD CHARGE PUMP RF PRESCALER fIN RF PHASE COMP 18-BIT RF N COUNTER CLOCK DATA LE DO RF 22-BIT DATA REGISTER FIGURE 14. SIMPLIFIED BLOCK DIAGRAM Programmable Reference Dividers (IF and RF R Counters) If the Control Bits are 00 or 01 (00 for IF and 01 for RF) data is transferred from the 22-bit shift register into a latch which sets the 15-bit R Counter. Serial data format is shown below. LSB C1 MSB C2 R 1 R 2 R 3 R 4 R 5 R 6 R 7 R 8 R 9 R 10 R 11 R 12 R 13 R 14 R 15 R 16 Divide ratio of the reference divider, R (Control bits) R 17 R 18 R 19 R 20 Program Modes 15-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER) DIVIDE RATIO R 15 R 14 R 13 R 12 R 11 R 10 R 9 R 8 R 7 R 6 R 5 R 4 R 3 R 2 R 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 * * * * * * * * * * * * * * * * 32767 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 NOTES: 8. Divide ratios less than 3 are prohibited. 9. Divide ratio: 3 to 32767. 10. R1 to R15: These bits select the divide ratio of the programmable reference divider. 11. Data is shifted in MSB first. 9 HFA3524 Programmable Divide (N Counter) The N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the Control Bits are 10 or 11 (10 for IF counter and 11 for RF counter) data is transferred from the 22-bit shift register into a 4-bit or 7-bit latch (which sets the Swallow (A) Counter) and an 11-bit latch (which sets the 11-bit programmable (B) Counter), MSB first. Serial data format is shown below. For the IF N counter bits 5, 6, and 7 are don't care bits. The RF N counter does not have don't care bits. LSB C1 MSB C2 N 1 N 2 N 3 N 4 N 5 (Control bits) N 6 N 7 N 8 N 9 N 10 N 11 N 12 N 14 N 15 N 16 N 17 N 18 Divide ratio of the programmable divider, N 7-Bit Swallow Counter Divide Ratio (A Counter) N 19 Program Pulse Swallow Function DIVIDE RATIO A N 7 N 6 N 5 N 4 N 3 N 2 N 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 * * * * * * * * 127 1 1 1 1 1 1 1 NOTES: 12. Divide ratio 0 to 127. 13. B A. IF DIVIDE RATIO A N 7 N 6 N 5 N 4 N 3 N 2 N 1 0 X X X 0 0 0 0 1 X X X 0 0 0 1 * * * * * * * * 15 X X X 1 1 1 1 Programmable Modes Several modes of operation can be programmed with bits R16-R19 including the phase detector polarity, charge pump High Z State and the output of the FO/LD pin. The prescaler and powerdown modes are selected with bits N19 and N20. The programmable modes are shown in Table 1. Truth table for the programmable modes and FO/LD output are shown in Table 2 and Table 3. X = Don't care condition. TABLE 1. PROGRAMMABLE MODES 11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO (B COUNTER N 17 N 16 N 15 N 14 N 13 N 12 N 11 N 10 N 9 N 8 3 0 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 0 0 0 0 1 0 0 * * * * * * * * * * * * 2047 1 1 1 1 1 1 1 1 1 1 1 C1 C2 R19 R20 0 0 IF Phase Detector Polarity R16 IF ICPO IF DO High Z R17 IF LD IF FO 0 1 RF Phase RF ICPO RF DO Detector Polarity High Z RF LD RF FO N19 R18 C1 C2 14. Divide ratio 3 to 2047 (divide ratios less than 3 are prohibited). 1 0 IF Prescaler Powerdown IF 15. B A. 1 1 RF Prescaler Powerdown RF NOTES: 10 N 20 fVCO = [(P x B) + A] x fOSC/R fVCO: Output frequency of external voltage controlled oscillator (VCO) B: Preset divide ratio of binary 11-bit programmable counter (3 to 2047) A: Preset divide ratio of binary 7-bit swallow counter (0 A 127 {RF}, 0 A 15 {IF}, A B) fOSC: Output frequency of the external reference frequency oscillator R: Preset divide ratio of binary 15-bit programmable reference counter (3 to 32767) P: Preset modulus of dual modulus prescaler (for IF: P = 8 or 16; for RF: P = 32 or 64) RF DIVIDE N RATIO B 18 N 13 N20 HFA3524 TABLE 2. MODE SELECT TRUTH TABLE D POLARITY DO HIGH Z STATE (NOTE 16) ICPO IF PRESCALER RF PRESCALER (NOTE 17) POWERDOWN 0 Negative Normal Operation LOW 8/9 32/33 Powered Up 1 Positive High Z State HIGH 16/17 64/65 Powered Down NOTES: 16. The ICPO LOW current state = 1/4 x ICPO HIGH current. 17. Activation of the IF PLL or RF PLL powerdown modes result in the disabling of the respective N counter divider and debiasing of its respective fIN inputs (to a high impedance state). Powerdown forces the respective charge pump and phase comparator logic to a High Z State condition. The R counter functionality does not become disabled until both IF and RF powerdown bits are activated. The OSCIN pin reverts to a high impedance state when this condition exists. The control register remains active and capable of loading and latching in data during all of the powerdown modes. TABLE 3. THE FO/LD (PIN 10) OUTPUT TRUTH TABLE RF R [19] (RF LD) IF R [19] (IF LD) RF R [20] (RF FO) IF R [20] (IF FO) 0 0 0 0 Disabled (Note 18) 0 1 0 0 IF Lock Detect (Note 19) 1 0 0 0 RF Lock Detect (Note 19) 1 1 0 0 RF/IF Lock Detect (Note 19) X 0 0 1 IF Reference Divider Output X 0 1 0 RF Reference Divider Output X 1 0 1 IF Programmable Divider Output X 1 1 0 RF Programmable Divider Output 0 0 1 1 Fastlock (Note 20) 0 1 1 1 For Internal Use Only 1 0 1 1 For Internal Use Only 1 1 1 1 For Internal Use Only 1 1 1 1 Counter Reset (Note 21) FO OUTPUT STATE X = Don't care condition NOTES: 18. When the FO /LD output is disabled, it is actively pulled to a low logic state. 19. Lock detect output provided to indicate when the VCO frequency is in "lock". When the loop is locked and a lock detect mode is selected, the pins output is HIGH, with narrow pulses LOW. In the RF/IF lock detect mode a locked condition is indicated when RF and IF are both locked. 20. The Fastlock mode utilizes the FO /LD output pin to switch a second loop filter damping resistor to ground during fastlock operation. Activation of Fastlock occurs whenever the RF loop's lcpo magnitude bit #17 is selected HIGH (while the #19 and #20 mode bits are set for Fastlock). Phase Detector Polarity Depending upon VCO characteristics, R16 bit should be set accordingly, (see Figure 15). * When VCO characteristics are positive like (1), R16 should be set HIGH. * When VCO characteristics are negative like (2), R16 should be set LOW. VCO OUTPUT FREQUENCY 21. The Counter Reset mode bits R19 and R20 when activated reset all counters. Upon removal of the Reset bits, the N counter resumes counting in "close" alignment with the R counter. (The maximum error is one prescaler cycle.) If the Reset bits are activated, the R counter is also forced to Reset, allowing smooth acquisition upon powering up. (1) (2) VCO INPUT VOLTAGE FIGURE 15. VCO CHARACTERISTICS 11 HFA3524 DATA N20: MSB N19 (R20: MSB) N10 (R19) N9 (R8) N1 (R7) (R6) CONTROL BIT: LSB (R1) CONTROL BIT: LSB CLOCK tCWL LE tCS tCH tCWH tEW tES OR LE NOTES: 22. Parenthesis data indicates programmable reference divider data. 23. Data shifted into register on clock rising edge. 24. Data is shifted in MSB first. Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around VCC/2. The test waveform has an edge rate of 0.6V/ns with amplitudes of 2.2V at VCC = 2.7V and 2.6V at VCC = 5.5V. FIGURE 16. SERIAL DATA INPUT TIMING fR fP LD DO H I I I Z L fR > fP fR = fP fR < fP fR < fP fR < fP NOTES: 25. Phase difference detection range: -2 to +2 26. The minimum width pump up and pump down current pulses occur at the DO pin when the loop is locked. 27. R16 = HIGH. FIGURE 17. PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS 12 HFA3524 Typical Application Example VP VCO (NOTE 28) R2 C3 0.01F IF OUT 10pF 100pF C4 RIN (NOTE 29) VCC 0.01F 100pF VCC 20 VP 19 DO IF 18 GND 17 fIN IF 16 FROM CONTROLLER 100pF f IN IF 15 GND LE DATA CLOCK 14 13 12 11 7 8 9 10 HFA3524 1 100pF 2 3 VCC VP VCC VP 0.01F 4 5 DO RF GND 6 fIN RF f IN RF GND OSCIN GND 100pF FO/LD FO/LD 100pF RIN (NOTE 29) CRYSTAL OSCILLATOR INPUT 51 (NOTE 30) 100pF 0.01F 10pF VCO (NOTE 28) RF OUT R1 C1 C2 NOTES: 28. VCO is assumed AC coupled. 29. RIN increases impedance so that VCO output power is provided to the load rather than the PLL. Typical values are 10 to 200 depending on the VCO power level. fIN RF impedance ranges from 40 to 100. fIN IF impedances are higher. 30. 50 termination is often used on test boards to allow use of external reference oscillator. For most typical products a CMOS clock is used and no terminating resistor is required. OSCIN may be AC or DC coupled. AC coupling is recommended because the input circuit provides its own bias (see Figure 16). 31. Proper use of grounds and bypass capacitors is essential to achieve a high level of performance. Crosstalk between pins can be reduced by careful board layout. 32. This is a static sensitive device. It should be handled only at static free work stations. FIGURE 18. VCC 100k 100K OSCIN LD MMBT200 33K LOCK DETECT 0.01F FIGURE 19. 10K Typical Locked Detect Circuit A lock detect circuit is needed in order to provide a steady LOW signal when the PLL is in the locked state. A typical circuit is shown in Figure 20. 13 FIGURE 20. HFA3524 CHARGE PUMP fR 1/R CRYSTAL REFERENCE REFERENCE DIVIDER fP FREQUENCY SYNTHESIZER VP PHASE DETECTOR R LOOP FILTER DO P REFERENCE FREQUENCY fREF VCO fOUT Z(s) fIN 1/N MAIN DIVIDER FIGURE 21. BASIC CHARGE PUMP PHASE LOCKED LOOP Application Information A block diagram of the basic phase locked loop is shown in Figure 21. Loop Gain Equations A linear control system model of the phase feedback for a PLL in the locked state is shown in Figure 22. The open loop gain is the product of the phase comparator gain (K), the VCO gain (KVCO/s), and the loop filter gain Z(s) divided by the gain of the feedback counter modulus (N). The passive loop filter configuration used is displayed in Figure 23, while the complex impedance of the filter is given in Equation 2. R + E - K I Z(s) KVCO s O 1/N FIGURE 22. PLL LINEAR MODEL DO VCO R2 C1 C2 FIGURE 23. PASSIVE LOOP FILTER Open loop gain = H(s) G(s) = I E = K Z(s) K VCO Ns (EQ. 1) s ( C2 * R2 ) + 1 Z ( s ) = ----------------------------------------------------------------------------------2 s ( C1 * C2 * R2 ) + sC1 + sC2 (EQ. 2) The time constants which determine the pole and zero frequencies of the filter transfer function can be defined as: C1 * C2 T1 = R2 * ---------------------C1 + C2 (EQ. 3A) and T2 = R2 * C2 (EQ. 3B) 14 The 3rd order PLL Open Loop Gain can be calculated in terms of frequency, , the filter time constants T1 and T2, and the design constants K, KVCO, and N. - K * K VCO ( 1 + j * T2 ) T1 G ( s ) * H ( s ) s = j * w = ------------------------------------------------------------------- * ------2 T2 C1 * N ( 1 + j * T1 ) (EQ. 4) From Equation 3 we can see that the phase term will be dependent on the single pole and zero such that the phase margin is determined in Equation 5. ( ) = tan -1 ( * T2 ) - tan -1 o ( * T1 ) + 180 (EQ. 5) A plot of the magnitude and phase of G(s)H(s) for a stable loop, is shown in Figure 24 with a solid trace. The parameter P shows the amount of phase margin that exists at the point the gain drops below zero (the cutoff frequency wp of the loop). In a critically damped system, the amount of phase margin would be approximately 45 degrees. If we were now to redefine the cut off frequency, wp', as double the frequency which gave us our original loop bandwidth, wp, the loop response time would be approximately halved. Because the filter attenuation at the comparison frequency also diminishes, the spurs would have increased by approximately 6dB. In the proposed Fastlock scheme, the higher spur levels and wider loop filter conditions would exist only during the initial lock-on phase - just long enough to reap the benefits of locking faster. The objective would be to open up the loop bandwidth but not introduce any additional complications or compromises related to our original design criteria. We would ideally like to momentarily shift the curve of Figure 24 over to a different cutoff frequency, illustrated by the dotted line, without affecting the relative open loop gain and phase relationships. To maintain the same gain/phase relationship at twice the original cutoff frequency, other terms in the gain and phase Equations 4 and 5 will have to compensate by the corresponding "1/w" or 1/w2" factor. Examination of Equations 3 and 5 indicates the damping resistor variable R2 could be chosen to compensate the "w" terms for the phase margin. This implies that another resistor HFA3524 normal current per unit phase error while an open drain NMOS on chip device switches in a second R2 resistor element to ground. The user calculates the loop filter component values for the normal steady state considerations. The device configuration ensures that as long as a second identical damping resistor is wired in appropriately, the loop will lock faster without any additional stability considerations to account for. Once locked on the correct frequency, the user can return the PLL to standard low noise operation by sending an instruction with the RF IcpO bit set low. This transition does not affect the charge on the loop filter capacitors and is enacted synchronous with the charge pump output. This creates a nearly seamless change between Fastlock and standard mode. of equal value to R2 will need to be switched in parallel with R2 during the initial lock period. We must also insure that the magnitude of the open loop gain, H(s)G(s) is equal to zero at wp' = 2wp. KVCO, K, N, or the net product of these terms can be changed by a factor of 4, to counteract the w2 term present in the denominator of Equation 3. The K term was chosen to complete the transformation because it can readily be switched between 1X and 4X values. This is accomplished by increasing the charge pump output current from 1mA in the standard mode to 4mA in Fastlock. Fastlock Circuit Implementation A diagram of the Fastlock scheme as implemented in Intersil Corporations HFA3524 PLL is shown in Figure 25. When a new frequency is loaded, and the RF IcpO bit is set high, the charge pump circuit receives an input to deliver 4 times the GAIN PHASE |<G(s) H(s)| G(s) H(s) P P' = 2P -90 0dB P P' -180 FREQUENCY FIGURE 24. OPEN LOOP RESPONSE BODE PLOT DIVIDER MAIN fIN 1/N CHARGE PUMP PHASE DETECTOR fP R fR 1/R CRYSTAL REFERENCE VP DO P VCO LOOP FILTER RFOUT C1 C2 R2' R2 REFERENCE DIVIDER 1X 4X FOLD FASTLOCK FIGURE 25. FASTLOCK CIRCUIT IMPLEMENTATION All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com 15