ANALOG DEVICES LC?M0S Complete, High Speed 12-Bit ADC AD7572 FEATURES 12-Bit Resolution and Accuracy Fast Conversion Time AD7572XX05: Sys AD7572XX12: 12.5ys Complete with On-Chip Reference Fast Bus Access Time: 90ns Low Power: 135mW Smail, 0.3", 246-Pin Package and 28-Terminal Surface Mount Packages GENERAL DESCRIPTION The AD7572 is a complete, 12-bit ADC that offers high speed performance combined with low, CMOS power levels. The AD7572 uses an accurate, high speed DAC and comparator in a successive-approximation loop to achieve a fast conversion time. An on-chip, buried Zener diodc provides a stable reference voltage to give low drift performance over the full temperature range and the specified accuracy is achieved without any user trims. An on-chip clock circuit is provided, which may be used with a crystal for stand-alone operation, or the clock input may be driven from an external clock source such as a divided-down microprocessor clock. The only other external components re- quired for basic operation of the AD7572 are decoupling capacitors for the supply voltages and reference output. The AD7572 has a high speed digital interface with three-state data outputs and can operate under the control of standard microprocessor Read (RD) and decoded address (CS) signals. Interface timing is sufficiently fast to allow the AD7572 to operate with most popular microprocessors, with three-state enable times of only 90ns and bus relinquish times of 75ns. The AD7572 is fabricated in Analog Devices Linear Compatible CMOS process (LC?MOS), an advanced, all ion-implanted process that combines fast CMOS logic and linear, bipolar circuits on a single chip, thus achieving excellent linear performance while still retaining low CMOS power levels. The AD7572 is available in both 0.3 wide , 24-pin DIPs and in a 28-terminal plastic leaded chip carrier (PLCC) and leadless ceramic chip carrier (LCCC). REV.A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. FUNCTIONAL BLOCK DIAGRAM ajc wor | A : MULTIPLEXER 18) WEEN B)eaw our TWARE-STATE THREE STATE : DUTPUT OUTPUT osentaTon 17 CLIN TOT O-O-W E oO Oe 07) 606 =BGND Dwrl ows PRODUCT HIGHLIGHTS 1. Fast, Sys and 12.5ys conversion imes make the AD7572 ideal for a wide range of applications in telecommunications, sonar and radar signal processing or any wideband data acquisition system. 2. On-chip buried-Zencr reference has temperature coefficient as low as 25ppm/"C, giving low full-scale drift over the operating temperature range. 3. Stable DAC and comparator give excellent linearity and low zero error over the full temperature range. 4. Fast, easy-to-use digital interface has three-state bus access times of 90ns and bus relinquish times of 75ns, allowing the AD7572 to interface to most popular microprocessors. 5. LC?MOS circuitry gives low power drain (135mW) from +5, 15 volt supplies. 6. 24-pin 0.3" package offers space saving over parts in 28-pin 0.6" DIP. One Technology Way, P.O. Box 9106, Norwood, MA 02062-3106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 Twx: 710/394-6577 Telex: 924491 Cable: ANALOG NORWOODMASS(Vg = SV & 5%, Veg = 15V & 5%, fey: 2.5MHz for ADTS72XX05, 1MNz for AD7572 SPECIFIC ATION on Mee) Tia tO Trax Unless otherwise noted. Specifications J,A,S K,8,T Gu Parameter Versions Versions L Version Versions Units Test Conditions/Comments ACCURACY Resolution 12 12 Ps 12 Bits Integral Nonlinearity @ + 25C zl x1 212 212 LSB max Tai t Tras 21 21 22 2a LSB max Differential Nonlinearity zl zl zl 21 LSB max Minimum Resolution for which no Missing Codes are Guaranteed 12 2 12 h2 Bits Offset Error @: + 23C 24 23 23 +3 LSB max Trin 0 Tae 26 +5 24 +4 LSB max Typical Change over Temp Is = ILSB Full Scale (FS) Ercor? @: +25C 21S 210 210 210 LSB max Von = 5ViVs5 ~ SV; FS = SV Full Scale Tc? 4s 2s 2s 25 pervC max Ideal Last Code Transition = FS - 3/2LSBs ANALOG INPUT Input Voltage Range Ow+S Oto +5 Oto +$ Oro + $ Volts For Bipolar Operation See input Current 3.5 3.5 3.$ 3.5 mA max Figures 10. & 12 INTERNAL REFERENCE VOLTAGE Veer Output @ + 25C =~$.-$.3 | -S.2-$.3 J -$.7-5.3 | -5.2/-9.3 | VenivVmax | -5.25V 21% Vaer Output TC 0 20 20 20 pem/*Ctyp Output Current Sink Capability $50 $$0 550 550 pA max External Load Should Not Change During Conversion POWER SUPPLY REJECTION Vp Only 212 212 242 212 LSB typ FS Change, Vss = ~ 15V Vop= +4.75V to +5.25V Vy Only 212 22 212 +12 LS8 typ FS Change, Vpn = SV Vsg = 14.25V.w - 15.75V LOGIC INPUTS CS,RB,HBEN,CLKIN Vonz. Input Low Voltage +0.8 +0.8 +0.8 +0.8 Vmax Voy = SV +S% Vinve input High Voltage +26 +24 +24 +24 V min Cyy,? Input Capacitance 10 10 10 10 pF max CS, RD, HBEN Ir, Input Currents 210 210 +10 210 A max Vin = O10 Vpn CLKIN Tig, Input Current 220 =20 220 +20 pA max Vin = 000 Von LOGIC OUTPUTS Dil-Deve, SUSY, CLK OUT Vox. Output Low Voltage +04 40.4 +04 +0.4 Vmax Isinx = 1.6mA Von, Output High Voliage +40 +40 +40 +4.0 Vmin Isounce = 200nA Dii-DO8 Floating State Leakage Current 210 210 +10 210 pA max Floating State Output Capacitance? | 15 15 1S 15 pF max CONVERSION TIME AD7572XX05 Synchronous Clock 5 5 5 5 ps max for = 2.SMHz. See Under Asynchronous Clock 4.8/5.2 4.8/5.2 4.8/5.2 4.8/5.2 uS min/max Control Inputs Synchronization AD7572XX12 Synchronous Clock 12.5 12.5 12.5 12.5 ys max forx = IMHz Asynchronous Clock 12/13 12/13 312/13 12/13 ps min/ps max POWER REQUIREMENTS Von v$ +5 +$ +5 VNOM 2 5% for Specified Performance Vss -IS 15 ~-15 ~-15 VNOM + 5% for Specified Performance lon 7 7 7 7 mA max TS = RD = Vop, AIN=5V . Igs 12 12 12 12 mA max CS = RD = Vpp, AIN = 5V Power Dissipation 135 135 135 135 mW typ 2s 21s 25 2s. mW max NOTES "Tempereture range as follows: }, K, L Versions; 010 + 70C. A,B,C Versions; 25C 10 + 85C. $,T,U Versions; - $$C to + 125C. *tachudes internel voltage reference error. Full-Scale TC = APS/AT, where OFS is Full-Scale change (romT, = 25C wT n.g OF Tass Includes imernal vokeage reference drift. *Seanple rested to ensure commpliaace. _ Power supply current is measured when AD7572 is inactive, i.c..C$ = RD = BUSY = HIGH. Specifications pebject to change without notice. REV. AADI572 TIMING CHARACTERISTICS ,. - 5.. -130 Limit at +25C | Limit at Taias Twas Limit at Tye T max Parameter (All Grades) Uj, K,L, A, B, CGrades) | (S, T, U Grades) Units | Conditions/Comments u 0 0 0 nsmin| CStoRD Setup Time t 190 230 270 nsmax| RD to BUSY Propagation Dclay t;? 0 0 120 nsmax| Data Access Time after RD, C= 20pF 125 150 170 nsmax| Data Access Time after RD, C, = 100pF G Ty ty ty ns min RD Pulse Width ts 0 0 0 nsmin} CStoRD Hold Time te 70 90 100 nsmax| Data Setup Time after BUSY 7 20 20 20 nsmin| Bus Relinquish Time 78 8$ 90 ns max ts 0 0 0 asmin| HBEN toRD Setup Time & 0 0 0 nsmin| HBENto RD Hold Time to ~ 200 200 200 nsmin| Delay Between Successive Read Operations NOTES "Timing Specifications are sample tested at + 25C to ensure compliance. All input control signals are specified with u = ef = Sns(10% to 90% of + 5V) and timed from a voltage level of 1.6V. 2, and t, are measured with the loed circuits of Figure | and defined as the time required for an ourput rocross 0.8V or 2.4V. 5. is defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2. Specifications subject to change without notice. bv aun ABSOLUTE MAXIMUM RATINGS* (Ta = + 25C unless otherwise noted) pen OBN Vpn toDGND .......-..--008] -0.3V to +7V saat L J m VsstoDGND 0.000 ee eee +0.3V to -17V AGNDtoDGND............ -0.3V, Vop + 0.3V DGND pend AINtOAGND ............0.--. -15V to +15V a. High-Z to Vow (te) b. High-Z 0 Vou (ts! Digital Input Voltage to DGND and Vo, to Vou {tel and Vow to Vox (te! (CLK IN, HBEN, RD,CS) ..... -0.3V, Vpp +0.3V Digital Output Voltage to DGND Figure 1. Load Circuits for Access Time (D11-D0/8, CLK OUT, BUSY) ... -0.3V, Vpp +0.3V Operating Temperature Range sv Commercial (J, K, I. Versions)... 0... - 0 ta + 70C on Industrial (A, B, C Versions)... .... - 28C to +85C Extended (S, T, U Versions) ....... -$5C to +125C OBN DEN Storage Temperature 2.2... 0 ee -65C to +150C aks 10pF 10pF Lead Temperature (Soldering, 10secs) ........ + 300C L L Power Dissipation (Any Package) to +75C ... . 1,000mW DGND DGND Derates above +75C by 2.2... 00 ee ees 10mW/C : . *Stress a lis r Al te Maxi ings n 8. Vow to High-2Z 6. Vor to High-Z damage vethedenee Thisisa vues ring only and fonctions operstion ofthe device at these or any other condition above those indicated in the operational sectivns of this pecification is not implied. Exposure to absol i rating conditions for ex- tended periods may affect device reliability. Figure 2. Load Circuits for Output Float Delay CAUTION ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protect- WARNING! aa ed; however, permanent damage may uccur on unconnected devices subject to high energy ie aie ? ( electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective aaa Za foam should be discharged to the destination socket before devices are removed. RRR IN at yao REV. A -3-ADT572 ORDERING GUIDE! Conversion | Temperature Full-Scale | Accuracy | Package ModeF? Time Range TC Grade Option* AD7572JNO5 | Sus 0 to +70C 4SppmC | zILSB N-24 AD7572KN05 | Sys 0 to +70C 2Sppm/C | +ILSB N-24 AD7572LNO05 | Sys 0 to +70C 2Sppm/C | +1/2LSB | N-24 AD7S72JP0S | Sus 0 to +70C 4Sppm/C | +ILSB P-28A AD7S72KP05 | Sus 0 to +70C 25ppm/C | +1LSB P-28A AD7572LP05 | Sys 0 to +70C 25ppm/C | +V/2LSB |; P-28A AD7572AQ05 | Sys ~25C to +85C + | 4Sppm/C | +ILSB Q-24 AD7572BQ05 | Sys ~25C to +8S5C: | 25ppm/C. | +ILSB Q-24 AD7572CQ05 | Sus -25C to +85C || 2Sppm/*C | +IV/2LSB | Q-24 AD7572SQ0S_| Sus ~55C to +125C | 45ppm/C | +1LSB Q-24 AD7572TQ0S | Sps -55C to +125C | 25ppm/C | +ILSB Q-24 AD7572UQ05 | 5ps ~55C to +125C | 2Sppm/"C (| +1/2LSB | Q-24 AD7572SE05 | Sps 55C to +125C | 45ppm/C | =1LSB E-28A AD7572TE05 | 5ps 55C to +125C | 2SppmC | +1 LSB E-28A AD7572UE05 | 5ys ~55C to +125C | 25ppm/C | +V/2LSB | E-28A AD7572JN12 | 12.5us 0 to +70C 45ppm/C | +1LSB N-24 AD7572KN12 | 12.Sps 0 to +70C 2Sppm/C | +1LSB N-24 AD7S872LN12 | 12.5ps 0 to +70C 25ppm/*C | +MV/2LSB | N-24 AD7S72JPi2 | 12.5ps 0 to +70C 4SppnvC | +1LSB P-28A AD7572KP12 | 12.5ps 0 to +70C 2Sppm/C | +1LSB P-28A AD7572LPi2 | 12.Sus 0 to +70C 25ppm/C | +1/2LSB | P-28A AD7S72AQ12 | 12.5ps ~25C to +85C | 45ppm/*C | tILSB Q-24 AD7572BQ12 | 12.5ps ~25C 10 +8SC | 2ppm/C | +1LSB Q-24 AD7572CQ12 | 12.Sps 25C to +85C | USppm/C | +1/2LSB | Q-24 AD7572SQ12 | 12.5ps 55C to +125C | 4Sppm/C | +1LSB Q-24 AD7572TQi2 | 12.5us 5SC to +125C | 25ppm/C | +1 LSB Q-24 AD7572UQ12 | 12.5ys ~$5C to +125C | 25ppm/C | +V2LSB | Q-24 AD7572SEi2 | 12.5ps ~55C 10 +125C | 4Sppm/C | +1LSB E-28A AD7572TE1!2 | 12.5ps 55C to +125C | 25ppm/C | +1LSB E-28A AD7572UE12 | 12.5ps 5SC to +128C | 2ppm/C | +1/2LSB | E-28A NOTES Analog Devices Reserves the right to ship ceramic (D-24A) in lieu cerdip (Q-24) hermetic package. *To order MIL-STD-883, Class B processed parts, add /883B to part number. Contact your focal sales office for military data sheet. For U.S. Standard Military Drawing (SMD) see DESC Drawing #5962-87591. D = Ceramic DIP; E = Leadless Ceramic Chip Carrier (LCCC); N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip. PIN CONFIGURATIONS DIP Lccc PLCC VF mle = Gisyssh Veer (2 23) Vee 432 1 222 aanp | 3 22] BUSY m4 on te 20} & ons ore & 20] fo ow 6 o [6 AD7S72 Fis] ween oa TOP View nc 8 os [7] tette Seated [i5} ceux our oe) {Not to Scale) ov [es a7] cu or 0 os [3 19] ows ben os [10 3} pis oe in im e2w 12 13 14 961617~18 pas [12 13} own sseege : ncenoconnecr 8 ea REV.AAD7572 "To order MIL-STID-883, Clase B processed ports, odd 2833 to part number. Contact your loca) sales affice for military data sheet 2 analog Devices cesctves the right 10 ship either cerdip or ceramic hermetic packages. PLOC: Plastic Leaded Chip Carrier. "LOCC. Leadiess Ceramic Chip Carrier. REV. A PIN FUNCTION DESCRIPTION DIP Pin No. Mnemonic Description 1 AIN Analog Input. 2 VreF Voltage Reference Output. The AD7572 has its own internal 5.25V reference. 3 AGND Analog Ground. _ 4.0.01 Dil ...D Three State data outputs. They become active when CS and RD are brought low. 13...16 D3/11 ... DO/8 Individual pin function is dependent upon High Byte Enable(HBEN) Input. _ DATA BUS OUTPUT. RD = Low Ping | Pin5 | Ping | Pin7 | PinS | Pie? | Pis 10 | Pis bB 14} Pie 15; Pin 16 HBEN = HIGH | DB11}DB10] DB? | DB8 | LOW |LOW| LOW 11/DB10|DB9 | DBS NOTE *D1] . . . DO/Sare the ADC dats output pins. DB1! . . . DBO are the 12-bit conversion results, DB11 is the MSB. 12 DGND Digital Ground. 17 CLKIN Clock Input pin. An external TTL compatible clock may be applied to this pin. Alternatively a crystal or ceramic resonator may be connected berween CLK IN (Pin 17) and CLK OUT (Pin 18). 18 CLK OUT Clock Output Pin. An inverted CLK IN signal appears at CLK OUT when an external clock is used. See CLK IN (Pin 17) description for crystal (resonator). 19 HBEN High Byte Enable input. Its primary function is to multiplex the 12-bits of conversion data onto the lower D7 . . . DO/8 outputs (4MSBs or 8 LSBs). See Pin description 4... 1) and 13... . 16. __ It also disables conversion start when HBEN is high. _ 20 RD READ input. This active LOW signal, in conjunction with CS is used to enable the output data three state drivers and initiate a conversion if CS and HBEN arc low. 21 cs CHIP SELECT Input. This active LOW signal, in conjunction with RD is used to enable the output data three state drivers and initiate a conversion if RD aod HREN are low. 22 BUSY BUSY output indicates converter status. BUSY is LOW during conversion. 23 Vss Negative Supply, 15V. 24 Vpp Positive Supply, + 5V. OPERATIONAL DIAGRAM ORDERING INFORMATION'* An operational diagram for the AD7572 is shown in CONVERSION TIME = Sys Figure 3. The AD7572 is a 12-bit successive approximation Temperorare Range and Package Options A/D converter. The addition of just a crystal/ceramic resonator F Accucac and a few capacitors enables the device to perform the analog- wll-Scale beuracy - os . Tc Grade Oto +70C -28'Cro +as'c | -55C1o +125C | to-digital function. Plastic DIP Hermetic? DIP Hermetic? DIP oT0 +sv sppmrc | 24Lsz | AD7S72jNOS | A1D7572AQ0S AD7572SQ05 ANALOG +8v ppc | 2ILSB | AD7S72KNOS | AD7572BQ05 ADIS7Z1QUS INPUT pparC | =V2LSB } AD7S72LN0S | AD7572CQ0S AD7S72UQ05 Ves OURO -15V rice! Lece* OwFS 5 5 STATUS 4Sppmc | 2 ILSB | AD7572]P0S AD7S72SE0S g OUTPUT 2ppmec | =ILSB | AD7$72KPOS AD?$72T E05 DSppmPC | + V2LSR | AD75721.Pos AD?872UE05 we CONTRO WePUTS CONVERSION TIME = 12.5ps 0 Temperature Range aad Package Options 1 Full-Scale | Accuracy a. | Tc Grade Bo + 70C 29C10 +45C =$88Cto + RSC Plastic DIP | Hermetic DIP | Hermetic DIP o 4sppmrC | 21LSB | AD7572)NI2. | AD7372AQI2 AD7S72SQ12 25pm. + ILSB AD7S72KN12 AD?728Q12 AD7$72TQIZ ppmeC | + V2LSB | ADIS72LNI2 | AD7572CQ12 ADIS72UQI2 PLCC? Lcecc* 4SppmrC | 2 1LSB | AD7$72)P12 AD7S72SE}2 BppmrC | 21LSB | AD7S72KPI2 AD?S72TE12 Sppmv"C | x V2LSB | AD?S72.-P1z ADTS72UE12 60600600 0000 NOTES j ' LE ep para ous NOTES AD7ET2ZXNGS - 2. SMH CRYSTALICERAMIC RESONATOR. ADTS72XX 12 1.0MHz CRYSTAUCERAMIC RESONATOR. Ct and C2 CAPACITANCE VALUES DEPEND ON CRYSTALICERAMIC RESONATOR MANUFACTURER. TYPICAL VALUEG ARE FROM 3010 100pF. Figure 3. AD7572 Operational DiagramAD7572 CONVERTER DETAILS Conversion start is controlled by the CS, RD and HBEN inputs. At the start of conversion the successive approximation register (SAR) is reset and the three-state data outputs are enabled. Once a conversion cycle has begun it cannot be re- started. During conversion, the internal 12-bit voltage mode DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 4, the AIN input connects to the comparator input via 2.5kKQ. The DAC which has 2 similar 2.5kN output impedance connects to the same comparator input. Bit decisions are made by the comparator (zero crossing detector) which cheeks the addition of each successive weighted bit from the DAC output. The MSB decision is made 80ns (typically) after the second falling edge of CLK IN following a conversion start. Similarly, the succeeding bit decisions are made ap- proximately 80ns after a CLK IN edge until conversion is finished. At the end of conversion, the DAC output current balances the AIN input current. The SAR contents (12-bit data word) which represent the AIN input signal is losded into a 12-bit latch. Poac _ 7 COMPARATOA [amu | ! lst T LL_u Vv SAR AD7572 s z 12-817 taATCH Figure 4. AD7572 AIN input aw_\ [7 1, 11 om \ 45 / wn Pr PA ALT aoe t 0611 oat oes po (mse) LSB) Figure . Operating Waveforms Using an External Clock Source for CLK IN CONTROL INPUTS SYNCHRONIZATION In applications where the RD control input is not synchronized with the ADC clock then conversion time can vary from 12 to 13 CLK IN periods. This is because the ADC waits for the first falling CLK IN edge after conversion start before the conversion procedure begins. Without synchronization, this delay can vary from zero to an entire clock period. If a constant conversion time is required, then the following approach ensures a fixed 5ys conversion time for the AD7572XX05 and 12.5ps for the AD7572XX12: when in- itiating a conversion, RD must go low on either the rising edge of CLK IN or the falling edge of CLK OUT. DRIVING THE ANALOG INPUT During conversion, the AIN input current is modulated by the DAC output current at a rate equal to che CLK IN frequency (i.e., 2.5MHz when CLK IN = 2.5MHz). The analog input voltage must remain fixed during this period and as @ result must be driven from an op amp or sample hold with a low output impedance. The output impedance of an op amp is equal to the open loop output impedance divided by the loop gain at the frequency of interest. Suitable devices capable of driving the AD7S72 AIN input are the AD OP-27 and AD711 op amps or the ADS85 sample hold. INTERNAL CLOCK OSCILLATOR Figure 6 shows the AD7572 internal clock circuit. A crystal or ceramic resonator may be connected between CLK IN (Pin 17) and CLK OUT (Pin 18) to provide a clock oscillator for the ADC timing. Alternatively the crystal/resonator may be omitted and an external clock source may be connected to CLK IN. For an external clock the mark/space ratio must be 50/50. An inverted CLK IN signal will appear et the CLK OUT pin as shown in the operating waveforms of Figure 5. A07572 food cet Ie Ad NOTES AD7672XX06 - 2.6MHe CRYSTAL CERAMIC RESONATOR. A07572XX 12 - 1.0MH2 CRYSTALCERAMIC RESONATOR. C1 and C2 CAPACITANCE VALUES DEPEND ON CRYSTALICERAMIC RESONATOR MANUFACTURER. TYPICAL VALUES AE FHOM 30 to 100pF. Figure 6. AD772 Internal Clock Circuit INTERNAL REFERENCE The AD7572 has an on-chip, buffered, temperature-compensated, buried Zener reference, which is factory trimmed to ~5.25V + 1%. It is internally connected to the DAC and is also available at Pin 2 to provide up to 550pA current to an external load. For minimum code transition noise the reference output should be decoupled with a capacitor to filter out wideband noise from the reference diode (JOwF of tantalum in parallel with 100nF ceramic). However, large values af decoupling capacitor can affect the dynamic response and stability of the reference amplifier. A 102 resistor in series with the decoupling capacitors will eliminate this problem without adversely affecting the filtering effect of the capacitors. A simplified schematic of the reference with its recommended decoupling components is shown in Figure 7. AD7572 TEMPERATURE COMPENSATION to | Pp vac b . S.28V -1$v aGND Vv, 3 \ Ome $10 10yF Figure 7. AD7572 Internal ~5.25V Reference 6 REV. AAD7S72 UNIPOLAR OPERATION Figure 8 shows the ideal input/output characteristic for the 0 to 5 volt input range of the AD7572. The designed code transitions occur midway between successive integer LSB values (i.c., V/2LSB, 3/2LSBs, 5/2LSBs . . . FS-3/2LSBs). The output code is natural binary with ILSB = FS/4096 = (5/4096)V = 122mV. output PULL SCALE CODE TRANSITION Wan W190 11... 108 1 ' 7 i / FS = SV i / suse - FS 1 aR5g , 4096 00...017 00... 010 00... 001 00 .. 000 oe we ans no peepee 04123 | FS LSB LSB'S LSBS FS -1186 AIN, INPUT VOLTAGE (IN TERMS OF LS8s) Figure 8. AD7572 Ideal Input/Output Transfer Characteristic UNIPOLAR OFFSET AND FULL-SCALE ERROR ADJUSTMENT In applications where absolute accuracy is important then offset and full-scale error can be adjusted to zero. Offset error must be adjusted before full-scale error. Figure 9 shows the extra com- ponents required for full-scale error adjustment. Zero offset is achieved by adjusting the offset of the op amp driving AIN (i.e., Al in Figure 9.). For zero offset error apply 0.6lmV (i.c., V/2LSB) at Vpy and adjust the op amp offset voltage until the ADC output code flickers between 0000 0000 0000 and 0000 0000 0001. For zero full-scale error apply an analog input of 4.99817V (i.c., FS-3/2LSBs or Ist code wansition) at Vpy and adjust R1 until the ADC output code flickers between 1111 1111 1110 and VE LUE VE. ADOP-27 Apri 0-5V ANALOG PUT Vay AlN AD772 AGND * ADDITIONAL PINS OMITTED FOR CLARITY Figure 9. Unipolar 0 to + 5V Operation with Gain Error Adjust REV. A BIPOLAR OPERATION Figures 10 and 12 show how bipolar operation can be achieved with the AD7572. Both circuits use an op-amp to offsct the analog signal (Viy) by 2.SV. Alternatively, the op amp (A1) can be replaced by 2 sample hold as shown in Figure 24. The op amp transfer functions are given below: Figure 10: AIN = (Vin + 2.5) volts Figure }2: AIN = (Vin + 2.5) volts Both circuits have an analog input range of + 2.5V and an LSB size of 1.22mV. The output codes are offset binary for Figure 10 and complementry offset binary for Figure 12. Their ideal input/output transfer characteristics after offset and full scale adjustment are shown in Figures 11 and 13. Signal ranges other than + 2.5V ure easily accommodated using different values of R3 and R4 for Figure 10, and a different R2 value for Figure 12. These resistors should be chosen such that the voltage range at AIN covers the full dynamic range (i.e., OV to $V) of the ADC. All resistors should be the same type and from the same manufacturer so that their temperature coefficients match. A07572 Ww ca AA Ww AAD *ADDITIONAL PINS OMITTED FOR CLARITY Figure 10. AD7572 Bipolar Operation - Output Code is Offset Binary VV... 111 | TAT... 110 i 1 ~ 7 ! 100...010 > ' ! ~ V2LsB8 100...001 + | =fs ' 100., .000 s 4h = i pid - 1488 gy...44t T! +1/2LSB O14... 110 Fy L , ' 4 FS = 5V ' 000. . .001 ! Fs 1L5B = 7096 000... .000 4g af < ar ov Lo Vie HNPUT VOLTAGE Figure 11. Ideal Input/Output Transfer Characteristic for the Bipolar Circuit of Figure 10AD7572 ANALOG INPUT *ADDITIONAL PINS OMITTED FOR CLARITY Figure 12. AD7572 Bipolar Operation - Output Code is Complementary Offset Binary V1... 199 111...190 191,..101 ve Bl @ # wn < Le ea 100 eo J ' 1 100...900 + { . +F iss 2 on... 18 = $- $f r o11...199 4 2 O11... 301 | F 1 & 000. ..010 + | 000. ..001 +t 000...000 4 ov Vin. INPUT VOLTAGE Figure 13. Ideal Input-Output Transfer Characteristic for the Bipolar Circuit of Figure 12 OFFSET AND FULL-SCALE ERROR In most Digital Signal Processing (DSP) applications offset and full-scale error have little or no effect on system performance. A typical example is a digital filter, where an analog signal is quan- tized, digitally processed and recreated using a DAC. In these type of applications the offset error can be eliminated by ac coupling the recreated signal. Full-scale error effect is linear and does not cause problems 2s long as the input signal is within the full dynamic range of the ADC. An important parameter in DSP applications is Differential Nonlinearity and this is not affected by either offset or full-scale error. In measurement applications where absolute accuracy is required, offset and full-scale error can be adjusted to zero as in Figure 14. ANALOG input m ons zoe AD.OP-2? avi R6 ADSES 5005 4 NM $ my AD7572 Rte mt * ADDITIONAL PINS OMITTED FOR CLARITY Figure 14. AD7572 Bipolar Operation with Offset and Gain Error Adjust BIPOLAR OFFSET AND FULL-SCALE ERROR ADJUSTMENT The bipolar circuit of Figure 10 can be adjusted for offset and full-scale errors, by including two potentiometers RS and R6, as shown in Figure 14. Offset must be adjusted before full-scale error. This is achieved by applying an analog input of 0.61mV (1/2LSB) at Vin and adjusting RS unul the ADC output code flickers between 1000 0000 0000 and 1000 0000 0001. For full-scale error adjustment, the analog input must be at 2.49817 volts (i.e., FS/2 3/2LSBs or last transition point). Then R6 is adjusted until the ADC output code flickers between TILL RIVE V2NO-and 1202 101 1111. A similar offset and full-scale error adjustment procedure may be employed for Figure 12 by making R1 and R2 variable. Offset must again be adjusted before full scale error. This is achieved by applying an anslog input of 0.61mV at Vin and adjusting R! until the ADC output code flickers between OVE TELL 1110 and OFEE PAVE P11. For full-scale error adjust, apply a signal source of 2.49817V at Vin and adjust R2 until the ADC output code flickers between 0000 0000 0000 and 0000 0000 0001. REV. AAD7S72 APPLICATION HINTS Wire wrap boards are not recommended for high resolution or high-speed A/D converters. To obtain the best performance from the AD7572 a printed circuit board is required. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the AD7572. The analog input should be screened by AGND. A single point analog ground (STAR ground) separate from the logic system ground should be established at Pit 3 (AGND) or as close as possible to the AD7572 as shown in Figure 15. Pin 12 (AD7S872 DGND) and all other analog grounds should be connected to this single analog ground point. No other digital grounds should be connected to this analog ground point. Low impedance analog and digital power supply common returns are essential to low noise operation of the ADC and the foil width for these tracks should be as wide as possible. Noise: Input signal Icads to AIN and signal rcturn icads from AGND (Pin 3) should be kept as short as possible to minimize input noise coupling. In applications where this is not possible, a shielded cable berween source and ADC is recommended. Also, since any potential difference in grounds between the signal source and ADC appears as an error voltage in series with the input signal, attention should be paid to reducing the ground circuit impedances as much as possible. In applications where the AD7572 data outputs and control signals are connected to 2 continuously active microprocessor bus, it is possible to get LSB errors in conversion results. These errors are due to feedthrough from the microprocessor to the successive approximation comparator. The probicm can be eliminated by forcing the microprocessor into a WAIT state during conversion (see Slow Memory Mode interfacing), or by using three-state buffers to isolate the AD7572 data bus. ANALOG DIGITAL SUPPLY SUPPLY +15V GND - SV +8V +, + +, + Howie Ft 1 Hii HR WH OH SAMPLE AL AOS Hotb 07572 oncoaty Figure 15. Power Supply Grounding Practice TIMING AND CONTROL Conversion start and data read operations are controlled by three AD7572 digital inputs; HBEN, CS and RD. Figure 16 shows the logic structure associated with these inputs. The three signals are internally gated so that a logic 0 is required on all three inputs to initiate a conversion, Once iniuated it cannot be re-started until conversion is complete. Converter status is indi- cated by the BUSY output, and this is low while conversion is in progress. REV. A There are two modes of operation as outlined by the timing diagrams of Figures 17 to 20. Slow Memory Mode is designed for microprocessors which can be driven into a WAIT state, a READ operation brings TS and RD low which initiates a con- version and data is read when conversion is complete. The second is the ROM Mode which does not require micro-_ processor WAIT states, a READ operation brings CS and RD low which initiates a conversion and reads the previous conversion result. DATA FORMAT The output data format can either be 2 complete parallel load (DB11..DBO) for 16-bit microprocessors or a two byte load for 8-bit microprocessors. Data is always right justificd (i.c., LSB is the most right-hand bit in a 16-bit word. For a two byte read, only data vuiputs D7 . . . DO/8 are used. Byte selection is governed by the HBEN input which controls an internal digital muluplexer. This multiplexes the 12-bits of conversion data onto the lower D7... DO/8 outputs (4 MSBs or 8 LSBs) where it can be read in two read cycles. The 4 MSBs always appear on Dil. . . D8 whenever the three-state output drives are turned on. *SV AD7S$72 Ty |e CONVERSION START HSEN Or inisinG EDGE TRIGGER: Br , Fur ce FLOP %6 Qe CLEAR | ACTIVE HIGH ENABLE THREE-STATE OUTPUTS O11...008 ~ OBI1... ACTIVE HIGH ENAGLE THREE.STATE OUTPUTS 011...08 = O81... OBS 87...04 = LOW 0311. OO@ = DHTS.. Des NOTE: O11... 00:3 ARE THE ADC DATA OUTOUT PINS. O11... DRO ARE THE 12-6!T CONVERSION RESULTS. Figure 16. Internal Logic for Control Inputs CS, RD and HBEN SLOW MEMORY MODE, PARALLEL READ (HBEN = LOW) Figure 17 and Table I shows the timing diagram and data bus status for Slow Memory Mode, Parallel Read. CS and RD going low triggers a conversion and the AD7572 acknowledges by taking BUSY low. Data from the previous conversion appears on the three state data outputs. BUSY returns high at the end of conversion when the output latches have been updated and the conversion result is placed on data outputs D1! . . . D0/8. SLOW MEMORY MODE, TWO BYTE READ For a two byte read only 8 data outputs D7 . . . DO/8 are used. Conversion start procedure and data output status for the first read operation is identical to Slow Memory Mode, Parallel Read. See Figure 18 timing diagram and Table IT data bus status. At the end of conversion the low data byte (DB7 . . . DBO} is read from the ADC. A second READ operation with HBEN high, places the high byte on data outputs D3/1] . . . D0/8 and disables conversion start. Note the 4MSBs appear on data outputs D111. . . D8 during the two READ operations above.AD7572 + ae sek ey eee alah aie DATA { oert-bed DENLOBe Figure 17. Slow Memory Mode, Paraliel Read Timing Diagram AD7572 Data Outputs pul | Die [D9 | Ds |D7 | D6 | DS | D4 | DIZ | D210} DY | DOs Read DBI}] DB10] DB9 | DB8 | DB7 | DB6 | DBS | DB4 | DB3 | DB2 | DB! | DBO Table |, Slow Memory Mode, Parallel Read Data Bus Status A a TAL te ue ale te eee ty = toon + 4 > | ub lube tube au uke GLODATA NEWDATA NEWOaTA DATA 087-D80 Da7-DBo paii-D88 Figure 18. Slow Memory Mode, Two Byte Read Timing Diagram AD7572 Data Outputs D7 [D6 {DS [D4 {D311 | D210 | DIA | Dos First Read DB7 | DB6 | DBS | DB4 |DB3 | DB2 | DB) | DBO Second Read LOW] LOW {LOW LOW |DBI1i | DBI0 | DBY | DBS Table Ii, Slow Memory Mode, Two Byte Read Data Bus Status : apo af ee SUSY | | ube ~ t me 7 ~| ty Ae {oreom f DATA f NEW OATA DATA 0811-080 0811-D80 }____ Figure 19. ROM Mode, Parallel Read Timing Diagram AD7572 Data Outputs Dili |D1I0 |D9 {DS |D7 | D6 | DS {D4 | D3i1 | D2/i0 } DI | DOS First Read (Old Data) DBI]| DB10|DB9 | DBS {DB7 | DB6 | DBS | DB4 | DB3 | DB2 {| DBI | DBO Second Read DB11| DB10(DB9 | DBS |DB7 | DB6 | DBS ; DB4 | DB3 |DB2 | DE) | DBO Table ill. ROM Mode, Paraliel Read Data Bus Status -10- REV. AAD7572 =| ye ols p. 1 ut aloe OLD DATA 0 ATA 087-080 ae of nf efabe ole, uke ae 4 | ty j~ NEWDATA DB11-DBe NEW DATA 087-D80 Figure 20. ROM Mode, Two Byte Read Timing Diagram AD7572 Data Outputs D7 {D6 {DS {D4 |D311 | D210 | DIV | DOS First Read (Old Data) DB7 | DB6 | DBS |DB4 |DB3 {| DB2 | DBI ; DBO Second Read LOW] LOW} LOW] LOW | DB11 | DBIO | DB? | DB8 Third Read DB7 | DB6 |DBS |DB4 |DB3 | DB2 | DBI | DBO Table lV. ROM Mode, Two Byte Read Data Bus Status ROM MODE, PARALLEL READ (HBEN = LOW) The ROM Mode avoids placing a microprocessor into @ wait state. A conversion is started with a READ operation and the 12-bits of data from the previous conversion is available on data outputs D1]. . . DO/8 (see Figure 19 and Table Ill). This data may be disregarded if not required. A second READ operation reads the new data (DB11 . . . DBO)and starts another conversion. A delay at least as long as the AD7572 conversion time must be allowed between READ operations. ROM MODE, TWO BYTE READ As previously mentioned for a two byte read, only data outputs MC68000 Microprocessor Figure 21 shows a typical interface for the 68000. The AD7572 is operating in the Slow Memory Mode. Assuming the AD7572 is located at address C000, then the following single 16-bit MOVE instruction both starts a conversion and reads the conversion result, Move.W $C000,D0 At the beginning of the instruction cycle when the ADC address is selected, BUSY and CS assert DIACK, so that the 68000 is forced into a WAIT state. At the end of conversion BUSY returns high and the conversion result is placed in the DO register of the UP. D7... D0/8 arc used. Conversion is started in the normal way with a READ operation and the data output status is the samc as the ROM Mode, Parallel Read. See Figure 20 timing diagram Aza} and Table IV data bus status. Two more READ operations are ADDRESS BUS required to access the new conversion result. A delay equal to a J the AD7572 conversion time must be allowed between conversion start and the second data READ operation. The second READ Ks En (pores operation, with HBEN high, disables conversion start and places MC68000 AD7572" the high byte (4MSBs) on data outputs 3/1]. . . DO/8. A __ third READ operation accesses the low data byte (DB7 . . . DBO) DTACK t+ fev and starts another conversion. The 4MSBs appear on data Rai }__!>0+| i outputs DI]. . . D8 during all three read operations above. DATA BUS MICROPROCESSOR INTERFACING 00h pos The AD7572 is designed to interface with microprocessors as & we memory mapped device. The CS and RD control inputs are common to all peripheral memory interfacing. The HBEN input serves as a data byte select for 8-bit processors and is normally connected to the microprocessor address bus. REV. A LINEAR CIRCUITRY OMITTED FUR CLARITY Figure 21. AD7572 - MC68000 Interface =AD7572 8085A, Z80 MICROPROCESSOR Figure 22 shows an AD7572 interface for the Z80 and 8085A. The AD7572 is operating in the Slow Memory Mode and a two byte read is required. Not shown in the figure is the 8-bit latch required to demultiplex the 8085A common address/data bus. AO is used to assert HBEN, so that an even address (HBEN = LOW) to the AD7572 will start a conversion and read the low data byte. An odd address (HBEN = HIGH) will read the high data byte. This is accomplished with the single 16-bit LOAD instruction below. For the 8085A LHLD(B000) * For the Z80 LD HL, (B000) This is a two byte read instruction which loads the ADC data (address BOOO) into the HL register pair. During the first read operation, BUSY forces the microprocessor to WAIT for the AD7572 conversion. No WAIT states are inserted during the second read operation when the microprocessor is reading the high data byte. AS ANORFSS BUS Ao Ss AG 2} REG za ADDRESS HBEN Decne A07572* oes Ls 208s a Walt Busy rr} Ro 07 AL 07 DATA BUS oo AT i LINEAR CIRCUITRY OMITTED FOR CLARITY ) Figure 22, AD7572 - 8085A/280 Interface TMS32010 MICROCOMPUTER Figure 23 shows an AD7572-TMS$32010 interface. The AD7572 is operating in the ROM Mode. The interface is designed for a maximum TMS32010 clock frequency of 18MHz but will typically work over the full TMS32010 clock frequency range. The AD7572 is mapped at a port address. The following 1/0 instruction starts a conversion and reads the previous conversion result into data memory. IN A,PA (PA = PORT ADDRESS) When conversion is complete, a second I/O instruction reads the up-to-date data into data memory and starts another conversion. A delay at least as long as the ADC conversion time must be allowed between 1/O instructions. -12- PAQ | PORT ADDHESS AUS PAG -7 TMS32010 rT RO AD7S72* p11 row OATA 8US be Deva HBEN Vv [__ *LINEAR CIRCUITRY OMITTED FOR CLARITY Figure 23. AD7572 - TMS32010 Interface AD7572-AD585 SAMPLE-HOLD INTERFACE Figure 24 shows an AD585 sample-hold amplifier driving the AIN input of the AD7572. The interface contains resistors R}, R2, R3 and R4 to allow a bipolar input signal range of + 2.5 volts. The maximum sampling frequency is 125kHz fur the AD7572XX05 (Sps conversion) and 64.SkHz for the AD7$72XX12 (12.5pys conversion). This includes the sample-hold amplifier acquisition time (3ys). When an AD7572 conversion is initiated, the converter BUSY output goes low indicating conversion is in progress. The falling edge of this BUSY output signal places the sample-hold amplifier into the HOLD mode freezing the input signal to the AD7572. When conversion is finished, the BUSY output returns HIGH allowing the sample-hold to track the input signal. To achicve the maximum sampling ratc, the AD7572 output data must be read within 3ps immediately after conversion while the sample- hold amplifier is acquiring the next sample. ANALOG SADOTTIONAL MAE OMNTTER FOR CLAHITY Figure 24. AD772 - AD585 Sample-and-Hold lntertace REV. AAD7572 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Pin Plastic (Suffix N) 24-Pin Ceramic (Suffix Q) RAAAAAAAAAL aie _ |e ti rr eae aise, Enea f | 0 796i3 351 sears VIN NINA NNN VN sonst sees T ain 28 -a mt (28) je a je Sateen a siceem oe A eso aoe? Teese tw ad 082109; WIE. 7B O8rtl el _ THA mie cans} r mel "ae nsec wOTES 1. LEAD NO. 4 IDENTIFIED By DOT OR NOTCH. 2 PLASTIC LEADS WILL BE EITHER SOLDER OPED 08 THAEAD Ls Te teao wo VSDENTIFED SY DOT AR NOTCH PLATED IN ACCORDANCE WITH SMI. M-20518 REQUINESRENTS. 1 CERAM OW LEAUS WEL BE. }TMER GOLD OM TIN PLATED I $00, WL 3OR 10 REQLUNEMENTS a verve ia aD as rs commecieo Ty DGND 24-Pin Cerdip (Suffix Q) ; he tT Soro, ee i [ene | tm | eeu jf; Ma tte a fl dk Has toi zan see a x MOTES. LEAD NO. 1 IDENTIFIED BY SOT OR NOTCH. 2 cosow LEADE WAL Of EEA IN one Wt ACCORDANCE WITH SML.54-29590 REQUIREMENTS. 28-Terminal LCCC (Suffix E) 28-Terminal PLCC (Suffix P) 0 1002.80)" 0.086 11.007 Tessa Tearia 0.075 (7 Ott REF _.- + 3 q ahve D Sp se spe ade oeiors q 5 pares Gd ow~SCOB LE UE agecest an p 4 serv iensy | q D rT 6.093 10.3311 NO. | Fiy INDEX q D q b - Ji. onze ses WVuUUuUUvUUU { | sre Vb Se | ; hen E sea - ge en REV. A -13-