MB89857P-SH - Fujitsu - Datasheet.Directory

DS07-12504-5E

FUJITSU SEMICONDUCTOR

DATA SHEET

8-bit Proprietary Microcontroller

CMOS

F2MC-8L MB89860/850 Series

MB89865/867/P867/W867

MB89855/857/P857/W857/T855

■DESCRIPTION

The MB89860/850 series has been developed as a general-purpose version of the F2MC*-8L family consisting

of proprietary 8-bit, single-chip, microcontrollers.

In addition to the F2MC-8L CPU core which can operate at low voltage but at high speed, the microcontrollers

contain a variety of peripheral functions such as a timer unit, PWM timers, a UART, a serial interface, a 10-bit

A/D converter, and an external interrupt.

The MB89860/850 series is applicable to a wide range of applications from welfare products to industrial

equipment, including portable devices.

*: F2MC stands for FUJITSU Flexible Microcontroller.

■FEATURES

• Various package options

QFP package (80 pins): MB89860

SDIP package (64 pins): MB89850

• High-speed processing at low voltage

Minimum execution time: 0.4 µs/3.5 V, 0.8 µs/2.7 V

(Continued)

■PACKAGE

80-pin Plastic QFP

(FPT-80P-M06)

64-pin Plastic SH-DIP

(DIP-64P-M01)

80-pin Ceramic QFP

(FPT-80C-A02)

64-pin Plastic SH-DIP

(DIP-64C-A06)

MB89860/850 Series

(Continued)

•F

2MC-8L family CPU core Multiplication and division instructions

16-bit arithmetic operations

Test and branch instructions

Bit manipulation instructions, etc.

• 8-bit PWM timers: 2 channels

Also usable as a reload timer

•UART

Full-duplex double buffer

Synchronous and asynchronous data transfer

• 8-bit serial I/O

Switchable transfer direction allows communication with various equipment.

• 10-bit A/D converter

Conversion time: 13.2 µs

Activation by an external input or a timer unit capable

• External interrupt: 4 channels

Four channels are independent and capable of wake-up from low-power consumption modes (with an edge

detection function).

• Low-power consumption modes

Stop mode (Oscillation stops to minimize the current consumption.)

Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.)

• Bus interface functions

Including hold and ready functions

• Timer unit

Outputs non-overlap three-phase waveforms to control an AC inverter motor.

Also usable as a PWM timer (4 channels)

Instruction set optimized for controllers

MB89860/850 Series

■PRODUCT LINEUP

* :Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)

MB89865 MB89857 MB89867 MB89P857

MB89W857 MB89P867

MB89W867

Classification Mass production products (mask ROM products) One-time PROM pruducts/

EPROM products, also

used for evaluation

ROM size 16 K × 8 bits

(internal mask ROM)

Note: In MB89T855, no

internal R OM can be used but

external ROM is used.

32 K × 8 bits

(internal mask ROM) 32 K × 8 bits

(internal PROM,

programming with general-

purpose EPROM

programmer)

RAM size 512 × 8 bits 1 K × 8 bits

CPU functions Number of instructions: 136

Instruction bit length: 8 bits

Instruction length: 1 to 3 bytes

Data bit length: 1, 8, 16 bits

Minimum execution time: 0.4 µs/10 MHz

Interrupt processing time: 3.6 µs/10 MHz

Ports Input ports: 5 (All also serve as peripherals)

Output ports (N-ch open drain): 8 (All also serve as peripherals)

I/O ports (N-ch open drain): 15 (MB89860 series only)

Output ports (CMOS): 8 (All also serve as bus control pins)

I/O ports (CMOS): 32 (All also serve as bus pins or peripherals)

Total: 68 (53 pins for MB89850 series)

Timer unit 10-bit up/down count timer × 1

Compare registers with buffer × 4

Compare timer unit clear register with buffer × 1

Zero detection pin control

4 output channels

Non-overlap three-phase waveform output

Independent three-phase dead-time timer

8-bit PWM timer 1,

8-bit PWM timer 2 8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 µs to

25.6 µs)

8-bit resolution PWM operation (conversion cycle: 102 µs to 6.528 ms)

UART 8 bits

Clock synchronous/asynchronous data transfer capable

8-bit serial I/O 8 bits

LSB first/MSB first selectability

One clock selectable from four transfer clocks

(one external shift clock, three internal shift clocks: 0.8 µs, 3.2 µs, 12.8 µs)

10-bit A/D converter 10-bit resolution × 8 channels

A/D conversion time: 13.2 µs

Continous activation by a compare channel 0 in timer unit or an external activation capable

External interrupt 4 independent channels (edge selection, interrupt vector, source flag)

Rising edge/falling edge selectability.

Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.)

Standby modes Sleep mode, stop mode

Process CMOS

Operating voltage* 2.7 V to 6.0 V 2.7 V to 5.5 V

MB89855

MB89T855

Parameter

Part number

MB89860/850 Series

■PACKAGE AND CORRESPONDING PRODUCTS

: Available × : Not available

Note: For more information about each package, see section “■ Package Dimensions.”

■DIFFERENCES AMONG PRODUCTS

1. Memory Size

Before evaluating using the OTPROM (one-time PROM) products (also used for evaluation), verify its differences

from the product that will actually be used.

Take particular care on the following point:

• The stack area, etc., is set at the upper limit of the RAM.

2. Current Consumption

When operated at lo w speed, the product with an OTPROM or an EPROM will consume more current than the

product with a mask ROM.

However, the current consumption in sleep/stop modes is the same.

3. Mask Options

In the MB89P857/W857/P867/W867/T855, no option can be set.

Before using options check section “■ Mask Options.”

Take particular care on the following point:

• A pull-up resistor can be set for P00 to P07, P10 to P17 and P20 to P27 only at single-chip mode.

Package MB89855

MB89T855

MB89857

MB89P857 MB89W857 MB89865

MB89867

MB89P867 MB89W867

DIP-64P-M01 ×××

DIP-64C-A06 ×××

FPT-80P-M06 ×× ×

FPT-80C-A02 ×××

MB89860/850 Series

■PIN ASSIGNMENT

P31/SO1

P30/SCK1

P47/TRGI

P46/Z

P45/Y

P44/X

P43/RTO3/W

P42/RTO2/V

P41/RTO1/U

P40/RTO0

P50/AN0

P51/AN1

P52/AN2

P53/AN3

P54/AN4

P55/AN5

P56/AN6

P57/AN7

AVCC

AVR

AVSS

P64/DTTI

P63/INT3/ADST

P62/INT2

P61/INT1

P60/INT0

RST

MOD0

MOD1

VSS

VCC

P32/SI1

P33/SCK2

P34/SO2

P35/SI2

P36/PTO1

P37/PTO2

VSS

P00/AD0

P01/AD1

P02/AD2

P03/AD3

P04/AD4

P05/AD5

P06/AD6

P07/AD7

P10/A08

P11/A09

P12/A10

P13/A11

P14/A12

P15/A13

P16/A14

P17/A15

P20/BUFC

P21/HAK

P22/HRQ

P23/RDY

P24/CLK

P25/WR

P26/RD

P27/ALE

(DIP-64P-M01)

(DIP-64C-A06)

(Top view)

MB89860/850 Series

P82

P81

P80

P76

P75

P74

P73

P72

P71

P70

MOD0

MOD1

VSS

RST

P27/ALE

P26/RD

P25/WR

P24/CLK

P23/RDY

P22/HRQ

P21/HAK

P20/BUFC

N.C.

P40/RTO0

P41/RTO1/U

P42/RTO2/V

P43/RTO3/W

P44/X

VSS

P45/Y

P46/Z

VCC

P47/TRGI

P60/INT0

P61/INT1

P62/INT2

P63/INT3/ADST

P64/DTTI

P30/SCK1

P31/SO1

P32/SI1

P33/SCK2

P34/SO2

P35/SI2

P36/PTO1

P37/PTO2

P83

AVSS

AVR

AVCC

P57/AN7

P56/AN6

P55/AN5

P54/AN4

P53/AN3

P52/AN2

P51/AN1

P50/AN0

P84

P85

P86

P87

P17/A15

P16/A14

P15/A13

P14/A12

P13/A11

P12/A10

P11/A09

P10/A08

P07/AD7

P06/AD6

P05/AD5

P04/AD4

P03/AD3

P02/AD2

P01/AD1

P00/AD0

(FPT-80P-M06)

(Top view)

(FPT-80C-A02)

MB89860/850 Series

■PIN DESCRIPTION

(Continued)

*1: DIP-64P-M01, DIP-64C-A06

*2: FPT-80P-M06, FPT-80C-A02

Pin no. Pin name Circuit

type Function

SH-DIP*1 QFP*2

30 13 X0 A Crystal oscillator pins (10 MHz)

31 14 X1

28 11 MOD0 B Operating mode selection pins

Connect directly to VCC or VSS.

29 12 MOD1

27 16 RST C Reset I/O pin

This pin is an N-ch open-drain output type with a pull-up

resistor , and a h ysteresis input type. “L” is output from this

pin by an internal reset source. The internal circuit is

initialized by the input of “L”.

56 to 49 40 to 33 P00 /AD0 to

P07/AD7 D General-pur pose I/O ports

When an external bus is used, these ports function as

multiplex pins of lower address output and data I/O.

48 to 41 32 to 25 P10 /A08 to

P17/A15 D General-pur pose I/O ports

When an external bus is used, these ports function as

upper address output.

40 24 P20/BUFC F General-purpose output port

When an external bus is used, this port can also be used

as a buffer control output.

39 23 P21/HAK F General-purpose output port

When an external bus is used, this port can also be used

as a hold acknowledge output.

38 22 P22/HRQ D General-purpose output port

When an external bus is used, this port can also be used

as a hold request input.

37 21 P23/RDY D General-purpose output port

When an external bus is used, this port functions as a

ready input.

36 20 P24/CLK F General-purpose output port

When an external bus is used, this port functions as a

clock output.

35 19 P25/WR F General-purpose output port

When an external bus is used, this port functions as a

write signal output.

34 18 P26/RD F General-purpose output port

When an external bus is used, this port functions as a

read signal output.

33 17 P27/ALE F General-purpose output port

When an external bus is used, this port functions as an

address latch signal output.

2 48 P30/SCK1 E General-purpose I/O port

Also serves as the clock I/O for the UART.

This port is a hysteresis input type.

MB89860/850 Series

(Continued)

*1: DIP-64P-M01, DIP-64C-A06

*2: FPT-80P-M06, FPT-80C-A02

Pin no. Pin name Circuit

type Function

SH-DIP*1 QFP*2

1 47 P31/SO1 E General-purpose I/O port

Also serves as the data output for the UART.

This port is a hysteresis input type.

63 46 P32/SI1 E General-purpose I/O port

Also serves as the data input for the UART.

This port is a hysteresis input type.

62 45 P33/SCK2 E General-purpose I/O port

Also serves as the clock I/O for the 8-bit serial I/O.

This port is a hysteresis input type.

61 44 P34/SO2 E General-purpose I/O port

Also serves as the data output for the 8-bit serial I/O.

This port is a hysteresis input type.

60 43 P35/SI2 E General-purpose I/O port

Also serves as the data input for the 8-bit serial I/O.

This port is a hysteresis input type.

59 42 P36/PTO1 E General-purpose I/O port

Also serv es as the pulse output for the 8-bit PWM timer 1.

This port is a hysteresis input type.

58 41 P37/PTO2 E General-purpose I/O port

Also serv es as the pulse output for the 8-bit PWM timer 2.

This port is a hysteresis input type.

10 63 P40/RTO0 E General-purpose I/O port

Also serves as the pulse output for the timer unit.

This port is a hystereisis input type.

62,

61,

P41/RTO1/U,

P42/RTO2/V,

P43/RTO3/W

E General-pur pose I/O ports

Also serve as the pulse output for the timer unit or a non-

overlap three-phase waveform output.

These ports are a hysteresis input type.

59,

57,

P44/X,

P45/Y,

P46/Z

E General-pur pose I/O ports

Also serve as a non-overlap three-phase output.

These ports are a hysteresis input type.

3 54 P47/TRGI E General-purpose I/O port

Also serves as the trigger input for the timer unit.

This port is a hysteresis input type.

11 to 18 69 to 76 P50/AN0 to

P57/AN7 H N-ch open-drain output ports

Also serve as the analog input for the A/D converter.

26 to 24 53 to 51 P60/INT0 to

P62/INT2 I General-purpose input ports

Also serve as an external interrupt input.

These ports are a hysteresis input type.

23 50 P63/INT3/

ADST I General-purpose input port

Also serves as an external interrupt input and as the

activation trigger input for the A/D converter.

This port is a hysteresis input type.

MB89860/850 Series

(Continued)

*1: DIP-64P-M01, DIP-64C-A06

*2: FPT-80P-M06, FPT-80C-A02

Pin no. Pin name Circuit

type Function

SH-DIP*1 QFP*2

22 49 P64/DTTI I General-purpose input port

Also serves as a dead-time timer disable input.

This port is a hysteresis input type.

DTTI input is with a noise canceller.

— 10 to 4 P70 to P76 G N-ch open-drain I/O ports

These ports are a hysteresis input type.

— 3 to 1, 80,

68 to 65 P80 to P87 G N-ch open-drain I/O ports

These ports are a hysteresis input type.

64 55 VCC — Power supply pin

32, 57 15, 58 VSS — Power supply (GND) pins

19 77 AVCC — A/D converter power supply pin

20 78 AVR — A/D converter reference voltage input pin

21 79 AVSS — A/D converter power supply (GND) pin

Use this pin at the same voltage as VSS.

— 64 N.C. — Internally connected pin

Be sure to leave it open.

MB89860/850 Series

■I/O CIRCUIT TYPE

(Continued)

Type Circuit Remarks

A • At an oscillation feedback resitor of approximately

1 MΩ/5.0 V

C • At an output pull-up resistor (P-ch) of approximately

50 kΩ/5.0 V

• Hysteresis input

D•CMOS output

•CMOS input

• Pull-up resistor optional (Mask ROM products)

• At a pull-up resistor of approximately 50 kΩ/5.0 V

E•CMOS output

• Hysteresis input

• Pull-up resistor optional (Mask ROM products)

• At a pull-up resistor of approximately 50 kΩ/5.0 V

Standby control signal

P-ch

N-ch

P-ch

N-ch

P-ch

N-ch

P-ch

MB89860/850 Series

(Continued)

Type Circuit Remarks

F•CMOS output

• Pull-up resistor optional (Mask ROM products)

• At a pull-up resistor of approximately 50 kΩ/5.0 V

G • N-ch open-drain output

• Hysteresis input

• Pull-up resistor optional (Mask ROM products)

• At a pull-up resistor of approximately 50 kΩ/5.0 V

H • N-ch open-drain output

• Analog input

I • Hysteresis input

• Pull-up resistor optional (Mask ROM products)

• At a pull-up resistor of approximately 50 kΩ/5.0 V

P-ch

N-ch

P-ch

N-ch

P-ch

N-ch

Analog input

MB89860/850 Series

■HANDLING DEVICES

1. Preventing Latchup

Latchup ma y occur on CMOS ICs if v oltage higher than VCC or lower than VSS is applied to input and output pins

other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum

Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS.

When latchup occurs, power supply current increases rapidly and might thermally damage elements. When

using, take great care not to exceed the absolute maximum ratings.

Also , tak e care to prev ent the analog pow er supply (AVCC and AVR) and analog input from e xceeding the digital

power supply (VCC) when the analog system power supply is turned on and off.

2. Treatment of Unused Input Pins

Leaving un used input pins open could cause malfunctions . The y should be connected to a pull-up or pull-down

resistor.

3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters

Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.

4. Treatment of N.C. Pin

Be sure to leave (internally connected) N.C. pin open.

5. Power Supply Voltage Fluctuations

Although VCC power supply voltage is assured to operate within the rated range , a rapid fluctuation of the voltage

could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore

impor tant. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P

value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient

fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.

6. Precautions when Using an External Clock

Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and

wake-up from stop mode.

MB89860/850 Series

■PROGRAMMING TO THE EPROM ON THE MB89P867/W867/P857/W857

The MB89P867/W867/P857/W857 are an OTPROM version of the MB89860/850 ser ies.

1. Features

• 32-Kbyte PROM on chip

• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)

2. Memory Space

Memory space in EPROM mode is diagrammed below.

3. Programming to the EPROM

In EPR OM mode, the MB89P867/W867/P857/W857 functions equiv alent to the MBM27C256A. This allows the

PR OM to be prog r ammed with a general-purpose EPROM prog r ammer (the electronic signature mode cannot

be used) by using the dedicated socket adapter.

• Programming procedure

(1) Set the EPROM programmer to the MBM27C256A.

(2) Load program data into the EPROM programmer at 0000H to 7FFFH (note that addresses 8000H to FFFFH

while operating as a single chip assign to addresses 0000H to 7FFFH in EPROM mode.)

(3) Program to 0000H to 7FFFH with the EPROM programmer.

0480H

8000H

FFFFH

0080H

0000H

PROM

32 KB

Not available

RAM

I/O

0000H

7FFFH

EPROM

32 KB

Single chip EPROM mode

( Corresponding addresses on the EPROM programmer)

Address

MB89860/850 Series

4. Recommended Screening Conditions

High-temperature aging is recommended as the pre-assembly screening procedure for a product with a b lanked

OTPROM microcomputer program.

5. Programming Yield

All bits cannot be programmed at Fujitsu shipping test to a b lank ed OTPROM microcomputer, due to its nature.

For this reason, a programming yield of 100% cannot be assured at all times.

6. Erasure

In order to clear all locations of their progra mmed contents, it is necessary to e xpose the internal EPROM to an

ultra violet light source. A dosage of 10 W -seconds/cm2 is required to completely erase an internal EPROM. This

dosage can be obtained by exposure to an ultraviolet lamp (wavelength of 2537 Angstroms (Å)) with intensity

of 12000 µW/cm2 for 15 to 21 minutes. The internal EPROM should be about one inch from the source and all

filters should be removed from the UV light source prior to erasure.

It is important to note that the internal EPROM and similar devices, will erase with light sources having

wavelengths shor ter than 4000 Å. Although erasure time will be much longer than with UV source at 2537 Å,

nevertheless the exposure to fluorescent light and sunlight will eventually erase the internal EPROM, and

exposure to them should be prevented to realize maximum system reliability. If used in such an environment,

the package windows should be covered by an opaque label or substance.

7. EPROM Pr ogrammer Socket Adapter

* : Connect the adapter jumper pin to VSS when using.

Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760

Package Compatible socket adapter

DIP-64P-M01 ROM-64SD-28DP-8L*

FPT-80P-M01 ROM-80QF-28DP-8L2

Program, verify

Aging

+150°C, 48 Hrs.

Data verification

Assembly

MB89860/850 Series

■BLOCK DIAGRAM

Oscillator

Clock controller

Time-base timer

External bus

interface

CMOS output port

F2MC-8L

RAM

VCC , VSS × 2

RST

P00/AD0

to P07/AD7

ROM

8-bit serial I/O

N-ch open-drain output port

P47/TRGI

P46/Z

P45/Y

P44/X

P43/RTO3/W

P42/RTO2/V

P41/RTO1/U

P40/RTO0

P35/SI2

Reset circuit

(WDT)

CPU

CMOS I/O port

10-bit A/D converter

External interrupt

8-bit PWM timer 2

P64/DTTI

P60/INT0

to P62/INT2

AVR

8-bit PWM timer 1

UART

Timer unit

(Dead-time timer)

N-ch open-drain I/O port

Port 7 and port 8

CMOS I/O port

Input port

P34/SO2

P33/SCK2

P32/SI1

P31/SO1

P30/SCK1

8 8

4 3

P37/PTO2

P63/INT3/ADST

AVCC

AVSS

P80 to P87

P50/AN0

to P57/AN7

P70 to P76

P10/A08

to P17/A15

P27/ALE

P26/RD

P25/WR

P24/CLK

P23/RDY

P22/HRQ

P21/HAK

P20/BUFC

MOD0

MOD1

*2: Not included in the MB89850 series.

P36/PTO1

CMOS I/O port

Port 6 Port 4 Port 3

Port 2 Port 0 and port 1

Internal bus

Port 5

Part number RAM size ROM size

MB89865/855/T855*1

MB89857/867

MB89W857/P867

512 bytes

1 Kbyte

16 Kbytes

32 Kbytes

(EPROM)

*1: In the MB89T855, an external ROM can be used.

Other pins

MB89860/850 Series

■CPU CORE

1. Memory Space

The microcontrollers of the MB89860/850 series offer a memory space of 64 Kbytes for storing all of I/O, data,

and progra m areas. The I/O area is located at the low est address. The data area is provided immediately abo ve

the I/O area. The data area can be divided into register, stack, and direct areas according to the application.

The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables

of interrupt reset vectors and vector call instr uctions toward the highest address within the program area. The

memory space of the MB89860/850 series is structured as illustrated below.

Memory Space

ROM

FFFFH

0080H

0000H

I/O

MB89865

MB89855/T855*

C000H

0200H

ROM

I/O

RAM

512 B

RAM

1 KB

0280H

External area

0100H

FFFF H

0080H

0000H

0200H

0480H

0100H

8000H

MB89867/857

MB89W867/P867

MB89W857/P857

*1: The ROM area is an external area depending on the mode.

*2: In the MB89T855, an external ROM can be used.

16 KB

32 KB

MB89860/850 Series

2. Registers

The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-pur pose registers

in the memory. The following dedicated registers are provided:

Program counter (PC): A 16-bit register for indicating instruction storage positions

Accumulator (A): A 16-bit temporary register for storing arithmetic operations, etc. When the

instruction is an 8-bit data processing instruction, the lower byte is used.

Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator

When the instruction is an 8-bit data processing instruction, the lower byte is used.

Index register (IX): A 16-bit register for index modification

Extra pointer (EP): A 16-bit pointer for indicating a memory address

Stack pointer (SP): A 16-bit register for indicating a stack area

Progr am status (PS): A 16-bit register for storing a register pointer, a condition code

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for

use as a condition code register (CCR). (See the diagram below.)

16 bits

: Program counter

: Accumulator

: Temporary accumulator

: Index register

: Extra pointer

: Stack pointer

: Program status

FFFDH

Undefined

I-flag = 0, IL1, 0 = 11

Other bits are undefined.

Initial value

Structure of the Program Status Register

Vacancy Vacancy Vacancy

H I IL1, 0 N Z VC

RPPS

109876 321015 14 13 12 11

RP CCR

MB89860/850 Series

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents

and the actual address is based on the conversion rule illustrated below.

The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and

bits for control of CPU operations at the time of an interrupt.

H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared

otherwise. This flag is for decimal adjustment instructions.

I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0

when reset.

IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is

higher than the value indicated by this bit.

N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.

Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise.

V-flag: Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does

not occur.

C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.

Set to the shift-out value in the case of a shift instruction.

IL1 IL0 Interrupt level High-low

00 1High

Low = no interrupt

10 2

11 3

Rule for Conversion of Actual Addresses of the General-purpose Register Area

“0”

↓

A15

“0”

↓

A14

“0”

↓

A13

“0”

↓

A12

“0”

↓

A11

“0”

↓

A10

“0”

↓

“1”

↓

Lower OP codes

Generated addresses

MB89860/850 Series

The following general-purpose registers are provided:

General-purpose registers: An 8-bit register for storing data

The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains

eight registers and up to a total of 32 banks can be used on the MB89860/850 series. The bank currently in use

is indicated by the register bank pointer (RP).

Note: The number of register banks that can be used varies with the RAM size.

This address = 0100H + 8 × (RP)

Memory area

32 banks

R 0

R 1

R 2

R 3

R 4

R 5

R 6

R 7

MB89860/850 Series

■I/O MAP

(Continued)

Address Read/write Register name Register description

00H(R/W) PDR0 Port 0 data register

01H(W) DDR0 Port 0 data direction register

02H(R/W) PDR1 Port 1 data register

03H(W) DDR1 Port 1 data direction register

04H(R/W) PDR2 Port 2 data register

05H(W) BCTR External bus pin control register

06HVacancy

07HVacancy

08H(R/W) STBC Standby control register

09H(W) WDTC Watchdog timer control register

0AH(R/W) TBTC Time-base timer control register

0BHVacancy

0CH(R/W) PDR3 Port 3 data register

0DH(W) DDR3 Port 3 data direction register

0EH(R/W) PDR4 Port 4 data register

0FH(W) DDR4 Port 4 data direction register

10H(R/W) PDR5 Port 5 data register

11HVacancy

12H(R) PDR6 Port 6 data register

13HVacancy

14H(R/W) PDR7 Port 7 data register

15HVacancy

16H(R/W) PDR8 Port 8 data register

17H to 1BHVacancy

1CH(R/W) CTR1 PWM control register 1

1DH(W) CMR1 PWM compare register 1

1EH(R/W) CTR2 PWM control register 2

1FH(W) CMR2 PWM compare register 2

20H(R/W) SMC UART serial mode control register

21H(R/W) SRC UART serial rate control register

22H(R/W) SSD UART serial status/data register

23H(R/W) SIDR/SODR UART serial data register

24H(R/W) SMR Serial mode register

25H(R/W) SDR Serial data register

MB89860/850 Series

(Continued)

Notes: • Do not use vacancies.

• When a read-modify-write instruction (such as bit set) is used to access a write-only register or a register

containing a write-only bit, a bit designated by the instruction will have a predeter mined value. However,

a write-only bit included, if any, in bits not defined by the instruction will cause a malfunction. So no access

to the register should be tried with any read-modefy-write instruction.

Address Read/write Register name Register description

26H(R/W) EIC1 External interrupt control register 1

27H(R/W) EIC2 External interrupt control register 2

28H(R/W) ADC1 A/D converter control register 1

29H(R/W) ADC2 A/D converter control register 2

2AH(R) ADDH A/D converter data register (H)

2BH(R) ADDL A/D converter data register (L)

2CHVacancy

2DH(W) ZOCTR Zero detection output control register

2EH(W) CLRBRH Compare clear buffer register (H)

2FH(W) CLRBRL Compare clear buffer register (L)

30H(R/W) TCSR Timer control status register

31H(R/W) CICR Compare interrupt control register

32H(R/W) TMCR Timer mode control register

33H(R/W) COER Compare/port selection register

34H(R/W) C MCR Compare buffer mode control register

35H(R/W) DTCR Dead-time timer control register

36H(W) DTSR Dead-time setting register

37H(R/W) OCTBR Output control buffer register

38H(W) OCPBR0H Output compare buffer register 0 (H)

39H(W) OCPBR0L Output compare buffer register 0 (L)

3AH(W) OCPBR1H Output compare bu ffer register 1 (H)

3BH(W) OCPBR1L Output compare buffer register 1 (L)

3CH(W) OCPBR2H Output compare buffer register 2 (H)

3DH(W) OCPBR2L Output compare buffer register 2 (L)

3EH(W) OCPBR3H Output compare bu ffer register 3 (H)

3FH(W) OCPBR3L Output compare buffer register 3 (L)

40H to 7BHVacancy

7CH(W) ILR1 Interrupt level setting register 1

7DH(W) ILR2 Interrupt level setting register 2

7EH(W) ILR3 Interrupt level setting register 3

7FHVacancy

MB89860/850 Series

■ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(AVSS = VSS = 0.0 V)

*: Use AVCC and VCC set at the same voltage.

Take care so that AVCC does not ex ceed VCC, such as when power is turned on.

Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded.

Functional operation should be restricted to the conditions as detailed in the operational sections of

this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

Parameter Symbol Value Unit Remarks

Min. Max.

Power supply voltage VCC

AVCC VSS – 0.3 VSS + 7.0 V *

A/D converter reference input

voltage AVR VSS – 0.3 VSS + 7.0 V AVR must not exceed AVCC +

0.3 V.

Program voltage VPP VSS – 0.3 13.0 V MOD1 pins of MB89P867/

W867 and MB89P857/W857

Input voltage VIVSS – 0.3 VCC + 0.3 V

Output voltage VOVSS – 0.3 VSS + 0.3 V

“L” level maximum output current IOL —20mA

“L” level average output current IOLAV1 —4mA

P00 to P07, P10 to P17,

P20 to P27, P30 to P37,

P50 to P57, P70 to P76,

P80 to P87

IOLAV2 — 15 mA P40 to P47

“L” level total average output

current ΣIOLAV1 —30mA

P00 to P07, P10 to P17,

P20 to P27, P30 to P37,

P50 to P57, P70 to P76,

P80 to P87

ΣIOLAV2 — 50 mA P40 to P47

“H” level maximum output current IOH —–20mA

“H” level average output current IOHAV —–4mA

“H” level total maximum output

current ΣIOH —–20mA

Power consumption PD—300mW

Operating temperature TA–40 +85 °C

Storage temperature Tstg –55 +150 °C

MB89860/850 Series

2. Recommended Operating Conditions

(AVSS = VSS = 0.0 V)

*: These values vary with the operating frequency, instruction cycle, and analog assurance range. See Figure 1

and “5. A/D Converter Electrical Characteristics.”

Note: Connect the MOD0 and MOD1 pins to VCC or VSS.

Figure 1 Operating Voltage vs. Clock Operating Frequency

Parameter Symbol Value Unit Remarks

Min. Max.

Power supply voltage VCC

AVCC

2.7* 6.0* V Normal operation assurance

range*

MB89867/865, MB89857/855

2.7* 5.5* V Normal operation assurance

range*

MB89P867/W867,

MB89P857/W855/T855

1.5 6.0 V Retains the RAM state in stop

mode

A/D converter reference input

voltage AVR 0.0 AVCC V

Operating temperature TA–40 +85 °C

Operation assurance range

Operating voltage (V)

Clock operating frequency (MHz)

2345678910

5.5

Analog accuracy assured in the

VCC = AVCC = 3.5 V to 6.0 V range

4.0 2.0 0.8 0.4 (µs)

Minimum execution time (instruction cycle)

Note: The shaded area is assured only for the MB89865/867/855/857.

MB89860/850 Series

3. DC Characteristics

(AVCC = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Parameter Symbol Pin Condition Value Unit Remarks

Min. Typ. Max.

“H” level input

voltage

VIH P00 to P07, P10 to P17,

P22, P23 —0.7 VCC —VCC +

0.3 V

VIHS RST, P30 to P37,

P40 to P47, P60 to P64,

P70 to P76, P80 to P87 —0.8 VCC —VCC +

0.3 V

“L” level input

voltage

VIL P00 to P07, P10 to P17,

P22, P23 —VSS –

0.3 — 0.3 VCC V

VILS RST, P30 to P37,

P40 to P47, P60 to P64,

P70 to P76, P80 to P87 —VSS –

0.3 — 0.2 VCC V

“H” level output

voltage VOH P00 to P07, P10 to P17,

P20 to P27, P30 to P37,

P40 to P47 IOH = –2.0

mA 2.4 — — V

“L” level output

voltage VOL1

P00 to P07, P10 to P17,

P20 to P27, P30 to P37,

P50 to P57, P70 to P76,

P80 to P87 IOL = 1.8 mA — — 0.4 V

VOL2 P40 to P47 IOL = 15 mA — — 1.5 V

Input leackage

current ILI1

P00 to P07, P10 to P17,

P20 to P27, P30 to P37,

P40 to P47, P60 to P64,

P70 to P76, P80 to P87,

MOD0, MOD1

0.0 V < VI <

VCC ——±5µA

Pull-up resistance RPULL RST VI = 0.0 V 25 50 100 kΩWith pull-

up resistor

Power supply

current

ICC

VCC

FC = 10 MHz

Normal

operation

mode

(External

clock)

—1518mA

ICCS

FC = 10 MHz

Sleep mode

(External

clock) —6 8mA

ICCH Stop mode

TA = +25°C——10µA

IAAVCC

FC = 10 MHz,

when A/D

conv ersion is

activated —6—mA

Input capacitance CIN Other than AVCC,

AVSS, VCC, and VSS f = 1 MHz — 10 — pF

MB89860/850 Series

4. AC Characteristics

(1) Reset Timing

(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

* :tXCYL is the oscillation cycle (1/FC) to input to the X0 pin.

(2) Power-on Reset

(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Note: Make sure that power supply rises within the selected oscillation stabilization time.

If power supply v oltage needs to be varied in the course of operation, a smooth voltage rise is recommended.

Parameter Symbol Condition Value Unit Remarks

Min. Max.

RST “L” pulse width tZLZH — 16 t XCYL*— ns

Parameter Symbol Condition Value Unit Remarks

Min. Max.

Power supply rising time tR—— 50 ms Power-on reset function only

Power supply cut-off time tOFF 1 — ms Due to repeated operations

0.2 VCC 0.2 VCC

RST

t ZLZH

0.2 V 0.2 V

2.0 V

VCC 0.2 V

tRtOFF

MB89860/850 Series

(3) Clock Timing (AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

(4) Instruction Cycle

Parameter Symbol Pin Condition Value Unit Remarks

Min. Max.

Clock frequency FCX0, X1

—

110MHz

Clock cycle time tXCYL 100 1000 ns

Input clock pulse width PWH

PWL X0 20 — ns External clock

Input clock rising/falling time tCR

tCF — 10 ns External clock

Parameter Symbol Value (typical) Unit Remarks

Instruction cycle

(minimum ex ecution time) tinst 4/FCµstinst = 0.4 µs when operating at

FC = 10 MHz

0.2 VCC

0.8 VCC

X0 0.2 VCC

0.8 VCC

0.2 VCC

X0 X1 X0 X1

When a crystal

ceramic resonator is used When an external clock is used

Open

tXCYL PWL

PWH tCFtCR

X0 and X1 Timing Conditions

Clock Conditions

MB89860/850 Series

(5) Recommended Resonator Manufacturers

Inquiry: FUJITSU LIMITED

FAR part number

(built-in capacitor type) Frequency Initial deviation of

FAR frequency (TA = +25°C) Temperature characteristics

of FAR frequency

(TA = –25°C to +60°C)

FAR-C4CB-08000-M02 8.00 MHz ±0.5% ±0.5%

FAR-C4CB-10000-M02 10.00 MHz ±0.5% ±0.5%

X0 X1 *

FAR

C1 C2

*: Fujitsu Acoustic Resonator

C1 = C2 = 20 pF±8 pF (built-in FAR)

Sample Application of Piezoelectric Resonator (FAR Series)

MB89860/850 Series

Inquiry: Kyocera Corporation

•AVX Corporation

North American Sales Headquarters: TEL 1-803-448-9411

•AVX Limited

European Sales Headquarters: TEL 44-1252-770000

•AVX/Kyocera H.K. Ltd.

Asian Sales Headquarters: TEL 852-363-3303

Murata Mfg. Co., Ltd.

•Murata Electronics North America, Inc.: TEL 1-404-436-1300

•Murata Europe Management GmbH: TEL 49-911-66870

•Murata Electronics Singapore (Pte.) Ltd.: TEL 65-758-4233

Resonator manufacturer* Resonator Frequency C1 (pF) C2 (pF) R (kΩ)

Kyocera Cor poration KBR-7.68MWS 7.68 MHz 33 33 —

KBR-8.0MWS 8.0 MHz 33 33 —

Murata Mfg. Co., Ltd. CSA8.00MTZ 8.0 MHz 30 30 —

Sample Application of Ceramic Resonator

C1 C2

MB89860/850 Series

(6) Clock Output Timing (VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Parameter Symbol Pin Condition Value Unit Remarks

Min. Max.

Cycle time tCYC CLK Load

condition:

50 pF

200 — ns tXCYL × 2 at 10 MHz

oscillation

CLK ↑ → CLK ↓tCHCL 30 100 ns Approx. tCYC/2 at

10 MHz oscillation

2.4 V

0.8 V

2.4 V

CLK

t CYC

t CHCL

MB89860/850 Series

(7) Bus Read Timing (VCC = +5.0 V±10%, FC = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

* :For information on tinst, see “(4) Instruction Cycle.”

Parameter Symbol Pin Condition Value (10 MHz) Unit Remarks

Min. Max.

Valid address → RD ↓

time tAVRL RD, A15 to A08,

AD7 to AD0

Load

condition:

50 pF

1/4 tinst* – 64 ns —ns

RD pulse width tRLRH RD 1/2 tinst* – 20 ns —ns

Valid address → data

read time tAVDV AD7 to AD0,

A15 to A08 —1/2 t

inst*nsNo wait

RD ↓ → data read time tRLDV RD, AD7 to AD0 —1/2 tinst* – 80 ns ns No wait

RD ↑ → data hold time tRHDX AD7 to AD0, RD 0—ns

RD ↑ → ALE ↑ time tRHLH RD, ALE 1/4 tinst* – 40 ns —ns

RD ↑ → address invalid time tRHAX RD, A15 to A08 1/4 tinst* – 40 ns —ns

RD ↓ → CLK ↑ time tRLCH RD, CLK 1/4 tinst* – 60 ns —ns

CLK ↓ → RD ↑ time tCLRH 0—ns

RD ↓ → BUFC ↓ time tRLBL RD, BUFC –5 — ns

BUFC ↑ → valid

address time tBHAV A15 to A08,

AD7 to AD0,

BUFC 5—ns

ALE

BUFC

CLK 2.4 V 0.8 V

0.8 V

2.4 V

0.8 V

0.7 VCC

0.3 VCC

0.7 VCC

0.3 VCC

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

tRHDX

tBHAVtRLBL

tCLRH

tRHLH

tAVDV

tRLCH

tRLDV tRHAX

tRLRH

tAVRL

MB89860/850 Series

(8) Bus Write Timing

(VCC = +5.0 V±10%, FC = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

*1: For information on tinst, see “(4) Instruction Cycle.”

*2: These characteristics are also applicable to the bus read timing.

Parameter Symbol Pin Condition Value (10 MHz) Unit Remarks

Min. Max.

Valid address → ALE ↓ time tAVLL AD7 to AD0,

ALE, A15 to

A08

Load

condition:

50 pF

1/4 tinst*1 – 64 ns —ns

ALE ↓ time → address

invalid time tLLAX 5—ns

Valid address → WR ↓ time tAVWL WR, ALE 1/4 tinst*1 – 60 ns —ns

WR pulse width tWLWH WR 1/2 tinst*1 – 20 ns —ns

Write data → WR ↑ time tDVWH AD7 to AD0, WR 1/2 tinst*1 – 60 ns —ns

WR ↑ → address invalid time tWHAX WR, A15 to A08 1/4 tinst*1 – 40 ns —ns

WR ↑ → data hold time tWHDX AD7 to AD0, WR 1/4 tinst*1 – 40 ns —ns

WR ↑ → ALE ↑ time tWHLH WR, ALE 1/4 tinst*1 – 40 ns —ns

WR ↓ → CLK ↑ time tWLCH WR, CLK 1/4 tinst*1 – 60 ns —ns

CLK ↓ → WR ↑ time tCLWH 0—ns

ALE pulse width tLHLL ALE tXCYL – 35 ns*2 —ns

ALE ↓ → CLK ↑ time tLLCH ALE, CLK tXCYL – 35 ns*2 —ns

ALE

CLK 2.4 V 0.8 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V 2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

tCLWH

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

tLLAX

t WHLH

tLLCHtLHLL

tDVWH tWHDX

tWLCH

tWLWH

tWHAX

tAVWL

tAVLL

MB89860/850 Series

(9) Ready Input Timing (VCC = +5.0 V±10%, FC = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

* :These characteristics are also applicable to the read cycle.

Parameter Symbol Pin Condition Value Unit Remarks

Min. Max.

RDY valid → CLK ↑ time tYVCH RDY,

CLK Load condition:

50 pF 60 — ns *

CLK ↑ → RDY invalid time tCHYX 0—ns *

CLK

ALE

RDY

Address

t YVCH t CHYX

2.4 V 2.4 V

Data

0.3 VCC 0.3 VCC

0.7 VCC 0.7 VCC

Note: The bus cycle is also extended in the read cycle in the same manner.

MB89860/850 Series

(10) UART and Serial I/O Timing

(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

* :For information on tinst, see “(4) Instruction Cycle.”

Parameter Symbol Pin Condition Value Unit Remarks

Min. Max.

Serial clock cycle time tSCYC SCK1,SCK2

Internal shift

clock mode

Load

condition:

50 pF

2 tinst*—µs

SCK1 ↓ → SO1 time

SCK2 ↓ → SO2 time tSLOV SCK1, SO1

SCK2, SO2 –200 200 ns

Valid SI1 → SCK1 ↑

Valid SI2 → SCK2 ↑tIVSH SI1, SCK1

SI2, SCK2 1/2 tinst*—µs

SCK1 ↑ → va lid SI1 hold time

SCK2 ↑ → valid SI2 hold time tSHIX SCK1, SI1

SCK2, SI2 1/2 tinst*—µs

Serial clock “H” pulse width tSHSL SCK1, SCK2

External shift

clock mode

Load

condition:

50 pF

1 tinst*—µs

Serial clock “L” pulse width tSLSH 1 tinst*—µs

SCK1 ↓ → SO1 time

SCK2 ↓ → SO2 time tSLOV SCK1, SO1

SCK2, SO2 0 200 ns

Valid SI1 → SCK1 ↑

Valid SI2 → SCK2 ↑tIVSH SI1, SCK1

SI2, SCK2 1/2 tinst*—µs

SCK1 ↑ → va lid SI1 hold time

SCK2 ↑ → valid SI2 hold time tSHIX SCK1, SI1

SCK2, SI2 1/2 tinst*—µs

MB89860/850 Series

0.8 V

2.4 V

tSCYC

2.4 V

tSLOV

0.2 VCC

0.8 V

0.8 VCC

0.2 VCC

0.8 VCC

SCK1

SCK2

SO1

SO2

SI1

SI2

tIVSH tSHIX

t SLSH

2.4 V

t SLOV

0.2 VCC

tSHIX

0.8 VCC

0.8 V

tIVSH

0.8 VCC

0.2 VCC

0.8 VCC

t SHSL

0.8 VCC

0.2 VCC 0.2 VCC

SCK1

SCK2

SO1

SO2

SI1

SI2

Internal Shift Clock Mode

External Shift Clock Mode

MB89860/850 Series

(11) Peripheral Input Timing

(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

* :For information on tinst, see “(4) Instruction Cycle.”

5. A/D Converter Electrical Characteristics

(AVCC = VCC = +3.5 V to +6.0 V, FC = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

* :For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”

Parameter Symbol Pin Condition Value Unit Remarks

Min. Max.

Peripheral input “H”

pulse width 1 tILIH1 TRGI, DTTI,

ADST,

INT0 to INT3

Load

condition:

50 pF

2 tinst*— µs

Peripheral input “L”

pulse width 1 tIHIL1 2 tinst*— µs

Parameter Symbol Pin Condition Value Unit Remarks

Min. Typ. Max.

Resolution

—

AVCC = VCC

— — 10 bit

Linearity error — — ±2.0 LSB

Differential linearity error — — ±1.5 LSB

Total error — — ±3.0 LSB

Zero transition voltage VOT AN0 to

AN7

AVSS –

1.5 AVSS +

0.5 AVSS +

2.5 LSB

Full-scale transition voltage VFST AVR –

3.5 AVR –

1.5 AVR +

0.5 LSB

Interchannel disparity —— —— 4LSB

A/D mode conversion time — — 33 tinst*—µs

Analog port input current IAIN AN0 to

AN7 ———10µA

Analog input voltage —— 0 — AVR V

Reference voltage AVR —0—AV

CC V

Reference voltage supply

current IRAVR = 5.0

V— 200 — µA

0.2 VCC

0.8 VCC

tIHIL1

0.8 VCC

TRGI

DTTI

ADST

INT0 to INT3

0.2 VCC

tILIH1

MB89860/850 Series

(1) A/D Glossary

• Resolution

Analog changes that are identifiable with the A/D converter

• Linearity error

The de viation of the stra ight line connecting the zero tr ansition point (“00 0000 0000” ↔ “00 0000 0001”) with

the full-scale transition point (“11 1111 1111” ↔´“11 1111 1110”) from actual conversion characteristics

• Differential linearity error

The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value

• Total error

The total error indicates the diff erence between the actual v alue and theoretical v alue. This error is caused b y

the zero transition error, full-scale transition error, linearity error, quantization, and noise.

(Continued)

Actual conversion

value

3FF

3FE

3FD

004

003

002

001

VOT

0.5 LSB

AVSS

1 LSB

1.5 LSB

VFST

AVR

3FF

3FE

3FD

004

003

002

001 Theoretical value

AVSS

VNT

AVR

(1 LSB × N + 0.5 LSB)

1 LSB = 1022 (V)

VNT – (1 LSB × N + 0.5 LSB)

1 LSB

Digital output

Total error of digital output “N” =

VFST – VOT

Theoretical I/O value

Analog input

Total error

Analog input

Actual conversion

value

MB89860/850 Series

(Continued)

Actual conversion

value

Actual conversion

value

Actual conversion

value

Actual conversion

value

004

003

002

001

AVSS

VOT (Measured value)

3FF

3FE

3FD

3FC

Theoretical value

AVR

VFST

(Measured value)

Digital output

Zero transition error

Analog input

Full-scale transition error

Analog input

VOT (Measured value)

Theoretical value

Actual conversion

value

Actual conversion

value

Actual conversion

value

Actual conversion

value

Digital output

Linearity error

Analog input

Differential linearity error

Analog input

3FF

3FE

3FD

004

003

002

001

AVSS

VNT

AVR

(1 LSB

N +

VOT

)

1 LSB 1 LSB

VFST

(Measured

value)

N+1

N – 1

N – 2

V(N + 1)T

VNT

V(N + 1)T – VNT – 1

Linearity error of digital output “N” = Differential linearity error of digital output “N” =

VNT – (1 LSB × N + VOT)

MB89860/850 Series

(2) Precautions

• Input impedance of the analog input pins

The A/D conver ter used fo r the MB89860/850 series contains a sample hold circuit as illustrated below to

fetch analog input voltage into the sample hold capacitor for fifteen instruction cycles after activation A/D

conversion.

For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage

might not stabilize within the analog input sampling period. Theref ore , it is recommended to k eep the output

impedance of the external circuit low (below 10 kΩ).

Note that if the impedance connot be kept low, it is recommended to connect an e xternal capacitor of about

0.1 µF for the analog input pin.

•Error

The smaller the | AVR – AVSS |, the greater the error would become relatively.

Anlog input pin

Analog channel selector

Sample hold circuit

C = 64 pF

R = 3 kΩ

Close for 15 instruction cycles

after activating A/D conversion.

Comparator

If the analog input

impedance is higher

than 10 kΩ, it is

recommended to

connect an external

capacitor of approx.

0.1 µF.

Analog Input Equivalent Circuit

MB89860/850 Series

■EXAMPLE CHARACTERISTICS

1000

RPULL (kΩ)

VCC (V)

100

10 to 1123456

TA = +25˚C

RPULL vs. VCC

0.0

1.0

VCC − VOH (V)

VCC = 3.0 V

VCC = 4.0 V

VCC = 5.0 V

VCC = 6.0 V

IOH (mA)

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0 −0.5 −1.0 −1.5 −2.0 −2.5 −3.0

TA = +25˚C

VCC − VOH vs. IOH

600

500

400

300

200

100

IOL (mA)

VCC = 3.0 V

VCC = 4.0 V

VCC = 5.0 V

0 1 2 17181920345678910111213141516

TA = +25˚C

VOL (mV)

VCC = 6.0 V

VOL vs. IOL

010123456789

0.1

0.2

0.3

0.4

0.5

VOL (V)

VCC = 3.0 V

VCC = 4.0 V

VCC = 5.0 V

VCC = 6.0 V

IOL (mA)

TA = +25˚C

VOL vs. IOL

(3) “H” Level Output Voltage (P00 to P07, P10 to

P17, P20 to P27, P30 to P37, and P40 to P47) (4) Pull-up Resistance

(1) “L” Level Output Voltage (P00 to P07, P10 to

P17, P20 to P27, P30 to P37, P50 to P57, P70 to

P76, and P80 to P87)

(2) “L” Level Output Voltage (P40 to P47)

MB89860/850 Series

(5) “H” Level Input Voltage/“L” Level Input

Voltage (CMOS Input) (6) “H” Level Input Voltage/“L” level Input

Voltage (Hysteresis Input)

(7) Operating Supply Current vs. Frequency (8) Operating Supply Current vs. VCC

1234567

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

VIN (V)

VCC (V)

TA = +25˚C

VIN vs. VCC

VCC (V)

FC = 10 MHz

ICC (mA)

3.0 3.5 4.0 4.5 5.0 5.5 6.0

FC = 8 MHz

FC = 6 MHz

FC = 4 MHz

TA = +25˚C

ICC vs. VCC

1234567

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

VIN (V)

VCC (V)

VIHS

VILS

TA = +25˚C

VIN vs. VCC

VIHS:

VILS:

Threshold when input voltage in hysteresis

characteristics is set to “H” level

Threshold when input voltage in hysteresis

characteristics is set to “L” level

FC (MHz)

VCC = 5.0 V

VCC = 3.5 V

VCC = 3.0 V

246810

TA = +25˚C

ICC (mA) ICC vs. FC

MB89860/850 Series

(9) Sleep Power Supply Current vs. Frequency (10) Sleep Power Supply Current vs. VCC

VCC (V)

FC = 10 MHz

ICCS (mA)

3.0 3.5 4.0 4.5 5.0 5.5 6.0

FC = 8 MHz

FC = 6 MHz

FC = 4 MHz

TA = +25˚C

ICCS vs. VCC

FC (MHz)

VCC = 5.0 V

VCC = 3.5 V

VCC = 3.0 V

246810

TA = +25˚C

ICCS (mA) ICCS vs. FC

MB89860/850 Series

■INSTRUCTIONS

Execution instructions can be divided into the following four groups:

• Transfer

• Arithmetic operation

• Branch

•Others

Table 1 lists symbols used for notation of instructions.

Table 1 Instruction Symbols

(Continued)

Symbol Meaning

dir Direct address (8 bits)

off Offset (8 bits)

ext Extended address (16 bits)

#vct Vector table number (3 bits)

#d8 Immediate data (8 bits)

#d16 Immediate data (16 bits)

dir: b Bit direct address (8:3 bits)

rel Branch relative address (8 bits)

@ Register indirect (Example: @A, @IX, @EP)

A Accumulator A (Whether its length is 8 or 16 bits is determined b y the instruction in use.)

AH Upper 8 bits of accumulator A (8 bits)

AL Lower 8 bits of accumulator A (8 bits)

TTemporary accumulator T (Whether its length is 8 or 16 bits is determined by the

instruction in use.)

TH Upper 8 bits of temporary accumulator T (8 bits)

TL Lower 8 bits of temporary accumulator T (8 bits)

IX Index register IX (16 bits)

MB89860/850 Series

(Continued)

Columns indicate the following:

Mnemonic: Assembler notation of an instruction

~: Number of instructions

#: Number of by tes

Operation: Operation of an instruction

TL, TH, AH: A content change when each of the TL, TH, and AH instructions is executed. Symbols in

the column indicate the following:

•“–” indicates no change.

• dH is the 8 upper bits of operation description data.

• AL and AH must become the contents of AL and AH immediately bef ore the instruction

is executed.

• 00 becomes 00.

N, Z, V, C: An instruction of which the corresponding flag will change. If + is written in this column,

the relevant instruction will change its corresponding flag.

OP code: Code of an instruction. If an instruction is more than one code, it is written according to

the following rule:

Example: 48 to 4F ← This indicates 48, 49, ... 4F.

Symbol Meaning

EP Extra pointer EP (16 bits)

PC Program counter PC (16 bits)

SP Stack pointer SP (16 bits)

PS Program status PS (16 bits)

dr Accumulator A or index register IX (16 bits)

CCR Condition code register CCR (8 bits)

RP Register bank pointer RP (5 bits)

Ri General-purpose register Ri (8 bits, i = 0 to 7)

×Indicates that the very × is the immediate data.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

( × ) Indicates that the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

(( × )) The address indicated by the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

MB89860/850 Series

Table 2 Transfer Instructions (48 instructions)

Notes: •During byte transfer to A, T ← A is restricted to low bytes.

•Operands in more than one operand instruction must be stored in the order in which their mnemonics

are written. (Reverse arrangement of F2MC-8 family)

Mnemonic ~ # Operation TL TH AH N Z V C OP code

MOV dir,A

MOV @IX +off,A

MOV ext,A

MOV @EP,A

MOV Ri,A

MOV A,#d8

MOV A,dir

MOV A,@IX +off

MOV A,ext

MOV A,@A

MOV A,@EP

MOV A,Ri

MOV dir,#d8

MOV @IX +off,#d8

MOV @EP,#d8

MOV Ri,#d8

MOVW dir,A

MOVW @IX +off,A

MOVW ext,A

MOVW @EP,A

MOVW EP,A

MOVW A,#d16

MOVW A,dir

MOVW A,@IX +off

MOVW A,ext

MOVW A,@A

MOVW A,@EP

MOVW A,EP

MOVW EP,#d16

MOVW IX,A

MOVW A,IX

MOVW SP,A

MOVW A,SP

MOV @A,T

MOVW @A,T

MOVW IX,#d16

MOVW A,PS

MOVW PS,A

MOVW SP,#d16

SWAP

SETB dir: b

CLRB dir: b

XCH A,T

XCHW A,T

XCHW A,EP

XCHW A,IX

XCHW A,SP

MOVW A,PC

(dir) ← (A)

( (IX) +off ) ← (A)

(ext) ← (A)

( (EP) ) ← (A)

(Ri) ← (A)

(A) ← d8

(A) ← (dir)

(A) ← ( (IX) +off)

(A) ← (ext)

(A) ← ( (A) )

(A) ← ( (EP) )

(A) ← (Ri)

(dir) ← d8

( (IX) +off ) ← d8

( (EP) ) ← d8

(Ri) ← d8

(dir) ← (AH),(dir + 1) ← (AL)

( (IX) +off) ← (AH),

( (IX) +off + 1) ← (AL)

(ext) ← (AH), (ext + 1) ← (AL)

( (EP) ) ← (AH),( (EP) + 1) ← (AL)

(EP) ← (A)

(A) ← d16

(AH) ← (dir), (AL) ← (dir + 1)

(AH) ← ( (IX) +off),

(AL) ← ( (IX) +off + 1)

(AH) ← (ext), (AL) ← (ext + 1)

(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)

(AH) ← ( (EP) ), (AL) ← ( (EP) + 1)

(A) ← (EP)

(EP) ← d16

(IX) ← (A)

(A) ← (IX)

(SP) ← (A)

(A) ← (SP)

( (A) ) ← (T)

( (A) ) ← (TH),( (A) + 1) ← (TL)

(IX) ← d16

(A) ← (PS)

(PS) ← (A)

(SP) ← d16

(AH) ↔ (AL)

(dir): b ← 1

(dir): b ← 0

(AL) ↔ (TL)

(A) ↔ (T)

(A) ↔ (EP)

(A) ↔ (IX)

(A) ↔ (SP)

(A) ← (PC)

–

– – – –

+ + – –

– – – –

+ + – –

– – – –

+ + + +

– – – –

48 to 4F

08 to 0F

88 to 8F

A8 to AF

A0 to A7

MB89860/850 Series

Table 3 Arithmetic Operation Instructions (62 instructions)

(Continued)

Mnemonic ~ # Operation TL TH AH N Z V C OP code

ADDC A,Ri

ADDC A,#d8

ADDC A,dir

ADDC A,@IX +off

ADDC A,@EP

ADDCW A

ADDC A

SUBC A,Ri

SUBC A,#d8

SUBC A,dir

SUBC A,@IX +off

SUBC A,@EP

SUBCW A

SUBC A

INC Ri

INCW EP

INCW IX

INCW A

DEC Ri

DECW EP

DECW IX

DECW A

MULU A

DIVU A

ANDW A

ORW A

XORW A

CMP A

CMPW A

RORC A

ROLC A

CMP A,#d8

CMP A,dir

CMP A,@EP

CMP A,@IX +off

CMP A,Ri

DAA

DAS

XOR A

XOR A,#d8

XOR A,dir

XOR A,@EP

XOR A,@IX +off

XOR A,Ri

AND A

AND A,#d8

AND A,dir

(A) ← (A) + (Ri) + C

(A) ← (A) + d8 + C

(A) ← (A) + (dir) + C

(A) ← (A) + ( (IX) +off) + C

(A) ← (A) + ( (EP) ) + C

(A) ← (A) + (T) + C

(AL) ← (AL) + (TL) + C

(A) ← (A) − (Ri) − C

(A) ← (A) − d8 − C

(A) ← (A) − (dir) − C

(A) ← (A) − ( (IX) +off) − C

(A) ← (A) − ( (EP) ) − C

(A) ← (T) − (A) − C

(AL) ← (TL) − (AL) − C

(Ri) ← (Ri) + 1

(EP) ← (EP) + 1

(IX) ← (IX) + 1

(A) ← (A) + 1

(Ri) ← (Ri) − 1

(EP) ← (EP) − 1

(IX) ← (IX) − 1

(A) ← (A) − 1

(A) ← (AL) × (TL)

(A) ← (T) / (AL),MOD → (T)

(A) ← (A) ∧ (T)

(A) ← (A) ∨ (T)

(A) ← (A) ∀ (T)

(TL) − (AL)

(T) − (A)

(A) − d8

(A) − (dir)

(A) − ( (EP) )

(A) − ( (IX) +off)

(A) − (Ri)

Decimal adjust for addition

Decimal adjust for subtraction

(A) ← (AL) ∀ (TL)

(A) ← (AL) ∀ d8

(A) ← (AL) ∀ (dir)

(A) ← (AL) ∀ ( (EP) )

(A) ← (AL) ∀ ( (IX) +off)

(A) ← (AL) ∀ (Ri)

(A) ← (AL) ∧ (TL)

(A) ← (AL) ∧ d8

(A) ← (AL) ∧ (dir)

–

+ + + +

+ + + –

– – – –

+ + – –

+ + + –

– – – –

+ + – –

– – – –

+ + R –

+ + + +

+ + – +

+ + + +

+ + R –

28 to 2F

38 to 3F

C8 to CF

D8 toDF

18 to 1F

58 to 5F

←

→

C→A

←A

MB89860/850 Series

(Continued)

Table 4 Branch Instructions (17 instructions)

Table 5 Other Instructions (9 instructions)

Mnemonic ~ # Operation TL TH AH N Z V C OP code

AND A,@EP

AND A,@IX +off

AND A,Ri

OR A

OR A,#d8

OR A,dir

OR A,@EP

OR A,@IX +off

OR A,Ri

CMP dir,#d8

CMP @EP,#d8

CMP @IX +off,#d8

CMP Ri,#d8

INCW SP

DECW SP

(A) ← (AL) ∧ ( (EP) )

(A) ← (AL) ∧ ( (IX) +off)

(A) ← (AL) ∧ (Ri)

(A) ← (AL) ∨ (TL)

(A) ← (AL) ∨ d8

(A) ← (AL) ∨ (dir)

(A) ← (AL) ∨ ( (EP) )

(A) ← (AL) ∨ ( (IX) +off)

(A) ← (AL) ∨ (Ri)

(dir) – d8

( (EP) ) – d8

( (IX) +off) – d8

(Ri) – d8

(SP) ← (SP) + 1

(SP) ← (SP) – 1

–

+ + R –

+ + + +

– – – –

68 to 6F

78 to 7F

98 to 9F

Mnemonic ~ # Operation TL TH AH N Z V C OP code

BZ/BEQ rel

BNZ/BNE rel

BC/BLO rel

BNC/BHS rel

BN rel

BP rel

BLT rel

BGE rel

BBC dir: b,rel

BBS dir: b,rel

JMP @A

JMP ext

CALLV #vct

CALL ext

XCHW A,PC

RET

RETI

If Z = 1 then PC ← PC + rel

If Z = 0 then PC ← PC + rel

If C = 1 then PC ← PC + rel

If C = 0 then PC ← PC + rel

If N = 1 then PC ← PC + rel

If N = 0 then PC ← PC + rel

If V ∀ N = 1 then PC ← PC + rel

If V ∀ N = 0 then PC ← PC + reI

If (dir: b) = 0 then PC ← PC + rel

If (dir: b) = 1 then PC ← PC + rel

(PC) ← (A)

(PC) ← ext

Vector call

Subroutine call

(PC) ← (A),(A) ← (PC) + 1

Return from subrountine

Return form interrupt

–

– – – –

– + – –

– – – –

Restore

B0 to B7

B8 to BF

E8 to EF

Mnemonic ~ # Operation TL TH AH N Z V C OP code

PUSHW A

POPW A

PUSHW IX

POPW IX

NOP

CLRC

SETC

CLRI

SETI

–

– – – –

– – – R

– – – S

– – – –

MB89860/850 Series

■INSTRUCTION MAP

0123456789ABCDEF

0NOP SWAP RET RETI PUSHW

APOPWAMOV

A,ext MOVW

A,PS CLRI SETI CLRB

dir: 0 BBC

dir: 0,rel INCW ADECWAJMP@A MOVW

A,PC

1MULUADIVU AJMP

addr16 CALL

addr16 PUSHW

IX POPW

IX MOV

ext,A MOVW

PS,A CLRC SETC CLRB

dir: 1 BBC

dir: 1,rel INCW

SP DECW

SP MOVW

SP,A MOVW

A,SP

2ROLC ACMP AADDCASUBC AXCHA, T XOR AAND AOR AMOV

@A,T MOV

A,@A CLRB

dir: 2 BBC

dir: 2,rel INCWIX DECW

IX MOVW

IX,A MOVW

A,IX

3RORCACMPWAADDCW

ASUBCW

AXCHW

A, T XORWAANDWAORW AMOVW

@A,T MOVW

A,@A CLRB

dir: 3 BBC

dir: 3,rel INCW

EP DECW

EP MOVW

EP,A MOVW

A,EP

4MOV

A,#d8 CMP

A,#d8 ADDC

A,#d8 SUBC

A,#d8 XOR

A,#d8 AND

A,#d8 OR

A,#d8 DAA DAS CLRB

dir: 4 BBC

dir: 4,rel MOVW

A,ext MOVW

ext,A MOVW

A,#d16 XCHW

A,PC

5MOV

A,dir CMP

A,dir ADDC

A,dir SUBC

A,dir MOV

dir,A XOR

A,dir AND

A,dir OR A,dir MOV

dir,#d8 CMP

dir,#d8 CLRB

dir: 5 BBC

dir: 5,rel MOVW

A,dir MOVW

dir,A MOVW

SP,#d16 XCHW

A,SP

6MO V

A,@IX +d CMP

A,@IX +d ADDC

A,@IX +d SUBC

A,@IX +d MOV @IX

+d,A XOR

A,@IX +d AND

A,@IX +d OR

A,@IX +d MOV

@IX +d,#d8 CMP

@IX +d,#d8 CLRB

dir: 6 BBC

dir: 6,rel MOVW

A,@IX +d MO VW

@IX +d,A MOVW

IX,#d16 XCHW

A,IX

7MO V

A,@EP CMP

A,@EP ADDC

A,@EP SUBC

A,@EP MOV

@EP,A XOR

A,@EP AND

A,@EP OR

A,@EP MO V

@EP,#d8 CMP

@EP,#d8 CLRB

dir: 7 BBC

dir: 7,rel MOVW

A,@EP MO VW

@EP,A MOVW

EP,#d16 XCHW

A,EP

8MOV

A,R0 CMP

A,R0 ADDC

A,R0 SUBC

A,R0 MOV

R0,A XOR

A,R0 AND

A,R0 ORA,R0 MOV

R0,#d8 CMP

R0,#d8 SETB

dir: 0 BBS

dir: 0,rel INC R0 DEC R0 CALLV

#0 BNC rel

9MOV

A,R1 CMP

A,R1 ADDC

A,R1 SUBC

A,R1 MOV

R1,A XOR

A,R1 AND

A,R1 ORA,R1 MOV

R1,#d8 CMP

R1,#d8 SETB

dir: 1 BBS

dir: 1,rel INC R1 DEC R1 CALLV

#1 BC rel

AMOV

A,R2 CMP

A,R2 ADDC

A,R2 SUBC

A,R2 MOV

R2,A XOR

A,R2 AND

A,R2 ORA,R2 MOV

R2,#d8 CMP

R2,#d8 SETB

dir: 2 BBS

dir: 2,rel INC R2 DEC R2 CALLV

#2 BP rel

BMOV

A,R3 CMP

A,R3 ADDC

A,R3 SUBC

A,R3 MOV

R3,A XOR

A,R3 AND

A,R3 ORA,R3 MOV

R3,#d8 CMP

R3,#d8 SETB

dir: 3 BBS

dir: 3,rel INC R3 DEC R3 CALLV

#3 BN rel

CMOV

A,R4 CMP

A,R4 ADDC

A,R4 SUBC

A,R4 MOV

R4,A XOR

A,R4 AND

A,R4 ORA,R4 MOV

R4,#d8 CMP

R4,#d8 SETB

dir: 4 BBS

dir: 4,rel INC R4 DEC R4 CALLV

#4 BNZ rel

DMOV

A,R5 CMP

A,R5 ADDC

A,R5 SUBC

A,R5 MOV

R5,A XOR

A,R5 AND

A,R5 ORA,R5 MOV

R5,#d8 CMP

R5,#d8 SETB

dir: 5 BBS

dir: 5,rel INC R5 DEC R5 CALLV

#5 BZ rel

EMOV

A,R6 CMP

A,R6 ADDC

A,R6 SUBC

A,R6 MOV

R6,A XOR

A,R6 AND

A,R6 ORA,R6 MOV

R6,#d8 CMP

R6,#d8 SETB

dir: 6 BBS

dir: 6,rel INC R6 DEC R6 CALLV

#6 BGE rel

FMOV

A,R7 CMP

A,R7 ADDC

A,R7 SUBC

A,R7 MOV

R7,A XOR

A,R7 AND

A,R7 ORA,R7 MOV

R7,#d8 CMP

R7,#d8 SETB

dir: 7 BBS

dir: 7,rel INC R7 DEC R7 CALLV

#7 BLT rel

MB89860/850 Series

■MASK OPTIONS (MB89855/857/865/867)

■STANDARD OPTION LIST

■ORDERING INFORMATION

Option type Option selection Remarks

Power-on reset 0: Without power-on reset

1: With power-on reset —

Initial value of oscillation

stabilization delay time 0: 218/FC (s) (Crystal oscillator)

1: 214/FC (s) (Ceramic oscillator) Selects the initial value of the OSCS bit

in the STBC register during power-on

reset.

Reset pin output 0: Without reset output

1: With reset output —

Pull-up resistor at port pin

P00 to P07, P10 to P17,

P20 to P27, P30 to P37,

P40 to P47, P60 to P64,

P70 to P76, P80 to P87

1: Without pull-up resistor

0: With pull-up resistor

• Can be set per pin.

• P70 to P76, and P80 to P87 are used

in the MB89860 series only.

• P00 to P07, P10 to P17, and P20 to

P27 with a pull-up resistor can be set

only for single-chip mode.

MB89P857/W857/

P867/W867/T855

Power-on reset Available

Initial value of oscillation

stabilization delay time 218/FC (s)

Output at reset pin Available

Pull-up resistor at port pin Not available

Part number Package Remarks

MB89865PF

MB89867PF

MB89P867PF 80-pin Plastic QFP

(FPT-80P-M06)

MB89855P-SH

MB89T855P-SH

MB89857P-SH

MB89P857P-SH

64-pin Plastic SH-DIP

(DIP-64P-M01)

MB89W867CF 80-pin Ceramic QFP

(FPT-80C-A02) ES level only

MB89W857C-SH 64-pin Ceramic SH-DIP

(DIP-64C-A06) ES level only

Parameter Part number

MB89860/850 Series

■PACKAGE DIMENSIONS

"A"

LEAD No.

(.031±.008)

0.80±0.20

0.30(.012)

0.25(.010)

64 41

241

22.30±0.40(.878±.016)

18.40(.724)REF

0.16(.006)

(.014±.004)

0.35±0.10

0.80(.0315)TYP

(.705±.016)(.551±.008)

14.00±0.20 17.90±0.40

20.00±0.20(.787±.008)

23.90±0.40(.941±.016)

INDEX

0.15±0.05(.006±.002)

(STAND OFF)

0.05(.002)MIN

3.35(.132)MAX

(.642±.016)

16.30±0.40

REF

12.00(.472)

Details of "B" part

0 10°

Details of "A" part

0.18(.007)MAX

0.58(.023)MAX

0.10(.004)

"B"

1994 FUJITSU LIMITED F80010S-3C-2

Dimensions in mm (inches)

80-pin Plastic QFP

(FPT-80P-M06)

+0.50

–0

+.020

–.022

+.008

–0.55

+0.22

55.118(2.170)REF

INDEX-2

15°MAX TYP

19.05(.750)

(.010±.002)

0.25±0.05

MAX

1.778(.070) (.070±.007)

1.778±0.18

1.00

.039 (.018±.004)

0.45±0.10 0.51(.020)MIN

3.00(.118)MIN

5.65(.222)MAX

INDEX-1

(.669±.010)

17.00±0.25

2.283

58.00

1994 FUJITSU LIMITED D64001S-3C-4

CDimensions in mm (inches)

64-pin Plastic SH-DIP

(DIP-64P-M01)

MB89860/850 Series

–0.07

+0.08 0.80±0.10

(.0315±.0040)

0.35

8.50(.335)TYP

0.80(.0315) TYP22.30(.878) TYP

22.00(.866) TYP

1.60(.063) TYP

(.014±.003)

0.80±0.10

(.0315±.0040)

18.40(.725) REF

(.787±.010)

20.00±0.25

23.90(.941) TYP

(.006±.002)

0.15±0.05

4.45(.175)MAX

0.51(.020) TYP

REF

12.00(.472)

TYP

16.31(.642)

TYP

16.00(.630)

(.551±.010)

TYP

17.91(.705)

14.00±0.25

INDEX AREA

1994 FUJITSU LIMITED F80014SC-1-2

80-pin Ceramic QFP

(FPT-80P-A02)

Dimensions in mm (inches)

+0.13

–0.08

–.003

+.005 0°~9°

5.84(.230)MAX

8.89(.350) DIA

TYP

(.134±.014)

3.40±0.36

55.118(2.170)REF

(.738±.010)

18.75±0.25

(2.240±.022)

56.90±0.56

(.750±.010)

19.05±0.25

(.010±.004)

0.25±0.05

1.27±0.25

(.050±.010)

1.45(.057)

MAX

1.778±0.180

(.070±.007) 0.90±0.10

(.0355±.0040) 0.46

.018

INDEX AREA

R1.27(.050)

REF

1994 FUJITSU LIMITED D64006SC-1-2

CDimensions in mm (inches)

64-pin Ceramic SH-DIP

(DIP-64C-A06)

MB89860/850 Series

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

KAWASAKI PLANT, 1015, Kamikodanaka

Nakahara-ku, Kawasaki-shi

Kanagawa 211, Japan

Tel: (044) 754-3753

Fax: (044) 754-3329

Nor t h and South America

FUJITSU MICROELECTRONICS, INC.

Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, U.S.A.

Tel: (408) 922-9000

Fax: (408) 432-9044/9045

Europe

FUJITSU MIKROELEKTRONIK GmbH

Am Siebenstein 6-10

63303 Dreieich-Buchschlag

Germany

Tel: (06103) 690-0

Fax: (06103) 690-122

Asia Pacific

FUJITSU MICROELECTR ONICS ASIA PTE. LIMITED

No. 51 Bras Basah Road,

Plaza By The Park,

#06-04 to #06-07

Singapore 189554

Tel: 336-1600

Fax: 336-1609

F9606

 FUJITSU LIMITED Printed in Japan

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