SLAS289C − OCTOBER 2001 − REVISED OCTOBER 2004
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FEATURES
DAnalog Supply 3 V
DDigital Supply 3 V
DConfigurable Input Functions:
− Single-Ended
− Single-Ended With Analog Clamp
− Single-Ended With Programmable Digital
Clamp
− Differential
DBuilt-In Programmable Gain Amplifier (PGA)
DDifferential Nonlinearity: ±0.45 LSB
DSignal-to-Noise: 60 dB Typ f(IN) at 4.8 MHz
DSpurious Free Dynamic Range: 72 dB
DAdjustable Internal Voltage Reference
DUnsigned Binary/2s Complement Output
DOut-of-Range Indicator
DPower-Down Mode
APPLICATIONS
DVideo/CCD Imaging
DCommunications
DSet-Top-Box
DMedical
DESCRIPTION
The THS1041 is a CMOS, low power, 10-bit, 40 MSPS
analog-to-digital converter (ADC) that operates from a
single 3-V supply. The THS1041 has been designed to
give circuit developers flexibility. The analog input to the
THS1041 can be either single-ended or differential.
This device has a built-in clamp amplifier whose clamp
input level can be driven from an external dc source or
from an internal high-precision 10-bit digital clamp level
programmable via an internal CLAMP register. A 3-bit
PGA is included to maintain SNR for small signals. The
THS1041 provides a wide selection of voltage
references to match the user’s design requirements.
For more design flexibility, the internal reference can be
bypassed to use an external reference to suit the dc
accuracy and temperature drift requirements of the
application. The out-of-range output indicates any
out-of-range condition in THS1041’s input signal. The
format of the digital output can be coded in either
unsigned binary or 2s complement.
The speed, resolution, and single-supply operation of
the THS1041 are suited to applications in set-top-box
(STB), video, multimedia, imaging, high-speed
acquisition, and communications. The built-in clamp
function allows dc restoration of a video signal and is
suitable for video applications. The speed and
resolution ideally suit charge-couple device (CCD) input
systems such as color scanners, digital copiers, digital
cameras, and camcorders. A wide input voltage range
allows the THS1041 to be applied in both imaging and
communications systems.
The THS1041C is characterized for operation from 0°C
to 70°C, while the THS1041I is characterized for
operation from −40°C to 85°C.
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Copyright 2002 − 2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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AGND
DVDD
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
OVR
DGND
AVDD
AIN+
VREF
AIN−
REFB
MODE
REFT
CLAMPOUT
CLAMPIN
CLAMP
REFSENSE
WR
OE
CLK
28-PIN TSSOP/SOIC PACKAGE
(TOP VIEW)
SLAS289C − O C TOBER 2001 − REVISED OCTOBER 2004
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AVAILABLE OPTIONS
PRODUCT PACKAGE
LEAD PACKAGE
DESGIGNATOR†
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKINGS ORDERING
NUMBER TRANSPORT MEDIA,
QUANTITY
THS1041C
0°C to 70°C
TH1041
THS1041CPW Tube, 50
THS1041C
TSSOP−28
PW
0°C to 70°C TH1041 THS1041CPWR Tube and Reel, 2000
THS1041I
TSSOP−28 PW
−40°C to 85°C
TJ1041
THS1041IPW Tube, 50
THS1041I −40°C to 85°C TJ1041 THS1041IPWR Tube and Reel, 2000
THS1041C
0°C to 70°C
TH1041
THS1041CDW Tube, 20
THS1041C
SOP−28
DW
0°C to 70°C TH1041 THS1041CDWR Tube and Reel, 1000
THS1041I
SOP−28 DW
−40°C to 85°C
TJ1041
THS1041IDW Tube, 20
THS1041I −40°C to 85°C TJ1041 THS1041IDWR Tube and Reel, 1000
†For the most current specification and package information, refer to the TI web site at www.ti.com.
functional block diagram
10 Bit
DAC
SHPGA 10 Bit
ADC
ADC
Reference
Resistor
Digital
Interface
3-State
Output
Buffers
Mode
Detection
0.5 V
CLAMPOUT
CLAMP
AIN+
AIN−
MODE
REFSENSE
VREF
REFB REFT
WR
I/O (0−9)
OVR
OE
Timing
Circuit CLK
AVDD
AGND
CLAMPIN
Clamp
Logic
Clamp
Logic
Clamp
Logic
A2 +
−
A1
VREF
DVDD
DGND
NOTE: A1 − Internal bandgap reference
A2 − Internal ADC reference generator
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Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
AGND 1 I Analog ground
AIN+ 27 I Positive analog input
AIN− 25 I Negative analog input
AVDD 28 I Analog supply
CLAMP 19 I High to enable clamp mode, low to disable clamp mode
CLAMPIN 20 I Connect to an external analog clamp reference input.
CLAMPOUT 21 O The CLAMPOUT pin can provide a dc restoration or a bias source function (see AC reference generation
section). If neither function is required then the clamp can be disabled to save power (see power management
section).
CLK 15 I Clock input
DGND 14 I Digital ground
DVDD 2 I Digital supply
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
3
4
5
6
7
8
9
10
11
12
I/O
Digital I/O bit 0 (LSB)
Digital I/O bit 1
Digital I/O bit 2
Digital I/O bit 3
Digital I/O bit 4
Digital I/O bit 5
Digital I/O bit 6
Digital I/O bit 7
Digital I/O bit 8
Digital I/O bit 9 (MSB)
MODE 23 I Operating mode select (AGND, AVDD/2, AVDD)
OE 16 I High to high-impedance state the data bus, low to enable the data bus
OVR 13 O Out-of-range indicator
REFB 24 I/O Bottom ADC reference voltage
REFSENSE 18 I VREF mode control
REFT 22 I/O Top ADC reference voltage
VREF 26 I/O Internal or external reference
WR 17 I Write strobe
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absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range: AVDD to AGND, DVDD to DGND −0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AGND to DGND −0.3 V to 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AVDD to DVDD −4 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODE input voltage range, MODE to AGND −0.3 V to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference voltage input range, REFT, REFB, to AGND −0.3 V to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog input voltage range, AIN to AGND −0.3 V to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference input voltage range, VREF to AGND −0.3 V to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference output voltage range, VREF to AGND −0.3 V to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock input voltage range, CLK to AGND −0.3 V to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range, digital input to DGND −0.3 V to DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital output voltage range, digital output to DGND −0.3 V to DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating junction temperature range, TJ0°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds 300°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
over operating free-air temperature range TA, (unless otherwise noted)
PARAMETER CONDITION MIN NOM MAX UNIT
Power Supply
Supply voltage AVDD, DVDD 3 3 3.6 V
Analog and Reference Inputs
VREF input voltage VI(VREF) REFSENSE = AVDD 0.5 1 V
REFT input voltage VI(REFT) MODE = AGND 1.75 2 V
REFB input voltage VI(REFB) MODE = AGND 1 1.25 V
Reference input voltage VI(REFT) − VI(REFB) MODE = AGND 0.5 1 V
Reference common mode voltage (VI(REFT)
+ V
I(REFB))/2 MODE = AGND (AVDD/2) − 0.05 (AVDD/2) + 0.05 V
Analog input voltage differential (see Note 1)
VI(AIN)
REFSENSE = AGND −1 1 V
Analog input voltage differential (see Note 1) VI(AIN) REFSENSE = VREF −0.5 0.5 V
Analog input capacitance, CI10 pF
Clock input (see Note 2) 0AVDD V
Clamp input voltage VI(CLAMPIN) 0.1 AVDD − 0.1 V
Digital Outputs
Maximum digital output load resistance RL100 kΩ
Maximum digital output load capacitance CL10 pF
Digital Inputs
High-level input voltage, VIH 2.4 DVDD V
Low-level input voltage, VIL DGND 0.8 V
Clock frequency (see Note 3) tcf(CLK) = 5 MHz to 40 MHz 25 200 nS
Clock pulse duration tw(CKL), tw(CKH) f(CLK) = 40 MHz 11.25 12.5 13.75 nS
Operating free-air temperature, TA
THS1041C 0 70
°C
Operating free-air temperature, T
ATHS1041I −40 85 °
C
NOTE 1: VI(AIN) is AIN+ − AIN− range, based on VI(REFT)
− VI(REFB) = 1 V. Varies proportional to the VI(REFT)
− VI(REFB) value. Input common mode
voltage is recommended to be AVDD/2.
NOTE 2: The clock pin is referenced to AVSS and powered by AVDD.
NOTE 3: Clock frequency can be extended to this range without degradation of performance.
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electrical characteristics
over recommended operating conditions, AVDD = 3 V, DVDD = 3 V, fs = 40 MSPS/50% duty cycle, MODE = AVDD (internal reference),
differential input range = 1 Vpp and 2 Vpp, PGA = 1X, TA = Tmin to Tmax (unless otherwise noted)
power supply
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AVDD
Supply voltage
3 3 3.6
V
DVDD Supply voltage 3 3 3.6 V
ICC Operating supply current See Note 4 34 42 mA
PDPower dissipation See Note 4 103 125 mW
PD(STBY) Standby power 75 µW
Power up time for all references from standby, t(PU) 10 µF bypass 770 µs
Wake-up time, t(WU) See Note 5 45 µs
REFT, REFB internal ADC reference voltages outputs (MODE = AVDD or AVDD/2) (See Note 6)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Reference voltage top, REFT
VREF = 0.5 V
AVDD = 3 V
1.75
V
Reference voltage top, REFT VREF = 1 V AVDD = 3 V 2V
Refence voltage bottom, REFB
VREF = 0.5 V
AVDD = 3 V
1.25
V
Refence voltage bottom, REFB VREF = 1 V AVDD = 3 V 1V
Input resistance between REFT and REFB 1.4 1.9 2.5 kΩ
VREF (on-chip voltage reference generator)
PARAMETER MIN TYP MAX UNIT
Internal 0.5-V reference voltage (REFSENSE = VREF) 0.45 0.5 0.55 V
Internal 1-V reference voltage (REFSENSE = AGND) 0.95 1 1.05 V
Reference input resistance (REFSENSE = AVDD, MODE = AVDD/2 or AVDD) 7 14 21 kΩ
dc accuracy
PARAMETER MIN TYP MAX UNIT
Resolution 10 Bits
INL Integral nonlinearity (see definitions) −1.5 ±0.75 1.5 LSB
DNL Differential nonlinearity (see definitions) −0.9 ±0.3 1 LSB
Zero error (see definitions) −1.5 0.7 1.5 %FSR
Full-scale error (see definitions) −3 2.2 3 %FSR
Missing code No missing code assured
NOTES: 4. A −1 dBFS 10-KHz triangle wave is applied at AIN+ and AIN−. Internal bandgap reference and ADC reference are enabled,
CLAMPOUT is set to AVDD/2. ADC conversions are taking place during power measurements at 40 MSPS. A CLAMPOUT load or
VREF load may result in additional current.
5. Wake-up time is from the power-down state to accurate ADC samples being taken and is specified for MODE = AGND with external
reference sources applied to the device at the time of release of power-down and an applied 40-MHz clock. Circuits that need to
power up are the bandgap, bias generator, ADC, and SHPGA.
6. External reference values are listed in the Recommended Operating Conditions Table.
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electrical characteristics
over recommended operating conditions, AVDD = 3 V, DVDD = 3 V, fs = 40 MSPS/50% duty cycle, MODE = AVDD (internal reference),
differential input range = 1 Vpp and 2 Vpp, PGA = 1X, TA = Tmin to Tmax (unless otherwise noted) (continued)
dynamic performance (ADC and PGA)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ENOB
Effective number of bits
f = 4.8 MHz, −0.5 dBFS 8.8 9.6
Bits
ENOB Effective number of bits f = 20 MHz, −0.5 dBFS 9.5 Bits
SFDR
Spurious free dynamic range
f = 4.8 MHz, −0.5 dBFS 60.5 72
dB
SFDR Spurious free dynamic range f = 20 MHz, −0.5 dBFS 70 dB
THD
Total harmonic distortion
f = 4.8 MHz, −0.5 dBFS −72.5 −61.3
dB
THD Total harmonic distortion f = 20 MHz, −0.5 dBFS −71.6 dB
SNR
Signal-to-noise ratio
f = 4.8 MHz, −0.5 dBFS 55.7 60
dB
SNR Signal-to-noise ratio f = 20 MHz, −0.5 dBFS 57 dB
SINAD
Signal-to-noise and distortion
f = 4.8 MHz, −0.5 dBFS 55.6 59.7
dB
SINAD Signal-to-noise and distortion f = 20 MHz, −0.5 dBFS 59.6 dB
BW Full power bandwidth (−3 dB) 900 MHz
PGA (See Note 7)
PARAMETER MIN TYP MAX UNIT
Gain range (linear scale) 0.5 4 V/V
Gain step size (linear scale) 0.485 0.5 0.515 V/V
Gain error (deviation from ideal, all gain settings) −3% 3%
Number of control bits 3 Bits
clamp amplifier and clamp DAC (See Note 8)
PARAMETER MIN TYP MAX UNIT
Resolution 10 Bits
DAC output range REFB REFT V
DAC differential nonlinearity −1 1 LSB
DAC integral nonlinearity −3 3 LSB
Clamping analog output voltage range 0.1 AVDD−0.1 V
Clamping analog output voltage error −40 40 mV
Clamping analog output bias voltage MODE = AVDD AVDD/2 − 0.1 AVDD/2 + 0.1 mV
NOTES: 7. Gain settings increment by the gain step size for eight binary settings of 000 to 111 to correspond to the ideal gain range.
8. The CLAMPOUT pin must see a load capacitance of at least 10 nF to ensure stability of the on-chip clamp buffer. When using the
clamp for dc restoration, the signal coupling capacitor should be at least 10 nF. When using the clamp buffer as a dc biasing reference,
CLAMPOUT should be decoupled to analog ground through at least a 10-nF capacitor.
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electrical characteristics
over recommended operating conditions, AVDD = 3 V, DVDD = 3 V, fs = 40 MSPS/50% duty cycle, MODE = AVDD (internal reference),
differential input range = 1 Vpp and 2 Vpp, PGA = 1X, TA = Tmin to Tmax (unless otherwise noted) (continued)
digital specifications
PARAMETER MIN NOM MAX UNIT
Digital Inputs
VIH
High-level input voltage
Clock input 0.8 × AVDD
V
VIH High-level input voltage All other inputs 0.8 × DVDD V
VIL
Low-level input voltage
Clock input 0.2 × AVDD
V
VIL Low-level input voltage All other inputs 0.2 × DVDD V
IIH High-level input current 1µA
IIL Low-level input current |−1| µA
CiInput capacitance 5 pF
Digital Outputs
VOH High-level output voltage Iload = 50 µA DVDD−0.4 V
VOL Low-level output voltage Iload = 50 µA 0.4 V
High impedance output current ±1µA
Rise/fall time Cload = 15 pF 3.5 ns
Clock Input
tcClock cycle 25 200 ns
tw(CKH) Pulse duration, clock high 11.25 110 ns
tw(CKL) Pulse duration, clock low 11.25 110 ns
Clock duty cycle 45% 50% 55%
td(o) Clock to data valid, delay time 9.5 16 ns
Pipeline latency 4 Cycles
td(AP) Aperture delay time 0.1 ns
Aperture uncertainty (jitter) 1 ps
timing
PARAMETER MIN TYP MAX UNIT
td(DZ) Output disable to Hi-Z output, delay time 0 10 ns
td(DEN) Output enable to output valid, delay time 0 10 ns
td(OEW) Output disable to write enable, delay time 12 ns
td(WOE) Write disable to output enable, delay time 12 ns
tw(WP) Write pulse duration 15 ns
tsu Input data setup time 5 ns
thInput data hold time 5 ns
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PARAMETER MEASUREMENT INFORMATION
See Note A
WE
OE
I/O Input ADC OutputADC Output Hi-Z Hi-Z
tw(WP)
td(OEW) td(WOE)
td(DEN)
tsu
th
td(DZ)
NOTE A: All timing measurements are based on 50% of edge transition.
See Note B
NOTE B: Output data is converted ADC digital data. The input data is stored in the internal write only control registers.
Figure 1. Write Timing Diagram
See
Note A
NOTE A: All timing measurements are based on 50% of edge transition.
Analog
Input
Input Clock
Digital
Output
Sample 1 Sample 2 Sample 3 Sample 4 Sample 5
tc
tw(CKH) tw(CKL)
td(o)
(I/O Pad Delay or
Propagation Delay)
Pipeline Latency
Sample 1 Sample 2
Sample 6
OE
td(DEN) td(DZ)
Sample 7
Figure 2. Digital Output Timing Diagram
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TYPICAL CHARACTERISTICS
−1.0
−0.5
0.0
0.5
1.0
0 128 256 384 512 640 768 896 1024
DIFFERENTIAL NONLINEARITY
vs
INPUT CODE
Input Code
DNL − Differential Nonlinearity − LSB
AVDD = 3 V
DVDD = 3 V
fs = 40 MSPS
Vref = 1 V
Figure 3
−1.0
−0.5
0.0
0.5
1.0
0 128 256 384 512 640 768 896 1024
INTEGRAL NONLINEARITY
vs
INPUT CODE
Input Code
INL − Integral Nonlinearity − LSB
AVDD = 3 V
DVDD = 3 V
fs = 40 MSPS
Vref = 1 V
Figure 4
−1.0
−0.5
0.0
0.5
1.0
0 128 256 384 512 640 768 896 1024
INTEGRAL NONLINEARITY
vs
INPUT CODE
Input Code
INL − Integral Nonlinearity − LSB
AVDD = 3 V
DVDD = 3 V
fs = 40 MSPS
Vref = 0.5 V
Figure 5
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TYPICAL CHARACTERISTICS
Figure 6
−40
−45
−50
−55
−60
−65
−70
−75
−80
0 102030405060708090100
−0.5 dBFS
−6 dBFS
−20 dBFS
THD − Total Harmonic Distortion − dB
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
fi − Input Frequency − MHz
Differential Input = 1 V
See Note
0 102030405060708090100
−0.5 dBFS
−6 dBFS
−20 dBFS
Differential Input = 2 V
THD − Total Harmonic Distortion − dB
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
fi − Input Frequency − MHz
Figure 7
See Note
−40
−45
−50
−55
−60
−65
−70
−75
−80
47
49
51
53
55
57
59
61
0 102030405060708090100
Diff Input = 2 V
SE Input = 2 V
Diff Input = 1 V
SE Input = 1 V
SNR − Signal-to-Noise Ratio − dB
SIGNAL-TO-NOISE RATIO
vs
INPUT FREQUENCY
fi − Input Frequency − MHz
Figure 8
See Note 35
40
45
50
55
60
65
70
75
80
85
0102030405060708090100
Diff Input = 2 V
SE Input = 2 V
Diff Input = 1 V
SE Input = 1 V
SFDR − Spurious Free Dynamic Range − dB
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY
fi − Input Frequency − MHz
Figure 9
See Note
NOTE: AVDD = DVDD = 3 V, fS= 40 MSPS, PGA = 1, 20-pF capacitors AIN+ to AGND and AIN− to AGND,
Input series resistor = 25 Ω,
2-V Input: Ext Ref, REFT = 2 V, REFB = 1 V, −0.5 dBFS
1-V Input: Ext Ref, REFT = 1.75 V, REFB = 1.25 V, −0.5dBFS
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TYPICAL CHARACTERISTICS
35
40
45
50
55
60
0102030405060708090
100
Diff Input = 2 V
SE Input = 2 V
Diff Input = 1 V
SE Input = 1 V
SIGNAL-TO-NOISE PLUS DISTORTION
vs
INPUT FREQUENCY
fi − Input Frequency − MHz
65
Figure 10
See Note
SINAD − Signal-to-Noise Plus Distortion − dB
−35
−40
−45
−50
−55
−60
−65
−70
−75
−80
−85
0102030405060708090100
Diff Input = 2 V
SE Input = 2 V
Diff Input = 1 V
SE Input = 1 V
THD − Total Harmonic Distortion − dB
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
fi − Input Frequency − MHz
Figure 11
See Note
NOTE: AVDD = DVDD = 3 V, fS = 40 MSPS, PGA = 1, 20-pF capacitors AIN+ to AGND and AIN− to AGND,
Input series resistor = 25 Ω,
2-V Input: Ext Ref, REFT = 2 V, REFB = 1 V
1-V Input: Ext Ref, REFT = 1.75 V, REFB = 1.25 V
Figure 12
−40
−45
−50
−55
−60
−65
−70
−75
0 5 10 20 25 30 35 40 45 50
THD − Total Harmonic Distortion − dB
Sample Rate − MSPS
TOTAL HARMONIC DISTORTION
vs
SAMPLE RATE
15
Diff Input = 2 V
fi = 20 MHz, −0.5 dBFS
Figure 13
40
45
50
55
60
65
70
75
0 5 10 20 25 30 35 40 45 50
SNR − Signal-to-Noise Ratio − dB
Sample Rate − MSPS
SIGNAL-TO-NOISE RATIO
vs
SAMPLE RATE
15
Diff Input = 2 V
fi = 20 MHz, −0.5 dBFS
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TYPICAL CHARACTERISTICS
Figure 14
57
59
61
63
65
67
69
71
73
75
3 3.1
Spurious Free Dynamic Range − dB
SPURIOUS FREE DYNAMIC RANGE
vs
SUPPLY VOLTAGE
VDD − Supply Voltage − V 3.63.2 3.3 3.4 3.5
Diff Input = 2 V,
fi = 10 MHz, −0.5 dBFS
fS = 40 MSPS
Figure 15
THD − Total Harmonic Distortion − dB
TOTAL HARMONIC DISTORTION
vs
SUPPLY VOLTAGE
−57
−59
−61
−63
−65
−67
−69
−71
−73
−75
VDD − Supply Voltage − V
3 3.1 3.63.2 3.3 3.4 3.5
Diff Input = 2 V,
fi = 10 MHz, −0.5 dBFS
fS = 40 MSPS
Figure 16
57
59
61
63
65
67
69
71
73
75
SNR − Signal-to-Noise Ratio − dB
SIGNAL-TO-NOISE RATIO
vs
SUPPLY VOLTAGE
VDD − Supply Voltage − V
3 3.1 3.63.2 3.3 3.4 3.5
Diff Input = 2 V,
fi = 10 MHz, −0.5 dBFS
fS = 40 MSPS
Figure 17
Diff Input = 2 V,
fi = 10 MHz, −0.5 dBFS
fS = 40 MSPS
57
59
61
63
65
67
69
71
73
75
3 3.5 3.6
SNRD − Signal-to-Noise Plus Distortion − dB
SIGNAL-TO-NOISE PLUS DISTORTION
vs
SUPPLY VOLTAGE
VDD − Supply Voltage − V
3.1 3.2 3.3 3.4
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TYPICAL CHARACTERISTICS
Figure 18
−140
−120
−100
−80
−60
−40
−20
0
0510
FFT
15 20
fi = 10 MHz at −0.5 dBFS,
fS = 40 MSPS
Input = 2 V Differential
Amplitude − dB
Frequency − MHz
Figure 19
Vref = 0.5 V
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
−40 −20 0 20 40 60 80
Vref = 1 V
Reference Voltage Error − %
REFERENCE VOLTAGE ERROR
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
Figure 20
90
95
100
105
110
115
120
125
ADC Codes
ADC CODES
vs
WAKE-UP SETTLING TIME
Wake-Up Settling Time − µs
MODE = AGND,
fS = 40 MSPS,
Ext. REF = 1 V and 2 V,
AVDD = 3 V
See Note
−10 5 20 35 50 65 80 95 110
NOTE: See wake-up time in definitions at the end of this data sheet.
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TYPICAL CHARACTERISTICS
Figure 21
0
0.4
0.8
1.2
1.6
2
2.4
0
90
180
270
360
450
540
630
720
810
900
990
1080
1170
Vreft
Vrefb
Vref = 1 V, Reft = 10 µF,
Refb = 10 µF, AVDD = 3 V
Reft, Refb Reference Voltage − V
POWER-UP TIME FOR INTERNAL
REFERENCE VOLTAGE FROM STANDBY
Powerup Time − µs
Figure 22
70
90
110
4 8 12 16 20 24 28 32 36 40 44
Int. Ref
TA = 25°C
Ext. Ref
TA = 25°C
AVDD = 3 V,
Vref = 1 V
− Power Dissipation − mW
POWER DISSIPATION
vs
SAMPLE RATE
PD
fs − Sample Rate − MSPS
Figure 23
−8
−6
−4
−2
0
2
4
10 100 300 500 700 900 1100
INPUT BANDWIDTH
fi − Input Frequency − MHz
AVDD = 3 V
DVDD = 3 V
fs = 40 MSPS
See Note
Amplitude − dB
Figure 24
TA − Free-Air Temperature − °C
9.35
9.40
9.45
9.50
9.55
9.60
9.65
9.70
9.75
−40 −30 −20 −10 0 10 20 30 40 50 60 70 80
Effective Number of Bits
EFFECTIVE NUMBER OF BITS
vs
FREE-AIR TEMPERATURE
Diff Input = 2 V,
fi = 4.4 MHz, −0.5 dBFS
fS = 40 MSPS
NOTE: No series resistors and no bypass capacitors at AIN+ and AIN− inputs
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PRINCIPLES OF OPERATION
functional overview
Refer to functional block diagram. A single-ended, sample rate clock is required at pin CLK for device operation.
Analog inputs AIN+ and AIN− are sampled on each rising edge of CLK in a switched capacitor sample and hold
unit, the output of which feeds a programmable gain amplifier (PGA) to the ADC core, where analog-to-digital
conversion is performed against the ADC reference voltages REFT and REFB.
Internal or external ADC reference voltage configurations are selected by connecting the MODE pin
appropriately. When MODE = AGND, the user must provide external sources at pins REFB and REFT. When
MODE = AVDD or MODE = AVDD/2, an internal ADC references generator (A2) is enabled, which drives the
REFT and REFB pins using the voltage at pin VREF as its input. The user can choose to drive VREF from the
internal bandgap reference, or they can disable A1 and provide their own reference voltage at pin VREF.
On the fourth rising CLK edge following the edge that sampled AIN+ and AIN−, the conversion result is output
via data pins I/O0 to I/O9. The output buf fers can be disabled by pulling pin OE high, allowing the user to place
device configuration data on the data pins, which are then latched into the internal control registers by strobing
the WR pin high then low. The internal registers control the data output format (unsigned or twos complement),
the PGA gain, device powerdown, the clamp functions, and the clamp DAC voltage.
The THS1041 offers a clamp circuit suitable for dc restoration of ac-coupled signals. The clamp voltage level
can be set using an external reference applied to the CLAMPIN pin, or it can be set to a reference level provided
by an on-chip 10-bit DAC. The CLAMPOUT pin must be connected externally to AIN+ or AIN− in applications
requiring the clamp function.
The following sections explain further:
DHow signals flow from AIN+ and AIN− to the ADC core, and how the reference voltages at REFT and REFB
set the ADC input range and hence the input range at AIN+ and AIN−
DHow to set the ADC references REFT and REFB using external sources or the internal ADC reference buffer
(A2) to match the device input range to the input signal
DHow to set the output of the internal bandgap reference (A1) if required
DHow to use the clamp and device control registers
signal processing chain (sample and hold, PGA, ADC)
Figure 25 shows the signal flow through the sample and hold unit and the PGA to the ADC core.
Sample
and
Hold
X1
X−1
ADC
Core
VP+
VP−
VQ+
VQ−
REFT
REFB
AIN+
AIN− PGA
Figure 25. Analog Input Signal Flow
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PRINCIPLES OF OPERATION
sample-and-hold
Differential input signal sources can be connected directly to the AIN+ and AIN− pins using either dc- or
ac-coupling.
For single-ended sources, the signal can be dc- or ac-coupled to one of AIN+ or AIN−, and a suitable reference
voltage (usually the midscale voltage, see operating configuration examples) must be applied to the other pin.
Note that connecting the signal to AIN− results in it being inverted during sampling.
The sample and hold differential output voltage VP = VP+ − VP− is given by
VP = (AIN+) − (AIN−)
A clamp is available for dc restoration of ac-coupled single-ended inputs (see clamp operation).
programmable gain amplifier
VP is amplified by the PGA and fed to the ADC as a voltage VQ = VQ+ − VQ− where
VQ = Gain × VP = Gain × [(AIN+) − (AIN−)]
analog-to-digital converter
VQ is digitized by the ADC, using the voltages at pins REFT and REFB to set the ADC zero-scale (code 0) and
full-scale (code 1023) input voltages.
VQ (ZS) = − (REFT − REFB)
VQ (FS) = (REFT − REFB)
Any inputs at AIN+ and AIN− that give VQ voltages less than VQ(ZS) or greater than VQ(FS) lie outside the
ADC’ s conversion range and attempts to convert such voltages are signalled by driving pin OVR high when the
conversion result is output. VQ voltages less than VQ(ZS) digitize to give ADC output code 0, and VQ voltages
greater than VQ(FS) give ADC output code 1023.
complete system and system input range
Combining the above equations to find the input voltages [(AIN+) − (AIN−)] that correspond to the limits of the
ADC’ s valid input range gives:
(REFB *REFT)
Gain v[(AIN))*(AIN*)] v(REFT *REFB)
Gain
For both single-ended and dif ferential inputs, the ADC can thus handle signals with a peak-to-peak input range
[(AIN+) − (AIN−)] of:
pk−pk input range +2 (REFT *REFB)
Gain
[(AIN+) − (AIN−)]
The next sections describe the options available to the user for setting the REFT and REFB voltages to obtain
the desired input range and performance in their THS1041 applications.
(1)
(2)
(3)
(4)
(5)
(6)
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PRINCIPLES OF OPERATION
ADC reference generation
The THS1041 ADC references REFT and REFB can be driven from external (off-chip) sources or from the
internal A2 reference buffer. The voltage at the MODE pin determines the ADC references source.
Connecting MODE to AGND enables external ADC references mode. In this mode the internal buffer A2 is
powered down and the user must provide the REFT and REFB voltages by connecting external sources directly
to these pins. This mode is useful where several THS1041 devices must share common references for best
matching of their ADC input ranges, or when the application requires better accuracy and temperature stability
than the on-chip reference source can provide.
Connecting MODE to AVDD or AVDD/2 enables internal ADC references mode. In this mode the buffer A2 is
powered up and drives the REFT and REFB pins. External reference sources should not be connected in this
mode. Using internal ADC references mode when possible helps to reduce the component count and hence
the system cost.
When MODE is connected to AVDD, a buffered AVDD/2 voltage is also available at the CLAMPOUT pin. This
voltage can be used as a dc bias level for any ac-coupling networks connecting the input signal sources to the
AIN+ and AIN− pins.
MODE PIN REFERENCE SELECTION CLAMPOUT PIN FUNCTION
AGND External Clamp
AVDD/2 Internal Clamp
AVDD Internal AVDD/2 for AIN± bias
external reference mode (MODE = AGND)
Sample
and
Hold
X1
X−1
ADC
Core
PGA
AIN+
AIN−
Internal
Reference
Buffer
VREF
REFT
REFB
Figure 26. ADC Reference Generation, MODE = AGND
Connecting pin MODE to AGND powers-down the internal references buffer A2 and disconnects its outputs
from the REFT and REFB pins. The user must connect REFT and REFB to external sources to provide the ADC
reference voltages required to match the THS1041 input range to their application requirements. The
common-mode reference voltage must be AVDD/2 for correct THS1041 operation:
(REFT )REFB)
2+AVDD
2
(7)
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PRINCIPLES OF OPERATION
internal reference mode (MODE = AVDD or AVDD/2)
Sample
and
Hold
X1
X−1
ADC
Core
PGA
AIN+
AIN−
Internal
Reference
Buffer
VREF
AGND
AV
DD
+ VREF
2
AVDD − VREF
2
Figure 27. ADC Reference Generation, MODE = AVDD/2
Connecting MODE to AVDD or AVDD/2 enables the internal ADC references buffer A2. The outputs of A2 are
connected to the REFT and REFB pins and its inputs are connected to pins VREF and AGND. The resulting
voltages at REFT and REFB are:
REFT +ǒAVDD )VREFǓ
2
REFB +ǒAVDD *VREFǓ
2
Depending on the connection of the REFSENSE pin, the voltage on VREF may be driven by an off-chip source
or by the internal bandgap reference (A1) (see onboard reference generator configuration) to match the
THS1041 input range to their application requirements.
When MODE = AVDD the CLAMPOUT pin provides a buffered, stabilized AVDD/2 output voltage that can be
used as a bias reference for ac coupling networks connecting the signal sources to the AIN+ or AIN− inputs.
This removes the need for the user to provide a stabilized external bias reference.
(8)
(9)
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PRINCIPLES OF OPERATION
internal reference mode (MODE = AVDD or AVDD/2) (continued)
AIN+
AIN−
REFT
REFB
REFSENSE
MODE
+FS
−FS
0.1 µF10 µF
0.1 µF
0.1 µF
VREF
+FS
−FS
AIN+
AIN−
AVDD or
CLAMPOUT
AV
DD
2
VMID if MODE = AVDD
AVDD
2
VCLAMP if MODE =
1 V (Output)
Figure 28. Internal Reference Mode, 1-V Reference Span
AIN+
AIN−
REFT
REFB REFSENSE
MODE
+FS
−FS
0.1 µF10 µF
0.1 µF
0.1 µF
VM
_
+
VM
DC SOURCE = VM
AVDD
2or AVDD
VREF 0.5 V (Output)
Figure 29. Internal Reference Mode, 0.5-V Reference Span, Single-Ended Input
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PRINCIPLES OF OPERATION
onboard reference generator configuration
The internal bandgap reference A1 can provide a supply-voltage-independent and temperature-independent
voltage on pin VREF.
External connections to REFSENSE control A1’s output to the VREF pin as shown in Table 1.
Table 1. Effect of REFSENSE Connection on VREF Value
REFSENSE CONNECTION A1 OUTPUT TO VREF REFER TO:
VREF pin 0.5 V Figure 30
AGND 1 V Figure 31
External divider junction (1 + Ra/Rb)/2 V Figure 32
AVDD Open circuit Figure 33
REFSENSE = AVDD powers the internal bandgap reference A1 down, saving power when A1 is not required.
If MODE is connected to AVDD or AVDD/2, then the voltage at VREF determines the ADC reference voltages:
REFT +AVDD
2)VREF
2
REFB +AVDD
2*VREF
2
REFT–REFB +VREF
_
+
_
+
VBG
ADC
References
Buffer A2
MODE =
REFSENSE
0.1 µF1 µF
AGND
VREF = 0.5 V
AVDD
2or AVDD
Figure 30. 0.5-V VREF Using the Internal Bandgap Reference A1
(10)
(11)
(12)
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PRINCIPLES OF OPERATION
onboard reference generator configuration (continued)
_
+
VBG
ADC
References
Buffer A2
MODE =
REFSENSE
0.1 µF1 µF
AGND
VREF = 1 V
10 kΩ
10 kΩ
_
+
AVDD
2or AVDD
Figure 31. 1-V VREF Using the Internal Bandgap Reference A1
_
+
VBG
ADC
References
Buffer A2
MODE =
REFSENSE
0.1 µF1 µF
AGND
VREF = (1 + Ra/Rb)/2
Ra
Rb
_
+
AVDD
2or AVDD
Figure 32. External Divider Mode
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PRINCIPLES OF OPERATION
onboard reference generator configuration (continued)
_
+
VBG
ADC
References
Buffer A2
MODE =
REFSENSE
AGND
VREF = External
AVDD
_
+
AVDD
2or AVDD
Figure 33. Drive VREF Mode
operating configuration examples
Figure 34 shows a configuration using the internal ADC references for digitizing a single-ended signal with span
0 V t o 2 V. Tying REFSENSE to ground gives 1 V at pin VREF. Tying MODE to AVDD/2 then sets the REFT and
REFB voltages via the internal reference generator for a 2-Vp-p ADC input range and the CLAMPOUT pin also
provides the midscale 1-V bias for the AIN− input. Using the clamp to drive AIN− rather than connecting AIN−
directly t o VREF helps to prevent kickback from the AIN− pin corrupting VREF. AIN− can be connected to VREF,
provided that VREF is well-decoupled to analog ground. Internal PGA gain setting is 1.
AIN+
AIN−
VREF = 1 V
REFB
MODE
REFSENSE
AVDD/2
2 V
0 V
1 V
CLAMPOUT
REFT
CLAMPIN
CLAMP
AVDD
20 Ω
20 Ω
10 µF
0.1 µF
0.1 µF
10 µF0.1 µF
20 pF
20 pF
1 µF
Figure 34. Operating Configuration: 2-V Single-Ended Input, Internal ADC References
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PRINCIPLES OF OPERATION
operating configuration examples (continued)
Figure 35 shows a configuration using the internal ADC references for digitizing a dc-coupled differential input
with 1.5-Vp-p span and 1.5-V common-mode voltage. External resistors are used to set the internal bandgap
reference output at VREF to 0.75 V. Tying MODE to AVDD then sets the REFT and REFB voltages via the internal
reference generator for a 1.5-Vp-p ADC input range.
If a transformer is used to generate the dif ferential ADC input from a single-ended signal, then the CLAMPOUT
pin provides a suitable bias voltage for the secondary windings center tap when MODE = AVDD.
AIN+
AIN−
VREF = 0.75 V
REFB
MODE
REFSENSE
AVDD
1.875 V
1.125 V
1.875 V
1.125 V
1.5 V
1.5 V
REFT
5 kΩ
10 kΩ
0.1 µF
10 µF
20 pF
20 pF
20 Ω
20 Ω
0.1 µF
0.1 µF
10 µF
Figure 35. Operating Configuration: 1.5-V Differential Input, Internal ADC References
Figure 36 shows a configuration using the internal ADC references and an external VREF source for digitizing
a dc coupled single-ended input with span 0.5 V to 2 V. A 1.25-V external source provides the bias voltage for
the AIN− pin and also, via a buffered potential divider; the 0.75 VREF voltage required to set the input range
to 1.5 Vp-p MODE is tied to AVDD to set internal ADC references configuration.
AIN+
AIN− REFT
MODE
REFB
2 V
0.5 V
1.25 V
VREF
AVDD
10 kΩ_
+
REFSENSE AVDD
15 kΩ
(0.75 V)
1.25
Source
0.1 µF10 µF
0.1 µF
0.1 µF
20 pF
20 pF
20 Ω
20 Ω
10 µF
Figure 36. Operating Configuration: 1.5-V Single-Ended Input, External VREF Source
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PRINCIPLES OF OPERATION
operating configuration examples (continued)
Figure 37 shows a configuration using external ADC references for digitizing a dif ferential input with span 0.8 V.
To maximize the signal swing at the ADC core, the PGA gain is set to 2.5 to give a 2-Vp-p output from the PGA.
MODE is tied to ground to disable the internal reference buffer. The external ADC reference sources must set
REFT 1 V higher than REFB to set the ADC input span to 2 Vp-p, and the voltages provided by the external
sources must be centered near AVDD/2 for best ADC operation. REFSENSE is shown tied to AVDD to disable
the internal bandgap refence (A1), though other components in the system may use the VREF output if desired.
External ADC references are best suited to applications which require the tighter reference voltage tolerance
and temperature coefficient than the internal bandgap reference (A1) can provide, or where the references are
to be shared among several THS1041 ADCs for best matching of their ADC channels.
AIN+
AIN−
REFB
MODE
REFSENSE AVDD
1.7 V
1.3 V
1.7 V
1.3 V
1.5 V
1.5 V
REFT
2 V
1 V
0.1 µF
10 µF
20 pF
20 pF
20 Ω
20 Ω
10 µF
10 µF
Figure 37. Operating Configuration: 0.8-V Differential Input and External ADC References
clamp operation
10-Bit
DAC
_
+
CLAMPIN
CLAMP
AIN+
RIN
CIN
V(Clamp)
Control Register (Bit CLINT)
S/H
VIN
SW1
CLAMPOUT
Figure 38. Schematic of Clamp Circuitry
The THS1041 provides a clamp function for restoring a dc reference level to the signal at AIN+ or AIN− which
has been lost through ac-coupling from the signal source to this pin.
Figure 38 and Figure 39 show an example of using the clamp to restore the black level of a composite video
input ac-coupled to AIN+. While the clamp pin is held high, the clamp amplifier forces the voltage at AIN+ to equal
the clamp reference voltage, setting the dc voltage at AIN+ for the video black level.
After power up, the clamp reference voltage is the voltage on the CLAMPIN pin. This reference can instead be
taken from the internal CLAMP DAC by suitably programming the THS1041 clamp and control registers.
Clamp acquisition and clamp droop design calculations are discussed later.
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PRINCIPLES OF OPERATION
clamp operation (continued)
Line Sync Black
Level
Video at AIN
CLAMP
Figure 39. Example Waveforms for Line-Clamping to a Video Input Black Level
clamp DAC output voltage range and limits
When using the internal clamp DAC, the user must ensure that the desired dc clamp level at AIN+/− lies within
the voltage range VREFB to VREFT. This is because the clamp DAC voltage is constrained to lie within this range
VREFB to VREFT. Specifically:
VDAC +VREFB )(VREFT *VREFB) (0.006 )0.988 (DAC code)ń1024)
DAC codes can range from 0 to 1023. Figure 40 graphically shows the clamp DAC output voltage versus the
DAC code.
VDAC
0 1023
VREFB + 0.006(VREFT−VREFB)
VREFB + 0.987(VREFT−VREFB)
DAC Code
VREFT
VREFB
Figure 40. Clamp DAC Output Voltage Versus DAC Register Code Value
If the desired dc level at AIN+/− does not lie within the voltage range VREFT to VREFB, then either the CLAMPIN
pin can be used instead to provide a suitable reference voltage, or it may be possible to redesign the application
to move the AIN+/− input range into the CLAMP DAC voltage range.
(13)
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PRINCIPLES OF OPERATION
power management
In power-sensitive applications (such as battery-powered systems) where the THS1041 ADC is not required
to convert continuously, power can be saved between conversion intervals by placing the THS1041 into
power-down mode. This is achieved by setting bit 3 (PWDN) of the control register to 1. In power-down mode,
the device typically consumes less than 0.1 mW. Power-down mode is exited by resetting control register bit
3 to 0. On power up, typical wake-up and power-up times apply. See power supply section.
In systems where the ADC must run continuously, but where the clamp is not required, the supply current can
be reduced by approximately 1.2 mA by setting the control register bit 6 (CLDIS) to 1, which disables the clamp
circuit. Similarly, when REFSENSE is tied to AVDD, the reference generator is disabled and supply current
reduced by approximately 1.2 mA.
output format and digital I/O
While the OE pin is held low , ADC conversion results are output at pins I/O0 (LSB) to I/O9 (MSB). The ADC input
over-range indicator is output at pin OVR. OVR is also disabled when OE is held high.
The default ADC output data format is unsigned binary (output codes 0 to 1023). The output format can be
switched to 2s complement (output codes −512 to 511) by setting control register bit 5 (TWOC) to 1.
writing to the internal registers through the digital I/O bus
Pulling pin OE high disables the I/O and OVR pin output drivers, placing the driver outputs in a high impedance
state. This allows control register data to be loaded into the THS1041 by presenting it on the I/O0 to I/O9 pins
and pulsing the WR pin high then low to latch the data into the chosen control or DAC register.
Figure 41 shows an example register write cycle where the clamp DAC code is set to 10F (hex) by writing to
clamp registers 1 and 2 (see the register map in Table 2). Pins I/O0 to I/O7 are driven to the clamp DAC code
lower byte (0F hex), and pins I/08 and I/O9 are both driven to 0 to select clamp register 1 as the data destination.
The clamp low-byte data is then loaded into this register by pulsing WR high. The top 2 bits of the DAC word
are then loaded by driving 01(hex) on pins I/O0 to I/O7 and by driving pin I/O8 to 1 and pin I/O9 to 0 to select
clamp register 2 as the data destination. WR is pulsed a second time to latch this second control word into clamp
register 2. Interface timing parameters are given in Figures 1 and 2.
OE
WR
I/O (0−9) ADC Output Input 00F Input 101 ADC Output
Load 0F Into
REGISTER 0 Load 01 Into
REGISTER 1
Figure 41. Example Register Write Cycle to Clamp DAC Register
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PRINCIPLES OF OPERATION
digital control registers
The THS1041 contains two clamp registers and a control register for user programming of THS1041 operation.
Binary data can be written into these registers by using pins I/O0 to I/O9 and the WR and OE pins (see the
previous section). In input mode, the two I/O bus MSBs are address bits, 00 addressing clamp register 1, 01
clamp register 2, and 10 the control register. The clamp registers and control registers are write only registers,
and stored values cannot be read on the I/O data bus.
Table 2. Register Map
ADDRESS
DESCRIPTION
DEF
W
BIT
ADDRESS
I/O[9:8]
DESCRIPTION
DEF
(HEX)
W
B7 B6 B5 B4 B3 B2 B1 B0
00 Clamp register 1 00 W DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0]
01 Clamp register 2 00 W DAC[9] DAC[8]
10 Control register 01 W CLDIS TWOC CLINT PDWN PGA[2] PGA[1] PGA[0]
11†Reserved†
†Do not write to register 11
Table 3. Register Contents
REGISTER BIT NO BIT NAME(S) DEFAULT DESCRIPTION
2:0 PGA[2:0] 001
PGA gain:
000 = 0.5
001 = 1.0 (default value)
010 = 1.5
011 = 2.0
100 = 2.5
101 = 3.0
110 = 3.5
111 = 4.0
Control register
I/O[9:8] = 10
3 PDWN 0 Power down
0 = THS1041 powered up
1 = THS1041 powered down
I/O[9:8] = 10
4 CLINT 0 Clamp voltage internal/external
0 = external analog clamp voltage from CLAMPIN pin
1 = from onboard DAC (see clamp register)
5 TWOC 0 Output format
0 = unsigned binary
1 = twos complement
6 CLDIS 0 CLAMPOUT pin disable (for power saving)
0 = Enable
1 = Disable
7 Unused
Clamp register 1
I/O[9:8] = 00 7:0 DAC[7:0] 0
Clamp DAC voltage
(DAC[0] = LSB.)
DAC[9:0] = 00h: Clamp voltage = REFB
DAC[9:0] = 3Fh: Clamp voltage = REFT
Clamp register 2
7:2 Unused
Clamp register 2
I/O[9:8] = 01 1:0 DAC[9:8] 0 Clamp DAC voltage
(DAC[9] = MSB)
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APPLICATION INFORMATION
driving the THS1041 analog inputs
driving the clock input
Obtaining good performance from the THS1041 requires care when driving the clock input.
Different sections of the sample-and-hold and ADC operate while the clock is low or high. The user should
ensure that the clock duty cycle remains near 50% to ensure that all internal circuits have as much time as
possible in which to operate.
The CLK pin should also be driven from a low jitter source for best dynamic performance. To maintain low jitter
at the CLK input, any clock buffers external to the THS1041 should have fast rising edges. Use a fast logic family
such as AC or ACT to drive the CLK pin, and consider powering any clock buffers separately from any other
logic on the PCB to prevent digital supply noise appearing on the buffered clock edges as jitter.
As the CLK input threshold is nominally around AVDD/2, any clock buffers need to have an appropriate supply
voltage to drive above and below this level.
driving the sample and hold inputs
driving the AIN+ and AIN− pins
Figure 42 shows an equivalent circuit for the THS1041 AIN+ and AIN− pins. The load presented to the system
at the AIN pins comprises the switched input sampling capacitor, C Sample, and various stray capacitances, C1
and C2.
C1
8 pF
AVDD
AGND
CLK
CLK
C2
1.2 pF
1.2 pF
CSample
VCM = AIN+/AIN− Common Mode Voltage
AIN
_
+
Figure 42. Equivalent Circuit for Analog Input Pins AIN+ and AIN−
The input current pulses required to charge CSample and C2 can be time averaged and the switched capacitor
circuit modelled as an equivalent resistor:
RIN2 +1
CS fCLK
where C S is the sum of CSample and C2. This model can be used to approximate the input loading versus source
resistance for high impedance sources.
(14)
SLAS289C − O C TOBER 2001 − REVISED OCTOBER 2004
29
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APPLICATION INFORMATION
C1
8 pF
AVDD
AGND VCM = AIN+/AIN− Common Mode Voltage
AIN
_
+
IIN
R2 = 1/CS fCLK
Figure 43. Equivalent Circuit for the AIN Switched Capacitor Input
AIN input damping
The charging current pulses into AIN+ and AIN− can make the signal sources jump or ring, especially if the
sources are slightly inductive at high frequencies. Inserting a small series resistor of 20 Ω or less and a small
capacitor to ground of 20 pF or less in the input path can damp source ringing (see Figure 44). The resistor and
capacitor values can be made larger than 20 Ω and 20 pF if reduced input bandwidth and a slight gain error (due
to potential division between the external resistors and the AIN equivalent resistors) are acceptable.
Note that the capacitors should be soldered to a clean analog ground with a common ground point to prevent
any voltage drops in the ground plane appearing as a differential voltage at the ADC inputs.
AIN
R< 20 Ω
VSC < 20 pF
Figure 44. Damping Source Ringing Using a Small Resistor and Capacitor
driving the VREF pin
Figure 45 shows the equivalent load on the VREF pin when driving the ADC internal references buffer via this
pin (MODE = AVDD/2 or AVDD and REFSENSE = AVDD).
AVDD
AGND
(AVDD + VREF) /4
VREF RIN
10 kΩREFSENSE = AVDD,
MODE = AVDD/2 or AVDD
_
+
MODE = AVDD
Figure 45. Equivalent Circuit of VREF
The nominal input current IREF is given by:
IREF +3V
REF *AVDD
4 RIN
(15)
SLAS289C − O C TOBER 2001 − REVISED OCTOBER 2004
30 www.ti.com
APPLICATION INFORMATION
driving the VREF pin (continued)
Note that the maximum current may be up to 30% higher. The user should ensure that VREF is driven from a
low noise, low drift source, well decoupled to analog ground and capable of driving the maximum IREF.
driving REFT and REFB (external ADC references, MODE = AGND)
AVDD
AGND
AVDD
AGND
2 kΩ
REFT
REFB
To ADC Core
To ADC Core
Figure 46. Equivalent Circuit of REFT and REFB Inputs
designing the dc clamp
Figure 38 shows the basic operation of the clamp circuit with the analog input AIN+ coupled via an RC circuit.
AIN− must be connected to a dc source whose voltage level keeps the THS1041 dif ferential input within the ADC
input range. The clamp voltage output level may be established by an analog voltage on the CLAMPIN pin or
by programming the on-chip clamp DAC.
(Note that it is possible to reverse the AIN+ and AIN− connections if signal inversion is also required. The
following section assumes that the signal is coupled to AIN+ and that AIN− is connected to a suitable dc bias
level).
initial clamp acquisition time
Acquisition time is the time required to reach the target clamp voltage at AIN+ when the clamp switch SW1 is
closed for the first time. The acquisition time is given by
TACQ +CIN RlN ln ǒVC
VEǓ
where VC is the dif ference between the dc level of the input VIN and the target clamp output voltage, VClamp.
VE is the difference between the ideal VC and the actual VC obtained during the acquisition time. The maximum
tolerable error depends on the application requirements.
For example, consider clamping an incoming video signal that has a black level near 0.3 V to a black level of
1.3 V at the THS1041 AIN+ input. The voltage VC required across the input coupling capacitor is thus
1.3 − 0.3 = 1 V. If a 10 mV or less clamp voltage error VE gives acceptable system operation, the source
resistance RIN is 20 Ω and the coupling capacitor CIN is 1 µF, then the total clamp pulse duration required to
reach this error is:
TACQ = 1 µF × 20 Ω × ln(1/0.01) = 92 µs (approximate)
(16)
SLAS289C − O C TOBER 2001 − REVISED OCTOBER 2004
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APPLICATION INFORMATION
initial clamp acquisition time (continued)
Initial acquisition can be performed in two ways:
DPulsing the CLAMP pin as in normal operation. Provided that clamp droop (see below) is negligible, initial
acquisition is complete when the total clamped (CLAMP = high) time equals TACQ.
DPulling the CLAMP pin high for the required acquisition time before starting normal operation. This method
is faster, though possibly less convenient for the user to implement.
clamp droop
The charging currents drawn by the sample-and-hold switched capacitor input can charge or discharge CIN,
causing the dc voltage at AIN+ to drift towards the dc bias voltage at AIN− during the time between clamp pulses.
This effect is called clamp droop.
Voltage droop is a function of the AIN+ and AIN− input currents to the THS1041, IIN, and the time between clamp
intervals, tD:
VDROOP [ǒIIN
CINǓ td(approximate)
Worst case droop between clamping intervals occurs for maximum input bias current. Maximum input current
is IINFS, which occurs when the input level is at its maximum or minimum.
For example, at 40 MSPS IINFS is approximately 20 µA for a 2-V input range at AIN (assuming 2 V appear across
RIN2—see driving the sample and hold reference inputs to calculate RIN2). Note that IINFS may vary from this
by ±30% because of processing variations and voltage dependencies. Designs should allow for this variation.
If the time td between clamping intervals is 63.5 µs and C IN is 1 µF, then the maximum clamp level droop between
clamp pulses is
VDROOP(max) +20 mAń1mF 63.5 ms+1.25 mV (approximate, ignoring 30% tolerance)
+0.62 LSB at PGA gain +1, 2 V ADC references
If this droop is greater than can be tolerated in the application, then increase CIN to slow the droop and hence
reduce the voltage change between clamp pulses.
If a high leakage capacitor is used for coupling the input source to the AIN pin then the droop may be significantly
worse than calculated above. Avoid using electrolytic and tantalum coupling capacitors as these have higher
leakage currents than nonpolarized capacitor types. Electrolytic and tantalum capacitors also tend to have
higher parasitic inductance, which can cause problems at high input frequencies.
steady-state clamp voltage error
During the clamp pulse (CLAMP = high), the dc voltage on AIN is refreshed from the clamp voltage. Provided
that droop is not excessive, clamping fully reverses the ef fect of droop. However, using very short clamp pulses
with long intervals between pulses (td) can result in a steady-state voltage difference, VCOS, between the dc
voltage at AIN and V(Clamp).
Figure 47 shows the approximate voltage waveform at AIN resulting from a a large clamp droop during td and
clamp voltage reacquisition during the clamp pulse time, tc.
(17)
(18)
SLAS289C − O C TOBER 2001 − REVISED OCTOBER 2004
32 www.ti.com
APPLICATION INFORMATION
steady-state clamp voltage error (continued)
VCOS
VDROOP = ∆VAIN
tctd
V(Clamp)
VAIN
VM
Figure 47. Approximate Waveforms at AIN During Droop and Clamping
The voltage change at AIN during acquisition has been approximated as a linear charging ramp by assuming
that almost all of VCOS appears across RIN, giving a charging current VCOS/RIN (this is a reasonable
approximation when VCOS is large enough to be of concern). The voltage change at AIN during clamp
acquisition is then:
DVAIN +VCOS td
RIN CIN
The peak-to-peak voltage variation at AIN must equal the clamp droop voltage at steady state. Equating the
droop voltage to the clamp acquisition voltage change gives:
VCOS +RIN IIN td
tc
Thus for low offset voltage, keep RIN low, design for low droop and ensure that the ratio td/tc is not unreasonably
large.
reference decoupling
VREF pin
When the on-chip reference generator is enabled, the VREF pin should be decoupled to the circuit board’s
analog ground plane close to the THS1041 AGND pin via a 1-µF capacitor and a 0.1-µF ceramic capacitor.
REFT and REFB pins
In any mode of operation, the REFT and REFB pins should be decoupled as shown in Figure 48. Use short
board traces between the THS1041 and the capacitors to minimize parasitic inductance.
THS1041
REFT
REFB
0.1 µF
10 µF
0.1 µF
0.1 µF
Figure 48. Recommended Decoupling for the ADC Reference Pins REFT and REFB
(19)
(20)
SLAS289C − O C TOBER 2001 − REVISED OCTOBER 2004
33
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APPLICATION INFORMATION
CLAMPOUT decoupling (when used as dc bias source)
When using CLAMPOUT as a dc biasing reference (e.g., MODE = AVDD), the CLAMPOUT pin should be
decoupled to the circuit board’s analog ground plane close to the THS1041 AGND pin via a 1-µF capacitor and
a 0.1-µF ceramic capacitor.
supply decoupling
The analog (AVDD, AGND) and digital (DVDD, DGND) power supplies to the THS1041 should be separately
decoupled for best performance. Each supply needs at least a 10-µF electrolytic or tantalum capacitor (as a
charge reservoir) and a 100-nF ceramic type capacitor placed as close as possible to the respective pins (to
suppress spikes and supply noise).
digital output loading and circuit board layout
The THS1041 outputs are capable of driving rail-to-rail with up to 10 pF of load per pin at 40-MHz clock frequency
and 3-V digital supply. Minimizing the load on the outputs improves THS1041 signal-to-noise performance by
reducing the switching noise coupling from the THS1041 output buffers to the internal analog circuits. The
output load capacitance can be minimized by buf fering the THS1041 digital outputs with a low input capacitance
buffer placed as close to the output pins as physically possible, and by using the shortest possible tracks
between the THS1041 and this buffer. Inserting small resistors in the range 100 Ω to 300 Ω between the
THS1041 I/O outputs and their loads can help minimize the output-related noise in noise-critical applications.
Noise levels at the output buf fers, which may af fect the analog circuits within THS1041, increase with the digital
supply voltage. Where possible, consider using the lowest DVDD that the application can tolerate.
Use good layout practices when designing the application PCB to ensure that any off-chip return currents from
the THS1041 digital outputs (and any other digital circuits on the PCB) do not return via the supplies to any
sensitive analog circuits. The THS1041 should be soldered directly to the PCB for best performance. Socketing
the device degrades performance by adding parasitic socket inductance and capacitance to all pins.
user tips for obtaining best performance from the THS1041
DChoose differential input mode for best distortion performance.
DChoose a 2-V ADC input span for best noise performance.
DChoose a 1-V ADC input span for best distortion performance.
DDrive the clock input CLK from a low-jitter, fast logic stage, with a well-decoupled power supply and short
PCB traces.
DUse a small RC filter (typically 20 Ω and 20 pF) between the signal source(s) the AIN+ (and AIN−) input(s)
when the systems bandwidth requirements allow this.
SLAS289C − O C TOBER 2001 − REVISED OCTOBER 2004
34 www.ti.com
APPLICATION INFORMATION
definitions
DIntegral nonlinearity (INL)—Integral nonlinearity refers to the deviation of each individual code from a line
drawn from zero to full scale. The point used as zero occurs 1/2 LSB before the first code transition. The
full-scale point is defined as a level 1/2 LSB beyond the last code transition. The deviation is measured from
the center of each particular code to the true straight line between these two endpoints.
DDifferential nonlinearity (DNL)—An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL
is the deviation from this ideal value. Therefore this measure indicates how uniform the transfer function
step sizes are. The ideal step size is defined here as the step size for the device under test (i.e., (last
transition level – first transition level) ÷ (2n – 2)). Using this definition for DNL separates the effects of gain
and offset error. A minimum DNL better than –1 LSB ensures no missing codes.
DZero-error—Zero-error is defined as the dif ference in analog input voltage—between the ideal voltage and
the actual voltage—that switches the ADC output from code 0 to code 1. The ideal voltage level is
determined by adding the voltage corresponding to 1/2 LSB to the bottom reference level. The voltage
corresponding to 1 LSB is found from the difference of top and bottom references divided by the number
of ADC output levels (1024).
DFull-scale error—Full-scale error is defined as the difference in analog input voltage—between the ideal
voltage and the actual voltage—that will switch the ADC output from code 1022 to code 1023. The ideal
voltage level is determined by subtracting the voltage corresponding to 1.5 LSB from the top reference level.
The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by
the number of ADC output levels (1024).
DWake-up time—Wake-up time is from the power-down state to accurate ADC samples being taken and is
specified for MODE = AGND with external reference sources applied to the device at the time of release
of power-down, and an applied 40-MHz clock. Circuits that need to power up are the bandgap, bias
generator, SHPGA, and ADC.
DPower-up time—Power-up time is from the power-down state to accurate ADC samples being taken and
is specified for MODE = AVDD/2 or AVDD and an applied 40-MHz clock. Circuits that need to power up
include VREF reference generation (A1), bias generator, ADC, the SHPGA, and the on-chip ADC reference
generator (A2).
DAperture delay—The delay between the 50% point of the rising edge of the clock and the instant at which
the analog input is sampled.
DAperture uncertainty (Jitter)—The sample-to-sample variation in aperture delay.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
THS1041CDW ACTIVE SOIC DW 28 20 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS1041CDWG4 ACTIVE SOIC DW 28 20 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS1041CPW ACTIVE TSSOP PW 28 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS1041CPWG4 ACTIVE TSSOP PW 28 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS1041CPWR ACTIVE TSSOP PW 28 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS1041CPWRG4 ACTIVE TSSOP PW 28 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS1041IDW ACTIVE SOIC DW 28 20 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS1041IDWG4 ACTIVE SOIC DW 28 20 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS1041IPW ACTIVE TSSOP PW 28 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS1041IPWG4 ACTIVE TSSOP PW 28 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 3-Apr-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
THS1041CPWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
THS1041CPWR TSSOP PW 28 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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