MC100LVELT23DR2G - ON Semiconductor L.L.C.

August, 2010 − Rev. 18

1Publication Order Number:

MC100LVELT23/D

MC100LVELT23

3.3 V Dual Differential

LVPECL/LVDS to LVTTL

Translator

Description

The MC100LVELT23 is a dual differential LVPECL/LVDS to

LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels

are used only +3.3 V and ground are required. The small outline 8-lead

package and the dual gate design of the LVELT23 makes it ideal for

applications which require the translation of a clock and a data signal.

The LVELT23 is available in only the ECL 100K standard. Since

there are no LVPECL outputs or an external VBB reference, the

LVELT23 does not require both ECL standard versions. The LVPECL

inputs are differential. Therefore, the MC100LVELT23 can accept any

standard differential LVPECL input referenced from a VCC of +3.3 V.

Features

•2.0 ns Typical Propagation Delay

•Maximum Frequency > 180 MHz

•Differential LVPECL Inputs

•PECL Mode Operating Range:VCC = 3.0 V to 3.8 V

with GND = 0 V

•24 mA LVTTL Outputs

•Flow Through Pinouts

•Internal Pulldown and Pullup Resistors

•Pb−Free Packages are Available

*For additional marking information, refer to

Application Note AND8002/D.

MARKING

DIAGRAMS*

KR23

ALYWG

SOIC−8

D SUFFIX

CASE 751

TSSOP−8

DT SUFFIX

CASE 948R

http://onsemi.com

KVT23

ALYW

DFN8

MN SUFFIX

CASE 506AA

4J M G

(Note: Microdot may be in either location)

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

M= Date Code

G= Pb−Free Package

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

ORDERING INFORMATION

MC100LVELT23

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GND

VCC

Figure 1. 8−Lead Pinout (Top View)

and Logic Diagram

Q1D1

LVPECL LVTTL

Table 1. PIN DESCRIPTION

Pin Function

Q0, Q1

D0*, D1*

VCC

GND

LVTTL Outputs

Differential LVPECL Inputs

Positive Supply

Ground

(DFN8 only) Thermal exposed pad must

be connected to a sufficient thermal con-

duit. Electrically connect to the most neg-

ative supply (GND) or leave unconnec-

ted, floating open.

** Pins will default to VCC/2 when left open.

Table 2. ATTRIBUTES

Characteristics Value

Internal Input Pulldown Resistor 50 kW

Internal Input Pullup Resistor 50 kW

ESD Protection Human Body Model

Machine Model

CDM

> 1500 V

> 100 V

> 2000 V

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Level 1

Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in

Transistor Count 91

Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. Refer to Application Note AND8003/D for additional information.

MC100LVELT23

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Table 3. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

VCC PECL Power Supply GND = 0 V 3.8 V

VIInput Voltage GND = 0 V,

VI not more positive than VCC

3.8 V

Iout Output Current Continuous

Surge

100

TAOperating Temperature Range −40 to +85 °C

Tstg Storage Temperature −65 to +150 °C

qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

SOIC−8

190

130

°C/W

qJC Thermal Resistance (Junction−to−Case) Standard Board SOIC−841 to 44 ± 5% °C/W

qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

TSSOP−8

185

140

°C/W

qJC Thermal Resistance (Junction−to−Case) Standard Board TSSOP−841 to 44 ± 5% °C/W

qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

DFN8

129

°C/W

Tsol Wave Solder Pb

Pb−Free

<2 to 3 sec @ 248°C

<2 to 3 sec @ 260°C

265

°C

qJC Thermal Resistance (Junction−to−Case) (Note 2) DFN8 35 to 40 °C/W

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)

Table 4. LVPECL INPUT DC CHARACTERISTICS VCC = 3.3 V; GND = 0 V (Note 3)

Symbol Characteristic

−40°C 25°C 85°C

Min Typ Max Min Typ Max Min Typ Max Unit

ICCH Power Supply Current (Outputs set to HIGH) 10 20 35 10 20 35 10 20 35 mA

ICCL Power Supply Current (Outputs set to LOW) 15 27 40 15 27 40 15 27 40 mA

VIH Input HIGH Voltage (Note 5) 2135 2420 2135 2420 2135 2420 mV

VIL Input LOW Voltage (Note 5) 1490 1825 1490 1825 1490 1825 mV

VIHCMR Input HIGH Voltage Common Mode Range

(Notes 4 and 5)

1.2 VCC 1.2 VCC 1.2 VCC V

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current D −150 −150 −150 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

3. All values vary 1:1 with VCC. VCC can vary ±0.3 V.

4. VIHCMR min varies 1:1 with GND, max varies 1:1 with VCC.

5. LVTTL output RL = 500 W to GND.

MC100LVELT23

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Table 5. LVTTL OUTPUT DC CHARACTERISTICS VCC = 3.3 V; GND = 0V (Note 6)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

VOH Output HIGH Voltage (IOH = −3.0 mA) (Note 7) 2.4 2.4 2.4 V

VOL Output LOW Voltage (IOL = 24 mA) (Note 7) 0.5 0.5 0.5 V

IOS Output Short Circuit Current −180 −50 −180 −50 −180 −50 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

6. All values vary 1:1 with VCC. VCC can vary ±0.3 V.

7. LVTTL output RL = 500 W to GND.

Table 6. AC CHARACTERISTICS VCC = 3.3 V; GND = 0 V (Notes 8, 9)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

Fmax Maximum Toggle Frequency (Note 10) 180 180 180 MHz

tPLH,

tPHL

Propagation Delay to

Output Differential

1.0 1.5 2.5 1.0 1.7 2.5 1.0 1.7 2.5 ns

tSK+ +

tSK− −

tSKPP

Output−to−Output Skew++

Output−to−Output Skew− −

Part−to−Part Skew (Note 11)

500

140

125

500

tJITTER Random Clock Jitter (RMS) 4.0 10 4.0 10 4.0 10 ps

VPP Input Voltage Swing (Differential Configuration)

(Note 12)

200 800 1000 200 800 1000 200 800 1000 mV

Output Rise/Fall Times

(0.8 V − 2.0 V) Q, Q

330 600 900 330 600 900 330 650 900 ps

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

8. All values vary 1:1 with VCC. VCC can vary ±0.3 V.

9. LVTTL output RL = 500 W to GND and CL = 20 pF to GND. Refer to Figure 2.

10.Fmax guaranteed for functionality only. VOL and VOH levels are guaranteed at DC only.

11. Skews are measured between outputs under identical conditions.

12.200 mV input guarantees full logic swing at the output.

Figure 2. TTL Output Loading Used for Device Evaluation

CHARACTERISTIC TEST

CL*R

AC TEST LOAD

GND

*CL includes

fixture

capacitance

APPLICATION

TTL RECEIVER

MC100LVELT23

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ORDERING INFORMATION

Device Package Shipping†

MC100LVELT23D SOIC−898 Units / Rail

MC100LVELT23DG SOIC−8

(Pb−Free)

98 Units / Rail

MC100LVELT23DR2 SOIC−82500 / Tape & Reel

MC100LVELT23DR2G SOIC−8

(Pb−Free)

2500 / Tape & Reel

MC100LVELT23DT TSSOP−8100 Units / Rail

MC100LVELT23DTG TSSOP−8

(Pb−Free)

100 Units / Rail

MC100LVELT23DTR2 TSSOP−82500 / Tape & Reel

MC100LVELT23DTRG TSSOP−8

(Pb−Free)

2500 / Tape & Reel

MC100LVELT23MNRG DFN8

(Pb−Free)

1000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

Resource Reference of Application Notes

AN1405/D −ECL Clock Distribution Techniques

AN1406/D −Designing with PECL (ECL at +5.0 V)

AN1503/D −ECLinPSt I/O SPiCE Modeling Kit

AN1504/D −Metastability and the ECLinPS Family

AN1568/D −Interfacing Between LVDS and ECL

AN1672/D −The ECL Translator Guide

AND8001/D −Odd Number Counters Design

AND8002/D −Marking and Date Codes

AND8020/D −Termination of ECL Logic Devices

AND8066/D −Interfacing with ECLinPS

AND8090/D −AC Characteristics of ECL Devices

MC100LVELT23

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PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AJ

SEATING

PLANE

X 45 _

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

0.10 (0.004)

DIM

MIN MAX MIN MAX

INCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B3.80 4.00 0.150 0.157

C1.35 1.75 0.053 0.069

D0.33 0.51 0.013 0.020

G1.27 BSC 0.050 BSC

H0.10 0.25 0.004 0.010

J0.19 0.25 0.007 0.010

K0.40 1.27 0.016 0.050

M0 8 0 8

N0.25 0.50 0.010 0.020

S5.80 6.20 0.228 0.244

−X−

−Y−

0.25 (0.010)

−Z−

0.25 (0.010) ZSXS

____

1.52

0.060

7.0

0.275

0.6

0.024

1.270

0.050

4.0

0.155

ǒmm

inchesǓ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

MC100LVELT23

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PACKAGE DIMENSIONS

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A2.90 3.10 0.114 0.122

B2.90 3.10 0.114 0.122

C0.80 1.10 0.031 0.043

D0.05 0.15 0.002 0.006

F0.40 0.70 0.016 0.028

G0.65 BSC 0.026 BSC

L4.90 BSC 0.193 BSC

M0 6 0 6

____

SEATING

PLANE

PIN 1

DETAIL E

2X L/2

−U−

U0.15 (0.006) T

0.10 (0.004) V S

0.10 (0.004)

−T−

−V−

−W−

0.25 (0.010)

8x REFK

IDENT

K0.25 0.40 0.010 0.016

TSSOP−8

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948R−02

ISSUE A

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.

PROTRUSIONS OR GATE BURRS. MOLD FLASH

OR GATE BURRS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED 0.25 (0.010)

PER SIDE.

5. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

6. DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE -W-.

MC100LVELT23

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PACKAGE DIMENSIONS

ÇÇ

DFN8 2x2, 0.5P

CASE 506AA−01

ISSUE E

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994 .

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.20 MM FROM TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

C0.10

PIN ONE

REFERENCE

TOP VIEW

SIDE VIEW

BOTTOM VIEW

(A3)

C0.10

C0.08

NOTE 4 A1 SEATING

PLANE

e/2

NOTE 3

0.10 C

0.05 C

ABB

DIM MIN MAX

MILLIMETERS

A0.80 1.00

A1 0.00 0.05

A3 0.20 REF

b0.20 0.30

D2.00 BSC

D2 1.10 1.30

E2.00 BSC

E2 0.70 0.90

e0.50 BSC

L0.25 0.35

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

2.30

0.50

DIMENSIONS: MILLIMETERS

0.30 PITCH

PACKAGE

OUTLINE

RECOMMENDED

DETAIL A

OPTIONAL

CONSTRUCTIONS

ÉÉ

DETAIL B

MOLD CMPDEXPOSED Cu

OPTIONAL

CONSTRUCTION

DETAIL B

DETAIL A

L1 −−− 0.10

0.30 REF

0.90

1.30

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