Document Number: MPC17533
Rev. 3.0, 12/2013
Freescale Semiconductor
Technical Data
© Freescale Semiconductor, Inc., 2012-2013. All rights reserved.
0.7 A 6.8 V Dual H-Bridge Motor
Driver
The 17533 is a monolithic dual H-Bridge power IC ideal for portable
electronic applications containing bipolar stepper motors and/or brush
DC-motors (e.g., cameras and disk drive head positioners).
The 17533 operates from 2.0 V to 6.8 V, with independent control of
each H-Bridge via parallel MCU interface (3.0 V and 5.0 V compatible
logic). The device features built-in shoot-through current protection
and an undervoltage shutdown function.
The 17533 has four operating modes: forward, reverse, brake, and
tri-stated (high-impedance). The 17533 has a low total RDS(ON) of
1.2 Ω (max at 25 °C).
The 17533’s low output resistance and high slew rate provides
efficient drive for many types of micromotors.
Features
• Low total RDS(ON) 0.8 Ω (typ), 1.2 Ω (max) at 25 °C
• Output current 0.7 A (DC), 1.4 A (peak)
• Shoot-through current protection circuit
•3.0 V/ 5.0 V CMOS-compatible inputs
• PWM control Input frequency up to 200 kHz
• Built-in 2-channel H-Bridge driver
• Low power consumption
• Undervoltage detection and shutdown circuit
Figure 1. 17533 Simplified Application Diagram
H-BRIDGE MOTOR DRIVER
EV SUFFIX (Pb-FREE)
98ASA10614D
16-PIN VMFP
17533
ORDERING INFORMATION
Device
(For Tape and Reel, a dd
an R2 Suffix)
Temperature
Range (TA)Package
MPC17533EV/EL -20 °C to 65 °C 16 VMFP
VDD
VG
IN2B
OE
IN2A
IN1A
OUT2B
OUT2A
OUT1B
OUT1A
VM
GND
MCU
IN1B
5.0 V
13 V
5.0 V
17533
Bipolar
Step
Motor
N
S
Analog Integrated Circuit Device Data
2Freescale Semiconductor
17533
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
Figure 2. 17533 Simplified Internal Block Diagram
VM1
OUT2B
OUT2A
OUT1A
PGND2
IN1A
IN1B
VDD
Low
Shutdown
Level Shifter
VM2
OUT1B
IN2A
IN2B
OE
LGND
PGND1
Control Pre-driver
Voltage
H-Bridge 1
H-Bridge 2
Logic
V
DD
VG
Analog Integrated Circuit Device Data
Freescale Semiconductor 3
17533
PIN CONNECTIONS
PIN CONNECTIONS
Figure 3. 17533 Pin Conne ctions
Table 1. PIN Function Description
Pin Pin Name Formal Name Definition
1OUT1A H-Bridge Output 1A Output A of H-Bridge channel 1.
2VM1 Motor Drive Power Supply 1 Positive power source connection for H-Bridge 1 (Motor Drive Power Supply).
3IN1A Logic Input Control 1A Logic input control of OUT1A (refer to Table 5, Truth Table, page 7).
4IN1B Logic Input Control 1B Logic input control of OUT1B (refer to Table 5, Truth Table, page 7).
5VDD Logic Supply Control circuit power supply pin.
6OE Output Enable Logic output Enable control of H-Bridges (Low = True).
7LGND Logic Ground Low-current logic signal ground.
8OUT1B H-Bridge Output 1B Output B of H-Bridge channel 1.
9PGND1 Power Ground 1 High-current power ground 1.
10 OUT2B H-Bridge Output 2B Output B of H-Bridge channel 2.
11 VM2 Motor Drive Power Supply 2 Positive power source connection for H-Bridge 2 (Motor Drive Power Supply).
12 VG Gate Driver Circuit Voltage Input Input pin for the gate drive voltage.
13 IN2B Logic Input Control 2B Logic input control of OUT2B (refer to Table 5, Truth Table, page 7).
14 IN2A Logic Input Control 2A Logic input control of OUT2A (refer to Table 5, Truth Table, page 7).
15 OUT2A H-Bridge Output 2A Output A of H-Bridge channel 2.
16 PGND2 Power Ground 2 High-current power ground 2.
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
OUT2A
IN2A
IN2B
VG
VM2
OUT2B
PGND1
OUT1A
VM1
IN1A
IN1B
VDD
OE
LGND
OUT1B
PGND2
Analog Integrated Circuit Device Data
4Freescale Semiconductor
17533
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding the ratings may cause a malfunction or permanent
damage to the device.
Rating Symbol Value Unit
Motor Supply Voltage VM-0.5 to 8.0 V
Gate Driver Circuit Power Supply Voltage VG-0.5 to 14 V
Logic Supply Voltage VDD -0.5 to 7.0 V
Signal Input Voltage VIN -0.5 to VDD + 0.5 V
Driver Output Current
Continuous
Peak (1)
IO
IOPK
0.7
1.4
A
ESD Voltage (2)
Human Body Model
Machine Model
VESD1
VESD2
±1500
± 200
V
Operating Junction Temperature TJ-55 to 150 °C
Operating Ambient Temperature TA-20 to 65 °C
Storage Temperature Range TSTG -55 to 150 °C
Thermal Resistance (3) RθJA 150 °C/W
Power Dissipation (4) PD830 mW
Peak Package Reflow Temperature During Reflow (5), (6) TPPRT Note 6 °C
Notes
1. TA = 25°C. 10 ms pulse at 200 ms intervals.
2. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in
accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
3. Mounted on 37 mm x 50 mm x 1.6 mm glass epoxy board mount.
4. TA = 25 °C.
5. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause a malfunction or permanent damage to the device.
6. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and
enter the core ID to view all orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics.
Analog Integrated Circuit Device Data
Freescale Semiconductor 5
17533
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions TA = 25 °C, VDD = VM = 5.0 V, GND = 0 V, unless otherwise noted. Typical values noted
reflect the approximate parameter means at TA = 25 °C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
POWER
Motor Supply Voltage VM2.0 5.0 6.8 V
Logic Supply Voltage VDD 2.7 5.0 5.7 V
Quiescent Power Supply Current
Driver Circuit Power Supply Current
Logic Supply Current (7)
Gate Driver Circuit Power Supply Current
IQM
IQVDD
IQVG
–
–
–
–
–
–
1.0
20
150
μA
Operating Power Supply Current
Logic Supply Current (8)
Gate Driver Circuit Power Supply Current (9)
IVDD
IVG
–
––
–3.0
0.7
mA
Low VDD Detection Voltage (10) VDDDET 1.5 2.0 2.5 V
Driver Output ON Resistance
Source + Sink at IO = 0.7 A(11)
VG = 9.5 V, VM = 5.0 V, TA = 25 °C(12)
RDS(ON)
RDS(ON)2
–
–0.8
–1.2
1.5
Ω
GATE DRIVE
Gate Drive Circuit Power Supply Voltage VG12 13 13.5 V
CONTROL LOGIC
Logic Input Voltage VIN 0 – VDD V
Logic Inputs (2.7 V < VDD < 5.7 V)
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current
Low-Level Input Current
OE Pin Input Current Low
VIH
VIL
IIH
IIL
IIL-OE
VDD x 0.7
–
–
-1.0
–
–
–
–
–
50
–
VDD x 0.3
1.0
–
100
V
V
μA
μA
μA
Notes
7. IQVDD includes the current to pre-driver circuit.
8. I VDD includes the current to pre-driver circuit at fIN = 100 kHz.
9. At fIN = 20 kHz.
10. Detection voltage is defined as when the output becomes high-impedance after VDD drops below the detection threshold. When gate
voltage VG is applied from an external source, VG = 7.5 V.
11. The total H-Bridge ON resistance when VG is 13 V.
12. Increased RDS(ON) value as the result of a reduced VG value of 9.5 V.
Analog Integrated Circuit Device Data
6Freescale Semiconductor
17533
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions TA = 25 °C, VDD = VM = 5.0 V, GND = 0 V, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
INPUT
Pulse Input Frequency f IN – – 200 kHz
Input Pulse Rise Time (13) t R– – 1.0
(14) μs
Input Pulse Fall Time (15) t F – – 1.0
(14) μs
OUTPUT
Propagation Delay Time (16)
Turn-ON Time
Turn-OFF Time
t PLH
t PHL –
–0.1
0.1 0.5
0.5
μs
Low Voltage Detection Time(17) tVDDDET – – 10 ms
Notes
13. Time is defined between 10% and 90%.
14. That is, the input waveform slope must be steeper than this.
15. Time is defined between 90% and 10%.
16. Load of Output is 8.0 Ω resistance. see Figure 4
17. See Figure 5
Analog Integrated Circuit Device Data
Freescale Semiconductor 7
17533
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
Figure 4. tPLH, tPHL, and tPZH Timing Figure 5. Low-Vo ltage Detection Timing Diagram
10%
IN1, 50%
OUTA,
OUTB
IN2,
90%
tPLH tPHL
OE
tVDDDET
0%
IM
50%
tVDDDET
VDDDETon VDDDEToff
90%
(<1.0 μA)
VDD
2.5 V
1.5 V
Table 5. Truth Table
INPUT OUTPUT
OE IN1A
IN2A IN1B
IN2B OUT1A
OUT2A OUT1B
OUT2B
L L L L L
L H L H L
L L H L H
L H H Z Z
H X X Z Z
H = High.
L = Low.
Z = High-impedance.
X = Don’t care.
OE pin is pulled up to VDD with internal resistance.
Analog Integrated Circuit Device Data
8Freescale Semiconductor
17533
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 17533 is a monolithic dual H-Bridge ideal for portable
electronic applications to control bipolar stepper motors and
brush DC motors, such as those found in camera len
assemblies, camera shutters, optical disk drives, etc.
The 17533 operates from 2.0 V to 6.8 V, with independent
control of each H-Bridge via parallel MCU interface (3.0 V
and 5.0 V compatible I/O). The device features built-in shoot-
through current protection and undervol ta ge shutdown.
The 17533 has four operating modes: forward, reverse,
brake, and tri-Stated (high-impedance). The MOSFETs
comprising the output bridge have a total source + sink
RDS(ON) ≤ 1.2 Ω.
The 17533 can simultaneously drive two brush DC motors
or, as shown in Figure 1, 17533 Simplified Application
Diagram on page 1, one bipolar ste pper motor. The drive rs
are designed to be PWM’ed at freq uencies up to 200 kHz.
FUNCTIONAL PIN DESCRIPTION
LOGIC SUPPLY (VDD)
The VDD pin carries the logic supply voltage and current
into the logic sections of the IC. VDD has an undervoltage
threshold. If the supply voltage drops below the undervoltage
threshold, the output power stag e switches to a tri-state
condition. When the supply voltage returns to a level that is
above the threshold, the power stage automatically resumes
normal operation according to the established condition of
the input control pins.
LOGIC INPUT CONTROL (IN1A, IN1B, IN2A, AND
IN2B)
These logic input pins control each H-Bridge output (e.g.,
IN1A logic HIGH = OUT1A HIGH, etc.). However, if all inputs
are taken HIGH, the outputs bridges are both tri-stated (refer
to Table 5, Truth Table, page 7).
OUTPUT ENABLE (OE)
The OE pin is a LOW = TRUE ena ble input. When
OE = HIGH, all H-Bridge outputs (OUT1A, OUT1B, OUT2A,
and OUT2B) are tri-stated (high-impedance), regardless of
logic inputs (IN1A, IN1B, IN2A, and IN2B) states.
OUTPUT A AND B OF H-BRIDGE CHANNEL 1 AND
2 (OUT1A, OUT1B, OUT2A, AND OUT2B)
These pins provide connection to the outputs of each of
the internal H-Bridges (see Figure 2, 17533 Simplifi ed
Internal Block Diagram, page 2).
MOTOR DRIVE POWER SUPPLY (VM1 AND VM2)
The VM pins carry the main supply voltage and current into
the power sections of the IC. This supply then becomes
controlled and/or modulated by the IC as it delivers the power
to the loads attached between the output pins. All VM pins
must be connected together on the printed circuit board.
GATE DRIVER CIRCUIT VOLTAGE INPUT (VG)
The VG pin is the input pin for the gate drive voltage.
POWER GROUND (PGND)
Power ground pins. They must be tied together on the
PCB.
LOGIC GROUND (LGND)
Logic ground pin.
Analog Integrated Circuit Device Data
Freescale Semiconductor 9
17533
TYPICAL APPLICATIONS
INTRODUCTION
TYPICAL APPLICATIONS
INTRODUCTION
Figure 6 shows a typical appli ca tion for the 17533. When
applying the gate voltage to the VG pin from an external
source, be sure to connect it via a resistor equal to, or greater
than, RG = VG / 0.02 Ω.
Care must be taken to provide sufficient gate-source
voltage for the high-side MOSFETs when VM >> VDD (e.g.,
VM = 5.0 V, VDD = 3.0 V), in order to ensure full enhancement
of the high-side MOSFET channels.
Figure 6. 17533 Typical Application Diagram
CEMF SNUBBING TECHNIQUES
Care must be taken to protect the IC from potentially
damaging CEMF spikes induced when commuting currents
in inductive loads. Typical practice is to provide snubbing of
voltage transients by placing a zener or a capacitor at the
supply pin (VM) (see Figure 7).
Figure 7. CEMF Snubbing Techniques
PCB LAYOUT
When designing the printed circuit board (PCB), connect
sufficient capacitance between power supply and ground
pins to ensure proper filtering from transients. For all high-
current paths, use wide copper traces and shortest possible
distances.
MCU
17533
5.0 V
GND
VG
IN1B
IN2A
IN2B
OE
VM
VDD
OUT1B
OUT2B
0.01 μF
OUT1A
IN1A OUT2A
VG < 14 V
RG > VG/0.02Ω
RG
17533
5.0 V 5.0 V
GND
VM
VDD
OUT
OUT
OUT
OUT
17533
5.0 V 5.0 V
GND
VM
VDD
OUT
OUT
OUT
OUT
Analog Integrated Circuit Device Data
10 Freescale Semiconductor
17533
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
Package dimensions are provided in package drawings. To fi nd the most current package outline drawing, go to
www.freescale.com and perform a keyword search for the drawing’s document number.
Table 6.
Package Suffix Package Outline Drawing Number
16-PIN VMFP EV 98ASA10614D
Analog Integrated Circuit Device Data
Freescale Semiconductor 11
17533
PACKAGING
PACKAGE DIMENSIONS
EV (Pb-FREE) SUFFIX
16-LEAD VMFP
98ASA10614D
ISSUE B
Analog Integrated Circuit Device Data
12 Freescale Semiconductor
17533
PACKAGING
PACKAGE DIMENSIONS
EV (Pb-FREE) SUFFIX
16-LEAD VMFP
98ASA10614D
ISSUE B
Analog Integrated Circuit Device Data
Freescale Semiconductor 13
17533
REVISION HISTORY
REVISION HISTORY
REVISION DATE DESCRIPTION OF CHANGES
2.0 5/2006 • Converted to Freescale format
• Added Revision History page
3.0 7/2006 • Updated to the prevailing form and style
• Corrected device isometric drawing on page 1
• Added RoHS compliance
12/2013 • No technical changes
• Revised back page
• Updated document properties
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© 2013 Freescale Semiconductor, Inc.
Document Number: MPC17533
Rev. 3.0
12/2013
