SCD5031 Rev L
FEATURES
❑Radiation hardness:
- Total dose 1MRad(Si)
- Single event latchup (SEL) immune to 100MeV-cm2/mg
- Single event upset (SEU) 20MeV-cm2/mg
(Upsets found were benign and non-stressful to the PWM or supporting electronic components)
❑CMOS low power design
❑Sleep & enable control lines
❑Optimized for applications: buck, boost, flyback, forward and center tapped push-pull converters
❑Supports current mode or voltage mode operations
❑Selectable 50% / 100% duty cycle
❑Under-Voltage lockout with hysteresis
❑Dual ±1Amp peak totem pole outputs
❑1 MHz maximum – user selectable
❑Low RO error amp
❑Auxiliary op amp with shut down pin
❑Power OK indicator
❑PWM5034 - Same as PMW5032 except straight leads
❑Designed for commercial, industrial and aerospace applications
❑Ceramic 24-lead, hermetic package, .6L x .3W x .13H
- PWM5031/5032 Gull Wing leads
- PWM5034 Straight leads
- Weight: 1.2 g max
- Contact factory for die availability
❑Evaluation board available for test and evaluation. See Aeroflex Application Note AN5031-1
❑DSCC SMD: 5962-06251 approved
NOTE: Aeroflex Plainview does not currently have a DSCC Certified Radiation Hardened Assurance Program
Developed in Partnership with JHU/APL and the Technology Application Group for the
Mars Technology Program; Part of NASA’s Mars Exploration Program
OVERVIEW AND GENERAL OPERATION
The chip is a fixed frequency Pulse Width Modulator based on the industry standard UC1843x Series with significant
enhancements in performance and functionality. The chip operates in either the voltage or current mode and can support a wide
variety of converter topologies.
Radiation hardened by design techniques ensure the chip’s outstanding radiation tolerance (>1MRads) while reducing operating
current by more than an order of magnitude over comparable parts.
The PWM5031 provides an under voltage lockout feature with hysteresis that also provides an output to indicate Power is OK.
An input called Sleep is used to power down the entire chip, the Enable input is used to shut down the Oscillator / Output Drives,
and the Soft input drives the Output to zero. There is also a signal input called ENAUX that is used to disable the output to the
auxiliary op-amp.
The dual output drivers are designed using a Totem Pole output capable of sinking and sourcing 50mA constant current and peak
currents up to 1 Amp to support a large variety of Power MOSFETs.
Additional features that boost the appeal and utility of the part are:
◆Dual break-before-make Totem Pole output stage is employed that virtually eliminates cross conduction and current shoot
through
◆Logic level input that allows the user to select either 50% or 100% maximum duty cycle operation
◆Improved oscillator stage that vastly increases waveform linearity and reduces output voltage error
◆Uncommitted on-board op-amp which can be used for signal conditioning, pulse feedback, or any other user defined
purpose
PWM5031 / PWM5032 RadHard High Speed PWM Controller
Standard Products
www.aeroflex.com/RadHard
November 3, 2008
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SCD5031 Rev L 11/3/08 Aeroflex Plainview
FIGURE 1 – Block Diagram
Isense
VFB
Comp
SOFT
Rset
Cset
Error Amp
1.4V
VEE AOUT
1V
Current Sense
Comparators
ENAUX
Internal Enable /
Shutdown Control
Lockout
SLEEP EN 50%PWROK DRVP
OUTA
DRVN
Uncommited
Op-Amp
VCC
Undervoltage
VREF
OUTB
Output
Reference Logic & Control
Functions
Duty Cycle
Limiting
(50% or 100%)
Drive
Internal Bias
Oscillator
PIN NIN
12 15 16 14 13 18,19
20
21
22,2321731011 1,24
8
9
7
4
5
6
S
R
Q
Q
2.5V
2R
R
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SCD5031 Rev L 11/3/08 Aeroflex Plainview
PWM5031 PWM PIN DESCRIPTION
PIN # SIGNAL NAME FUNCTION DESCRIPTION
1
24
VCC Logic Power
2 50% Input selects maximum duty cycle (50% or 100%). Logic ''1'' selects 50% max duty cycle
and Output B is the complement of Output A. Logic ''0'' selects 100% and Output A is
in-phase with Output B.
3 SLEEP This Input shuts down all functions on chip when asserted (Active Hi)
4 COMP Output of the error amplifier. Place compensation network from this pin to VFB to stabilize
converter.
5 VFB Negative Input to the error amplifier
6 ISENSE Input Current sense pin used for current mode control
7 SOFT This High impedance Input is used to limit the error amplifier output voltage. Applying an
RC circuit to this pin provides the standard softstart function. Pull the pin to ground to force
zero duty cycle. This input is internally shorted to ground when Enable (pin 17) is low or
Sleep (pin 3) is high or an Under Voltage is detected.
8 CSET Works with Rset to establish oscillator free running frequency. Place cap from this Input pin
to ground. Can synchronize oscillator by overdriving this pin with an external frequency
source.
9 RSET Works with Cset to establish oscillator free running frequency. Place resistor from this Input
pin to ground.
10 PWROK Logical output of UV lockout circuit -- logic ''1'' indicates chip has valid Vcc
11 VREF Buffered 3V Output reference voltage
12 VEE Logic Ground
13 NIN Auxiliary Op-Amp Inverting Input
14 PIN Auxiliary Op-Amp Non-Inverting Input
15 AOUT Auxiliary Op-Amp Output (Short circuit protected)
16 ENAUX Input Enable of Auxiliary Op-Amp (Active Hi)
17 EN Logic Input that enables the oscillator and output drivers. Reference voltage remains valid
(Active Hi).
18
19
DRVN Output stage negative rail
20 OUT B Totem pole Output B
21 OUTA Totem pole Output A
22
23
DRVP Output stage positive rail
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SCD5031 Rev L 11/3/08 Aeroflex Plainview
ABSOLUTE MAXIMUM RATINGS 1, 4
Operating Temperature Range -55°C to +125°C
Maximum Junction Temperature +135°C
Storage Temperature Range -65°C to +150°C
VCC Supply Voltage 7.0VDC
DRVP Supply Voltage PWM5031 7.0VDC
PWM5032 14.0VDC
Steady State Output Current ±50mA
Peak Output Current (Internally Limited) ±1.0A
Analog Inputs (Pins 5, 6, 13, 14) VEE -0.5V to VCC +0.5V
Power Dissipation at TA = +25°C 500mW
ESD Rating Note 2 450V
Lead Temperature (soldering, 10 seconds) 300°C
NOTICE: Stresses above those listed under "Absolute Maximums Rating" may cause permanent damage to the device. These are stress rating only;
functional operation beyond the "Operation Conditions" is not recommended and extended exposure beyond the "Operation Conditions"
may effect device reliability.
OPERATING CONDITIONS 1, 4
PARAMETER CONDITION SYMBOL MIN TYP MAX UNIT
DC Operating Voltage - VCC 4.5 5.0 5.5 V
Quiescent Current PWM5031 SLEEP @ '0'; EN & ENAUX
@ '1': No loads on Outputs
PWROK, AOUT and VREF
ICC - - 5.8 mA
PWM5032 - - 7.1 mA
Output Drive Voltage PWM5031 - DRVP - - 5.0 V
PWM5032 - - 12.0 V
Output Duty Cycle – Maximum
50% Pin = Logic 0
50% Pin = Logic 1
100% Duty Cycle
50% Duty Cycle
-
-97*
-
-
-
-
50
%
%
Thermal Resistance TJC --- - 6.0 °C/W
Sleep Mode - ICCS - - 20 µA
* Dependent on Value of CSET & Operating Frequency
ELECTRICAL CHARACTERISTICS 1, 4
4.5 V < Vcc < 5.5V, -55°C < TA<+125°C, unless otherwise specified
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Reference Section
Reference Voltage TA = 25°C, IO = -1 mA 3.00 3.05 3.10 V
Line Regulation - ±.1 ±.12 %
Load Regulation 0 < IO<3 mA Note 3 - ±.05 ±.075 %
Thermal Regulation - ±1 ±1.6 %
Output Short Circuit Note 3 - - -40 mA
Oscillator Section
Initial Accuracy Range PWM5031
PWM5032
208.5
190
212
210
219
230
KHz
KHz
Frequency Range Note 3 20 - 1,000 KHz
Frequency Stability (Part to Part) - ±1.5 ±2.5 %
Temperature Stability TMIN < TA < TMAX, Note 3 - ±0.5 ±1 %
RSET Range Note 3 50 - - KΩ
CSET Range - - 600 pF
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SCD5031 Rev L 11/3/08 Aeroflex Plainview
Error Amp Section
Input Offset Voltage Note 3 - - 3.3 mV
Input Common Mode Voltage Range V
EE +0.2 - VCC -0.2 V
Input Bias Current - - -1.0 µA
Open Loop Voltage Gain (AVOL) 100 - - dB
Unity Gain Bandwidth 1.0 2.0 - MHz
Power Supply Rejection Ratio (PSRR) 60 - - dB
Output Sink Current VFB = 3.0V, VSOFT = 1.1V, Note 3 - - +10 mA
Output Source Current VFB = 2.0V, VSOFT = 5V, Note 3 - - -28 mA
V
OUT High (Limited by VSOFT)VFB = 2.0V, RL = 15K to GND VSOFT -
0.2
-- V
V
OUT Low VFB = 3.0V, RL = 15K to +5V - - VEE +0.2 V
Gain (VCOMP/VISENSE) Note 3 2.85 3 3.15 V/V
Current Sense Section
Input Offset Voltage Note 3 - - 3.3 mV
Common Mode Input Voltage VSOFT = 5V, Note 3 & 4 0.1 - 1.0 V
Input Bias Current Note 3 - - 1.0 µA
ISENSE to Output Delay - 80 100 ns
Output Section
Output Low Level ISINK = 1.0mA - - 0.1 V
ISINK = 50mA PWM5031 - - 0.25 V
ISINK = 50mA PWM5032 - - 0.6 V
Output High Level-PWM5031 ISOURCE = 1.0mA, DRVP = 5V 4.9 - - V
ISOURCE = 50mA, DRVP = 5V 4.6 - - V
Output High Level-PWM5032 ISOURCE = 1.0mA, DRVP = 12V 11.9 - - V
ISOURCE = 50mA, DRVP = 12V 11.4 - - V
Peak Output Current Note 3 ±1.0 ±1.35 - A
Steady State Output Current - - 50 mA
Rise Time TA = 25°C, CL = 20pF, DRVP = 5V
Note 3
- 8 18 ns
Fall Time - 6 28 ns
Enable Output Off Delay Note 3 - - 100 ns
Sleep Output Off Delay - - 100 ns
Under Voltage Output Off Delay - - 100 ns
ELECTRICAL CHARACTERISTICS 1, 4 con’t
4.5 V < Vcc < 5.5V, -55°C < TA<+125°C, unless otherwise specified
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
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SCD5031 Rev L 11/3/08 Aeroflex Plainview
Auxiliary Amp Section
Input Offset Voltage - - 3.5 mV
Input Common Mode Voltage Range Off VEE or VCC Rail, Note 3 VEE +0.2 - VCC -0.2 V
Input Bias Current Note 3 - - 1.0 µA
AVOL f = 40KHz, 2V < VO<4V, Note 3 100 - - dB
Unity Gain Bandwidth Note 3 1.0 - - MHz
PSRR 4.5V < VCC <5.5V, Note 3 60 70 - dB
Output Sink Current VPIN < VNIN, ENAUX = Hi, Note 3 --+45mA
Output Source Current - - -28 mA
V
OUT High VPIN > VNIN, ENAUX = Hi, IO = 2mA VCC -0.3 - - V
V
OUT Low --VEE +0.2 V
Under-Voltage Lockout Section
Start Threshold 3.9 4.1 4.25 V
Operating Voltage After Turn On 3.35 3.5 3.65 V
Digital Inputs
VIL Logic Low, Note 3 - - 0.8 V
VIH Logic High, Note 3 2.0 - - V
Leakage Current - IIN Note 3 - - 100 nA
Digital Ouput (PWROK)
V
OL Logic low at 1.6mA - - VEE +0.3 V
V
OH Logic high at -1.6mA VCC -0.6 - - V
Notes
1. All voltages are with respect to Pin 12. All currents are positive into the specified terminal.
2. Meets ESD testing per MIL-STD-883, method 3015, Class 1A.
3. Parameters are guaranteed by design, not tested.
4. All electrical characterizations for the PWM5034 are the same as the PWM5032.
ELECTRICAL CHARACTERISTICS 1, 4 con’t
4.5 V < Vcc < 5.5V, -55°C < TA<+125°C, unless otherwise specified
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
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SCD5031 Rev L 11/3/08 Aeroflex Plainview
DETAILED COMPONENT OPERATION AND PERFORMANCE
POWER SUPPLIES
Three I/O pins are used to supply power to the chip:
1) Two DRVP (referenced to DRVN) for the output stage.
2) VCC (referenced to VEE) for all other functions.
For protection against inadvertent over/undervoltages, the chip’s input pins are diode clamped to the supply rails through
current limiting resistors.
Undervoltage Lockout
The chip includes an internal undervoltage lockout circuit with built in hysteresis and a logic level power good indicator.
The positive and negative going thresholds are nominally 4.1V and 3.5V, respectively. If Vcc is below this range, the
oscillator, error amplifier, main comparators, and output drive circuits are all disabled. The power OK indicator is active
high (logic ''1'') when a valid supply voltage is applied.
Shutdown Logic
The chip has two logic level inputs for implementing shutdown functions. Asserting a logic ''1'' on the SLEEP pin disables
all chip functions and puts the chip into a very low power consumption mode. Asserting a logic ''0'' on the EN pin shuts
down all functions except the reference, bias generators, and auxiliary amplifier.
INPUTS OUTPUTS
Sleep EN ENAUX OUTA&B AOUT COMP PWROK Vref
0 0 0 0 0 0 Active 3 VDC
00 1 0Active0Active3 VDC
0 1 0 Active 0 Active Active 3 VDC
0 1 1 Active Active Active Active 3 VDC
1XX00000
X = Don’t care.
Truth Table
3.5V
Von
Voff
4.1V
Vcc
POWER OK
ON/OFF COMMAND
TO REST OF IC
24
VON
ICC
1.6mA
VOFF VCC
1
FIGURE 2 –Undervoltage Lockout
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SCD5031 Rev L 11/3/08 Aeroflex Plainview
OSCILLATOR
The chip uses two precision current mirrors that alternately charge and discharge an external capacitor to generate an
extremely linear sawtooth oscillator waveform. At the start of each cycle, the charging current, set by the choice of
resistor at the Rset pin, is 1:1 mirrored over to the Cset pin where it charges an external capacitor. When the capacitor
voltage reaches the comparator’s upper threshold (nominally VREF), the comparator switches current mirrors and begins
to discharge the external capacitor. The discharge current is set at roughly five times the charging current to result in fast
discharge and minimal Dead Time. When the voltage reaches the comparator’s lower threshold (0.9V), the comparator
switches back to the charging mirror, powers down the discharge mirror, and the whole process repeats.
The frequency is set by choosing Rset and Cset such that:
Suggested Ranges for Cset and Rset are:
50K ohms < Rset < 300K
10pf < Cset < 600pF
Rt
Ct
Rset
Cset
GND
6
7
12
FOSC
1
0.84 RSET
×
CSET
×
------------------------------------------------
≈
20KHz FOSC 1MHz
≤≤
FIGURE 3 – Timing Resistance vs Frequency
47pF
100pF
200pF
390pF 200pF
20pF 10pF
10K 100K
Frequency Hz
RSET
Ω
160K
140K
120K
100K
80K
60K
40K
1M
Frequency Hz
300K
280K
260K
240K
220K
200K
180K
320K
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SCD5031 Rev L 11/3/08 Aeroflex Plainview
Dead Time
The amount of dead time determines the maximum duty cycle that can be achieved. The Dead Time and the frequency of
operation will determine the duty cycle.
Selecting Rset and Cset
To select values for Rset and Cset perform the following steps to insure the smallest Dead Time..
1) Determine what frequency is required for your design.
2) Use Figure 4 to select a capacitor value for Cset that will provide the highest duty cycle (shortest Dead Time) at
the frequency required.
3) Calculate the value of Rset using the formula:
Note small values of Rset increase power consumption for the PWM5031 and small values of Cset may make PCB and
stray capacitance a source of error.
Dead Time 5280 Cset 12pF+()=Duty Cycle 1 Dead Time
1Fosc
⁄
-----------------------------
⎝⎠
⎛⎞
–
=
Rset
1
.84 Fosc
×
Cset
×
-----------------------------------------=
10K 100K
Duty Cycle
1M
%
86
100
98
96
94
92
90
88
47pF
100pF
200pF
20pF
10pF
390pF
Frequency Hz
FIGURE 4 – Duty Cycle vs Frequency
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SCD5031 Rev L 11/3/08 Aeroflex Plainview
If desired, the user can synchronize the oscillator to an external frequency source by coupling a pulse train to the Cset
pin:
FIGURE 5 – PWM can be synchronized to external source
with just two additional components.
Operation is similar to the free running case. Cset is alternately charged and discharged by the same current mirrors and
the same comparator and thresholds are used. The only difference is that when a sync pulse is received, the capacitor
voltage is level shifted up and reaches the comparator’s upper threshold voltage before it normally would in the free
running case. If a series of pulses are received with shorter period than that of the free running oscillator, the comparator
will trip in response to the sync pulse and the oscillator will be synchronized. (NOTE: The user must ensure that the sync
pulse does not induce a voltage on CSET that exceeds the PWM5031 voltage rating. If this cannot be guaranteed, a
simple diode clamp to the positive rail should be used to prevent damage to the PWM)
ERROR AMPLIFIER
The main error amplifier is a N-type input folded cascade configuration with a few interesting additions. The positive
input is internally tied to 2.5V derived from the on chip reference. The negative input typically draws less than 1µA and
has a voltage offset of less than 2mV. At 20µA bias current, the amplifier exceeds 2MHz bandwidth and 120dB open
loop gain (see Figure 7).
The amplifier is designed to limit at whatever voltage is applied to the SOFT pin. As mentioned previously, this function
will allow the user to implement a softstart circuit, a controlled turn-on delay, or any number of other useful functions.
Sync Pulse
2nF 24
Ω
Cset To P W M
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SCD5031 Rev L 11/3/08 Aeroflex Plainview
FIGURE 6 – Current Sense Circuit
Error
1.4V
1V
Current
Comparators
2R
R
Amp
5
7
4
12
6
V
SOFT
2.5V
V
FB
CURRENT
SENSE
V
EE
R
S
R
C
I
S
Sense
S
R
Q
Q
Peak Current (Is) is determined by the formula:
A small RC filter may be required to suppress switch transients
ISMAX 1.0V
RS
------------
=
or if
ISMAX
VSOFT 1.4–
3RS
--------------------------------
=
VRS
1Volt
<
then
COMP
FIGURE 7 – Error Amplifier Open-Loop Frequency Response
at +125°C & -55°C
Gain
Frequency Hz (Log Scale)
dB
120
80
40
0
-40
10 100 1K 10K 100K 1M 10M1
+125°C
-55°C
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SCD5031 Rev L 11/3/08 Aeroflex Plainview
OUTPUT DRIVE
Dual push-pull outputs OutA and OutB are provided for driving off chip switches. The output stages are identical:
◆Totem Pole configuration
◆Break-before-make switching to prevent harmful cross-conduction spikes
◆Separate positive and negative supply connections to decouple power stage and sensitive logic
◆Near rail-to-rail voltage swing
◆±1A maximum peak current capability (capacitive load)
The outputs have two modes of control depending on whether the 50% toggle option is selected. In the case where the
50% pin is logic low, the outputs are in-phase with each other and the duty cycle is free to take on any value up to 100%.
However, when the 50% pin is asserted high (logic ''1''), the outputs become limited to a maximum 50% duty cycle by
turning off each output on every other clock period of the oscillator. In addition Output A and Output B will never turn
on during the same clock cycle, see Figure 7A below. This would lend itself to a two phase switching system that would
be 180° out of phase..
FIGURE 7A – Output Drive Options
OSC
OUT A
OUT B
OUT A
OUT B
MAX OUTPUT @ 50%
OUTPUT @ 25%
PIN 2 SET LOW, 100% MODE
PIN 2 SET HI, 50% MODE
OUT A
OUT B
MAX OUTPUT @ 100%
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SCD5031 Rev L 11/3/08 Aeroflex Plainview
AUXILIARY AMPLIFIER
The chip includes an uncommitted op-amp with independent shutdown feature for use in any user-defined application.
Some possibilities are:
◆Signal conditioning of an isolated configuration feedback voltage
◆Implementation of more sophisticated compensation networks for control loop optimization
The Auxiliary amplifier has a unity gain bandwidth greater than 1MHz and an open loop gain greater than 100dB. The
ENAUX pin is active high such that a logic ''1'' enables the amplifier and logic ''0'' disables it. The amplifier has near
rail-to-rail capability on both the input and output.
A typical single output forward converter application is shown in Figure 9 to aid in the following operational description.
During normal operation, the oscillator jumpstarts each switching cycle by resetting the RS latch, causing the output
stage to go high and turn on M1. Current begins to build linearly through T1 and M1 and a proportional voltage is
developed across the small sense resistor Rs. Switching spikes are filtered by C1 and R1, and the resulting sawtooth
waveform is passed into the PWM to serve as the current comparator input. Meanwhile, a portion of the output voltage
is sensed and compared to the PWM’s internal precision 2.5V reference. The difference is then amplified and level
shifted to serve as the comparator threshold. When the voltage on the ISENSE pin exceeds this threshold, the comparator
fires and resets the latch. The output then turns off until the beginning of the next oscillator cycle when the process
repeats.
FIGURE 8 – Output Sink and Source Saturation Characteristics at +25°C
VSAT
110
mV
500
400
300
200
0
600
100
Current mA
100
5031
5032
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SCD5031 Rev L 11/3/08 Aeroflex Plainview
TYPICAL APPLICATIONS
Like all current mode PWMs, the chip provides built in fault protection by limiting peak switch current on a cycle by
cycle basis. When an overload condition occurs, the sensed current reaches the current trip threshold earlier in the
switching cycle than it otherwise would and thus forces the PWM latch off until the start of the next cycle. The process
repeats until the overload condition is removed and the PWM can return to a normal duty cycle. The chip is capable of
operating in this mode indefinitely without sustaining damage.
There are two ways to set the current limit trip point. One is to simply tailor the sense resistor Rs:
Some users may find the power is dissipated in Rs to be unacceptably high. In this case, the user can fix Rs at a small
value and vary the current comparator threshold instead. Fortunately, the PWM chip provides a very convenient method
for doing so. Because the error amplifier output is internally clamped to the SOFT pin, the user need simply apply the
desired voltage level to the SOFT pin to arbitrarily lower the current comparator threshold.
Recalling that the EA output is level shifted and divided before being applied to the comparator input, the peak current
limit is chosen by applying a voltage VSOFT such that:
Clamping the EA output to the soft pin also makes implementing a softstart ciruit easy. Rsoft and Csoft are connected as
in Figure 9 to provide the SOFT pin an asymptotically rising voltage. Because of the internal clamp on the EA output,
the PWM duty cycle will increase only as fast as the chosen time constant will allow. In this way, excessive duty cycle
and surge currents into the output capacitors are avoided. A transistor may be optionally connected across the softstart
FIGURE 9 – Typical Forward Converter Application
Rset
Cset
C
SOFT
0.1µF
R
SOFT
M2
C1
R1
Rs
T1
Isolation Barrier
3.3V, 0.5A
Opto-Isolator or
Pulse Transformer
Optional circuit
to force zero
duty cycle
M1
R
SET
C
SET
V
EE
DRVN
V
FB
COMP
50%
I
SENSE
Out A
Out B
V
CC
DRVP
EN
SOFT
V
REF
+5V
DC
Ipk
Vsoft 1.4–
3Rs
×
-------------------------=1.4V Vsoft 4.4V
≤≤
15
SCD5031 Rev L 11/3/08 Aeroflex Plainview
capacitor to force zero duty cycle on command. This is a particularly convenient method for implementing an externally
controlled turn-on delay.
The discussion so far assumes the user operates the chip in the current mode: switch current is sensed and compared to
the error between the output voltage and a precision reference. Alternatively, the user may wish to implement voltage
mode control in which the control loop is dependent only on the output voltage. The PWM chip readily supports this
configuration with the following modification:
FIGURE 10 – Circuit for implementing voltage mode control.
A portion of the oscillator’s sawtooth waveform is coupled to the ISENSE pin and becomes the input to the comparator
stage. The operation is now identical to the current mode application: when the sawtooth voltage exceeds the amplified
difference between the output and a voltage reference, the comparator fires and latches off the output until the start of the
next cycle.
SELECTED APPLICATION EXAMPLES
The flexibility and performance of the chip makes it suitable for an enormous range of power converter applications –
step-up, step-down, DC-DC, AC-DC, isolated/non-isolated, and many more. This section will cover two of the more
popular power converter applications for which this chip is particularly well suited although many more can be
envisioned.
5V Input, 3.3V Isolated Output (Single Ended Forward Converter)
The isolated step down DC/DC converter is a staple of many satellite and aerospace systems. A common bus distributes
raw primary power to various system loads which must then convert the primary to one or more low voltage secondary
outputs. These outputs are filtered, regulated, and ground isolated from the primary side to keep EMI and undesired
subsystem interaction at a minimum. Figure 9 is one example of a circuit that very efficiently performs this conversion.
The values here were chosen to work for a 5V input and 3.3V output but the circuit topology is general enough to
support an infinite variety of applications. For example, output voltages can be adjusted by changing values of just a few
components. A wider input voltage range can be supported by varying the transformer’s turns ratios and by proper
selection of M1. Thus, a very wide range of power converter applications can be satisfied by simple variations of the
circuit.
At the start of each switching cycle, the PWM output goes high and turns on M1. Energy is coupled across T1’s turns
ratios to the secondary side where it is caught, rectified, and filtered to produce a clean DC voltage. A sampling network
on the output side feeds back a portion of the output across the isolation barrier into the error amplifier negative input.
This feedback can be accomplished in a number of different ways: pulse transformers, optocouplers, or capacitive
coupling are a few methods. The compensation network may need modification depending on the feedback method
chosen. The additional winding and rectifier on T1 are used to reset the transformer core after the PWM latches off M1
to prevent staircase saturation of the core.
Note the chip is powered directly from the main power bus (via a zener and current limit resistor) without the need for
additional bootstrap transformer windings. This is one of the main advantages this PWM chip provides over other
products. This scheme could not be implemented with other chips which draw significantly more current. On the other
hand, supplying bias to our PWM chip is about as simple as it gets.
Out
Isense
Vref
2N2222
Cset
Cset
M1
Switch
Current
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SCD5031 Rev L 11/3/08 Aeroflex Plainview
5V to 1.8V Buck Converter
A second application is a secondary side, non-isolated buck converter. The circuit takes a high voltage (5V in this case)
and steps down to a lower voltage (5V to 1.8V in this example, although as pointed out above, these values are
completely adjustable with proper component selection). If the output voltage is less than 2.5V the auxiliary amplifier
can be used to provide the gain necessary to get VFB back up to 2.5V.
FIGURE 11 – Buck Converter
The circuit switches M1 twice per cycle, chopping the 5VDC input into a fixed frequency pulse train whose DC average
is the desired output voltage. The LC filter then simply smoothes this pulse train to produce a clean DC output. The
control loop regulates against operating point perturbations (temperature, line, load) by adjusting M1's duty cycle. The
circuit is operated in the voltage mode since switch current is not referenced to circuit ground. Alternatively, a current
transformer may be used to properly reference the ISENSE signal to permit current mode control. An inverter is needed in
the output path to properly drive the P-channel MOSFET. For low current applications (less than -50mA output current),
it may be possible to use the PWM's output drive stage as the switching elements and eliminate M1 and D1 altogether.
R
SET
C
SET
I
NPUT
5V
Rcomp
1V/1.8V/2.5V/3.3V
M1
O
UTPUT
R
SOFT
C
SOFT
Ccomp
0.1µF
R
SET
C
SET
V
EE
DRVN
V
FB
COMP
50%
I
SENSE
Out A
V
CC
DRVP
SOFT
V
REF
D1
17
SCD5031 Rev L 11/3/08 Aeroflex Plainview
FIGURE 12 – Package Pin vs Function
24 VCC
23 DRVP
22 DRVP
21 OUTA
20 OUT B
19 DRVN
18 DRVN
17 EN
16 ENAUX
15 A OUT
14 PIN
13 NIN
VCC 1
50% 2
SLEEP 3
COMP 4
VFB 5
ISENSE 6
SOFT 7
CSET 8
RSET 9
PWROK 10
VREF 11
VEE 12
18
SCD5031 Rev L 11/3/08 Aeroflex Plainview
.300 MAX
.500
.500
PIN 1 &
ESD IDENT
.614 MAX .110 MAX
(1.300)
.022
1 3 0 MA X
.0 0 8
± . 0 0 1 2
. 6 1 4
MA X . 0 1 9
.3 0 0 .3 9 4
.4 1 9
MA X
1 1 x . 0 5 0 =
. 0 1 5
.3 3 5
MI N
. 0 2 2
±.00 5 . 0 1 2 . 0 2 2 MA X
RE F
.3 5 4
. 0 3 0 RE F
. 5 5 0 ± . 0 0 6
.0 0 8
± . 0 0 1 2
.0 0 8
± . 0 0 1 2
.0 0 8
± . 0 0 1 2
. 6 1 4
MA X . 0 1 9
.3 0 0 .3 9 4
.4 1 9
MA X
1 1 x . 0 5 0 =
P I N 24
. 0 1 5
. 0 1 9
. 0 1 5
. 0 1 9
. 0 1 5
.3 3 5
MI N
. 0 2 2
±.00 5 . 0 1 2 . 0 2 2 MA X
RE F
.3 5 4
.
.
0 3 0 RE F
. 5 5 0 ± . 0 0 6
P I N 2 4
1 1 x . 0 5 0 =
. 5 5 0 ± . 0 0 6
1 1 x . 0 5 0 =
. 5 5 0 ± . 0 0 6
PIN 1 &
ESD IDENT
FIGURE 13 – PWM5031 /PWM5032 Flat Package (Gull Wing) Configuration Outline
FIGURE 14 – PWM5034 Flat Package (Straight Leads) Configuration Outline
19
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Aeroflex Microelectronic Solutions reserves the right to
change at any time without notice the specifications, design,
function, or form of its products described herein. All
parameters must be validated for each customer's application
by engineering. No liability is assumed as a result of use of
this product. No patent licenses are implied.
SCD5031 Rev L 11/3/08
EXPORT CONTROL: EXPOR T WARNING:
This product is controlled for export under the International Traffic in
Arms Regulations (ITAR). A license from the U.S. Department of
State is required prior to the export of this product from the United
States.
Aeroflex’s military and space products are controlled for export under
the International Traffic in Arms Regulations (ITAR) and may not be
sold or proposed or offered for sale to certain countries. (See ITAR
126.1 for complete information.)
CONFIGURATIONS AND ORDERING INFORMATION
MODEL NO. DSCC SMD # SCREENING 1/ CASE
PWM5031-7 - Class C Flat Package, Gull Wing
PWM5031-S
Military Temperature, -55°C to +125°C
Screened in accordance with
MIL-PRF-38534, Class K
PWM5031-Die 2/ Die Size – .136L x .114W inch
PWM5032-7 Class C Flat Package, Gull Wing
PWM5032-S
Military Temperature, -55°C to +125°C
Screened in accordance with
MIL-PRF-38534, Class K
PWM5032-Die 2/ Die Size – .183L x .122W inch
PWM5034-7 Class C Flat Package, Straight Lead
PWM5034-S
Military Temperature, -55°C to +125°C
Screened in accordance with
MIL-PRF-38534, Class K
PWM5032-EM2 Engineering unit, Non-Flight,
Room Temperature, Non-Hermetic Flat Package, Gull Wing
PWM5031-EVAL - See Application note AN5031-1 3/ 8'' x 11'' x 3.25''ht
PWM5032-EVAL
PWM5031-001-1S
PWM5031-001-2S
5962-0625101KXC
5962-0625101KXA
Per DSCC SMD 5962-06251 Flat Package, Gull Wing
PWM5032-001-1S
PWM5032-001-2S
5962-0625102KXC
5962-0625102KXA
PWM5034-001-1S 5962-0625102KYC Flat Package, Straight Lead
1. Level of Screening – Class C = Commercial Flow, Commercial Temp. Range, 0°C to +70°C testing.
2. Each die shall be 100% visually inspected to assure conformance with the applicable die related requirements of MIL-STD-883, method 2010,
cond A or cond B.
3. Application note AN5031-1, titled “ High Speed Pulse Width Modulator Controller Evaluation Board”. Evaluation board PWM5031-EVA L i s
supplied with a PWM5031-EM component and the PWM5032-EVAL board is supplied with a PWM5032-EM component.
PWM5031 Formerly released as ACT5031 Series