18-Bit Register
f
ax id: 7031
CY74FCT16823T
CY74FCT162823T
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Au
g
ust 1994 - Revis ed October 30
,
1997
2
823T
Features
• Lo w pow er, pin compati ble replaceme nt for ABT
functions
• FCT-E speed at 4.4 ns
• Power-off disable outputs permits live insertion
• Edge-rate control circui try for significant ly impr oved
noise characteristics
• Typical output skew < 250 ps
• ESD > 2000V
• TSSOP (19.6 -mil pit ch) and SSOP (25-mil pitch)
packages
• Industrial temperature range of −40°C to +85°C
•V
CC = 5V ± 10%
CY74FCT16823T Features:
• 64 mA sink current, 32 mA source current
• Typical VOLP (ground bounce) <1.0V at VCC = 5V,
TA = 25°C
CY74FCT162823T Feat ures:
• Balanced 24 mA output drivers
• R educed system switching noise
• Typical VOLP (ground bounce) <0.6V at VCC = 5V,
TA= 25°C
Functional Descripti on
The CY74FCT16823T and the CY74FCT162823T 18-bi t bus
interface register are designed for use in high-speed,
low-power systems needing wide registers and parity. 18-bit
operat ion is ac hie ved b y conne cting the control li nes of the two
9-bit registers. Flow-through pinout and sm all shrink packag-
ing aid s in si m plifying bo ard la yout. The outputs are desig ned
with a power-off disable feature to allow live insertion of
boards.
The CY74FCT16823T is ideally suited for driving
high-capacitance loads and low-impedance backpl anes.
The CY74FCT162823T has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The
CY74FCT162823T is ideal f or driving transmission lines.
Logic Block Diagrams
C
Pin Configuration
D
R
1
2
3
4
5
6
7
8
9
10
11
12
33
32
31
30
29
36
35
1CLR
34
SSOP/TSSOP
Top View
13
15
16
17
18
19
20
21
22
23
24
45
44
43
42
41
37
38
39
40
48
47
46
1CLR
1D1
1OE
1OE
1Q1
1Q2
GND
VCC
GND
FCT16823-1
1CLK
1CLKEN
1Q1
TO 8 OTHER CHANNELS
GND
1D1
1D2
1D3
1D4
1CLK
GND
1D5
1D6
1D7
1D9
VCC
GND
2D1
2D2
2D4
GND
2D5
2D6
2D7
2D8
VCC
2CLK
1CLKEN
25
26
27
28
49
50
51
52
53
54
55
56
1D8
2D3
2D9
2CLKEN
C
D
R
2CLR
2D2
2OE
2CLK
2CLKEN
2Q1
TO 8 OTHER CHANNELS
1Q3
1Q4
1Q5
1Q7
1Q8
1Q9
1Q6
14
2Q1
2Q2
2Q3
2Q4
2Q6
2Q7
2Q8
2Q5
2Q9
GND
VCC
GND
2OE
2CLR
FCT16823-2 FCT16823-3
CY74FCT16823T
CY74FCT162823T
2
Maximum Ratings[3, 4]
(Above which the useful life may be impaired. For user
guidelines, not test ed.)
Storage Temperature .....................................−55°C to +125°C
Ambient Tempera ture with
Power Applied..................................................−55°C to +125°C
DC Input Voltage.................................................−0.5V to +7.0V
DC Output Voltage..............................................−0.5V to +7.0V
DC Output Current
(Maximum Sink Current/Pin)...........................−60 to +120 mA
Power Dissipation.......................................................... 1.0W
Static Discharge Voltage ...........................................>2001V
(per MIL- STD-883, Method 3015)
Notes:
1. H = HIGH Voltage Level.
L = LOW Voltage Level.
X = Don’t Care.
Z = HIGH Impedance.
=LOW-to-HIGH transition.
2. Output level before indicated steady-state input conditions were established.
3. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range.
4. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
Pin Description
Name Description
DData Inputs
CLK Clock Inputs
CLKEN Clock Enable I nputs (Acti ve LOW)
CLR Asynchronous Clear Inputs (Active LOW)
OE Output Enable Inputs (Act ive LOW)
QThree- State Outputs
Function Table[1]
Inputs Outputs
OE CLR CLKEN CLK D Q Function
H X X X X Z High Z
L L X X X L Clear
L H H X X Q[2] Hold
H H L L Z Load
H H L H Z
L H L L L
L H L H H
Operating Range
Range Ambient
Temperature VCC
Industrial −40°C to +85°C 5V ± 10%
CY74FCT16823T
CY74FCT162823T
3
Electrica l Characteris tics Over the O perating Range
Parameter Description Test Conditi ons Min. Typ.[5] Max. Unit
VIH Input HIGH Voltage 2.0 V
VIL Input LOW Voltage 0.8 V
VHInput Hysteresi s[6] 100 mV
VIK Input Clamp Diode Volta ge VCC=Min., IIN=−18 mA −0.7 −1.2 V
IIH Input HIGH Current VCC=Max., VI=VCC ±1µA
IIL Input LOW Current VCC=Max., VI=GND ±1µA
IOZH High Impedance Output Current
(Three-State Outp ut pins) VCC=Max., VOUT=2.7V ±1µA
IOZL High Impedance Output Current
(Three-State Outp ut pins) VCC=Max., VOUT=0.5V ±1µA
IOS Short Circuit Current[7] VCC=Max., VOUT=GND −80 −140 −200 mA
IOOutput Driv e Current[7] VCC=Max., VOUT=2.5V −50 −180 mA
IOFF Power-Off Disable VCC=0V, VOUT≤4.5V[8] 1µA
Output Drive Characteristics for CY 74FCT16823T
Parameter Description Test Conditions Min. Typ.[5] Max. Unit
VOH Output HIGH Voltage VCC=M in ., IOH=−3 mA 2.5 3.5 V
VCC=M in ., IOH=−15 mA 2.4 3.5
VCC=M in ., IOH=−32 mA 2.0 3.0
VOL Output LO W Voltage VCC=M in ., IOL=64 mA 0.2 0.55 V
Output Drive Characteristics for CY 74FCT162823T
Parameter Description Test Conditi ons Min. Typ.[5] Max. Unit
IODL Out put LOW Voltage[7] VCC=5V, VIN=VIH or VIL, VOUT=1.5V 60 115 150 mA
IODH Out put HIGH Voltage[7] VCC=5V, VIN=VIH or VIL, VOUT=1.5V −60 −115 −150 mA
VOH Output HIGH Voltage VCC=Min., IOH=−24 mA 2.4 3.3 V
VOL Output LO W Voltage VCC=Min., IOL=24 m A 0.3 0.55 V
Capacitance[9] (TA = +25°C, f = 1.0 M Hz)
Parameter Description Test Conditions Typ.[5] Max. Unit
CIN Input Capacitance VIN = 0V 4.5 6.0 pF
COUT Output Capacitance VOUT = 0 V 5.5 8.0 pF
Notes:
5. Typical values are at VCC= 5.0V, TA= +25°C ambient.
6. This input is guaranteed but not tested.
7. Not more than one output should be shorted at a time . Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.
8. Tested at +25°C.
9. This parameter is guaranteed but not tested.
CY74FCT16823T
CY74FCT162823T
4
Power Supply Characteri stic s
Parameter Description Test Condi ti ons [10] Min. Typ.[5] Max. Unit
ICC Quiescent Power Supply
Current VCC=Max. VIN<0.2V
VIN>VCC−0.2V — 5 500 µA
∆ICC Quiescent Power Supply
Current (TTL i nputs HIGH) VCC=Max. VIN=3.4V[11] —0.5 1.5 mA
ICCD Dynamic Power Supply
Current[12] VCC=Max.,
On e Input Toggling,
50% Dut y Cycle ,
Ou tputs Open,
OE=CLKEN=GND
VIN=VCC or
VIN=GND —75 120 µA/
MHz
ICTotal Po wer Supply Current[13] VCC=Max.,
f0=10 M H z,
50% Dut y Cycle ,
Ou tputs Open,
On e Bit Toggling,
OE=CLKEN=GND
at f1=5 MHz
VIN=VCC or
VIN=GND —0.8 1.7 mA
VIN=3.4V or
VIN=GND —1.3 3.2
VCC=Max.,
at f1=2.5 MHz,
50% Dut y Cycle ,
Ou tputs Open,
Eighteen Bits Toggling,
OE=CLKEN=GND
f0=10 M H z
VIN=VCC or
VIN=GND —4.2 7.1[14]
VIN=3.4V or
VIN=GND —9.2 22.1[14]
Notes:
10. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
11. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.
12. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
13. IC=I
QUIESCENT + IINPUTS + IDYNAMIC
IC=I
CC+∆ICCDHNT+ICCD(f0/2 + f1N1)
ICC = Quiescent Current with CMOS input levels
∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V)
DH= Duty Cycle for TTL inputs HIGH
NT= Number of TTL inputs at DH
ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)
f0= Clock frequency for registered devices, otherwise zero
f1= Input signal frequency
N1= Number of inputs changing at f1
All currents are in milliamps and all frequencies are in megahertz.
14. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
CY74FCT16823T
CY74FCT162823T
5
Swi tch i ng C h ara cter i sti cs Over the Operating Range[15]
CY74FCT16823AT
CY74FCT162823AT CY74FCT16823BT
CY74FCT162823BT
Parameter Description Condition[16] Min. Max. Min. Max. Unit Fig.No.[16]
tPLH
tPHL Propagation Del ay
CLK to Q CL=50 pF
RL=500Ω1.5 10.0 1.5 7.5 ns 1, 5
CL=300 pF[17]
RL=500Ω1.5 20.0 1.5 15.0
tPHL Propagation Delay
CLR to Q CL=50 pF
RL=500Ω1.5 14.0 1.5 9.0 ns 1, 5
tPZH
tPZL Output Enable Time
OE to Q CL=50 pF
RL=500Ω1.5 12.0 1.5 8.0 ns 1, 7, 8
CL=300 pF[17]
RL=500Ω1.5 23.0 1.5 15.0
tPHZ
tPLZ Output Disable Time
OE to Q CL=5 pF[17]
RL=500Ω1.5 7.0 1.5 6.5 ns 1, 7, 8
CL=50 pF
RL=500Ω1.5 8.0 1.5 7.5
tSU Set-Up Time
HIGH or LOW, D to CLK CL=50 pF
RL=500Ω3.0 —3.0 —ns 4
tHHold Time
HIGH or LOW, D to CLK 1.5 —1.5 —ns 4
tSU Set-Up Time
HIGH or LOW, CLKEN to CLK 3.0 —3.0 —ns 9
tHHold Time HIGH or LOW
CLKEN to C L K 0.0 —0.0 —ns 9
tWCLK Pulse Width
HIGH or LOW 6.0 —6.0 —ns 5
tWCLR Pulse Width LOW 6.0 —6.0 —ns 5
tREM Recovery Time
CLR to CLK 6.0 —6.0 —ns 6
tSK(O) Output Skew[18] —0.5 —0.5 ns —
Swi tch i ng C h ara cter i sti cs Over the Operating Range[15]
CY74FCT16823CT
CY74FCT162823CT CY74FCT16823ET
CY74FCT162823ET
Parameter Description Condition[16] Min. Max. Min. Max. Unit Fig.No.[16]
tPLH
tPHL Propagation Delay
CLK to Q CL=50 pF
RL=500Ω1.5 6.0 1.5 4.4 ns 1, 5
CL=300 pF[17]
RL=500Ω1.5 12.5 1.5 8.0
tPHL Propagation Delay
CLR to Q CL=50 pF
RL=500Ω1.5 6.1 1.5 4.4 ns 1, 5
tPZH
tPZL Output Enable Time
OE to Q CL=50 pF
RL=500Ω1.5 5.5 1.5 4.4 ns 1, 7, 8
CL=300 pF[17]
RL=500Ω1.5 12.5 1.5 9.0
tPHZ
tPLZ Outp ut Disable Tim e
OE to Q CL=5 pF [17]
RL=500Ω1.5 5.2 1.5 3.6 ns 1, 7, 8
CL=50 pF
RL=500Ω1.5 6.5 1.5 3.6
CY74FCT16823T
CY74FCT162823T
6
Document #: 38-00385-C
tSU Set-Up Time
HIGH or LOW, D to CLK CL=50 pF
RL=500Ω2.0 —1.5 —ns 4
tHHold Time
HIGH or LOW, D to CLK 1.5 —0.0 —ns 4
tSU Set-Up Time
HIGH or LOW, CLKEN to CLK 3.0 —2.5 —ns 9
tHHold Time HIGH or LOW
CLKEN to CLK 0.0 —0.0 —ns 9
tWCLK Pulse Width
HIGH or LOW 3.3 —3.3 —ns 5
tWCLR Pulse W idth LOW 3.3 —3.0 —ns 5
tREM Recovery Time
CLR to CLK 6.0 —3.0 —ns 6
tSK(O) Output Skew[18] —0.5 —0.5 ns —
Notes:
15. Minimum limits are guaranteed but not tested on Propagation Delays.
16. See “Parameter Measurement Information” in the General Information section.
17. These limits are guaranteed but not tested.
18. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
Swi tch i ng C h ara cter i sti cs Over the Operating Range[15] (continued)
CY74FCT16823CT
CY74FCT162823CT CY74FCT16823ET
CY74FCT162823ET
Parameter Description Condition[16] Min. Max. Min. Max. Unit Fig.No.[16]
Orde ring Information CY74FCT16823
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
4.4 CY74FCT16823ETPAC Z56 56-Lead (24 0-Mil) TSSOP Industrial
CY74FCT16823ETPVC O56 56-Lead (300-Mil) SSOP
6.0 CY74FCT16823CTPAC Z56 56-Lead (24 0-Mil) TSSOP Industrial
CY74FCT16823CTPVC O56 56-Lead (300-Mil) SSOP
7.5 CY74FCT16823BTPAC Z56 56-Lead (240-Mil) TSSOP Industrial
CY74FCT16823BTPVC O56 56-Lead (300-Mil) SSOP
10.0 CY74FCT16823ATPAC Z56 56-Lead (24 0-Mil) TSSOP Industrial
CY74FCT16823ATPVC O56 56-Lead (30 0-Mil) SSOP
Orde ring Information CY74FCT162823
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
4.4 CY74FCT162823ETPAC Z56 56-Lead (24 0-Mil) TSSOP Industrial
CY74FCT162823ETPVC O56 56-Lead (300-Mil) SSOP
6.0 CY74FCT162823CTPAC Z56 56-Lead (24 0-Mil) TSSOP Industrial
CY74FCT162823CTPVC O56 56-Lead (300-Mil) SSOP
7.5 CY74FCT162823BTPAC Z56 56-Lead (240-Mil) TSSOP Industrial
CY74FCT162823BTPVC O56 56-Lead (300-Mil) SSOP
10.0 CY74FCT162823ATPA C Z56 56-Lead (24 0-Mil) TSSOP Industrial
CY74FCT162823ATPVC O56 56-Lead (30 0-Mil) SSOP
CY74FCT16823T
CY74FCT162823T
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circui try other than circuitry embodied in a Cypress Semiconduc tor produc t. Nor does it conv ey or imply any license under patent or other rights. Cypress Semi conductor does not author ize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufac turer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Di ag ra ms
56-Lead Shrunk Small Outline Package O56
56-Lead Thin Shrunk Small Outline Package Z56
