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FEATURES APPLICATIONS
D,DGK,ORP PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
NC
CAP+
GND
CAP−
VCC
OSC
LV
VOUT
NC − Nointernalconnection
DESCRIPTION/ORDERING INFORMATION
TL7660CMOS VOLTAGE CONVERTER
SCAS794 – JUNE 2006
•On-Board Negative Supplies•Simple Voltage Conversion, Including
•Data-Acquisition Systems– Negative Converter
•Portable Electronics– Voltage Doubler•Wide Operating Range …1.5 V to 10 V•Requires Only Two External (Noncritical)Capacitors
•No External Diode Over Full Temperature andVoltage Range•Typical Open-Circuit Voltage ConversionEfficiency …99.9%•Typical Power Efficiency …98%•Full Testing at 3 V
The TL7660 is a CMOS switched-capacitor voltage converter that perform supply-voltage conversions frompositive to negative. With only two noncritical external capacitors needed for the charge pump and chargereservoir functions, an input voltage within the range from 1.5 V to 10 V is converted to a complementarynegative output voltage of –1.5 V to –10 V. The device can also be connected as a voltage doubler to generateoutput voltages up to 18.6 V with a 10-V input.
The basic building blocks of the IC include a linear regulator, an RC oscillator, a voltage-level translator, and fourpower MOS switches. To ensure latch-up-free operation, the circuitry automatically senses the most negativevoltage in the device and ensures that the N-channel switch source-substrate junctions are not forward biased.The oscillator frequency runs at a nominal 10 kHz (for V
CC
= 5 V), but that frequency can be decreased byadding an external capacitor to the oscillator (OSC) terminal or increased by overdriving OSC with an externalclock.
For low-voltage operation (V
IN
< 3.5 V), LV should be tied to GND to bypass the internal series regulator. Above3.5 V, LV should be left floating to prevent device latchup.
The TL7660C is characterized for operation over a free-air temperature range of –40 °C to 85 °C. The TL7660I ischaracterized for operation over a free-air temperature range of –40 °C to 125 °C.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
(2)
Reel of 250 TL7660CDGKTMSOP/VSSOP – DGK TM_Reel of 2500 TL7660CDGKR–40 °C to 85 °C PDIP – P Tube of 50 TL7660CP TL7660CPTube of 75 TL7660CDSOIC – D 7660CReel of 2500 TL7660CDRReel of 250 TL7660IDGKTMSOP/VSSOP – DGK TN_Reel of 2500 TL7660IDGKR–40 °C to 125 °C PDIP – P Tube of 50 TL7660IP TL7660IPTube of 75 TL7660IDSOIC – D 7660IReel of 2500 TL7660IDR
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
(2) DGK: The actual top-side marking has one additional character that indicates the assembly/test site.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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OSC
RC
Oscillator
Voltage-Level
Translator
Voltage
Regulator
LV
Logic
Network
CAP+
CAP−
VCC
VOUT
¸2
Absolute Maximum Ratings
(1)
Recommended Operating Conditions
TL7660
CMOS VOLTAGE CONVERTER
SCAS794 – JUNE 2006
FUNCTIONAL BLOCK DIAGRAM
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage TL7660 10.5 VV
CC
< 5.5 V –0.3 V
CC
+ 0.3V
I
OSC and LV input voltage range
(2)
VV
CC
> 5.5 V V
CC
– 5.5 V
CC
+ 0.3I
LV
Current into LV
(2)
V
CC
> 3.5 V 20 µAt
OS
Output short-circuit duration V
SUPPLY
±5.5 V ContinuousD package 97θ
JA
Package thermal impedance
(3) (4)
DGK package 172 °C/WP package 85T
J
Junction temperature 150 °CT
stg
Storage temperature range –55 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) Connecting any input terminal to voltages greater than V
CC
or less than GND may cause destructive latchup. It is recommended that noinputs from sources operating from external supplies be applied prior to power up of the TL7660.(3) Maximum power dissipation is a function of T
J
(max), θ
JA
, and T
A
. The maximum allowable power dissipation at any allowable ambienttemperature is P
D
= (T
J
(max) – T
A
)/ θ
JA
. Operating at the absolute maximum T
J
of 150 °C can affect reliability.(4) The package thermal impedance is calculated in accordance with JESD 51-7.
MIN MAX UNIT
V
CC
Supply voltage TL7660 1.5 10 VTL7660C –40 85T
A
Operating free-air temperature °CTL7660I –40 125
2
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Electrical Characteristics
Electrical Characteristics
TL7660CMOS VOLTAGE CONVERTER
SCAS794 – JUNE 2006
V
CC
= 5 V, C
OSC
= 0, LV = Open, T
A
= 25 °C (unless otherwise noted) (see Figure 1 )
PARAMETER TEST CONDITIONS T
A
(1)
MIN TYP MAX UNIT
25 °C 45 110I
CC
Supply current R
L
=∞–40 °C to 85 °C 120 µA–40 °C to 125 °C 135V
CC,LOW
Supply voltage range (low) R
L
= 10 k Ω, LV = GND Full range 1.5 3.5 VV
CC,HIGH
Supply voltage range (high) R
L
= 10 k Ω, LV Open Full range 3 10 V25 °C 45 70I
O
= 20 mA –40 °C to 85 °C 85–40 °C to 125 °C 135R
OUT
Output source resistance Ω25 °C 125V
CC
= 2 V, I
O
= 3 mA, LV = GND –40 °C to 85 °C 200–40 °C to 125 °C 250f
OSC
Oscillator frequency 25 °C 10 kHz25 °C 96 98η
POWER
Power efficiency R
L
= 5 k Ω%–40 °C to 125 °C 9525 °C 99 99.9η
VOUT
Voltage conversion efficiency R
L
=∞%–40 °C to 125 °C 99V
CC
= 2 V 1 M ΩZ
OSC
Oscillator impedance 25 °CV
CC
= 5 V 100 k Ω
(1) Full range is –40 °C to 85 °C for the TL7660C and –40 °C to 125 °C for the TL7660I.
V
CC
= 3 V, C
OSC
= 0, LV = GND, (unless otherwise noted) (see Figure 1 )
PARAMETER TEST CONDITIONS T
A
MIN TYP MAX UNIT
25 °C 24 50I
CC
Supply current
(1)
R
L
=∞–40 °C to 85 °C 60 µA–40 °C to 125 °C 7525 °C 60 100R
OUT
Output source resistance I
O
= 10 mA –40 °C to 85 °C 110 Ω–40 °C to 125 °C 12025 °C 5 9f
OSC
Oscillator frequency C
OSC
= 0 kHz–40 °C to 125 °C 325 °C 96 98η
POWER
Power efficiency R
L
= 5 k Ω%–40 °C to 125 °C 9525 °C 99η
VOUT
Voltage conversion efficiency R
L
=∞%–40 °C to 125 °C 99
(1) Derate linearly above 50 °C by 5.5 mW/ °C.
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TYPICAL CHARACTERISTICS
0
1
2
3
4
5
6
7
8
9
10
1 10 100 1000
COSC – Oscillator Capacitance – pF
fOSC – Oscillator Frequency – kHz
VCC = 5 V
TA= 25°C
5
7
9
11
13
15
17
19
21
-40 -25 -10 5 20 35 50 65 80 95 110 125
TA– Free-Air Temperature – °C
fOSC – Oscillator Frequency – kHz
VCC = 5 V
VCC = 10 V
0
1
2
3
4
5
6
7
8
9
10
-40 -25 -10 5 20 35 50 65 80 95 110 125
TA– Free-Air Temperature – °C
VCC – Supply Voltage – V
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
-40 -25 -10 5 20 35 50 65 80 95 11
012
5
TA– Free-Air Temperature – °C
ROUT – Output Source Resistance –
VCC = 2 V
IO= 3 mA
VCC = 5 V
IO= 20 mA
VCC = 10 V
IO= 20 mA
Ω
TL7660
CMOS VOLTAGE CONVERTER
SCAS794 – JUNE 2006
OSCILLATOR FREQUENCY OSCILLATOR FREQUENCYvs vsOSCILLATOR CAPACITANCE TEMPERATURE
OUTPUT RESISTANCE SUPPLY VOLTAGEvs vsTEMPERATURE TEMPERATURE
4
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0
25
50
75
100
125
150
175
012345678910
VCC – Supply Voltage – V
ROUT – Output Source Resistance –
TA= 125°C
TA= 25°C
TA= –40°C
0
50
100
150
200
250
300
350
400
450
500
550
600
100 1000 10000 100000
fOSC – Oscillator Frequency – Hz
Output Resistance – W
VCC = 5 V
TA= 25°C
IO= 10 mA
C = 100 µF
OSC
C = 10 µF
OSC
C = 1 µF
OSC
100 1k 10k 100k
Ω
-2
-1.75
-1.5
-1.25
-1
-0.75
-0.5
-0.25
0
0 1 2 3 4 5 6 7 8 9
IL– Load Current – mA
VO– Output Voltage – V
VCC = 2 V
TA= 25°C
-5
-4.5
-4
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
0
0 5 10 15 20 25 30 35 40
IL– Load Current – mA
VO– Output Voltage – V
VCC = 5 V
TA= 25°C
TL7660CMOS VOLTAGE CONVERTER
SCAS794 – JUNE 2006
TYPICAL CHARACTERISTICS (continued)
OUTPUT RESISTANCE OUTPUT RESISTANCEvs vsSUPPLY VOLTAGE OSCILLATOR FREQUENCY
OUTPUT VOLTAGE OUTPUT VOLTAGEvs vsLOAD CURRENT LOAD CURRENT
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0
10
20
30
40
50
60
70
80
90
100
0123456789
IL– Load Current – mA
ePOWER
0
2
4
6
8
10
12
14
16
18
20
ICC – Supply Current – mA
VCC = 2 V
TA= 25°C
0
10
20
30
40
50
60
70
80
90
100
0 5 10 15 20 25 30 35 40 45
IL– Load Current – mA
ePOWER
0
10
20
30
40
50
60
70
80
90
100
ICC – Supply Current – mA
VCC = 5 V
TA= 25°C
88
90
92
94
96
98
100
1000 10000 100000
fOSC – Oscillator Frequency – Hz
ePOWER – Power-Conversion Efficiency – %
VCC = 5 V
TA= 25°C
IOUT = 1 mA
ηPOWER
1k 10k 100k
TL7660
CMOS VOLTAGE CONVERTER
SCAS794 – JUNE 2006
TYPICAL CHARACTERISTICS (continued)
EFFICIENCY AND SUPPLY CURRENT EFFICIENCY AND SUPPLY CURRENTvs vsLOAD CURRENT LOAD CURRENT
EFFICIENCY
vsOSCILLATOR FREQUENCY
6
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APPLICATION INFORMATION
1
2
3
4
8
7
6
5
TL7660
+
-
+
-
C
10 µF
1
C
10 µF
2
–VOUT
V+
(5V)
IS
IL
RL
COSC
(see
Note A)
8
3
2
5
3
7
V = –V
OUT IN
S2
S1
S3S4C2
VIN
C1
TL7660CMOS VOLTAGE CONVERTER
SCAS794 – JUNE 2006
A. In the circuit, there is no external capacitor applied to terminal 7. However when device is plugged into a testsocket,there is usually a very small but finite stray capacitance present on the order of 10 pF.
Figure 1. Test Circuit
The TL7660 contains all the necessary circuitry to complete a negative voltage converter, with the exception oftwo external capacitors which may be inexpensive 10 µF polarized electrolytic types. The mode of operation ofthe device may be best understood by considering Figure 2 , which shows an idealized negative voltageconverter. Capacitor C
1
is charged to a voltage, V
CC
, for the half cycle when switches S
1
and S
3
are closed.(Note: Switches S
2
and S
4
are open during this half cycle.) During the second half cycle of operation, switchesS
2
and S
4
are closed, with S
1
and S
3
open, thereby shifting capacitor C
1
negatively by V
CC
volts. Charge is thentransferred from C
1
to C
2
such that the voltage on C
2
is exactly V
CC
, assuming ideal switches and no load on C
2
.The TL7660 approaches this ideal situation more closely than existing non-mechanical circuits. In the TL7660,the four switches of Figure 2 are MOS power switches: S
1
is a p-channel device, and S
2
, S
3
, and S
4
aren-channel devices. The main difficulty with this design is that in integrating the switches, the substrates of S
3and S
4
must always remain reverse biased with respect to their sources, but not so much as to degrade theirON resistances. In addition, at circuit start up and under output short circuit conditions (V
OUT
= V
CC
), the outputvoltage must be sensed and the substrate bias adjusted accordingly. Failure to accomplish this results in highpower losses and probable device latchup. This problem is eliminated in the TL7660 by a logic network whichsenses the output voltage (V
OUT
) together with the level translators and switches the substrates of S
3
and S
4
tothe correct level to maintain necessary reverse bias.
The voltage regulator portion of the TL7660 is an integral part of the anti-latchup circuitry; however, its inherentvoltage drop can degrade operation at low voltages. Therefore, to improve low-voltage operation, the LVterminal should be connected to GND, disabling the regulator. For supply voltages greater than 3.5 V, the LVterminal must be left open to insure latchup proof operation and prevent device damage.
Figure 2. Idealized Negative-Voltage Converter
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Theoretical Power Efficiency Considerations
Do's and Don'ts
TL7660
CMOS VOLTAGE CONVERTER
SCAS794 – JUNE 2006
APPLICATION INFORMATION (continued)
In theory, a voltage converter can approach 100% efficiency if certain conditions are met.•The driver circuitry consumes minimal power.•The output switches have extremely low ON resistance and virtually no offset.•The impedances of the pump and reservoir capacitors are negligible at the pump frequency.
The TL7660 approaches these conditions for negative voltage conversion if large values of C
1
and C
2
are used.
Energy is only lost in the transfer of charge between capacitors if a change in voltage occurs. The energy lost isdefined by:E = ½ C
1
(V
1
2
– V
2
2
)
Where V
1
and V
2
are the voltages on C
1
during the pump and transfer cycles. If the impedances of C
1
and C
2are relatively high at the pump frequency (see Figure 2 ) compared to the value of R
L
, there is a substantialdifference in the voltages V
1
and V
2
. Therefore, it is not only desirable to make C
2
as large as possible toeliminate output voltage ripple but also to employ a correspondingly large value for C
1
in order to achievemaximum efficiency of operation.
•Do not exceed maximum supply voltages.•Do not connect LV terminal to GND for supply voltages greater than 3.5 V.•Do not short circuit the output to V
CC
supply for supply voltages above 5.5 V for extended periods, however,transient conditions including start-up are okay.•When using polarized capacitors, the positive terminal of C
1
must be connected to terminal 2 of the TL7660,and the positive terminal of C
2
must be connected to GND.•If the voltage supply driving the TL7660 has a large source impedance (25 Ω– 30 Ω), then a 2.2- µFcapacitor from terminal 8 to ground may be required to limit rate of rise of input voltage to less than 2V/ µs.•Ensure that the output (terminal 5) does not go more positive than GND (terminal 3). Device latch up occursunder these conditions. A 1N914 or similar diode placed in parallel with C
2
prevents the device from latchingup under these conditions (anode to terminal 5, cathode to terminal 3).
8
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Typical Applications
Simple Negative Voltage Converter
1
2
3
4
8
7
6
5
+TL7660
+
-
-
10 µF
V+
10 µF
V = –V+
OUT
TL7660CMOS VOLTAGE CONVERTER
SCAS794 – JUNE 2006
APPLICATION INFORMATION (continued)
The majority of applications will undoubtedly utilize the TL7660 for generation of negative supply voltages.Figure 3 shows typical connections to provide a negative supply negative (GND) for supply voltages below3.5 V.
Figure 3. Simple Negative-Voltage Converter
The output characteristics of the circuit in Figure 3 can be approximated by an ideal voltage source in series witha resistance. The voltage source has a value of –V
CC
. The output impedance (R
O
) is a function of the ONresistance of the internal MOS switches (shown in Figure 2 ), the switching frequency, the value of C
1
and C
2
,and the ESR (equivalent series resistance) of C
1
and C
2
. A good first order approximation for R
O
is:R
O
≈2(R
SW1
+ R
SW3
+ ESR
C1
) + 2(R
SW2
+ R
SW4
+ ESR
C1
)R
O
≈2(R
SW1
+ R
SW3
+ ESR
C1
) + 1/f
PUMP
C
1
+ ESR
C2
Where f
PUMP
= f
OSC
/2 , R
SWX
= MOSFET switch resistance.
Combining the four RSWX terms as RSW, we see that:R
O
≈2 (R
SW
) + 1/f
PUMP
C
1
+ 4 (ESR
C1
) + ESR
C2
R
SW
, the total switch resistance, is a function of supply voltage and temperature (See the Output SourceResistance graphs). Careful selection of C
1
and C
2
reduces the remaining terms, minimizing the outputimpedance. High value capacitors reduce the 1/f
PUMP
C
1
component, and low ESR capacitors lower the ESRterm. Increasing the oscillator frequency reduces the 1/f
PUMP
C
1
term but may have the side effect of a netincrease in output impedance when C
1
> 10 µF and there is no longer enough time to fully charge the capacitorsevery cycle. In a typical application where f
OSC
= 10 kHz and C = C1 = C2 = 10 µF:R
O
≈2(23) + 1/(5 ×10
3
)(10
–5
) + 4(ESR
C1
) + ESR
C2R
O
≈46 + 20 + 5 (ESR
C
)
Because the ESRs of the capacitors are reflected in the output impedance multiplied by a factor of 5, a highvalue could potentially swamp out a low 1/f
PUMP
C
1
term, rendering an increase in switching frequency or filtercapacitance ineffective. Typical electrolytic capacitors may have ESRs as high as 10 Ω.
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Output Ripple
A
B
0
V
t2t1
–V+
Paralleling Devices
+
-
1
2
3
4
8
7
6
5
TL7660
"1" 1
2
3
4
8
7
6
5
TL7660
"n"
+
-+
+
-
V+
C1
C2
RL
C1
TL7660
CMOS VOLTAGE CONVERTER
SCAS794 – JUNE 2006
APPLICATION INFORMATION (continued)
ESR also affects the ripple voltage seen at the output. The total ripple is determined by two voltages, A and B,as shown in Figure 4 . Segment A is the voltage drop across the ESR of C
2
at the instant it goes from beingcharged by C
1
(current flow into C
2
) to being discharged through the load (current flowing out of C
2
). Themagnitude of this current change is 2 ×I
OUT
, hence the total drop is 2 ×I
OUT
×eSR
C2
V. Segment B is thevoltage change across C
2
during time t
2
, the half of the cycle when C
2
supplies current to the load. The drop atB is I
OUT
×t
2
/C
2
V. The peak-to-peak ripple voltage is the sum of these voltage drops:V
RIPPLE
≈(1/(2f
PUMP
C
2
) + 2(ESR
C2
)) ×I
OUT
Again, a low ESR capacitor results in a higher performance output.
Figure 4. Output Ripple
Any number of TL7660 voltage converters may be paralleled to reduce output resistance (see Figure 5 ). Thereservoir capacitor, C
2
, serves all devices, while each device requires its own pump capacitor, C
1
. The resultantoutput resistance would be approximately:R
OUT
= R
OUT
(of TL7660)/n (number of devices)
Figure 5. Paralleling Devices
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Cascading Devices
1
2
3
4
8
7
6
5
TL7660
"1" 1
2
3
4
8
7
6
5
10 µF +
+
-+
+
-
V+
+
-
10 µF
V = –nV+
OUT
10 µF TL7660
"n"
+
-
10 µF
Changing the TL7660 Oscillator Frequency
1
2
3
4
8
7
6
5
TL7660
10 µF
+
-
CMOS
Gate
+
+
–
10 µF
VOUT
V+ V+
–
TL7660CMOS VOLTAGE CONVERTER
SCAS794 – JUNE 2006
APPLICATION INFORMATION (continued)
The TL7660 may be cascaded as shown to produced larger negative multiplication of the initial supply voltage(see Figure 6 ). However, due to the finite efficiency of each device, the practical limit is 10 devices for lightloads. The output voltage is defined by:V
OUT
= –n (V
IN
)
Where n is an integer representing the number of devices cascaded. The resulting output resistance would beapproximately the weighted sum of the individual TL7660 R
OUT
values.
Figure 6. Cascading Devices for Increased Output Voltage
It may be desirable in some applications, due to noise or other considerations, to increase the oscillatorfrequency. This is achieved by overdriving the oscillator from an external clock, as shown in Figure 7 . To preventpossible device latchup, a 1-k Ωresistor must be used in series with the clock output. When the external clockfrequency is generated using TTL logic, the addition of a 10-k Ωpullup resistor to V
CC
supply is required. Notethat the pump frequency with external clocking, as with internal clocking, will be 1/2 of the clock frequency.Output transitions occur on the positive-going edge of the clock.
Figure 7. External Clocking
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1
2
3
4
8
7
6
5
TL7660
+
-
+
-
+
-
+
-
V+
COSC
VOUT
C1
C2
Positive Voltage Doubling
1
2
3
4
8
7
6
5
TL7660
V+
V = (2V+) – (2VF)
OUT
D1
D2
C1
C2
TL7660
CMOS VOLTAGE CONVERTER
SCAS794 – JUNE 2006
APPLICATION INFORMATION (continued)It is also possible to increase the conversion efficiency of the TL7660 at low load levels by lowering the oscillatorfrequency (see Figure 8 ). This reduces the switching losses. However, lowering the oscillator frequency causesan undesirable increase in the impedance of the pump (C
1
) and reservoir (C
2
) capacitors; this is overcome byincreasing the values of C
1
and C
2
by the same factor that the frequency has been reduced. For example, theaddition of a 100-pF capacitor between terminal 7 (OSC) and V
CC
lowers the oscillator frequency to 1 kHz fromits nominal frequency of 10 kHz (a multiple of 10), and thereby necessitate a corresponding increase in thevalue of C
1
and C
2
(from 10 µF to 100 µF).
Figure 8. Lowering Oscillator Frequency
The TL7660 may be used to achieve positive voltage doubling using the circuit shown in Figure 9 . In thisapplication, the pump inverter switches of the TL7660 are used to charge C
1
to a voltage level of V
CC
– V
F(where V
CC
is the supply voltage and V
F
is the forward voltage drop of diode D1). On the transfer cycle, thevoltage on C
1
plus the supply voltage (V
CC
) is applied through diode D
2
to capacitor C
2
. The voltage thuscreated on C
2
becomes (2V
CC
) – (2V
F
) or twice the supply voltage minus the combined forward voltage drops ofdiodes D
1
and D
2
.
The source impedance of the output (V
OUT
) depends on the output current.
Figure 9. Positive-Voltage Doubler
12
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Combined Negative Voltage Conversion and Positive Supply Doubling
1
2
3
4
8
7
6
5
TL7660
V+
C2
D1
D2
C1+
-
+
-
C3
+
-
C4
+
-
V = –(nV –V )
OUT IN FDX
V = (2V+) – (V ) – (V )
OUT FD1 FD2
Voltage Splitting
1
2
3
4
8
7
6
5
TL7660
+
-
+
-
V+
V–
+
-
50 µF
RL1
RL2
50 µF
50 µF
V =
OUT 2
V+  V
TL7660CMOS VOLTAGE CONVERTER
SCAS794 – JUNE 2006
APPLICATION INFORMATION (continued)
Figure 10 combines the functions shown in Figure 3 and Figure 9 to provide negative voltage conversion andpositive voltage doubling simultaneously. This approach would be, for example, suitable for generating +9 V and–5 V from an existing 5-V supply. In this instance, capacitors C
1
and C
3
perform the pump and reservoirfunctions, respectively, for the generation of the negative voltage, while capacitors C
2
and C
4
are pump andreservoir, respectively, for the doubled positive voltage. There is a penalty in this configuration that combinesboth functions, however, in that the source impedances of the generated supplies are somewhat higher, due tothe finite impedance of the common charge pump driver at terminal 2 of the device.
Figure 10. Combined Negative-Voltage Converter and Positive-Voltage Doubler
The bidirectional characteristics can also be used to split a higher supply in half (see Figure 11 . The combinedload is evenly shared between the two sides. Because the switches share the load in parallel, the outputimpedance is much lower than in the standard circuits, and higher currents can be drawn from the device. Byusing this circuit and then the circuit of Figure 6 , 15 V can be converted (via 7.5 V, and –7.5 V) to a nominal–15 V, although with rather high series output resistance (~250 Ω).
Figure 11. Splitting a Supply in Half
13Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TL7660CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL7660CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL7660CDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL7660CDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL7660CDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL7660CDGKTG4 ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL7660CDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL7660CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL7660CP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TL7660CPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TL7660ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL7660IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL7660IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL7660IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL7660IDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL7660IDGKTG4 ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL7660IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL7660IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TL7660IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TL7660IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TL7660CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
TL7660CDGKT VSSOP DGK 8 250 180.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
TL7660CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL7660IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
TL7660IDGKT VSSOP DGK 8 250 180.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
TL7660IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TL7660CDGKR VSSOP DGK 8 2500 370.0 355.0 55.0
TL7660CDGKT VSSOP DGK 8 250 220.0 205.0 50.0
TL7660CDR SOIC D 8 2500 340.5 338.1 20.6
TL7660IDGKR VSSOP DGK 8 2500 370.0 355.0 55.0
TL7660IDGKT VSSOP DGK 8 250 220.0 205.0 50.0
TL7660IDR SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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