DS1990A-F3# - Maxim Integrated Products, Inc.

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GENERAL DESCRIPTION

The DS1990A Serial Number iButtonÒ is a rugged

data carrier that serves as an electronic registration

number for automatic identification. Data is trans-

ferred serially through the 1-WireÒ protocol, which

requires only a single data lead and a ground return.

Every DS1990A is factory lasered with a guaranteed

unique 64-bit registration number that allows for

absolute traceability. The durable stainless-steel

iButton package is highly resistant to environmental

hazards such as dirt, moisture, and shock. Its

compact coin-shaped profile is self-aligning with

mating receptacles, allowing the DS1990A to be

used easily by human operators. Accessories permit

the DS1990A iButton to be mounted on almost any

object, including containers, pallets, and bags.

APPLICATIONS

§ Access Control

§ Work-In-Progress Tracking

§ Tool Management

§ Inventory Control.

F3 and F5 MicroCAN

0.51

5.89

16.25

17.35

89 01

000000FBC52B

1-Wireâ

3.10

IO GND

0.51

GND

F3 size F5 size Branding

All dimensions are shown in millimeters.

SPECIAL FEATURES

§ Can Be Read in Less Than 5ms

§ Operating Range: 2.8V to 6.0V, -40°C to +85°C

COMMON iButton FEATURES

§ Unique Factory-Lasered 64-Bit Registration

Number Assures Error-Free Device Selection

and Absolute Traceability Because No Two Parts

are Alike

§ Built-In Multidrop Controller for 1-Wire Net

§ Digital Identification by Momentary Contact

§ Data can be Accessed While Affixed to Object

§ Economically Communicates to Bus Master with

a Single Digital Signal at 16.3kbps

§ Button Shape is Self-Aligning with Cup-Shaped

Probes

§ Durable Stainless-Steel Case Engraved with

Registration Number Withstands Harsh

Environments

§ Easily Affixed with Self-Stick Adhesive Backing,

Latched by its Flange, or Locked with a Ring

Pressed Onto its Rim

§ Meets UL#913 (4th Edit.); Intrinsically Safe

Apparatus: Approved Under Entity Concept for

use in Class I, Division 1, Group A, B, C, and D

Locations

ORDERING INFORMATION

PART TEMP RANGE PACKAGE

DS1990A-F5 -40°C to +85°C F5 iButton

DS1990A-F3 -40°C to +85°C F3 iButton

EXAMPLES OF ACCESSORIES

PART DESCRIPTION

DS9096P Self-Stick Adhesive Pad

DS9101 Multipurpose Clip

DS9093RA Mounting Lock Ring

DS9093A Snap-In Fob

DS9092 iButton Probe

DS1990

Serial Number iButton

www.maxim-ic.com

iButton, 1-Wire, and MicroCAN are registered trademarks of

Dallas Semiconductor.

DS1990A

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PHYSICAL SPECIFICATION

Size See mechanical drawing

Weight DS1990A Ca. 2.5 grams

Safety Meets UL#913 (4th Edit.); Intrinsically Safe Apparatus,

approval under Entity Concept for use in Class I, Division

1, Group A, B, C, and D Locations.

ABSOLUTE MAXIMUM RATINGS

IO Voltage to GND -0.5V, +6.0V

IO Sink Current 20mA

Junction Temperature +125°C

Storage Temperature Range -55°C to +125°C

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is

not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device.

ELECTRICAL CHARACTERISTICS

(VPUP = 2.8V to 6.0V, TA = -40°C to +85°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

IO Pin General Data

1-Wire Pullup Resistance RPUP (Notes 1, 2) 0.6 5 kW

Input Capacitance CIO (Note 3, 15) 100 800 pF

Input Load Current IL (Note 4) 0.25 µA

Input Low Voltage VIL (Notes 1, 5, 6) 0.8 V

Input High Voltage VIH (Notes 6, 7) 2.2 V

Output-Low Voltage at 4mA VOL (Note 6) 0.4 V

Output-High Voltage VOH (Notes 6, 8) VPUP V

Operating Charge QOP (Note 9, 15) 30 nC

Recovery Time tREC (Note 1) 1 µs

Timeslot Duration tSLOT (Note 1) 61 µs

IO Pin, 1-Wire Reset, Presence Detect Cycle

Reset Low Time tRSTL (Notes 1, 10) 480 µs

Reset High Time tRSTH (Notes 1, 11) 480 µs

Presence Detect High Time tPDH 15 60 µs

Presence Detect Low Time tPDL (Note 14) 60 240 µs

Presence Detect Sample

Time tMSP (Note 1) 60 75 µs

IO Pin, 1-Wire Write

Write-0 Low Time tW0L (Note 1) 60 120 µs

Write-1 Low Time tW1L (Notes 1, 12) 1 15 - e µs

IO Pin, 1-Wire Read

Read Low Time tRL (Notes 1, 13) 1 15 - d µs

Read Sample Time tMSR (Notes 1, 13) tRL + d 15 µs

DS1990A

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Note 1: System requirement.

Note 2: Full Rpup range guaranteed by design and simulation, not production tested. Production testing performed at a fixed Rpup value.

Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The

specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded

systems, an active pullup such as that found in the DS2480 may be required.

Note 3: Capacitance on the IO pin could be 800pF when power is first applied. If a 5kW resistor is used to pull up the IO line to VPUP, 5µs

after power has been applied the parasite capacitance will not affect normal communications.

Note 4: Input load is to ground.

Note 5: The voltage on IO needs to be less or equal to VILMAX whenever the master drives the line low. Under certain low voltage

conditions, VILMAX may have to be reduced to as much as 0.5V to always guarantee a Presence Pulse.

Note 6: All voltages are referenced to ground.

Note 7: VIH is a function of the internal supply voltage.

Note 8: VPUP = external pullup voltage.

Note 9: 30nC per 72 time slots at 5.0V pullup voltage with a 5kW pullup resistor and tSLOT £ 120µs.

Note 10: The reset low time (tRSTL) should be restricted to a maximum of 960 µs, to allow interrupt signaling; a longer duration could mask or

conceal interrupt pulses if this device is used in parallel with a DS1994.

Note 11: An additional reset or communication sequence cannot begin until the reset high time has expired.

Note 12: e represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VIH.

Note 13: d represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input-high threshold of the bus

master.

Note 14: Presence pulse is guaranteed only after a preceding Reset Pulse (tRSTL).

Note 15: Guaranteed by design, simulation only. Not production tested.

DESCRIPTION

The diagram in Figure 1 shows the major function blocks of the device. The DS1990A takes the energy it needs to

operate from the IO line, as indicated by the Parasite Power block. The ROM Function Control units includes the 1-

Wire interface and the logic to implement the ROM function commands, which access 64 bits of lasered ROM.

Figure 1. DS1990A BLOCK DIAGRAM

Parasite Power

64-bit

Lasered ROM

ROM

Function Control

64-BIT LASERED ROM

Each DS1990A contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next

48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. See Figure 2 for details. The 1-

Wire CRC is generated using a polynomial generator consisting of a Shift and XOR gates as shown in Figure 3.

The polynomial is X8 + X5 + X4 + 1. Additional information about the Dallas 1-Wire Cyclic Redundancy Check is

available in Application Note 27.

The Shift register bits are initialized to 0. Then starting with the least significant bit of the family code, one bit at a

time is shifted in. After the 8th bit of the family code has been entered, then the serial number is entered. After the

48th bit of the serial number has been entered, the Shift register contains the CRC value. Shifting in the 8 bits of

CRC returns the Shift register to all 0s.

DS1990A

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Figure 2. 64-BIT LASERED ROM

MSB LSB

8-BIT

CRC CODE 48-BIT SERIAL NUMBER 8-BIT FAMILY

CODE (01h)

MSB LSB MSB LSB MSB LSB

Figure 3. 1-WIRE CRC GENERATOR

X0X1X2X3X4X5X6X7X8

POLYNOMIAL = X8 + X5 + X4 + 1

1st

STAGE

2nd

STAGE

3rd

STAGE

4th

STAGE

6th

STAGE

5th

STAGE

7th

STAGE

8th

STAGE

INPUT DATA

1-Wire BUS SYSTEM

The 1-Wire bus is a system, which has a single bus master and one or more slaves. In all instances the DS1990A

is a slave device. The bus master is typically a microcontroller or PC. For small configurations the 1-Wire

communication signals can be generated under software control using a single port pin. Alternatively, the DS2480B

1-Wire line driver chip or serial port adapters based on this chip (DS9097U series) can be used. This simplifies the

hardware design and frees the microprocessor from responding in real-time. The discussion of this bus system is

broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types

and timing). The 1-Wire protocol defines bus transactions in terms of the bus state during specific time slots that

are initiated on the falling edge of sync pulses from the bus master. For a more detailed protocol description, refer

to Chapter 4 of the Book of DS19xx iButton Standards.

HARDWARE CONFIGURATION

The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at

the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open drain or tri-state

outputs. The 1-Wire port of the DS1990A is open-drain with an internal circuit equivalent to that shown in Figure 4.

A multi-drop bus consists of a 1-Wire bus with multiple slaves attached. At standard speed the 1-Wire bus has a

maximum data rate of 16.3kbps. The value of the pullup resistor primarily depends on the network size and load

conditions. For most applications the optimal value of the pullup resistor is approximately 2.2kW. The idle state for

the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be left in the idle

state if the transaction is to resume. If this does not occur and the bus is left low for more than 120µs, one or more

devices on the bus may be reset.

TRANSACTION SEQUENCE

The protocol for accessing the DS1990A through the 1-Wire port is as follows:

§ Initialization

§ ROM Function Command

DS1990A

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Figure 4. HARDWARE CONFIGURATION

Open Drain

Port Pin

RX = Receive

TX = Transmit 100 W

MOSFET

RXDATA

SIMPLE BUS MASTER DS1990A 1-Wire PORT

VPUP

RPUP

DS2480B

+5V

HOST CPU VDD

POL

RXD

TXD

VPP

1-W

GND

serial in

serial out

Serial

Port

To 1-Wire data

DS2480B BUS MASTER

INITIALIZATION

All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a

reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The presence

pulse lets the bus master know that the DS1990A is on the bus and is ready to operate. For more details, see the

1-Wire Signaling section.

1-Wire ROM FUNCTION COMMANDS

Once the bus master has detected a presence, it can issue one of ROM function commands that the DS1990A

supports. All ROM function commands are 8 bits long. A list of these commands follows (see flowchart in Figure 5).

READ ROM [33h]

This command allows the bus master to read the DS1990A’s 8-bit family code, unique 48-bit serial number, and 8-

bit CRC. This command can only be used if there is a single slave device on the bus. If more than one slave is

present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will pro-

duce a wired-AND result). The resultant family code and 48-bit serial number will result in a mismatch of the CRC.

SEARCH ROM [F0h]

When a system is initially brought up, the bus master might not know the number of devices on the 1-Wire bus or

their registration numbers. By taking advantage of the wired-AND property of the bus, the master can use a

process of elimination to identify the registration numbers of all slave devices. For each bit of the registration

number, starting with the least significant bit, the bus master issues a triplet of time slots. On the first slot, each

slave device participating in the search outputs the true value of its registration number bit. On the second slot,

each slave device participating in the search outputs the complemented value of its registration number bit. On the

third slot, the master writes the true value of the bit to be selected. All slave devices that do not match the bit

written by the master stop participating in the search. If both of the read bits are zero, the master knows that slave

devices exist with both states of the bit. By choosing which state to write, the bus master branches in the ROM

code tree. After one complete pass, the bus master knows the registration number of a single device. Additional

passes identify the registration numbers of the remaining devices. Refer to App Note 187: 1-Wire Search Algorithm

for a detailed discussion, including an example.

DS1990A

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Figure 5. ROM FUNCTIONS FLOW CHART

Bit 63

Match ?

DS1990A TX Bit 0

Master TX Bit 0

DS1990A TX Bit 1

Master TX Bit 1

DS1990A TX Bit 63

Master TX Bit 63

Bit 1

Match ?

Bit 0

Match ?

F0h

Search ROM

Command ?

DS1990A TX

CRC B

DS1990A TX

Serial Number

(6 Bytes)

DS1990A TX

Family Code

(1 Byte)

33h

Read ROM

Command ?

Bus Master TX ROM

Function Command

DS1990A TX

Presence Pulse

Bus Master TX

Reset Pulse

MATCH ROM [55h] / SKIP ROM [CCh]

The minimum set of 1-Wire ROM function commands includes a Match ROM and a Skip ROM command. Since the

DS1990A contains only the 64-bit ROM without any additional data fields, Match ROM and Skip ROM are not

applicable. The DS1990A will remain silent (inactive) upon receiving a ROM function command that it doesn't

support. This allows the DS1990A to coexist on a multidrop bus with other 1-Wire devices that do respond to Match

ROM or Skip ROM (example DS1990A and DS1994).

DS1990A

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1-Wire SIGNALING

The DS1990A requires strict protocols to ensure data integrity. The protocol consists of four types of signaling on

one line: Reset Sequence with Reset Pulse and Presence Pulse, Write-Zero, Write-One, and Read-Data. Except

for the presence pulse the bus master initiates all these signals.

To get from idle to active, the voltage on the 1-Wire line needs to fall from VPUP to below VILMAX. To get from active

to idle, the voltage needs to rise from VILMAX to above VIHMIN. The time it takes for the voltage to make this rise, ref-

erenced as e in Figure 6, depends on the value of the pullup resistor (RPUP) and capacitance of the 1-Wire network

attached.

The initialization sequence required to begin any communication with the DS1990A is shown in Figure 6. A Reset

Pulse followed by a Presence Pulse indicates the DS1990A is ready to receive a ROM function command. If the

bus master uses slew-rate control on the falling edge, it must pull down the line for tRSTL + tF to compensate for the

edge.

Figure 6. INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES”

RESISTOR MASTER DS1990A

tRSTL tPDL

tRSTH

tPDH

MASTER TX “RESET PULSE” MASTER RX “PRESENCE PULSE”

VPUP

VIHMIN

VILMAX

tFtREC

tMSP

After the bus master has released the line it goes into receive mode (RX). Now the 1-Wire bus is pulled to VPUP via

the pullup resistor or, in case of a DS2480B driver, by active circuitry. When the VIHMIN is crossed, the DS1990A

waits for tPDH and then transmits a Presence Pulse by pulling the line low for tPDL. To detect a presence pulse, the

master must test the logical state of the 1-Wire line at tMSP.

READ/WRITE TIME SLOTS

Data communication with the DS1990A takes place in time slots, which carry a single bit each. Write-time slots

transport data from bus master to slave. Read-time slots transfer data from slave to master. The definitions of the

write and read-time slots are illustrated in Figure 7.

All communication begins with the master pulling the data line low. As the voltage on the 1-Wire line falls below

VILMAX, the DS1990A starts its internal timing generator that determines when the data line will be sampled during a

write-time slot and how long data will be valid during a read-time slot.

MASTER-TO-SLAVE

For a write-one time slot, the voltage on the data line must have risen above VIHMIN after the write-one low time

tW1LMAX is expired. For a write-zero time slot, the voltage on the data line must stay below VILMAX until the write-zero

low time tW0LMIN is expired. For most reliable communication the voltage on the data line should not exceed VILMAX

during the entire tW0L window. After the voltage has risen above VIHMIN, the DS1990A needs a recovery time tREC

before it is ready for the next time slot.

DS1990A

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SLAVE-TO-MASTER

A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below VILMAX until

the read low time tRL is expired. During the tRL window, when responding with a 0, the DS1990A will start pulling the

data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again.

When responding with a 1, the DS1990A will not hold the data line low at all, and the voltage starts rising as soon

as tRL is over.

The sum of tRL + d (rise rime) on one side and the internal timing generator of the DS1990A on the other side

define the master sampling window (tMSRMIN to tMSRMAX) in which the master must perform a read from the data line.

For most reliable communication, tRL should be as short as permissible and the master should read close to but no

later than tMSRMAX. After reading from the data line, the master must wait until tSLOT is expired. This guarantees

sufficient recovery time tREC for the DS1990A to get ready for the next time slot.

Figure 7. READ/WRITE TIMING DIAGRAM

Write-One Time Slot

RESISTOR MASTER

VPUP

VIHMASTER

VIHMIN

VILMAX

tSLOT

tW1L

Write-Zero Time Slot

RESISTOR MASTER

tREC

VPUP

VIHMASTER

VIHMIN

VILMAX

tFtSLOT

tW0L

Read-Data Time Slot

RESISTOR MASTER DS1990A

tREC

VPUP

VIHMASTER

VIHMIN

VILMAX

Master

Sampling

Window

tSLOT

tRL tMSR