HI-506, HI-507, HI-508, HI-509 S E M I C O N D U C T O R August 1997 Single 16 and 8/Differential 8-Channel and 4-Channel CMOS Analog Multiplexers Features Description * Low ON Resistance . . . . . . . . . . . . . . . . . . . . . . . 180 The HI-506/HI-507 and HI-508/HI-509 monolithic CMOS multiplexers each include an array of sixteen and eight analog switches respectively, a digital decoder circuit for channel selection, voltage reference for logic thresholds, and an enable input for device selection when several multiplexers are present. The Dielectric Isolation (DI) process used in fabrication of these devices eliminates the problem of latchup. DI also offers much lower substrate leakage and parasitic capacitance than conventional junction isolated CMOS (see Application Note AN521). * Wide Analog Signal Range . . . . . . . . . . . . . . . . . . . . 15V * TTL/CMOS Compatible * Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns * Maximum Power Supply . . . . . . . . . . . . . . . . . . . . . . 44V * Break-Before-Make Switching * No Latch-Up * Replaces DG506A/DG506AA and DG507A/DG507AA * Replaces DG508A/DG508AA and DG509A/DG509AA Applications * Data Acquisition Systems * Precision Instrumentation * Demultiplexing * Selector Switch The switching threshold for each digital input is established by an internal +5V reference, providing a guaranteed minimum 2.4V for logic "1" and maximum 0.8V for logic "0". This allows direct interface without pullup resistors to signals from most logic families: CMOS, TTL, DTL and some PMOS. For protection against transient overvoltage, the digital inputs include a series 200 resistor and diode clamp to each supply. The HI-506 is a single 16-Channel, the HI-507 is an 8-Channel differential, the HI-508 is a single 8-Channel and the HI-509 is a 4-Channel differential multiplexer. The HI-506/HI-507 are available in a 28 lead ceramic or plastic DIP, 28 pad leadless chip carrier (CLCC), 28 pin plastic leaded chip carrier (PLCC) and 28 lead SOIC packages. The HI-508/HI-509 are available in a 16 pin plastic or ceramic DIP, a 20 pin plastic leaded chip carrier (PLCC), 20 pad ceramic leadless chip carrier (CLCC) and 16 lead SOIC packages. If input overvoltages are present, the HI-546/HI-547/HI-548/ HI-549 multiplexers are recommended. For further information see Application Notes AN520 and AN521. The HI-506/HI-507/HI-508/HI-509 is offered in both commercial and military grades. For additional High Reliability Screening including 160 hour burn-in specify the "-8" suffix. For MIL-STD-883 compliant parts, request the HI-506/883, HI-507/883, HI-508/883 or HI-509/883 data sheet. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright (c) Harris Corporation 1997 11-54 File Number 3142.1 HI-506, HI-507, HI-508, HI-509 Ordering Information PART NUMBER HI1-0506/883 HI1-0506-8 TEMP. RANGE (oC) -55 to 125 PACKAGE PKG. NO. 28 Ld CERDIP F28.6 Hi-Rel 28 Ld CERDIP Pressing with Burn-In F28.6 PART NUMBER HI1-0508-8 TEMP. RANGE (oC) PACKAGE Hi-Rel 16 Ld CERDIP Pressing with Burn-In PKG. NO. F16.3 HI4-0508/883 -55 to 125 20 Ld CLCC J20.A -55 to 125 16 Ld CERDIP F16.3 HI4-0506/883 -55 to 125 28 Ld CLCC J28.A HI1-0509/883 HI1-0507/883 -55 to 125 28 Ld CERDIP F28.6 HI1-0508-5 0 to 75 16 Ld CERDIP F16.3 HI9P0506-9 -40 to 85 28 Ld SOIC M28.6 HI3-0508-5 0 to 75 16 Ld PDIP E16.3 HI3-0506-5 0 to 75 28 Ld PDIP E28.6 HI1-0508-4 -25 to 85 16 Ld CERDIP F16.3 F28.6 HI1-0508-2 -55 to 125 16 Ld CERDIP F16.3 HI4P0508-5 0 to 75 20 Ld PLCC N20.35 HI9P0508-9 -40 to 85 16 Ld SOIC M16.15 HI9P0508-5 0 to 75 16 Ld SOIC M16.15 HI1-0506-7 0 to 75 + 96 28 Ld CERDIP Hour Burn-In HI9P0506-5 0 to 75 28 Ld SOIC M28.3 HI1-0506-5 0 to 75 28 Ld CERDIP F28.6 HI1-0506-4 -25 to 85 28 Ld CERDIP F28.6 HI1-0506-2 -55 to 125 28 Ld CERDIP F28.6 Hi-Rel 28 Ld CERDIP Pressing with Burn-In F28.6 HI1-0509-8 HI1-0507-8 HI4-0509/883 HI4-0507/883 -55 to 125 28 Ld CLCC J28.A HI1-0507-4 -25 to 85 28 Ld CERDIP F28.6 HI4P0507-5 0 to 75 28 Ld PLCC N28.45 HI9P0507-5 0 to 75 28 Ld SOIC M28.3 HI1-0507-5 0 to 75 28 Ld CERDIP F28.6 HI3-0507-5 0 to 75 28 Ld PDIP E28.3 HI9P0507-9 -40 to 85 28 Ld SOIC M28.3 HI1-0507-2 -55 to 125 28 Ld CERDIP F28.6 HI1-0508/883 -55 to 125 16 Ld CERDIP F16.3 Hi-Rel 16 Ld CERDIP Pressing with Burn-In F16.3 -55 to 125 20 Ld CLCC J20.A HI9P0509-5 0 to 75 16 Ld SOIC M16.15 HI9P0509-9 -40 to 85 16 Ld SOIC M16.15 HI1-0509-4 -25 to 85 16 Ld CERDIP F16.3 HI1-0509-5 0 to 75 16 Ld CERDIP F16.3 HI3-0509-5 0 to 75 16 Ld PDIP E16.3 HI4P0509-5 0 to 75 20 Ld PLCC N20.35 HI1-0509-2 -55 to 125 16 Ld CERDIP F16.3 0 to 75 + 96 16 Ld CERDIP Hour Burn-In F16.3 HI1-0509-7 11-55 HI-506, HI-507, HI-508, HI-509 Pinouts HI-506 (PDIP, CERDIP, SOIC) TOP VIEW HI-507 (PDIP, CERDIP, SOIC) TOP VIEW 28 OUT +VSUPPLY 1 28 OUT A +VSUPPLY 1 NC 2 27 -VSUPPLY 27 -VSUPPLY OUT B 2 NC 3 26 IN 8 NC 3 26 IN 8A IN 16 4 25 IN 7 IN 8B 4 25 IN 7A IN 15 5 24 IN 6 IN 7B 5 24 IN 6A IN 14 6 23 IN 5 IN 6B 6 23 IN 5A IN 13 7 22 IN 4 IN 5B 7 22 IN 4A IN 12 8 21 IN 3 IN 4B 8 21 IN 3A IN 11 9 20 IN 2 IN 3B 9 20 IN 2A IN 10 10 19 IN 1 IN 2B 10 19 IN 1A 18 ENABLE IN 1B 11 18 ENABLE IN 9 11 GND 12 17 ADDRESS A0 GND 12 17 ADDRESS A0 NC 13 16 ADDRESS A1 NC 13 16 ADDRESS A1 ADDRESS A3 14 15 ADDRESS A2 NC 14 15 ADDRESS A2 26 IN 8A 27 -VSUPPLY IN B 28 OUT A -VSUPPLY 1 +VSUPPLY OUT 2 OUT B +VSUPPLY 3 NC NC 4 IN 8B NC HI-507 (CLCC, PLCC) TOP VIEW IN 16 HI-506 (CLCC, PLCC) TOP VIEW 4 3 2 1 28 27 26 IN 6 IN 6B 6 24 IN 6A IN 13 7 23 IN 5 IN 5B 7 23 IN 5A IN 12 8 22 IN 4 IN 4B 8 22 IN 4A IN 11 9 21 IN 3 IN 3B 9 21 IN 3A IN 10 10 20 IN 2 IN 2B 10 20 IN 2A IN 9 11 19 IN 1 IN 1B 11 19 IN 1A 15 16 17 18 11-56 12 13 14 15 16 17 18 ENABLE 14 A0 13 A1 12 A2 24 NC 6 NC IN 14 GND IN 7A ENABLE 25 A0 5 A1 IN 7B A2 IN 7 A3 25 NC 5 GND IN 15 HI-506, HI-507, HI-508, HI-509 Pinouts (Continued) HI-508 (PDIP, CERDIP, SOIC) TOP VIEW A0 1 16 A1 ENABLE 2 15 A2 HI-509 (PDIP, CERDIP, SOIC) TOP VIEW 15 GND ENABLE 2 14 GND -VSUPPLY 3 16 A1 A0 1 14 +VSUPPLY -VSUPPLY 3 IN 1 4 13 +VSUPPLY IN 1A 4 13 IN 1B IN 2 5 12 IN 5 IN 2A 5 12 IN 2B IN 3 6 11 IN 6 IN 3A 6 11 IN 3B IN 4 7 10 IN 7 IN 4A 7 10 IN 4B OUT 8 9 IN 8 OUT A 8 A0 NC A1 A2 ENABLE A0 NC A1 GND HI-509 (CLCC, PLCC) TOP VIEW ENABLE HI-508 (CLCC, PLCC) TOP VIEW 9 OUT B 3 2 1 20 19 3 2 1 20 19 7 IN 3 8 13 5 17 IN 1B NC 6 16 NC 15 IN 5 IN 2A 7 15 IN 2B 14 IN 6 IN 3A 8 14 IN 3B 11-57 9 10 11 12 13 IN 4B IN 2 12 IN 1A OUT B 16 NC 11 18 +VSUPPLY NC 6 10 4 OUT A NC 9 -VSUPPLY IN 4A 17 +VSUPPLY IN 7 5 IN 8 IN 1 NC 18 GND OUT 4 IN 4 -VSUPPLY HI-506, HI-507, HI-508, HI-509 Functional Diagrams HI-506 HI-507 IN 1 IN 1A OUT OUT A IN 2 IN 8A DECODER/ DRIVER IN 1B OUT B IN 16 DECODER/ DRIVER IN 8B 5V REF LEVEL SHIFT DIGITAL INPUT PROTECTION A0 A1 A2 A3 EN 5V REF LEVEL SHIFT DIGITAL INPUT PROTECTION HI-508 A0 A1 A2 EN HI-509 IN 1 IN 1A OUT OUT A IN 2 IN 4A DECODER/ DRIVER IN 1B OUT B IN 8 DECODER/ DRIVER IN 4B 5V REF DIGITAL INPUT PROTECTION LEVEL SHIFT A0 A1 A2 EN 5V REF DIGITAL INPUT PROTECTION 11-58 LEVEL SHIFT A0 A1 EN HI-506, HI-507, HI-508, HI-509 Schematic Diagrams ADDRESS DECODER +V P P P P A0 OR A0 A1 OR A1 P P P N N N N N A2 OR A2 TO P-CHANNEL DEVICE OF THE SWITCH TO N-CHANNEL DEVICE OF THE SWITCH N A3 OR A3 N ENABLE DELETE A3 OR A3 INPUT FOR HI-507 DELETE A3 OR A3 INPUT FOR HI-508 DELETE A2 OR A2 INPUT FOR HI-509 V- ADDRESS INPUT BUFFER LEVER SHIFTER +V P3 P1 P5 A +V D1 P4 N1 VL VR D2 P6 P7 P8 P9 P10 N6 N7 N8 N9 N10 P2 N4 A 200 N5 N2 -V N3 AIN ALL N-CHANEL BODIES TO VALL P-CHANNEL BODIES TO V+ UNLESS OTHERWISE INDICATED -V TTL REFERENCE CIRCUIT MULTIPLEX SWITCH V+ P15 Q1P Q2P Q3P Q5N V+ Q6N VL Q8N N17 N19 IN Q7P Q11P V- D3 Q10N VR R3 6.8K Q9P N13 N14 P18 N15 P16 Q12N FROM DECODE V- OUT P17 R2 16.8K N12 N18 FROM DECODE Q4P GND 11-59 HI-506, HI-507, HI-508, HI-509 Absolute Maximum Ratings Thermal Information VSUPPLY(+) to VSUPPLY(-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44V VSUPPLY(+) to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +22V VSUPPLY(-) to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-25V Digital Input Overvoltage +VEN , +VA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VSUPPLY +4V -VEN , -VA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VSUPPLY -4V or 20mA, Whichever Occurs First Analog Signal Overvoltage (Note 7) +VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VSUPPLY +2V -VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VSUPPLY -2V Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA (Pulsed at 1ms, 10% Duty Cycle Max) Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) 16 Ld CERDIP Package . . . . . . . . . . . 85 32 16 Ld SOIC Package . . . . . . . . . . . . . . 115 N/A 16 Ld PDIP Package . . . . . . . . . . . . . . 100 N/A 20 Ld CLCC Package . . . . . . . . . . . . . 80 28 20 Ld PLCC Package . . . . . . . . . . . . . 80 N/A 28 Ld CERDIP Package . . . . . . . . . . . 55 18 28 Ld PDIP Package . . . . . . . . . . . . . . 60 N/A 28 Ld SOIC Package . . . . . . . . . . . . . . 70 N/A 28 Ld CLCC Package . . . . . . . . . . . . . 70 20 28 Ld PLCC Package . . . . . . . . . . . . . 70 N/A Maximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC and PLCC - Lead Tips Only) Operating Conditions Temperature Ranges HI-506/507/508/509-2, -8 . . . . . . . . . . . . . . . . . . . -55oC to 125oC HI-506/507/508/509-4 . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC HI-506/507/508/509-5 . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 75oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Supplies = +15V, -15V; VAH (Logic Level High) = +2.4V; VAL (Logic Level Low) = +0.8V, Unless Otherwise Specified. For Test Conditions, Consult Performance Curves PARAMETER TEST CONDITIONS HI-5XX-2, HI-5XX-8 TEMP (oC) MIN TYP HI-5XX-4, HI-5XX-5 MAX MIN TYP MAX UNITS SWITCHING CHARACTERISTICS Access Time, IA (Note 1) Break-Before-Make Delay, tOPEN (Note 1) Enable Delay (ON), tON(EN) (Note 1) Enable Delay (OFF), tOFF(EN) - 250 500 - 250 - ns - - 1000 - - 1000 ns 25 25 80 - 25 80 - ns 25 - 250 500 - 250 - ns Full - - 1000 - - 1000 ns 25 - 250 500 - 250 - ns Full - - 1000 - - 1000 ns Settling Time to 0.1%, tS (HI-506 and HI-507) 25 - 1.2 - - 1.2 - s Settling Time to 0.01%, tS (HI-506 and HI-507) 25 - 2.4 - - 2.4 - s Settling Time to 0.1%, tS (HI-508 and HI-509) 25 - 360 - - 360 - ns Settling Time to 0.01%, tS (HI-508 and HI-509) 25 - 600 - - 600 - ns 25 50 68 - 50 68 - dB Channel Input Capacitance, CS(OFF) 25 - 10 - - 10 - pF Channel Output Capacitance, CD(OFF) (HI-506) 25 - 52 - - 52 - pF Channel Output Capacitance, CD(OFF) (HI-507) 25 - 30 - - 30 - pF Channel Output Capacitance, CD(OFF) (HI-508) 25 - 17 - - 17 - pF Channel Output Capacitance, CD(OFF) (HI-509) 25 - 12 - - 12 - pF "Off Isolation" (Note 1) 25 Full (Note 5) 11-60 HI-506, HI-507, HI-508, HI-509 Electrical Specifications Supplies = +15V, -15V; VAH (Logic Level High) = +2.4V; VAL (Logic Level Low) = +0.8V, Unless Otherwise Specified. For Test Conditions, Consult Performance Curves (Continued) HI-5XX-2, HI-5XX-8 HI-5XX-4, HI-5XX-5 TEMP (oC) MIN Digital Input Capacitance, CA 25 - 6 - - 6 - pF Input to Output Capacitance, CDS(OFF) 25 - 0.08 - - 0.08 - pF PARAMETER TEST CONDITIONS TYP MAX MIN TYP MAX UNITS DIGITAL INPUT CHARACTERISTICS Input Low Threshold, VAL (Note 1) Full - - +0.8 - - +0.8 V Input High Threshold, VAH (Note 1) Full +2.4 - - +2.4 - - V Input Leakage Current (High or Low), IA (Notes 1, 4) Full - - 1.0 - - 1.0 A Full -15 - +15 -15 - +15 V (Notes 1, 2) 25 - 180 300 - 180 400 25 - 5 - - 5 - % Off Input Leakage Current, IS(OFF) (Note 3) 25 - 0.03 - - 0.03 - nA Full - - 50 - - 50 nA Off Output Leakage Current, ID(OFF) (Note 3) 25 - 0.3 - - 0.3 - nA HI-506 Full - - 300 - - 300 nA HI-507 Full - - 200 - - 200 nA HI-508 Full - - 200 - - 200 nA ANALOG CHANNEL CHARACTERISTICS Analog Signal Range, VS On Resistance, rON rON , (Any Two Channels) HI-509 Full - - 100 - - 100 nA 25 - 0.3 - - 0.3 - nA HI-506 Full - - 300 - - 300 nA HI-507 Full - - 200 - - 200 nA HI-508 Full - - 200 - - 200 nA HI-509 Full - - 100 - - 100 nA (Note 1) Full - - 50 - - 50 nA Current, I+, Pin 1 HI-506/HI-507 (Note 6) Full - 1.5 3.0 - 1.5 3.0 mA Current, I+, HI-508/HI-509 (Note 6) Full - 1.5 2.4 - 1.5 2.4 mA Current, I-, Pin 27 HI-506/HI-507 (Note 6) Full - 0.4 1.0 - 0.4 1.0 mA Current, I-, HI-508/HI-509 (Note 6) Full - 0.4 1.0 - 0.4 1.0 mA HI-506/HI-507 Full - - 60 - - 60 mW HI-508/HI-509 Full - - 51 - - 51 mW On Channel Leakage Current, ID(ON) Differential Off Output Leakage Current, IDIFF (HI-507, HI-509 Only) (Note 3) POWER REQUIREMENTS Power Dissipation, PD NOTES: 1. 100% tested for Dash 8. Leakage currents not tested at -55oC. 2. VOUT = 10V, IOUT = +1mA. 3. 10nA is the practical lower limit for high speed measurement in the production test environment. 4. Digital input leakage is primarily due to the clamp diodes (see Schematic). Typical leakage is less than 1nA at 25oC. 5. VEN = 0.8V, RL = 1K, CL = 15pF, VS = 7VRMS , f = 100kHz. 6. VEN , VA = 0V or 2.4V. 7. Signal voltage at any analog input or output (S or D) will be clamped to the supply rail by internal diodes. Limit the resulting current as shown under absolute maximum ratings. If an overvoltage condition is anticipated (analog input exceeds either power supply voltage), the Harris HI-546/HI-547/HI-548/HI-549 multiplexers are recommended. 11-61 HI-506, HI-507, HI-508, HI-509 Typical Performance Curves TA = 25oC, VSUPPLY = 15V, VAH = 2.4V, VAL = 0.8V, Unless Otherwise Specified 1mA V2 IN OUT VIN RON = V2 1mA FIGURE 1A. TEST CIRCUIT 2.2 NORMALIZED RESISTANCE (REFERRED TO VALUE AT 15V) ON RESISTANCE () 400 300 TA = 125oC 200 TA = 25oC 100 TA = -55oC 0 -15 -10 -5 0 +5 ANALOG INPUT (V) +10 1.8 1.6 1.4 1.2 1.0 0.8 0.6 7 +15 FIGURE 1B. ON RESISTANCE vs ANALOG INPUT VOLTAGE, TEMPERATURE 125oC TO -55oC VIN = 0V 2.0 8 9 10 11 12 SUPPLY VOLTAGE (V) 13 14 FIGURE 1C. NORMALIZED ON RESISTANCE vs SUPPLY VOLTAGE FIGURE 1. ON RESISTANCE 100nA OFF OUTPUT LEAKAGE CURRENT ID(OFF) LEAKAGE CURRENT 10nA +0.8V EN ID(ON) OUT 1nA A 10V +10V OFF INPUT LEAKAGE CURRENT IS(OFF) 100pA 10pA 25 50 75 100 125 TEMPERATURE (oC) FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE FIGURE 2B. ID(OFF) TEST CIRCUIT 11-62 ID(OFF) 15 HI-506, HI-507, HI-508, HI-509 Typical Performance Curves TA = 25oC, VSUPPLY = 15V, VAH = 2.4V, VAL = 0.8V, Unless Otherwise Specified (Continued) OUT OUT IS(OFF) A A +0.8V EN A0 A1 10V +10V 10V ID(ON) EN +10V +2.4V FIGURE 2C. IS(OFF) TEST CIRCUIT FIGURE 2D. ID(ON) TEST CIRCUIT FIGURE 2. ON RESISTANCE NOTE: 1. Two measurements per channel: +10V/-10V and -10V/+10V. (Two measurements per device for ID(OFF) +10V/-10V and -10V/+10V.) 100 (VS), (VD) OFF ISOLATION (dB) INPUT LOGIC THRESHOLD (V) 4 3 2 1 0 6 8 10 12 14 16 18 80 RL = 1K 60 RL = 10M 40 VEN = 0V CLOAD = 28pF VS = 7VRMS 20 0 104 20 105 FIGURE 3. LOGIC THRESHOLD vs POWER SUPPLY VOLTAGE 3 POWER SUPPLY CURRENT (mA) POWER SUPPLY CURRENT (mA) 107 FIGURE 4. OFF ISOLATION vs FREQUENCY 3 2 VEN = 2.4V VEN = 0V 1 0 -55 106 FREQUENCY (Hz) POWER SUPPLY VOLTAGE (V) -35 -15 -5 25 45 65 TEMPERATURE (oC) 85 105 2 EN = 5V 1 EN = 0V 0 -55 125 -35 -15 -5 25 45 65 TEMPERATURE (oC) FIGURE 5A. HI-506/HI-507 FIGURE 5B. HI-508/HI-509 FIGURE 5. POWER SUPPLY CURRENT vs TEMPERATURE 11-63 85 105 125 HI-506, HI-507, HI-508, HI-509 Typical Performance Curves TA = 25oC, VSUPPLY = 15V, VAH = 2.4V, VAL = 0.8V, Unless Otherwise Specified (Continued) 70 SWITCH CURRENT (mA) 60 TA = -55oC 50 TA = 25oC 40 TA = 125oC 30 20 A VIN 10 0 0 2 4 6 8 10 12 14 16 VOLTAGE ACROSS SWITCH (V) FIGURE 6A. ON CHANNEL CURRENT vs VOLTAGE FIGURE 6B. TEST CIRCUIT FIGURE 6. ON CHANNEL CURRENT vs VOLTAGE 8 +15V/+10V SUPPLY CURRENT (mA) +ISUPPLY A VSUPPLY = 15V 6 +V IN 1 A3 A2 4 VA 50 10V/5V HI-506 A1 IN 2 THRU IN 7/15 A0 IN 8/16 10V/5V 2 +3.5V VSUPPLY = 10V VA 0 1K 10K 100K TOGGLE FREQUENCY (Hz) 1M 10M OUT -V EN HIGH = 3.5V LOW = 0V 50% DUTY CYCLE GND Similar connection for HI-507/HI-508/ FIGURE 7A. SUPPLY CURRENT vs TOGGLE FREQUENCY 14 pF -ISUPPLY A HI-509 10 M -15V/-10V FIGURE 7B. TEST CIRCUIT FIGURE 7. SUPPLY CURRENT +15V ACCESS TIME (ns) 600 +V IN 1 A3 400 A2 VA 50 A1 10V IN 2 THRU IN 7/15 HI-506 A0 +10V PROBE IN 16 200 +3.5V EN GND OUT -V 0 2 3 4 5 13 LOGIC LEVEL (HIGH) (V) 14 -15V 15 Similar connection for HI-507/HI-508/ HI-509 FIGURE 8A. ACCESS TIME vs LOGIC LEVEL (HIGH) FIGURE 8B. TEST CIRCUIT 11-64 10 k 50 pF HI-506, HI-507, HI-508, HI-509 Switching Waveforms 3.5V ADDRESS DRIVE (VA) VA INPUT 2V/DIV. 50% 0V S1 ON +10V OUTPUT 90% OUTPUT 5V/DIV. -10V tA S16 ON 200ns/DIV. FIGURE 8C. WAVEFORMS FIGURE 8D. ACCESS TIME FIGURE 8. ACCESS TIME +15V +V A3 A2 50 VA A1 HI-506 +5V IN 1 IN 2 THRU IN 7/IN 15 IN 8 /16 A0 +3.5V VOUT EN GND OUT -V 50pF 200 -15V Similar connection for HI-507/HI-508/HI-509 FIGURE 9A. TEST CIRCUIT 3.5V VA INPUT 2V/DIV. S1 ON ADDRESS DRIVE (VA) 0V OUTPUT 1V/DIV. OUTPUT A 50% S16 ON 50% tOPEN 100ns/DIV. FIGURE 9B. WAVEFORMS FIGURE 9C. BREAK-BEFORE-MAKE DELAY (tOPEN) FIGURE 9. BREAK-BEFORE-MAKE DELAY (tOPEN) 11-65 HI-506, HI-507, HI-508, HI-509 Switching Waveforms (Continued) +15V +V A3 A2 A1 HI-506 IN 1 +10V IN 2 THRU IN 7/IN 15 IN 8 /16 A0 VOUT EN -VA 50 GND OUT -V 50pF 200 -15V Similar connection for HI-507/HI-508/HI-509 FIGURE 10A. TEST CIRCUIT ENABLE DRIVE 3.5V ENABLE DRIVE 2V/DIV. 50% 50% 0V OUTPUT A 90% S1 ON 10% S2THRU S16 OFF OUTPUT 2V/DIV. tON(EN) tOFF(EN) FIGURE 10B. WAVEFORMS FIGURE 10C. ENABLE DELAY tON(EN) , tOFF(EN) FIGURE 10. ENABLE DELAY 11-66 HI-506, HI-507, HI-508, HI-509 Truth Tables HI-506 HI-508 A3 A2 A1 A0 EN "ON" CHANNEL A2 A1 A0 EN "ON" CHANNEL X X X X L None X X X L None L L L L H 1 L L L H 1 L L L H H 2 L L H H 2 L L H L H 3 L H L H 3 L L H H H 4 L H H H 4 L H L L H 5 H L L H 5 L H L H H 6 H L H H 6 L H H L H 7 H H L H 7 L H H H H 8 H H H H 8 H L L L H 9 H L L H H 10 H L H L H 11 H L H H H 12 A1 A0 EN "ON" CHANNEL PAIR H H L L H 13 X X L None H H L H H 14 L L H 1 H H H L H 15 L H H 2 H H H H H 16 H L H 3 H H H 4 HI-509 HI-507 A2 A1 A0 EN "ON" CHANNEL X X X L None L L L H 1 L L H H 2 L H L H 3 L H H H 4 H L L H 5 H L H H 6 H H L H 7 H H H H 8 11-67 HI-506, HI-507, HI-508, HI-509 Die Characteristics DIE DIMENSIONS: WORST CASE CURRENT DENSITY: 1.4 x 105 A/cm2 129 mils x 82 mils METALLIZATION: TRANSISTOR COUNT: Type: CuAl Thickness: 16kA 2kA 421 PROCESS: SUBSTRATE POTENTIAL (NOTE): CMOS-DI -VSUPPLY PASSIVATION: Type: Nitride/Silox Nitride Thickness: 3.5kA 1kA Silox Thickness: 12kA 2kA NOTE: The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -VSUPPLY potential. Metallization Mask Layout HI-506 EN A0 A1 A2 HI-507 A3 EN GND A0 A1 A2 NC GND IN 1 IN 9 IN 1A IN 1B IN 2 IN 10 IN 2A IN 2B IN 3 IN 11 IN 3A IN 3B IN 4 IN 12 IN 4A IN 4B IN 5 IN 13 IN 5A IN 5B IN 6 IN 14 IN 6A IN 6B IN 7 IN 15 IN 7A IN 7B IN 8 IN 16 IN 8A IN 8B -V OUT +V NC -V OUT A NOTE: Pad numbers correspond to DIP pin numbers only. 11-68 +V OUT B HI-506, HI-507, HI-508, HI-509 Die Characteristics DIE DIMENSIONS: WORST CASE CURRENT DENSITY: 1.4 x 105 A/cm2 81.9 mils x 90.2 mils METALLIZATION: TRANSISTOR COUNT: Type: CuAl Thickness: 16kA 2kA 234 PROCESS: SUBSTRATE POTENTIAL (NOTE): CMOS-DI -VSUPPLY PASSIVATION: Type: Nitride/Silox Nitride Thickness: 3.5kA 1kA Silox Thickness: 12kA 2kA NOTE: The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -VSUPPLY potential. Metallization Mask Layout HI-508 EN A0 A1 A2 HI-509 GND EN A0 A1 +VSUP -VSUP GND -VSUP +VSUP IN 1 IN 5 IN 1A IN 1B IN 2 IN 6 IN 2A IN 2B IN 3A IN 3 IN 3B IN 7 IN 4 OUT IN 4A OUT A IN 8 NOTE: Pad numbers correspond to DIP pin numbers only. 11-69 OUT B IN 4B