SEMICONDUCTOR
11-54
Features
• Low ON Resistance . . . . . . . . . . . . . . . . . . . . . . . 180Ω
• Wide Analog Signal Range . . . . . . . . . . . . . . . . . . . . ±15V
• TTL/CMOS Compatible
• Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns
• Maximum Power Supply . . . . . . . . . . . . . . . . . . . . . .44V
• Break-Before-Make Switching
• No Latch-Up
• Replaces DG506A/DG506AA and DG507A/DG507AA
• Replaces DG508A/DG508AA and DG509A/DG509AA
Applications
• Data Acquisition Systems
• Precision Instrumentation
• Demultiplexing
• Selector Switch
Description
The HI-506/HI-507 and HI-508/HI-509 monolithic CMOS
multiplexers each include an array of sixteen and eight ana-
log s witches respectiv ely, a digital decoder circuit f or channel
selection, voltage reference for logic thresholds, and an
enable input for device selection when several multiplexers
are present. The Dielectric Isolation (DI) process used in fab-
rication of these devices eliminates the problem of latchup.
DI also offers much lower substrate leakage and parasitic
capacitance than conventional junction isolated CMOS (see
Application Note AN521).
The s witching threshold for each digital input is established by
an internal +5V reference, providing a guaranteed minimum
2.4V for logic “1” and maximum 0.8V for logic “0”. This allows
direct interface without pullup resistors to signals from most
logic f amilies: CMOS , TTL, DTL and some PMOS . For protec-
tion against transient overvoltage, the digital inputs include a
series 200Ω resistor and diode clamp to each supply.
The HI-506 is a single 16-Channel, the HI-507 is an
8-Channel differential, the HI-508 is a single 8-Channel and
the HI-509 is a 4-Channel differential multiplexer. The
HI-506/HI-507 are available in a 28 lead ceramic or plastic
DIP, 28 pad leadless chip carrier (CLCC), 28 pin plastic
leaded chip carrier (PLCC) and 28 lead SOIC packages. The
HI-508/HI-509 are available in a 16 pin plastic or ceramic
DIP, a 20 pin plastic leaded chip carrier (PLCC), 20 pad
ceramic leadless chip carrier (CLCC) and 16 lead SOIC
packages.
If input overvoltages are present, the HI-546/HI-547/HI-548/
HI-549 multiplexers are recommended. For further information
see Application Notes AN520 and AN521. The
HI-506/HI-507/HI-508/HI-509 is off ered in both commercial and
military grades. For additional High Reliability Screening
including 160 hour burn-in specify the “-8” suffix. For
MIL-STD-883 compliant parts, request the HI-506/883,
HI-507/883, HI-508/883 or HI-509/883 data sheet.
August 1997
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1997
HI-506, HI-507,
HI-508, HI-509
Single 16 and 8/Differential 8-Channel and
4-Channel CMOS Analog Multiplexers
File Number 3142.1
11-55
Ordering Information
PART NUMBER TEMP.
RANGE (oC) PACKAGE PKG.
NO.
HI1-0506/883 -55 to 125 28 Ld CERDIP F28.6
HI1-0506-8 Hi-Rel
Pressing with
Burn-In
28 Ld CERDIP F28.6
HI4-0506/883 -55 to 125 28 Ld CLCC J28.A
HI1-0507/883 -55 to 125 28 Ld CERDIP F28.6
HI9P0506-9 -40 to 85 28 Ld SOIC M28.6
HI3-0506-5 0 to 75 28 Ld PDIP E28.6
HI1-0506-7 0 to 75 + 96
Hour Burn-In 28 Ld CERDIP F28.6
HI9P0506-5 0 to 75 28 Ld SOIC M28.3
HI1-0506-5 0 to 75 28 Ld CERDIP F28.6
HI1-0506-4 -25 to 85 28 Ld CERDIP F28.6
HI1-0506-2 -55 to 125 28 Ld CERDIP F28.6
HI1-0507-8 Hi-Rel
Pressing with
Burn-In
28 Ld CERDIP F28.6
HI4-0507/883 -55 to 125 28 Ld CLCC J28.A
HI1-0507-4 -25 to 85 28 Ld CERDIP F28.6
HI4P0507-5 0 to 75 28 Ld PLCC N28.45
HI9P0507-5 0 to 75 28 Ld SOIC M28.3
HI1-0507-5 0 to 75 28 Ld CERDIP F28.6
HI3-0507-5 0 to 75 28 Ld PDIP E28.3
HI9P0507-9 -40 to 85 28 Ld SOIC M28.3
HI1-0507-2 -55 to 125 28 Ld CERDIP F28.6
HI1-0508/883 -55 to 125 16 Ld CERDIP F16.3
HI1-0508-8 Hi-Rel
Pressing with
Burn-In
16 Ld CERDIP F16.3
HI4-0508/883 -55 to 125 20 Ld CLCC J20.A
HI1-0509/883 -55 to 125 16 Ld CERDIP F16.3
HI1-0508-5 0 to 75 16 Ld CERDIP F16.3
HI3-0508-5 0 to 75 16 Ld PDIP E16.3
HI1-0508-4 -25 to 85 16 Ld CERDIP F16.3
HI1-0508-2 -55 to 125 16 Ld CERDIP F16.3
HI4P0508-5 0 to 75 20 Ld PLCC N20.35
HI9P0508-9 -40 to 85 16 Ld SOIC M16.15
HI9P0508-5 0 to 75 16 Ld SOIC M16.15
HI1-0509-8 Hi-Rel
Pressing with
Burn-In
16 Ld CERDIP F16.3
HI4-0509/883 -55 to 125 20 Ld CLCC J20.A
HI9P0509-5 0 to 75 16 Ld SOIC M16.15
HI9P0509-9 -40 to 85 16 Ld SOIC M16.15
HI1-0509-4 -25 to 85 16 Ld CERDIP F16.3
HI1-0509-5 0 to 75 16 Ld CERDIP F16.3
HI3-0509-5 0 to 75 16 Ld PDIP E16.3
HI4P0509-5 0 to 75 20 Ld PLCC N20.35
HI1-0509-2 -55 to 125 16 Ld CERDIP F16.3
HI1-0509-7 0 to 75 + 96
Hour Burn-In 16 Ld CERDIP F16.3
PART NUMBER TEMP.
RANGE (oC) PACKAGE PKG.
NO.
HI-506, HI-507, HI-508, HI-509
11-56
Pinouts
HI-506
(PDIP, CERDIP, SOIC)
TOP VIEW
HI-507
(PDIP, CERDIP, SOIC)
TOP VIEW
HI-506
(CLCC, PLCC)
TOP VIEW
HI-507
(CLCC, PLCC)
TOP VIEW
+VSUPPLY
NC
NC
IN 16
IN 15
IN 14
IN 13
IN 12
IN 11
IN 10
IN 9
GND
NC
ADDRESS A3
OUT
IN 8
IN 7
IN 6
IN 5
IN 3
IN 1
ENABLE
ADDRESS A0
ADDRESS A1
ADDRESS A2
-VSUPPLY
IN 4
IN 2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
+VSUPPLY
OUT B
NC
IN 8B
IN 7B
IN 6B
IN 5B
IN 4B
IN 3B
IN 2B
IN 1B
GND
NC
NC
OUT A
IN 8A
IN 7A
IN 6A
IN 5A
IN 3A
IN 1A
ENABLE
ADDRESS A0
ADDRESS A1
ADDRESS A2
-VSUPPLY
IN 4A
IN 2A
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
IN 15
IN 14
IN 13
IN 12
IN 11
IN 10
IN 9
IN 16
NC
NC
+VSUPPLY
OUT
-VSUPPLY
IN B
GND
NC
A3
A2
A1
ENABLE
A0
IN 7
IN 6
IN 5
IN 4
IN 3
IN 2
IN 1
11
10
5
6
7
8
9
23
24
25
22
21
20
19
14 15 16 17 1812 13
3214282726
IN 7B
IN 6B
IN 5B
IN 4B
IN 3B
IN 2B
IN 1B
IN 8B
NC
OUT B
+VSUPPLY
OUT A
-VSUPPLY
IN 8A
GND
NC
NC
A2
A1
ENABLE
A0
IN 7A
IN 6A
IN 5A
IN 4A
IN 3A
IN 2A
IN 1A
11
10
5
6
7
8
9
23
24
25
22
21
20
19
14 15 16 17 1812 13
3214282726
HI-506, HI-507, HI-508, HI-509
11-57
HI-508
(PDIP, CERDIP, SOIC)
TOP VIEW
HI-509
(PDIP, CERDIP, SOIC)
TOP VIEW
HI-508
(CLCC, PLCC)
TOP VIEW
HI-509
(CLCC, PLCC)
TOP VIEW
Pinouts
(Continued)
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
A0
ENABLE
-VSUPPLY
IN 1
IN 2
IN 3
OUT
IN 4
A1
GND
+VSUPPLY
IN 5
IN 6
IN 7
IN 8
A2
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
A0
ENABLE
-VSUPPLY
IN 1A
IN 2A
IN 3A
OUT A
IN 4A
A1
+VSUPPLY
IN 1B
IN 2B
IN 3B
IN 4B
OUT B
GND
-VSUPPLY
IN 1
NC
IN 2
IN 3
ENABLE
A0
NC
A1
A2
IN 4
OUT
NC
IN 8
IN 7
GND
+VSUPPLY
NC
IN 5
IN 6
4
5
6
7
8
10 11 12 139
3212019
16
17
18
15
14
-VSUPPLY
IN 1A
NC
IN 2A
IN 3A
ENABLE
A0
NC
A1
GND
IN 4A
OUT A
NC
OUT B
IN 4B
+VSUPPLY
IN 1B
NC
IN 2B
IN 3B
4
5
6
7
8
10 11 12 139
3212019
16
17
18
15
14
HI-506, HI-507, HI-508, HI-509
11-58
Functional Diagrams
HI-506 HI-507
HI-508 HI-509
DECODER/
DRIVER
† † † †
OUT
IN 1
IN 2
IN 16
† DIGITAL
PROTECTION
A0A1A2A3
†
EN
INPUT
LEVEL
SHIFT
5V
REF
DECODER/
DRIVER
† † †
OUT B
IN 8A
IN 1A
IN 1B
† DIGITAL
PROTECTION
A0A1A2
†
EN
INPUT
LEVEL
SHIFT
5V
REF
OUT A
IN 8B
DECODER/
DRIVER
† † †
OUT
IN 1
IN 2
IN 8
† DIGITAL
PROTECTION
A0A1A2
†
EN
INPUT
LEVEL
SHIFT
5V
REF
DECODER/
DRIVER
† †
OUT B
IN 4A
IN 1A
IN 1B
† DIGITAL
PROTECTION
A0A1
†
EN
INPUT
LEVEL
SHIFT
5V
REF
OUT A
IN 4B
HI-506, HI-507, HI-508, HI-509
11-59
Schematic Diagrams
ADDRESS DECODER
ADDRESS INPUT BUFFER LEVER SHIFTER
TTL REFERENCE CIRCUIT MULTIPLEX SWITCH
P
N
A0 OR A0
TO N-CHANNEL
DEVICE OF
THE SWITCH
A1 OR A1
A2 OR A2
A3 OR A3
ENABLE
PP PP P P
+V
V-
N
N
N
N
NN
TO P-CHANNEL
DEVICE OF
THE SWITCH
DELETE A3 OR A3 INPUT FOR HI-507
DELETE A3 OR A3 INPUT FOR HI-508
DELETE A2 OR A2 INPUT FOR HI-509
+V
P3
D1
D2
200Ω
AIN
VR
ALL N-CHANEL BODIES TO V-
ALL P-CHANNEL BODIES TO V+
UNLESS OTHERWISE INDICATED
A
-V
P1
N1
VL
P2
N2
N3
-V
+V
P4
P5
P6 P7 P8 P9 P10
N6 N7 N8 N9 N10
N4
N5
A
VL
Q9P
Q10N
N13 N14
P15 Q1P
N15
Q5N
D3
Q11P
R3
6.8K
P16
R2
16.8K
Q12N
Q6N
Q2P
V+
Q3P Q4P
N12
Q7P
V- GND
Q8N
VR
FROM DECODE
V+
N18
N19
P17
N17
V-
P18
OUT
FROM DECODE
IN
HI-506, HI-507, HI-508, HI-509
11-60
Absolute Maximum Ratings Thermal Information
VSUPPLY(+) to VSUPPLY(-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44V
VSUPPLY(+) to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +22V
VSUPPLY(-) to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-25V
Digital Input Overvoltage
+VEN, +VA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VSUPPLY +4V
-VEN, -VA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VSUPPLY -4V
or 20mA, Whichever Occurs First
Analog Signal Overvoltage (Note 7)
+VS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VSUPPLY +2V
-VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VSUPPLY -2V
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40mA
(Pulsed at 1ms, 10% Duty Cycle Max)
Operating Conditions
Temperature Ranges
HI-506/507/508/509-2, -8 . . . . . . . . . . . . . . . . . . . -55oC to 125oC
HI-506/507/508/509-4. . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC
HI-506/507/508/509-5. . . . . . . . . . . . . . . . . . . . . . . . .0oC to 75oC
Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)
16 Ld CERDIP Package . . . . . . . . . . . 85 32
16 Ld SOIC Package. . . . . . . . . . . . . . 115 N/A
16 Ld PDIP Package . . . . . . . . . . . . . . 100 N/A
20 Ld CLCC Package . . . . . . . . . . . . . 80 28
20 Ld PLCC Package . . . . . . . . . . . . . 80 N/A
28 Ld CERDIP Package . . . . . . . . . . . 55 18
28 Ld PDIP Package . . . . . . . . . . . . . . 60 N/A
28 Ld SOIC Package. . . . . . . . . . . . . . 70 N/A
28 Ld CLCC Package . . . . . . . . . . . . . 70 20
28 Ld PLCC Package . . . . . . . . . . . . . 70 N/A
Maximum Junction Temperature
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC
Plastic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC and PLCC - Lead Tips Only)
CA UTION: Stresses abo v e those listed in “Absolute Maximum Ratings” ma y cause permanent damage to the de vice. This is a stress only rating and oper ation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications Supplies = +15V, -15V; VAH (Logic Level High) = +2.4V; VAL (Logic Level Low) = +0.8V,
Unless Otherwise Specified. For Test Conditions, Consult Performance Curves
PARAMETER TEST
CONDITIONS TEMP
(oC)
HI-5XX-2, HI-5XX-8 HI-5XX-4, HI-5XX-5
UNITSMIN TYP MAX MIN TYP MAX
SWITCHING CHARACTERISTICS
Access Time, IA (Note 1) 25 - 250 500 - 250 - ns
Full - - 1000 - - 1000 ns
Break-Before-Make Delay, tOPEN (Note 1) 25 25 80 - 25 80 - ns
Enable Delay (ON), tON(EN) (Note 1) 25 - 250 500 - 250 - ns
Full - - 1000 - - 1000 ns
Enable Delay (OFF), tOFF(EN) (Note 1) 25 - 250 500 - 250 - ns
Full - - 1000 - - 1000 ns
Settling Time to 0.1%, tS
(HI-506 and HI-507) 25 - 1.2 - - 1.2 - µs
Settling Time to 0.01%, tS
(HI-506 and HI-507) 25 - 2.4 - - 2.4 - µs
Settling Time to 0.1%, tS
(HI-508 and HI-509) 25 - 360 - - 360 - ns
Settling Time to 0.01%, tS
(HI-508 and HI-509) 25 - 600 - - 600 - ns
“Off Isolation” (Note 5) 25 50 68 - 50 68 - dB
Channel Input Capacitance,
CS(OFF) 25 -10- -10-pF
Channel Output Capacitance,
CD(OFF) (HI-506) 25 -52- -52-pF
Channel Output Capacitance,
CD(OFF) (HI-507) 25 -30- -30-pF
Channel Output Capacitance,
CD(OFF) (HI-508) 25 -17- -17-pF
Channel Output Capacitance,
CD(OFF) (HI-509) 25 -12- -12-pF
HI-506, HI-507, HI-508, HI-509
11-61
Digital Input Capacitance, CA25 - 6 - - 6 - pF
Input to Output Capacitance,
CDS(OFF) 25 - 0.08 - - 0.08 - pF
DIGITAL INPUT CHARACTERISTICS
Input Low Threshold, VAL (Note 1) Full - - +0.8 - - +0.8 V
Input High Threshold, VAH (Note 1) Full +2.4 - - +2.4 - - V
Input Leakage Current
(High or Low), IA(Notes 1, 4) Full - - 1.0 - - 1.0 µA
ANALOG CHANNEL CHARACTERISTICS
Analog Signal Range, VSFull -15 - +15 -15 - +15 V
On Resistance, rON (Notes 1, 2) 25 - 180 300 - 180 400 Ω
∆rON, (Any Two Channels) 25 - 5 - - 5 - %
Off Input Leakage Current,
IS(OFF) (Note 3) 25 - 0.03 - - 0.03 - nA
Full - - 50 - - 50 nA
Off Output Leakage Current,
ID(OFF)(Note 3) 25 - 0.3 - - 0.3 - nA
HI-506 Full - - 300 - - 300 nA
HI-507 Full - - 200 - - 200 nA
HI-508 Full - - 200 - - 200 nA
HI-509 Full - - 100 - - 100 nA
On Channel Leakage Current,
ID(ON) (Note 3) 25 - 0.3 - - 0.3 - nA
HI-506 Full - - 300 - - 300 nA
HI-507 Full - - 200 - - 200 nA
HI-508 Full - - 200 - - 200 nA
HI-509 Full - - 100 - - 100 nA
Differential Off Output Leakage
Current, IDIFF
(HI-507, HI-509 Only)
(Note 1) Full - - 50 - - 50 nA
POWER REQUIREMENTS
Current, I+, Pin 1 HI-506/HI-507 (Note 6) Full - 1.5 3.0 - 1.5 3.0 mA
Current, I+, HI-508/HI-509 (Note 6) Full - 1.5 2.4 - 1.5 2.4 mA
Current, I-, Pin 27 HI-506/HI-507 (Note 6) Full - 0.4 1.0 - 0.4 1.0 mA
Current, I-, HI-508/HI-509 (Note 6) Full - 0.4 1.0 - 0.4 1.0 mA
Power Dissipation, PD
HI-506/HI-507 Full - - 60 - - 60 mW
HI-508/HI-509 Full - - 51 - - 51 mW
NOTES:
1. 100% tested for Dash 8. Leakage currents not tested at -55oC.
2. VOUT = ±10V, IOUT = +1mA.
3. 10nA is the practical lower limit for high speed measurement in the production test environment.
4. Digital input leakage is primarily due to the clamp diodes (see Schematic). Typical leakage is less than 1nA at 25oC.
5. VEN = 0.8V, RL = 1K, CL = 15pF, VS = 7VRMS, f = 100kHz.
6. VEN, VA = 0V or 2.4V.
7. Signal voltage at any analog input or output (S or D) will be clamped to the supply rail by internal diodes. Limit the resulting current as
shown under absolute maximum ratings. If an overvoltage condition is anticipated (analog input exceeds either power supply voltage),
the Harris HI-546/HI-547/HI-548/HI-549 multiplexers are recommended.
Electrical Specifications Supplies = +15V, -15V; VAH (Logic Level High) = +2.4V; VAL (Logic Level Low) = +0.8V,
Unless Otherwise Specified. For Test Conditions, Consult Performance Curves (Continued)
PARAMETER TEST
CONDITIONS TEMP
(oC)
HI-5XX-2, HI-5XX-8 HI-5XX-4, HI-5XX-5
UNITSMIN TYP MAX MIN TYP MAX
HI-506, HI-507, HI-508, HI-509
11-62
Typical P erf ormance Curves
TA = 25oC, VSUPPLY = ±15V, VAH = 2.4V, V AL = 0.8V, Unless Otherwise Specified
FIGURE 1A. TEST CIRCUIT
FIGURE 1B. ON RESISTANCE vs ANALOG INPUT VOLTAGE,
TEMPERATURE FIGURE 1C. NORMALIZED ON RESISTANCE vs SUPPLY
VOLTAGE
FIGURE 1. ON RESISTANCE
FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE FIGURE 2B. ID(OFF) TEST CIRCUIT
1mA
OUTIN
VIN RON = V2
1mA
V2
400
300
200
100
0
-15 ANALOG INPUT (V)
ON RESISTANCE (Ω)
-10 -5 0 +5 +10 +15
TA = 125oC
TA = 25oC
TA = -55oC
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
NORMALIZED RESISTANCE
(REFERRED TO VALUE AT ±15V)
±7±8±9±10 ±11 ±12 ±13 ±14 ±15
SUPPLY VOLTAGE (V)
125oC TO -55oC
VIN = 0V
100nA
10nA
1nA
100pA
10pA
LEAKAGE CURRENT
25 50 75 100 125
TEMPERATURE (oC)
OFF OUTPUT
LEAKAGE CURRENT
ID(OFF)
ID(ON)
OFF INPUT
LEAKAGE CURRENT
IS(OFF)
A
+10V
±10V
+0.8V
EN
OUT
ID(OFF)
HI-506, HI-507, HI-508, HI-509
11-63
FIGURE 2C. IS(OFF) TEST CIRCUIT FIGURE 2D. ID(ON) TEST CIRCUIT
FIGURE 2. ON RESISTANCE
NOTE:
1. Two measurements per channel: +10V/-10V and -10V/+10V. (Two measurements per device for ID(OFF) +10V/-10V and -10V/+10V.)
FIGURE 3. LOGIC THRESHOLD vs POWER SUPPLY VOLTAGE FIGURE 4. OFF ISOLATION vs FREQUENCY
FIGURE 5A. HI-506/HI-507 FIGURE 5B. HI-508/HI-509
FIGURE 5. POWER SUPPLY CURRENT vs TEMPERATURE
Typical P erf ormance Curves
TA = 25oC, VSUPPLY = ±15V, VAH = 2.4V, V AL = 0.8V, Unless Otherwise Specified (Continued)
+10V
±10V
+0.8V
EN
A
OUT
IS(OFF)
OUT
ID(ON)
A
+10V ±10V
+2.4V
EN
A0A1
±6±8±10 ±12 ±14 ±16 ±18 ±20
POWER SUPPLY VOLTAGE (V)
INPUT LOGIC THRESHOLD (V)
4
3
2
1
0
100
80
60
40
20
0
104
(VS), (VD) OFF ISOLATION (dB)
105106107
FREQUENCY (Hz)
VEN = 0V
CLOAD = 28pF
VS= 7VRMS
RL = 1K
RL = 10M
3
2
1
0
±POWER SUPPLY CURRENT (mA)
-55 TEMPERATURE (oC)
-35 -15 -5 4525 65 85 105 125
VEN = 2.4V
VEN = 0V
3
2
1
0
-55
POWER SUPPLY CURRENT (mA)
TEMPERATURE (oC)
-35 -15 -5 25 45 65 85 105 125
EN = 5V
EN = 0V
HI-506, HI-507, HI-508, HI-509
11-64
FIGURE 6A. ON CHANNEL CURRENT vs VOLTAGE FIGURE 6B. TEST CIRCUIT
FIGURE 6. ON CHANNEL CURRENT vs VOLTAGE
FIGURE 7A. SUPPLY CURRENT vs TOGGLE FREQUENCY FIGURE 7B. TEST CIRCUIT
FIGURE 7. SUPPLY CURRENT
FIGURE 8A. ACCESS TIME vs LOGIC LEVEL (HIGH) FIGURE 8B. TEST CIRCUIT
Typical P erf ormance Curves
TA = 25oC, VSUPPLY = ±15V, VAH = 2.4V, V AL = 0.8V, Unless Otherwise Specified (Continued)
70
60
50
40
30
20
10
00±2±4±6±8±10 ±12 ±14 ±16
VOLTAGE ACROSS SWITCH (V)
SWITCH CURRENT (mA)
TA = -55oC
TA= 25oC
TA = 125oC
A
±VIN
8
6
4
2
01K TOGGLE FREQUENCY (Hz)
SUPPLY CURRENT (mA)
10K 100K 1M 10M
VSUPPLY = ±15V
VSUPPLY = ±10V
±10V/±5V
+15V/+10V
+V
-V
IN 1
IN 2
IN 8/16
OUT
A0
EN
A1
10 14
MΩpF
A3
A2
50Ω
VA
+3.5V GND
A
-15V/-10V
A-ISUPPLY
+ISUPPLY
±10V/±5V
VAHIGH = 3.5V
LOW = 0V
50% DUTY CYCLE
THRU
IN 7/15
HI-506†
†Similar connection for HI-507/HI-508/
HI-509
600
400
200
02
ACCESS TIME (ns)
LOGIC LEVEL (HIGH) (V)
345 151413
±10V
+15V
+V
-V
IN 1
IN 2 THRU
IN 16
OUT
A0
EN
A1
10 50
kΩpF
A3
A2
50Ω
VA
+3.5V GND
-15V
+10V
IN 7/15
HI-506†
†Similar connection for HI-507/HI-508/
PROBE
HI-509
HI-506, HI-507, HI-508, HI-509
11-65
Switching Waveforms
FIGURE 8C. WAVEFORMS FIGURE 8D. ACCESS TIME
FIGURE 8. ACCESS TIME
FIGURE 9A. TEST CIRCUIT
FIGURE 9B. WAVEFORMS FIGURE 9C. BREAK-BEFORE-MAKE DELAY (tOPEN)
FIGURE 9. BREAK-BEFORE-MAKE DELAY (tOPEN)
50%
3.5V
90%
+10V
0V
OUTPUT
-10V
tA
ADDRESS
DRIVE (VA)
200ns/DIV.
S1 ON
S16 ON
VA INPUT
2V/DIV.
OUTPUT
5V/DIV.
+15V
+V
-V
IN 1
IN 2 THRU
IN 8 /16
OUT
A0
EN
A1
50pF
200Ω
VOUT
-15V
A3
A2
50Ω
VA
+3.5V
GND
+5V
IN 7/IN 15
HI-506†
†Similar connection for HI-507/HI-508/HI-509
50% 50%
3.5V
0V
OUTPUT A
ADDRESS
DRIVE (VA)
tOPEN
S1 ON S16 ON
VA INPUT
2V/DIV.
OUTPUT
1V/DIV.
100ns/DIV.
HI-506, HI-507, HI-508, HI-509
11-66
FIGURE 10A. TEST CIRCUIT
FIGURE 10B. WAVEFORMS FIGURE 10C. ENABLE DELAY tON(EN), tOFF(EN)
FIGURE 10. ENABLE DELAY
Switching Waveforms
(Continued)
+15V
+V
-V
IN 1
IN 2 THRU
IN 8 /16
OUT
A0
EN
A1
50pF
200Ω
VOUT
-15V
A3
A2
-VAGND
+10V
IN 7/IN 15
HI-506†
†Similar connection for HI-507/HI-508/HI-509
50Ω
3.5V
0V
OUTPUT A
tOFF(EN)
ENABLE DRIVE
10%
50%
50%
90%
tON(EN)
S2THRU
S16 OFF
OUTPUT
2V/DIV.
ENABLE
DRIVE
2V/DIV.
S1 ON
HI-506, HI-507, HI-508, HI-509
11-67
Truth Tables
HI-506
A3A2A1A0EN “ON” CHANNEL
XXXXL None
LLLLH 1
LLLHH 2
LLHLH 3
LLHHH 4
LHLLH 5
LHLHH 6
LHHLH 7
LHHHH 8
HLLLH 9
HLLHH 10
HLHLH 11
HLHHH 12
HHLLH 13
HHLHH 14
HHHLH 15
HHHHH 16
HI-507
A2A1A0EN “ON” CHANNEL
X X X L None
LLLH 1
LLHH 2
LHLH 3
LHHH 4
HLLH 5
HLHH 6
HHLH 7
HHHH 8
HI-508
A2A1A0EN “ON” CHANNEL
X X X L None
LLLH 1
LLHH 2
LHLH 3
LHHH 4
HLLH 5
HLHH 6
HHLH 7
HHHH 8
HI-509
A1A0EN “ON” CHANNEL
PAIR
X X L None
LLH 1
LHH 2
HLH 3
HHH 4
HI-506, HI-507, HI-508, HI-509
11-68
Die Characteristics
DIE DIMENSIONS:
129 mils x 82 mils
METALLIZATION:
Type: CuAl
Thickness: 16kű2kÅ
SUBSTRATE POTENTIAL (NOTE):
-VSUPPLY
PASSIVATION:
Type: Nitride/Silox
Nitride Thickness: 3.5kű1kÅ
Silox Thickness: 12kű2kÅ
WORST CASE CURRENT DENSITY:
1.4 x 105 A/cm2
TRANSISTOR COUNT:
421
PROCESS:
CMOS-DI
NO TE: The substrate appears resistiv e to the -VSUPPLY terminal, therefore it ma y be left floating (Insulating Die Mount) or it may be mounted
on a conductor at -VSUPPLY potential.
Metallization Mask Layout
HI-506 HI-507
NOTE: Pad numbers correspond to DIP pin numbers only.
+V
IN 16
IN 15
IN 14
IN 13
IN 12
IN 11
IN 10
IN 9
GND
NC
A3
OUT
IN 8
IN 7
IN 6
IN 5
IN 3
IN 1
EN A0A1A2
-V
IN 4
IN 2
+V
IN 8B
IN 7B
IN 6B
IN 5B
IN 4B
IN 3B
IN 2B
IN 1B
GND
OUT B
NC
OUT A
IN 8A
IN 7A
IN 6A
IN 5A
IN 3A
IN 1A
EN A0A1A2
-V
IN 4A
IN 2A
HI-506, HI-507, HI-508, HI-509
11-69
Die Characteristics
DIE DIMENSIONS:
81.9 mils x 90.2 mils
METALLIZATION:
Type: CuAl
Thickness: 16kű2kÅ
SUBSTRATE POTENTIAL (NOTE):
-VSUPPLY
PASSIVATION:
Type: Nitride/Silox
Nitride Thickness: 3.5kű1kÅ
Silox Thickness: 12kű2kÅ
WORST CASE CURRENT DENSITY:
1.4 x 105 A/cm2
TRANSISTOR COUNT:
234
PROCESS:
CMOS-DI
NO TE: The substrate appears resistiv e to the -VSUPPLY terminal, therefore it ma y be left floating (Insulating Die Mount) or it may be mounted
on a conductor at -VSUPPLY potential.
Metallization Mask Layout
HI-508 HI-509
NOTE: Pad numbers correspond to DIP pin numbers only.
+VSUP
GND
OUT IN 8
IN 7
IN 6
IN 5
IN 3
IN 1
EN A0A1A2
-VSUP
IN 4
IN 2
+VSUP
GND
OUT A IN 4B
IN 3B
IN 2B
IN 1B
IN 3A
IN 1A
EN A0A1
-VSUP
IN 4A
IN 2A
OUT B
HI-506, HI-507, HI-508, HI-509
