TECHNICAL DATA
KK74AC174
Hex D Flip-Flop with
Common Clock and Reset
High-Speed Silicon-Gate CMOS
ORDERING INFORMATION
KK74AC174N Plastic
KK74AC174D SOIC
TA = -40° to 85° C for all packages
The KK74AC174 is identical in pinout to the LS/ALS174,
HC/HCT174. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LS/ALS outputs.
This device consists of six D flip-flops with common Clock and Reset
inputs. Each flip-flop is loaded with a low-to-high transition of the Clock
input. Reset is asynchronous and active-low.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA; 0.1 µA @ 25°C
• High Noise Immunity Characteristic of CMOS Devices
• Outputs Source/Sink 24mA
FUNCTION TABLE
Inputs Output
Reset Clock D Q
L X X L
H H H
H L L
H L X no change
H X no change
X = Don’t care
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16=VCC
PIN 8 = GND
1
KK74AC174
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V
VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
IIN DC Input Current, per Pin ±20 mA
IOUT DC Output Sink/Source Current, per Pin ±50 mA
ICC DC Supply Current, VCC and GND Pins ±50 mA
PDPower Dissipation in Still Air, Plastic DIP+
SOIC Package+ 750
500 mW
Tstg Storage Temperature -65 to +150 °C
TLLead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package) 260 °C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TJJunction Temperature (PDIP) 140 °C
TAOperating Temperature, All Package Types -40 +85 °C
IOH Output Current - High -24 mA
IOL Output Current - Low 24 mA
tr, tfInput Rise and Fall Time *
(except Schmitt Inputs) VCC =3.0 V
VCC =4.5 V
VCC =5.5 V
0
0
0
150
40
25
ns/V
* VIN from 30% to 70% VCC
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or
VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
2
KK74AC174
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
V
CC Guaranteed Limits
Symbol Parameter Test Conditions V
25 °C -40°C to
85°C Unit
VIH Minimum High-
Level Input Voltage VOUT=0.1 V or VCC-0.1 V 3.0
4.5
5.5
2.1
3.15
3.85
2.1
3.15
3.85
V
VIL Maximum Low -
Level Input Voltage VOUT=0.1 V or VCC-0.1 V 3.0
4.5
5.5
0.9
1.35
1.65
0.9
1.35
1.65
V
VOH Minimum High-
Level Output Voltage IOUT ≤ -50 µA 3.0
4.5
5.5
2.9
4.4
5.4
2.9
4.4
5.4
V
*VIN=VIH or VIL
IOH=-12 mA
IOH=-24 mA
IOH=-24 mA
3.0
4.5
5.5
2.56
3.86
4.86
2.46
3.76
4.76
VOL Maximum Low-
Level Output Voltage IOUT ≤ 50 µA 3.0
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V
*VIN=VIH or VIL
IOL=12 mA
IOL=24 mA
IOL=24 mA
3.0
4.5
5.5
0.36
0.36
0.36
0.44
0.44
0.44
IIN Maximum Input
Leakage Current VIN=VCC or GND 5.5 ±0.1 ±1.0 µA
IOLD +Minimum Dynamic
Output Current VOLD=1.65 V Max 5.5 75 mA
IOHD +Minimum Dynamic
Output Current VOHD=3.85 V Min 5.5 -75 mA
ICC Maximum Quiesc ent
Supply Current
(per Package)
VIN=VCC or GND 5.5 8.0 80 µA
* All outputs loaded; thresholds on input associated with output under test.
+Maximum test duration 2.0 ms, one output loaded at a time.
Note: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC
3
KK74AC174
AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=3.0 ns)
V
CC*Guaranteed Limits
Symbol Parameter V
25 °C -40°C to
85°C Unit
Min Max Min Max
fmax Maximum Clock Frequency (Figure 1) 3.3
5.0 90
100 70
100 MHz
tPLH Propagation Delay, Clock to Q (Figure 1) 3.3
5.0 2.0
1.5 11.5
8.5 1.5
1.0 12.5
9.5 ns
tPHL Propagation Delay, Clock to Q (Figure 1) 3.3
5.0 2.0
1.5 11.0
8.0 1.5
1.0 12.0
9.0 ns
tPHL Propagation Delay, Reset to Q (Figure 2) 3.3
5.0 2.5
1.5 11.5
9.0 2.0
1.5 12.5
10.5 ns
CIN Maximum Input Capacitance 5.0 4.5 4.5 pF
Typical @25°C,VCC=5.0 V
CPD Power Dissipation Capacitance 85 pF
*Voltage Range 3.3 V is 3.3 V ±0.3 V
Voltage Range 5.0 V is 5.0 V ±0.5 V
TIMING REQUIREMENTS(CL=50pF,Input tr=tf=3.0 ns)
V
CC*Guaranteed Limits
Symbol Parameter V
25 °C -40°C to
85°C Unit
tsu Minimum Setup Time, Data to Clock
(Figure 3) 3.3
5.0 6.5
5.0 7.0
5.5 ns
thMinimum Hold Time, Clock to Data
(Figure 3) 3.3
5.0 3.0
3.0 3.0
3.0 ns
twMinimum Pulse Width, Reset (Figure 2) 3.3
5.0 5.5
5.0 7.0
5.0 ns
twMinimum Pulse Width, Clock (Figure 1) 3.3
5.0 5.5
5.0 7.0
5.0 ns
trec Minimum Recovery Time, Reset to Clock
(Figure 2) 3.3
5.0 2.5
2.0 2.5
2.0 ns
*Voltage Range 3.3 V is 3.3 V ±0.3 V
Voltage Range 5.0 V is 5.0 V ±0.5 V
4
KK74AC174
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
EXPANDED LOGIC DIAGRAM
5
KK74AC174
N SUF FI X PLASTIC DI P
(MS - 001BB)
Symbol MIN MAX
A18.67 19.69
B6.1 7.11
C5.33
D0.36 0.56
F1.14 1.78
G
H
J0°10°
K2.92 3.81
NOTES: L7.62 8.26
1. D imensions “A”, “B” do not include mold flash or protr usions. M0.2 0.36
Maxim um mold flash or protrusions 0.25 mm (0.010) per side. N0.38
D SUFFIX SOIC
(MS - 012AC)
Symbol MIN MAX
A9.8 10
B3.8 4
C1.35 1.75
D0.33 0.51
F0.4 1.27
G
H
J0°8°
NOTES: K0.1 0.25
1. Dimensions A and B do not inc lude mold flash or protrusion. M0.19 0.25
2. Maximum mold flash or protrusion 0.15 m m (0.006) per side P5.8 6.2
for A; for B ‑ 0.25 m m (0.010) per side. R0.25 0.5
5.72
2.54
7.62
1.27
Dimension, mm
Dimension, mm
A
B
H
C
K
CMJFM
P
G
D
R x 45
SEATING
PLANE
0.25 (0.010) M T
-T-
1
16
8
9
L
H
MJ
A
B
F
GD
SEATING
PLANE
N
K
0.25 (0. 010) M T
-T-
C
1
16
8
9
6
