IRFIZ24E
HEXFET® Power MOSFET
PD - 9.1673A
S
D
G
VDSS = 60V
RDS(on) = 0.071Ω
ID = 14A
lAdvanced Process Technology
lIsolated Package
lHigh Voltage Isolation = 2.5KVRMS
lSink to Lead Creepage Dist. = 4.8mm
lFully Avalanche Rated
TO-220 FULLPAK
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 5.2
RθJA Junction-to-Ambient ––– 65
Thermal Resistance
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power
MOSFETs are well known for, provides the designer
with an extremely efficient and reliable device for use
in a wide variety of applications.
The TO-220 Fullpak eliminates the need for additional
insulating hardware in commercial-industrial
applications. The moulding compound used provides
a high isolation capability and a low thermal resistance
between the tab and external heatsink. This isolation
is equivalent to using a 100 micron mica barrier with
standard TO-220 product. The Fullpak is mounted to
a heatsink using a single clip or by a single screw
fixing.
9/22/97
Description
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 14
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 9.6 A
IDM Pulsed Drain Current  68
PD @TC = 25°C Power Dissipation 29 W
Linear Derating Factor 0.19 W/°C
VGS Gate-to-Source Voltage ± 20 V
EAS Single Pulse Avalanche Energy  71 mJ
IAR Avalanche Current 10 A
EAR Repetitive Avalanche Energy2.9 mJ
dv /d t Peak Diode Recovery dv/dt  5.0 V/ns
TJOperating Junction and -55 to + 175
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case ) °C
Mounting torque, 6-32 or M3 screw 10 lbf•in (1.1N•m)
Absolute Maximum Ratings
°C/W
IRFIZ24E
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 60 –– – –– – V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJBreakdown Voltage Temp. Coefficient ––– 0.052 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– ––– 0.071 ΩVGS = 10V, ID = 7.8A
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 250µA
gfs Forward Transconductance 4.5 ––– ––– S VDS = 25V, ID = 10A
––– ––– 25 µA VDS = 60V, VGS = 0V
––– ––– 250 VDS = 48V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– – –– 100 VGS = 20V
Gate-to-Source Reverse Leakage ––– – –– -100 nA VGS = -20V
QgTotal Gate Charge –– – ––– 20 ID = 10A
Qgs Gate-to-Source Charge ––– – –– 5.3 nC VDS = 44V
Qgd Gate-to-Drain ("Miller") Charge ––– – –– 7.6 VGS = 10V, See Fig. 6 and 13 
td(on) Turn-On Delay Time ––– 4.9 – –– VDD = 28V
trRise Time ––– 34 ––– ID = 10A
td(off) Turn-Off Delay Time ––– 19 ––– RG = 24Ω
tfFall Time ––– 27 ––– RD = 2.6Ω, See Fig. 10 
Between lead,
––– ––– 6mm (0.25in.)
from package
and center of die contact
Ciss Input Capacitance ––– 370 ––– VGS = 0V
Coss Output Capacitance ––– 140 ––– VDS = 25V
Crss Reverse Transfer Capacitance ––– 65 –– – ƒ = 1.0MHz, See Fig. 5
C Drain to Sink Capacitance ––– 12 – –– ƒ = 1.0MHz
nH
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
LDInternal Drain Inductance
LSInternal Source Inductance ––– –––
S
D
G
IGSS
ns
4.5
7.5
IDSS Drain-to-Source Leakage Current
pF
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
VDD = 25V, starting TJ = 25°C, L = 1.0mH
RG = 25Ω, IAS = 10A. (See Figure 12) t=60s, ƒ=60Hz
ISD ≤ 10A, di/dt ≤ 280A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C Uses IRFZ24N data and test conditions
Pulse width ≤ 300µs; duty cycle ≤ 2%.
S
D
G
Parameter Min. Typ. Max. Units Conditions
ISContinuous Source Current MOSFET symbol
(Body Diode) ––– ––– showing the
ISM Pulsed Source Current integral reverse
(Body Diode) 
––– ––– p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 7.8A, VGS = 0V
trr Reverse Recovery Time ––– 56 83 ns TJ = 25°C, IF = 10A
Qrr Reverse RecoveryCharge ––– 120 180 µ C di/dt = 100A/µs 
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Source-Drain Ratings and Characteristics
A
14
68
IRFIZ24E
Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
1
10
100
0.1 1 10 100
I , Dra in-to-Sou rce Current (A)
D
V , D rain-to-S ource V oltage (V)
DS
V G S
TO P 15 V
1 0V
8 .0V
7 .0V
6 .0V
5 .5V
5 .0V
BO TTOM 4.5V
20µs PULSE WIDTH
T = 25° C
C
A
4.5V
1
10
100
0.1 1 10 100
4.5V
I , Drain -to-S ource C urrent (A)
D
V , D ra in - to-So urc e V oltag e (V)
DS
V GS
TO P 15V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
BO TTOM 4.5V
20µs PULSE WIDTH
T = 175°C
C
A
1
10
100
45678910
T = 25°C
J
GS
V , Gate-to-So urce Voltage (V)
D
I , Dr ain -to - So u r ce Cu rren t ( A)
T = 175°C
J
A
V = 25V
20µs PULSE WIDTH
DS
0.0
0.5
1.0
1.5
2.0
2.5
3.0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
J
T , J u nc tion Tempe r ature ( °C)
R , D rain -to -Sourc e O n R e sistan ce
DS(on)
(Normalized)
V = 1 0V
GS
A
I = 17 A
D
IRFIZ24E
1
10
100
1000
1 10 100 1000
OPERATION IN THIS AREA LIMITED
BY RDS(on)
Single Pulse
T
T = 175 C
= 25 C
°°
J
C
V , Drain-to-Source Voltage (V)
I , Drain Current (A)I , Drain Current (A)
DS
D
10us
100us
1ms
10ms
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 8. Maximum Safe Operating Area
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
0
100
200
300
400
500
600
700
1 10 100
C, Ca pacitance (pF)
DS
V , D r ai n-to- So ur c e V olt ag e (V )
A
V = 0 V, f = 1 MHz
C = C + C , C SHO RT ED
C = C
C = C + C
GS
iss gs g d ds
rs s g d
oss ds gd
C
iss
C
oss
C
rss
1
10
100
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
T = 25°C
J
V = 0V
GS
V , S o ur c e-to -D r ain V olt a ge (V)
I , R ev erse D rain C u rren t (A )
SD
SD
A
T = 175°C
J
0
4
8
12
16
20
0 4 8 12 16 20
Q , To tal G a te Ch arg e (nC )
G
V , G ate-to -S ou rc e Voltage (V)
GS
A
FO R TEST CIRCUIT
SEE F IGURE 13
V = 44V
V = 28V
I = 10 A
DS
DS
D
IRFIZ24E
Fig 10a. Switching Time Test Circuit
V
DS
90%
10%
V
GS t
d(on)
t
r
t
d(off)
t
f
Fig 10b. Switching Time Waveforms
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RGD.U.T.
10V
+
-
VDD
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
25 50 75 100 125 150 175
0
3
6
9
12
15
T , Case Temperature ( C)
I , Drain Current (A)
°
C
D
0.01
0.1
1
10
0.00001 0.0001 0.001 0.01 0.1 1
Notes:
1. Duty factor D = t / t
2. Peak T = P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Thermal Response (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
IRFIZ24E
Q
G
Q
GS
Q
GD
V
G
Charge
D.U.T. V
DS
I
D
I
G
3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
10 V
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
0
20
40
60
80
100
120
140
25 50 75 100 125 150 175
J
E , S ingle Pu lse Ava lanc he E nerg y (m J)
AS
A
Starting T , Junction Temperature (°C)
I
TOP 4 .2 A
7.2 A
BOTTOM 1 0 A
V = 25 V
D
DD
Fig 12a. Unclamped Inductive Test Circuit
Fig 12b. Unclamped Inductive Waveforms
V
DS
L
D.U.T.
V
DD
I
AS
t
p
0.01Ω
R
G
+
-
t
p
V
DS
I
AS
V
DD
V
(BR)DSS
5.0 V
IRFIZ24E
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current Body Diode Forward
Current
VGS=10V
VDD
ISD
Driver Gate Drive
D.U.T. ISD Waveform
D.U.T. VDS Waveform
Inductor Curent
D = P.W.
Period
+
-
+
+
+
-
-
-
Fig 14. For N-Channel HEXFETS
* VGS = 5V for Logic Level Devices
Peak Diode Recovery dv/dt Test Circuit
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
*
IRFIZ24E
PA RT NU M BE R
INTERNATIONAL
REC TIF IER
L O GO
D ATE CODE
(YYWW)
YY = YEAR
WW = WEEK
ASSEM BL Y
L O T CO D E
E401 9245
IRFI840G
EXAM PLE : T HIS IS AN IRFI840G
WITH ASSEM BL Y
LOT C OD E E4 01
A
Part Marking Information
TO-220 Fullpak
Package Outline
TO-220 Fullpak Outline
Dimensions are shown in millimeters (inches)
L EA D ASSIGNMENTS
1 - G ATE
2 - DRA IN
3 - SO URCE
NOTES:
1 DIMEN SIONING & TOLERA NCING
PER AN SI Y14.5M , 1982
2 C ON TROLLIN G D IM ENSION: INCH.
D
C
AB
MINIMUM CRE EP AGE
DISTANCE BETWEEN
A-B-C-D = 4.80 (.189)
3X
2.85 (.112 )
2.65 (.104 )
2.80 (.110)
2.60 (.102)
4.80 (.189)
4.60 (.181)
7.10 (.280)
6.70 (.263)
3.40 (.133 )
3.10 (.123 )
ø
- A -
3.70 (.145)
3.20 (.126)
1.15 (.04 5)
MIN.
3.30 (.130 )
3.10 (.122 )
- B -
0.90 (.035)
0.70 (.028)
3X
0.25 (.010 ) MA M B
2.54 (.100)
2 X
3X
13.70 (.540)
13.50 (.530)
16.00 (.630)
15.80 (.622)
1 2 3
10.60 (.41 7)
10.40 (.40 9)
1.40 (.05 5)
1.05 (.04 2)
0.48 (.019)
0.44 (.017)
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331
EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020
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IR FAR EAST: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 0086
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http://www.irf.com/ Data and specifications subject to change without notice. 9/97
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/