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Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
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(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
µ
PD780308, 780308Y Subseries
8-bit Single-Chip Microcontrollers
µ
PD780306
µ
PD780308
µ
PD78P0308
µ
PD780306Y
µ
PD780308Y
µ
PD78P0308Y
Document No. U11377EJ3V0UD00 (3rd edition)
Date Published October 2006 N CP(K)
1996, 2006
User’s Manual
Printed in Japan
©
2User’s Manual U11377EJ3V0UD
[MEMO]
3
User’s Manual U11377EJ3V0UD
1
2
3
4
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between V
IL
(MAX) and V
IH
(MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
IL
(MAX) and
V
IH
(MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
DD
or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
NOTES FOR CMOS DEVICES
5
6
4User’s Manual U11377EJ3V0UD
FIP, IEBus, and QTOP are trademarks of NEC Electronics Corporation.
MS-DOS, Windows, and Windows NT are either registered trademarks or trademarks of Microsoft
Corporation in the United States and/or other countries.
IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.
HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
5
User’s Manual U11377EJ3V0UD
The information in this document is current as of January, 2006. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
•
•
•
•
•
•
M8E 02. 11-1
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
"Standard":
"Special":
"Specific":
6User’s Manual U11377EJ3V0UD
PREFACE
Readers This manual has been prepared for user engineers who understand the functions of
the
µ
PD780308 and 780308Y Subseries and design and develop its application
systems and programs.
•
µ
PD780308 Subseries:
µ
PD780306, 780308, 78P0308, 780306(A), 780308(A)
•
µ
PD780308Y Subseries:
µ
PD780306Y, 780308Y, 78P0308Y
Purpose This manual is intended for users to understand the functions described in the
Organization below.
Organization The
µ
PD780308, 780308Y Subseries manual is separated into two parts: this manual
and the instruction edition (common to the 78K/0 Series).
µ
PD780308, 780308Y 78K/0 Series
Subseries User’s Manual Instructions
(This Manual) User’s Manual
•Pin functions • CPU functions
•Internal block functions • Instruction set
•Interrupt • Explanation of each instruction
•Other on-chip peripheral functions
•Electrical specifications
How to Read This Manual Before reading this manual, you should have general knowledge of electric and logic
circuits and microcontrollers.
•To those who use this manual as the manual of the
µ
PD780306(A) and 780308(A):
→The
µ
PD780306 and 780308, and
µ
PD780306(A) and 780308(A) differ only in
their quality grade. Regarding (A) models read the product name as follows:
µ
PD780306 →
µ
PD780306(A)
µ
PD780308 →
µ
PD780308(A)
•When you want to understand the functions in general:
→Read this manual in the order of the contents. The mark <R> shows major
revised points. The revised points can be easily searched by copying an “<R>”
in the PDF file and specifying it in the “Find what:” field.
7
User’s Manual U11377EJ3V0UD
•How to interpret the register format:
→ For the circled bit number, the bit name is defined as a reserved word in the
RA78K0, and is defined as an sfr variable using the #pragma sfr directive in the
CC78K0.
•When you know a register name and want to confirm its details:
→ Read APPENDIX B REGISTER INDEX.
•To know the
µ
PD780308 and 780308Y Subseries instruction function in detail:
→ Refer to the 78K/0 Series Instructions User’s Manual (U12326E).
•To know the electrical specifications of the
µ
PD780308 and 780308Y Subseries:
→ Refer to CHAPTER 25 ELECTRICAL SPECIFICATIONS.
Caution The application examples in this manual are for the “standard”
quality grade for general-purpose electronic systems. If the examples
in this manual are to be used for applications where a quality higher
than that of the “standard” quality grade is required, determine the
required quality grade of the respective components and circuits to
be used.
8User’s Manual U11377EJ3V0UD
Chapter Organization: This manual divides the descriptions for the
µ
PD780308 and 780308Y Subseries into
different chapters as shown below. Read only the chapters related to the device you use.
Chapter
µ
PD780308
µ
PD780308Y
Subseries Subseries
Chapter 1 Outline (
µ
PD780308 Subseries) √—
Chapter 2 Outline (
µ
PD780308Y Subseries) — √
Chapter 3 Pin Function (
µ
PD780308 Subseries) √—
Chapter 4 Pin Function (
µ
PD780308Y Subseries) — √
Chapter 5 CPU Architecture √√
Chapter 6 Port Functions √√
Chapter 7 Clock Generator √√
Chapter 8 16-bit Timer/Event Counter √√
Chapter 9 8-bit Timer/Event Counter √√
Chapter 10 Watch Timer √√
Chapter 11 Watchdog Timer √√
Chapter 12 Clock Output Controller √√
Chapter 13 Buzzer Output Controller √√
Chapter 14 A/D Converter √√
Chapter 15 Serial Interface Channel 0 (
µ
PD780308 Subseries) √—
Chapter 16 Serial Interface Channel 0 (
µ
PD780308Y Subseries) — √
Chapter 17 Serial Interface Channel 2 √√
Chapter 18 Serial Interface Channel 3 √√
Chapter 19 LCD Controller/Driver √√
Chapter 20 Interrupt and Test Functions √√
Chapter 21 Standby Function √√
Chapter 22 Reset Function √√
Chapter 23
µ
PD78P0308,
µ
PD78P0308Y √√
Chapter 24 Instruction Set √√
Chapter 25 Electrical Specifications √√
Chapter 26 Package Drawings √√
Chapter 27 Recommended Soldering Conditions √√
9
User’s Manual U11377EJ3V0UD
Differences between
µ
PD780308 and
µ
PD780308Y Subseries:
The
µ
PD780308 and
µ
PD780308Y Subseries are different in the following functions of
serial interface channel 0.
Modes of Serial Interface Channel 0
µ
PD780308
µ
PD780308Y
Subseries Subseries
3-wire serial I/O mode √√
2-wire serial I/O mode √√
SBI (serial bus interface) mode √—
I2C (Inter IC) bus mode — √
√: Supported
—: Not supported
Conventions Data significance: Higher digits on the left and lower digits on the right
Active low representation: ××× (overscore over pin or signal name)
Note: Footnote for item marked with Note in the text
Caution: Information requiring particular attention
Remark: Supplementary information
Numerical representation: Binary ··· ×××× or ××××B
Decimal ··· ××××
Hexadecimal ··· ××××H
Related Documents The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name Document No.
µ
PD780308, 780308Y Subseries User’s Manual This manual
78K/0 Series Instructions User’s Manual U12326E
78K/0 Series Basic (III) Application Note U10182E
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
<R>
10 User’s Manual U11377EJ3V0UD
Documents Related to PROM Writing (User’s Manuals)
Document Name Document No.
PG-1500 PROM Programmer U11940E
PG-1500 Controller PC-9800 Series (MS-DOSTM) Based EEU-1291
IBM PC Series (PC-DOSTM) Based U10540E
Other Documents
Document Name Document No.
SEMICONDUCTOR SELECTION GUIDE − Products and Packages −X13769X
Semiconductor Device Mount Manual Note
Quality Grades on NEC Semiconductor Devices C11531E
NEC Semiconductor Device Reliability/Quality Control System C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E
Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html).
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
Documents Related to Development Tools (Software) (User’s Manuals)
Document Name Document No.
RA78K0 Ver. 3.80 Assembler Package Operation U17199E
Language U17198E
Structured Assembly Language U17197E
CC78K0 Ver. 3.70 C Compiler Operation U17201E
Language U17200E
SM78K Series Ver. 2.52 System Simulator Operation U16768E
ID78K Series Integrated Debugger Ver. 2.30 or Later
Operation (WindowsTM Based) U15185E
PM plus Ver. 5.20 U16934E
Documents Related to Development Tools (Hardware) (User’s Manuals)
Document Name Document No.
IE-78K0-NS In-Circuit Emulator U13731E
IE-78K0-NS-A In-Circuit Emulator U14889E
IE-780308-NS-EM1 Emulation Board U13304E
IE-78001-R-A In-Circuit Emulator U14142E
IE-780308-R-EM Emulation Board U11362E
11
User’s Manual U11377EJ3V0UD
CONTENTS
CHAPTER 1 OUTLINE (
µ
PD780308 SUBSERIES) ....................................................................... 18
1.1 Features............................................................................................................................. 18
1.2 Applications ...................................................................................................................... 19
1.3 Ordering Information ....................................................................................................... 19
1.4 Quality Grade.................................................................................................................... 20
1.5 Pin Configuration (Top View) ......................................................................................... 21
1.6 78K0 Series Lineup.......................................................................................................... 26
1.7 Block Diagram .................................................................................................................. 28
1.8 Outline of Function .......................................................................................................... 29
1.9 Mask Options.................................................................................................................... 30
CHAPTER 2 OUTLINE (
µ
PD780308Y SUBSERIES)..................................................................... 31
2.1 Features............................................................................................................................. 31
2.2 Applications ...................................................................................................................... 32
2.3 Ordering Information ....................................................................................................... 32
2.4 Quality Grade.................................................................................................................... 32
2.5 Pin Configuration (Top View) ......................................................................................... 33
2.6 78K0 Series Lineup.......................................................................................................... 38
2.7 Block Diagram .................................................................................................................. 40
2.8 Outline of Function .......................................................................................................... 41
2.9 Mask Options.................................................................................................................... 42
CHAPTER 3 PIN FUNCTION (
µ
PD780308 SUBSERIES) ............................................................. 43
3.1 Pin Function List.............................................................................................................. 43
3.1.1 Normal operating mode pins .......................................................................................... 43
3.1.2 PROM programming mode pins (
µ
PD78P0308 only)................................................... 46
3.2 Description of Pin Functions ......................................................................................... 47
3.2.1 P00 to P05, P07 (Port 0)................................................................................................... 47
3.2.2 P10 to P17 (Port 1) ........................................................................................................... 48
3.2.3 P25 to P27 (Port 2) ........................................................................................................... 48
3.2.4 P30 to P37 (Port 3) ........................................................................................................... 49
3.2.5 P70 to P72 (Port 7) ........................................................................................................... 50
3.2.6 P80 to P87 (Port 8) ........................................................................................................... 51
3.2.7 P90 to P97 (Port 9) ........................................................................................................... 51
3.2.8 P100 to P103 (Port 10) ..................................................................................................... 51
3.2.9 P110 to P117 (Port 11) ..................................................................................................... 52
3.2.10 COM0 to COM3.................................................................................................................. 52
3.2.11 VLC0 to VLC2 ......................................................................................................................... 52
3.2.12 BIAS .................................................................................................................................... 52
3.2.13 AVREF ................................................................................................................................... 53
3.2.14 AVSS .................................................................................................................................... 53
3.2.15 RESET................................................................................................................................. 53
3.2.16 X1 and X2 ........................................................................................................................... 53
3.2.17 XT1 and XT2 ...................................................................................................................... 53
User’s Manual U11377EJ3V0UD
12
3.2.18 VDD0, VDD1 ............................................................................................................................ 53
3.2.19 VSS0, VSS1 ............................................................................................................................ 53
3.2.20 VPP (
µ
PD78P0308 only)..................................................................................................... 53
3.2.21 IC (Mask ROM version only) ........................................................................................... 53
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins ............................ 54
CHAPTER 4 PIN FUNCTION (
µ
PD780308Y SUBSERIES) .......................................................... 58
4.1 Pin Function List.............................................................................................................. 58
4.1.1 Normal operating mode pins .......................................................................................... 58
4.1.2 PROM programming mode pins (
µ
PD78P0308Y only) ................................................ 61
4.2 Description of Pin Functions ......................................................................................... 62
4.2.1 P00 to P05, P07 (Port 0)................................................................................................... 62
4.2.2 P10 to P17 (Port 1) ........................................................................................................... 63
4.2.3 P25 to P27 (Port 2) ........................................................................................................... 63
4.2.4 P30 to P37 (Port 3) ........................................................................................................... 64
4.2.5 P70 to P72 (Port 7) ........................................................................................................... 65
4.2.6 P80 to P87 (Port 8) ........................................................................................................... 66
4.2.7 P90 to P97 (Port 9) ........................................................................................................... 66
4.2.8 P100 to P103 (Port 10) ..................................................................................................... 66
4.2.9 P110 to P117 (Port 11) ..................................................................................................... 67
4.2.10 COM0 to COM3.................................................................................................................. 67
4.2.11 VLC0 to VLC2 ......................................................................................................................... 67
4.2.12 BIAS .................................................................................................................................... 67
4.2.13 AVREF ................................................................................................................................... 68
4.2.14 AVSS .................................................................................................................................... 68
4.2.15 RESET................................................................................................................................. 68
4.2.16 X1 and X2 ........................................................................................................................... 68
4.2.17 XT1 and XT2 ...................................................................................................................... 68
4.2.18 VDD0, VDD1 ............................................................................................................................ 68
4.2.19 VSS0, VSS1 ............................................................................................................................ 68
4.2.20 VPP (
µ
PD78P0308Y only) .................................................................................................. 68
4.2.21 IC (Mask ROM version only) ........................................................................................... 68
4.3 Pin I/O Circuits and Recommended Connection of Unused Pins ............................ 69
CHAPTER 5 CPU ARCHITECTURE ............................................................................................... 73
5.1 Memory Spaces ................................................................................................................ 73
5.1.1 Internal program memory space .................................................................................... 76
5.1.2 Internal data memory space ........................................................................................... 77
5.1.3 Special-function register (SFR) area ............................................................................. 77
5.1.4 Data memory addressing ................................................................................................ 78
5.2 Processor Registers ........................................................................................................ 81
5.2.1 Control registers ............................................................................................................... 81
5.2.2 General-purpose registers .............................................................................................. 83
5.2.3 Special-function register (SFR) ...................................................................................... 85
5.3 Instruction Address Addressing ................................................................................... 89
5.3.1 Relative addressing.......................................................................................................... 89
5.3.2 Immediate addressing...................................................................................................... 90
5.3.3 Table indirect addressing................................................................................................ 91
13
User’s Manual U11377EJ3V0UD
5.3.4 Register addressing ......................................................................................................... 92
5.4 Operand Address Addressing ....................................................................................... 93
5.4.1 Implied addressing ........................................................................................................... 93
5.4.2 Register addressing ......................................................................................................... 94
5.4.3 Direct addressing ............................................................................................................. 95
5.4.4 Short direct addressing ................................................................................................... 96
5.4.5 Special-function register (SFR) addressing ................................................................. 98
5.4.6 Register indirect addressing .......................................................................................... 99
5.4.7 Based addressing ............................................................................................................. 100
5.4.8 Based indexed addressing.............................................................................................. 101
5.4.9 Stack addressing .............................................................................................................. 101
CHAPTER 6 PORT FUNCTIONS .................................................................................................... 102
6.1 Port Functions .................................................................................................................. 102
6.2 Port Configuration ........................................................................................................... 105
6.2.1 Port 0 .................................................................................................................................. 105
6.2.2 Port 1 .................................................................................................................................. 107
6.2.3 Port 2 (
µ
PD780308 Subseries) ........................................................................................ 108
6.2.4 Port 2 (
µ
PD780308Y Subseries)...................................................................................... 110
6.2.5 Port 3 .................................................................................................................................. 112
6.2.6 Port 7 .................................................................................................................................. 113
6.2.7 Port 8 .................................................................................................................................. 115
6.2.8 Port 9 .................................................................................................................................. 116
6.2.9 Port 10 ................................................................................................................................ 117
6.2.10 Port 11 ................................................................................................................................ 118
6.3 Port Function Control Registers ................................................................................... 121
6.4 Port Function Operations ............................................................................................... 126
6.4.1 Writing to I/O port ............................................................................................................. 126
6.4.2 Reading from I/O port ...................................................................................................... 126
6.4.3 Operations on I/O port ..................................................................................................... 126
CHAPTER 7 CLOCK GENERATOR ............................................................................................... 127
7.1 Clock Generator Functions ............................................................................................ 127
7.2 Clock Generator Configuration...................................................................................... 127
7.3 Clock Generator Control Register ................................................................................. 129
7.4 System Clock Oscillator ................................................................................................. 133
7.4.1 Main system clock oscillator .......................................................................................... 133
7.4.2 Subsystem clock oscillator ............................................................................................. 134
7.4.3 Scaler.................................................................................................................................. 136
7.4.4 When no subsystem clocks are used ........................................................................... 136
7.5 Clock Generator Operations .......................................................................................... 137
7.5.1 Main system clock operations ........................................................................................ 138
7.5.2 Subsystem clock operations .......................................................................................... 139
7.6 Changing System Clock and CPU Clock Settings...................................................... 140
7.6.1 Time required for switchover between system clock and CPU clock...................... 140
7.6.2 System clock and CPU clock switching procedure .................................................... 141
User’s Manual U11377EJ3V0UD
14
CHAPTER 8 16-BIT TIMER/EVENT COUNTER ............................................................................ 142
8.1 Outline of Internal Timer of
µ
PD780308 and 780308Y Subseries ............................. 142
8.2 16-bit Timer/Event Counter Functions.......................................................................... 144
8.3 16-bit Timer/Event Counter Configuration ................................................................... 146
8.4 16-bit Timer/Event Counter Control Registers ............................................................ 151
8.5 16-bit Timer/Event Counter Operations ........................................................................ 160
8.5.1 Interval timer operations ................................................................................................. 160
8.5.2 PWM output operations ................................................................................................... 162
8.5.3 PPG output operations .................................................................................................... 165
8.5.4 Pulse width measurement operations ........................................................................... 166
8.5.5 External event counter operation................................................................................... 173
8.5.6 Square-wave output operation ....................................................................................... 175
8.5.7 One-shot pulse output operation ................................................................................... 177
8.6 16-bit Timer/Event Counter Operating Precautions ................................................... 181
CHAPTER 9 8-BIT TIMER/EVENT COUNTER .............................................................................. 184
9.1 8-bit Timer/Event Counter Functions............................................................................ 184
9.1.1 8-bit timer/event counter mode ...................................................................................... 184
9.1.2 16-bit timer/event counter mode .................................................................................... 187
9.2 8-bit Timer/Event Counter Configuration ..................................................................... 189
9.3 8-bit Timer/Event Counter Control Registers .............................................................. 193
9.4 8-bit Timer/Event Counter Operations .......................................................................... 198
9.4.1 8-bit timer/event counter mode ...................................................................................... 198
9.4.2 16-bit timer/event counter mode .................................................................................... 204
9.5 8-bit Timer/Event Counter Precautions ........................................................................ 209
CHAPTER 10 WATCH TIMER ........................................................................................................ 211
10.1 Watch Timer Functions ................................................................................................... 211
10.2 Watch Timer Configuration ............................................................................................ 212
10.3 Watch Timer Control Registers ..................................................................................... 212
10.4 Watch Timer Operations ................................................................................................. 216
10.4.1 Watch timer operation ..................................................................................................... 216
10.4.2 Interval timer operation ................................................................................................... 216
CHAPTER 11 WATCHDOG TIMER ................................................................................................ 217
11.1 Watchdog Timer Functions ............................................................................................ 217
11.2 Watchdog Timer Configuration...................................................................................... 219
11.3 Watchdog Timer Control Registers............................................................................... 220
11.4 Watchdog Timer Operations .......................................................................................... 223
11.4.1 Watchdog timer operation............................................................................................... 223
11.4.2 Interval timer operation ................................................................................................... 224
CHAPTER 12 CLOCK OUTPUT CONTROLLER ............................................................................. 225
12.1 Clock Output Controller Functions ............................................................................... 225
12.2 Clock Output Controller Configuration ........................................................................ 226
12.3 Clock Output Function Control Registers ................................................................... 227
15
User’s Manual U11377EJ3V0UD
CHAPTER 13 BUZZER OUTPUT CONTROLLER ......................................................................... 230
13.1 Buzzer Output Controller Functions ............................................................................. 230
13.2 Buzzer Output Controller Configuration ...................................................................... 230
13.3 Buzzer Output Function Control Registers ................................................................. 231
CHAPTER 14 A/D CONVERTER .................................................................................................... 234
14.1 A/D Converter Functions ................................................................................................ 234
14.2 A/D Converter Configuration.......................................................................................... 234
14.3 A/D Converter Control Registers................................................................................... 237
14.4 A/D Converter Operations .............................................................................................. 241
14.4.1 Basic operations of A/D converter................................................................................. 241
14.4.2 Input voltage and conversion results............................................................................ 243
14.4.3 A/D converter operating mode ....................................................................................... 244
14.5 A/D Converter Cautions .................................................................................................. 246
CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (
µ
PD780308 SUBSERIES) ........................... 249
15.1 Serial Interface Channel 0 Functions ........................................................................... 250
15.2 Serial Interface Channel 0 Configuration ..................................................................... 252
15.3 Serial Interface Channel 0 Control Registers .............................................................. 256
15.4 Serial Interface Channel 0 Operations.......................................................................... 262
15.4.1 Operation stop mode ....................................................................................................... 262
15.4.2 3-wire serial I/O mode operation .................................................................................... 263
15.4.3 SBI mode operation.......................................................................................................... 267
15.4.4 2-wire serial I/O mode operation .................................................................................... 293
15.4.5 SCK0/P27 pin output manipulation ................................................................................ 298
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (
µ
PD780308Y SUBSERIES) ............................. 299
16.1 Serial Interface Channel 0 Functions ........................................................................... 300
16.2 Serial Interface Channel 0 Configuration ..................................................................... 302
16.3 Serial Interface Channel 0 Control Registers .............................................................. 306
16.4 Serial Interface Channel 0 Operations.......................................................................... 313
16.4.1 Operation stop mode ....................................................................................................... 313
16.4.2 3-wire serial I/O mode operation .................................................................................... 314
16.4.3 2-wire serial I/O mode operation .................................................................................... 318
16.4.4 I2C bus mode operation................................................................................................... 323
16.4.5 Cautions on use of I2C bus mode .................................................................................. 343
16.4.6 Restrictions when using I2C bus mode ........................................................................ 346
16.4.7 SCK0/SCL/P27 pin output manipulation ....................................................................... 348
CHAPTER 17 SERIAL INTERFACE CHANNEL 2 ........................................................................... 350
17.1 Serial Interface Channel 2 Functions ........................................................................... 350
17.2 Serial Interface Channel 2 Configuration ..................................................................... 351
17.3 Serial Interface Channel 2 Control Registers .............................................................. 355
17.4 Serial Interface Channel 2 Operation............................................................................ 365
17.4.1 Operation stop mode ....................................................................................................... 365
17.4.2 Asynchronous serial interface (UART) mode............................................................... 367
17.4.3 3-wire serial I/O mode ...................................................................................................... 381
17.4.4 Limitations of UART mode .............................................................................................. 388
User’s Manual U11377EJ3V0UD
16
CHAPTER 18 SERIAL INTERFACE CHANNEL 3 ........................................................................... 391
18.1 Serial Interface Channel 3 Functions ........................................................................... 391
18.2 Serial Interface Channel 3 Configuration ..................................................................... 391
18.3 Serial Interface Channel 3 Control Registers .............................................................. 393
18.4 Serial Interface Channel 3 Operation............................................................................ 396
18.4.1 Operation stop mode ....................................................................................................... 396
18.4.2 3-wire serial I/O mode ...................................................................................................... 397
CHAPTER 19 LCD CONTROLLER/DRIVER.................................................................................. 400
19.1 LCD Controller/Driver Functions ................................................................................... 400
19.2 LCD Controller/Driver Configuration ............................................................................ 401
19.3 LCD Controller/Driver Control Registers ..................................................................... 403
19.4 LCD Controller/Driver Settings ...................................................................................... 407
19.5 LCD Display Data Memory.............................................................................................. 408
19.6 Common Signals and Segment Signals ....................................................................... 409
19.7 Supply of LCD Drive Voltages VLC0, VLC1, VLC2 .............................................................. 413
19.8 Display Modes .................................................................................................................. 417
19.8.1 Static display example ..................................................................................................... 417
19.8.2 2-time-division display example ..................................................................................... 420
19.8.3 3-time-division display example ..................................................................................... 423
19.8.4 4-time-division display example ..................................................................................... 427
CHAPTER 20 INTERRUPT AND TEST FUNCTIONS ................................................................... 430
20.1 Interrupt Function Types ................................................................................................ 430
20.2 Interrupt Sources and Configuration ............................................................................ 431
20.3 Interrupt Function Control Registers............................................................................ 434
20.4 Interrupt Request Servicing Operations ...................................................................... 443
20.4.1 Non-maskable interrupt request acknowledge operation .......................................... 443
20.4.2 Maskable interrupt request acknowledge operation ................................................... 446
20.4.3 Software interrupt request acknowledge operation .................................................... 449
20.4.4 Multiple interrupt request servicing .............................................................................. 449
20.4.5 Interrupt request hold ...................................................................................................... 452
20.5 Test Functions.................................................................................................................. 453
20.5.1 Registers controlling test function ................................................................................ 453
20.5.2 Test input signal acknowledge operation..................................................................... 456
CHAPTER 21 STANDBY FUNCTION .............................................................................................. 457
21.1 Standby Function and Configuration ........................................................................... 457
21.1.1 Standby function .............................................................................................................. 457
21.1.2 Standby function control register .................................................................................. 458
21.2 Standby Function Operations ........................................................................................ 459
21.2.1 HALT mode ........................................................................................................................ 459
21.2.2 STOP mode ........................................................................................................................ 462
CHAPTER 22 RESET FUNCTION .................................................................................................. 465
22.1 Reset Function ................................................................................................................. 465
17
User’s Manual U11377EJ3V0UD
CHAPTER 23
µ
PD78P0308, 78P0308Y ........................................................................................... 469
23.1 Internal Memory Size Switching Register .................................................................... 470
23.2 Internal Expansion RAM Size Switching Register ...................................................... 471
23.3 PROM Programming ........................................................................................................ 472
23.3.1 Operating modes .............................................................................................................. 472
23.3.2 PROM write procedure ..................................................................................................... 474
23.3.3 PROM reading procedure ................................................................................................ 478
23.4 Screening of One-Time PROM Versions ...................................................................... 479
CHAPTER 24 INSTRUCTION SET ................................................................................................. 480
24.1 Conventions ...................................................................................................................... 481
24.1.1 Operand identifiers and description methods ............................................................. 481
24.1.2 Description of “operation” column ................................................................................ 482
24.1.3 Description of “flag operation” column ........................................................................ 482
24.2 Operation List ................................................................................................................... 483
24.3 Instructions Listed by Addressing Type ...................................................................... 491
CHAPTER 25 ELECTRICAL SPECIFICATIONS .............................................................................. 495
CHAPTER 26 PACKAGE DRAWINGS ............................................................................................. 528
CHAPTER 27 RECOMMENDED SOLDERING CONDITIONS ......................................................... 530
APPENDIX A DEVELOPMENT TOOLS .......................................................................................... 532
A.1 Software Package ............................................................................................................ 534
A.2 Language Processing Software..................................................................................... 534
A.3 Control Software .............................................................................................................. 535
A.4 PROM Programming Tools ............................................................................................. 536
A.4.1 Hardware ............................................................................................................................ 536
A.4.2 Software ............................................................................................................................. 536
A.5 Debugging Tools (Hardware) ......................................................................................... 537
A.5.1 When using in-circuit emulator IE-78K0-NS, IE-78K0-NS-A ....................................... 537
A.5.2 When using in-circuit emulator IE-78001-R-A .............................................................. 538
A.6 Debugging Tools (Software) .......................................................................................... 539
A.7 Drawing for Conversion Adapter (TGC-100SDW) ....................................................... 540
A.8 Drawing and Footprint for Conversion Socket (EV-9200GF-100) ............................. 541
A.9 Notes on Target System Design .................................................................................... 543
APPENDIX B REGISTER INDEX ...................................................................................................... 547
B.1 Register Name Index ....................................................................................................... 547
B.2 Register Symbol Index .................................................................................................... 550
APPENDIX C REVISION HISTORY .................................................................................................. 553
C.1 Major Revisions in This Edition .................................................................................... 553
C.2 Revision History up to Previous Edition...................................................................... 554
<R>
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18 User’s Manual U11377EJ3V0UD
CHAPTER 1 OUTLINE (
µ
PD780308 SUBSERIES)
1.1 Features
●●On-chip high-capacity ROM and RAM
Note The capacity of internal PROM can be changed by means of the internal memory size switching register
(IMS).
●●Minimum instruction execution time changeable from high speed (0.4
µ
s: @ 5.0 MHz operation with main system
clock) to ultra-low speed (122
µ
s: @ 32.768 kHz operation with subsystem clock)
●●Instruction set suited to system control
• Bit manipulation possible in all address spaces
• Multiply and divide instructions
●●Fifty-seven I/O ports (including alternate-function pins for segment signal output)
●●LCD controller/driver
• Segment signal output: Max. 40
• Common signal output: Max. 4
• Bias: 1/2, 1/3 bias switching possible
• Power supply voltage: VDD = 2.0 to 5.5 V (can operate in all modes)
●●8-bit resolution A/D converter: 8 channels
●●Serial interface: 3 channels
• 3-wire serial I/O/SBI/2-wire serial I/O mode: 1 channel
• 3-wire serial I/O/UART mode: 1 channel
• 3-wire serial I/O mode: 1 channel
●●Timer: 5 channels
• 16-bit timer/event counter: 1 channel
• 8-bit timer/event counter: 2 channels
• Watch timer: 1 channel
• Watchdog timer: 1 channel
●●Twenty-one vectored interrupt sources
●●Two test inputs
●●Two types of on-chip clock oscillators (main system clock and subsystem clock)
●●Power supply voltage: VDD = 2.0 to 5.5 V
Program Memory
(ROM)
Part Number
Type
1024 bytes
48 KB
60 KB
60 KBNote
Internal High-Speed RAM Internal Expansion RAM LCD RAM
1024 bytes 40 × 4 bits
µ
PD780306
µ
PD780308
µ
PD78P0308
Data Memory
19
CHAPTER 1 OUTLINE (
µ
PD780308 SUBSERIES)
User’s Manual U11377EJ3V0UD
1.2 Applications
Cellular phones, CD players, cameras, meters, etc.
1.3 Ordering Information
Part Number Package Internal ROM
µ
PD780306GC-×××-8EU 100-pin plastic LQFP (Fine pitch) (14 × 14) Mask ROM
µ
PD780306GC-×××-8EU-A 100-pin plastic LQFP (Fine pitch) (14 × 14) Mask ROM
µ
PD780306GF-×××-3BA 100-pin plastic QFP (14 × 20) Mask ROM
µ
PD780306GF-×××-3BA-A 100-pin plastic QFP (14 × 20) Mask ROM
µ
PD780308GC-×××-8EU 100-pin plastic LQFP (Fine pitch) (14 × 14) Mask ROM
µ
PD780308GC-×××-8EU-A 100-pin plastic LQFP (Fine pitch) (14 × 14) Mask ROM
µ
PD780308GF-×××-3BA 100-pin plastic QFP (14 × 20) Mask ROM
µ
PD780308GF-×××-3BA-A 100-pin plastic QFP (14 × 20) Mask ROM
µ
PD780306GF(A)-×××-3BA 100-pin plastic QFP (14 × 20) Mask ROM
µ
PD780308GF(A)-×××-3BA 100-pin plastic QFP (14 × 20) Mask ROM
µ
PD78P0308GC-8EU 100-pin plastic LQFP (Fine pitch) (14 × 14) One-time PROM
µ
PD78P0308GC-8EU-A 100-pin plastic LQFP (Fine pitch) (14 × 14) One-time PROM
µ
PD78P0308GF-3BA 100-pin plastic QFP (14 × 20) One-time PROM
µ
PD78P0308GF-3BA-A 100-pin plastic QFP (14 × 20) One-time PROM
Remarks 1. ××× indicates ROM code suffix.
2. Products with -A at the end of the part number are lead-free products.
20
CHAPTER 1 OUTLINE (
µ
PD780308 SUBSERIES)
User’s Manual U11377EJ3V0UD
1.4 Quality Grade
Part Number Package Quality Grade
µ
PD780306GC-×××-8EU 100-pin plastic LQFP (Fine pitch) (14 × 14) Standard
µ
PD780306GC-×××-8EU-A 100-pin plastic LQFP (Fine pitch) (14 × 14) Standard
µ
PD780306GF-×××-3BA 100-pin plastic QFP (14 × 20) Standard
µ
PD780306GF-×××-3BA-A 100-pin plastic QFP (14 × 20) Standard
µ
PD780308GC-×××-8EU 100-pin plastic LQFP (Fine pitch) (14 × 14) Standard
µ
PD780308GC-×××-8EU-A 100-pin plastic LQFP (Fine pitch) (14 × 14) Standard
µ
PD780308GF-×××-3BA 100-pin plastic QFP (14 × 20) Standard
µ
PD780308GF-×××-3BA-A 100-pin plastic QFP (14 × 20) Standard
µ
PD780306GF(A)-×××-3BA 100-pin plastic QFP (14 × 20) Special
µ
PD780308GF(A)-×××-3BA 100-pin plastic QFP (14 × 20) Special
µ
PD78P0308GC-8EU 100-pin plastic LQFP (Fine pitch) (14 × 14) Standard
µ
PD78P0308GC-8EU-A 100-pin plastic LQFP (Fine pitch) (14 × 14) Standard
µ
PD78P0308GF-3BA 100-pin plastic QFP (14 × 20) Standard
µ
PD78P0308GF-3BA-A 100-pin plastic QFP (14 × 20) Standard
Remarks 1. ××× indicates ROM code suffix.
2. Products with -A at the end of the part number are lead-free products.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Electronics Corporation to know the specification of the quality grade on the device and its
recommended applications.
21
CHAPTER 1 OUTLINE (
µ
PD780308 SUBSERIES)
User’s Manual U11377EJ3V0UD
1.5 Pin Configuration (Top View)
(1) Normal operating mode
100-pin plastic LQFP (Fine pitch) (14 × 14)
Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1.
2. Connect the AVSS pin to VSS0.
Remarks 1. Pin connection in parentheses is intended for the
µ
PD78P0308.
2. When using the
µ
PD780308 Subseries in an application field where the noise generated from
the microcontroller must be reduced, it is recommended to take noise reduction measures by
supplying separate power to VDD0 and VDD1, and connecting VSS0 and VSS1 to separate ground
lines.
75
74
73
72
71
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
70
1
2
3
4
5
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
6
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
P70/SI2/RxD
P27/SCK0
P26/SO0/SB1
P25/SI0/SB0
P80/S39
P82/S37
P83/S36
P84/S35
P85/S34
P86/S33
P87/S32
P90/S31
P91/S30
P92/S29
P93/S28
P94/S27
P95/S26
P96/S25
P97/S24
S23
S22
S21
P81/S38
S20
S19
P11/ANI1
P12/ANI2
P13/ANI3
P14/ANI4
P15/ANI5
P17/ANI7
V
DD0
AV
REF
P100
P101
V
SS1
P102
P103
P30/TO0
P31/TO1
P32/TO2
P33/TI1
P34/TI2
P35/PCL
P36/BUZ
P37
COM0
P16/ANI6
COM1
COM2
P10/ANI0
AV
SS
P117
P116
P115
P114/RxD
P113/TxD
P112/SCK3
P111/SO3
P110/SI3
P05/INTP5
P04/INTP4
P03/INTP3
P02/INTP2
P01/INTP1/TI01
P00/INTP0/TI00
RESET
XT2
XT1/P07
V
DD1
X1
X2
IC (V
PP
)
P72/SCK2/ASCK
P71/SO2/TxD
COM3
BIAS
V
LC0
V
LC1
V
LC2
V
SS0
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
22
CHAPTER 1 OUTLINE (
µ
PD780308 SUBSERIES)
User’s Manual U11377EJ3V0UD
100-pin plastic QFP (14 × 20)
Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1.
2. Connect the AVSS pin to VSS0.
Remarks 1. Pin connection in parentheses is intended for the
µ
PD78P0308.
2. When using the
µ
PD780308 Subseries in an application field where the noise generated from
the microcontroller must be reduced, it is recommended to take noise reduction measures by
supplying separate power to VDD0 and VDD1, and connecting VSS0 and VSS1 to separate ground
lines.
31 32 35 3633 34 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 96 9598 97 94 93 9291 90 89 88 87 86 85 84 83 82 81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P26/SO0/SB1
P27/SCK0
P70/SI2/RxD
P72/SCK2/ASCK
IC (V
PP
)
X2
X1
V
DD1
XT1/P07
XT2
RESET
P00/INTP0/TI00
P02/INTP2
P03/INTP3
P04/INTP4
P05/INTP5
P110/SI3
P111/SO3
P112/SCK3
P113/TxD
P114/RxD
P115
P116
P117
AV
SS
P10/ANI0
P11/ANI1
P12/ANI2
P01/INTP1/TI01
P71/SO2/TxD
P25/SI0/SB0
P80/S39
P81/S38
P82/S37
P83/S36
P84/S35
P85/S34
P86/S33
P87/S32
P90/S31
P91/S30
P92/S29
P93/S28
P94/S27
P95/S26
P96/S25
P97/S24
S23
S22
S21
S20
S19
S18
S16
S15
S14
S13
S12
S11
S10
S9
S8
S6
S5
S4
S3
S2
S1
S0
V
SS0
V
LC2
V
LC1
V
LC0
BIAS
COM3
COM2
COM1
COM0
S7
S17
P13/ANI3
P14/ANI4
P15/ANI5
P16/ANI6
P17/ANI7
V
DD0
AV
REF
P100
P101
V
SS1
P102
P103
P30/TO0
P31/TO1
P32/TO2
P33/TI1
P34/TI2
P35/PCL
P36/BUZ
P37
23
CHAPTER 1 OUTLINE (
µ
PD780308 SUBSERIES)
User’s Manual U11377EJ3V0UD
ANI0 to ANI7: Analog input PCL: Programmable clock
ASCK: Asynchronous serial clock RESET: Reset
AVREF: Analog reference voltage RxD: Receive data
AVSS: Analog ground S0 to S39: Segment output
BIAS: LCD power supply bias control SB0, SB1: Serial bus
BUZ: Buzzer clock SCK0, SCK2, SCK3: Serial clock
COM0 to COM3: Common output SI0, SI2, SI3: Serial input
INTP0 to INTP5: Interrupt from peripherals SO0, SO2, SO3: Serial output
IC: Internally connected TI00, TI01: Timer input
P00 to P05, P07: Port 0 TI1, TI2: Timer input
P10 to P17: Port 1 TO0 to TO2: Timer output
P25 to P27: Port 2 TxD: Transmit data
P30 to P37: Port 3 VDD0, VDD1: Power supply
P70 to P72: Port 7 VLC0 to VLC2: LCD power supply
P80 to P87: Port 8 VPP: Programming power supply
P90 to P97: Port 9 VSS0, VSS1: Ground
P100 to P103: Port 10 X1, X2: Crystal (main system clock)
P110 to P117: Port 11 XT1, XT2: Crystal (subsystem clock)
24
CHAPTER 1 OUTLINE (
µ
PD780308 SUBSERIES)
User’s Manual U11377EJ3V0UD
(2) PROM programming mode
100-pin plastic LQFP (Fine pitch) (14 × 14)
Cautions 1. (L): Independently connect to VSS via a pull-down resistor.
2. VSS: Connect to the ground.
3. RESET: Set to the low level.
4. Open: Do not connect anything.
(L)
(L)
(L)
(L)
CE
OE
A9
RESET
Open
V
DD
PGM
V
PP
Open
A0
A1
A2
A3
A4
A5
A6
A7
A8
A16
A10
A11
A12
A13
A14
A15
75
74
73
72
71
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
70
1
2
3
4
5
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
6
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
(L)
V
DD
V
DD
D0
D1
V
SS
D2
D3
D4
D5
D6
D7
(L)
(L)
(L)
(L)
(L)
(L)
(L)
(L)
25
CHAPTER 1 OUTLINE (
µ
PD780308 SUBSERIES)
User’s Manual U11377EJ3V0UD
100-pin plastic QFP (14 × 20)
Cautions 1. (L): Independently connect to VSS via a pull-down resistor.
2. VSS: Connect to the ground.
3. RESET: Set to the low level.
4. Open: Do not connect anything.
A0 to A16: Address bus RESET: Reset
CE: Chip enable VDD: Power supply
D0 to D7: Data bus VPP: Programming power supply
OE: Output enable VSS: Ground
PGM: Program
(L)
A0
A1
A2
A3
A4
A5
A6
A7
A8
A16
A10
A11
A12
A13
A14
A15
(L)
V
PP
Open
V
DD
Open
RESET
A9
PGM
OE
CE
V
SS
V
DD
V
DD
D0
D1
D3
D2
D4
D5
D6
D7
31 32 35 3633 34 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 96 9598 97 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
(L)
(L)
(L)
(L)
(L)
(L)
(L)
(L)
(L)
(L)
26
CHAPTER 1 OUTLINE (
µ
PD780308 SUBSERIES)
User’s Manual U11377EJ3V0UD
1.6 78K0 Series Lineup
The products in the 78K0 Series are listed below. The names enclosed in boxes are subseries name.
PD78083
PD78018F PD78018FY
PD78014H EMI-noise reduced version of the PD78018F
Basic subseries for control
On-chip UART, capable of operating at low voltage (1.8 V)
µ
µ
µ
µ
42/44-pin
64-pin
64-pin
52-pin 52-pin version of the PD780024A
µ
µ
PD780024AS
µ
52-pin 52-pin version of the PD780034A
PD780034AS
PD78054 with IEBus
TM
controller
PD78054 with enhanced serial I/O
PD78078Y with enhanced serial I/O and limited functions
PD78054 with timer and enhanced external interface
64-pin
64-pin
80-pin
80-pin
80-pin EMI-noise reduced version of the PD78054
PD78018F with UART and D/A converter, and enhanced I/O
PD780034A
PD780988
PD780034AY
µ
µ
µ
64-pin
PD780024A with expanded RAM
PD780024A with enhanced A/D converter
µ
µ
µ
µ
On-chip inverter controller and UART. EMI-noise reduced.
PD78064
PD78064B
PD780308
100-pin
100-pin
100-pin PD780308Y
PD78064Y
80-pin
78K0
Series
LCD drive
PD78064 with enhanced SIO, and expanded ROM and RAM
EMI-noise reduced version of the PD78064
Basic subseries for driving LCDs, on-chip UART
Bus interface supported
µ
µµ
µ
µ
µ
µ
µ
µ
PD78018F with enhanced serial I/O
µ
µ
80-pin
100-pin
100-pin
Products in mass production Products under development
Y subseries products are compatible with I2C bus.
ROMless version of the PD78078
µ
100-pin
µ
µ
100-pin EMI-noise reduced version of the PD78078
µ
Inverter control
PD780208100-pin
VFD drive
PD78044F with enhanced I/O and VFD C/D. Display output total: 53
µ
µ
PD78098B
µ
100-pin
PD780024A PD780024AY
µµ
µ
80-pin
80-pin PD780852
PD780828B
µ
µ
For automobile meter driver. On-chip CAN controller
100-pin PD780958
µ
For industrial meter control
On-chip automobile meter controller/driver
Meter control
80-pin On-chip IEBus controller
80-pin
On-chip controller compliant with J1850 (Class 2)
PD780833Y
µ
PD780948 On-chip CAN controller
µ
64-pin PD780078 PD780078Y
µµ
PD780034A with timer and enhanced serial I/O
PD78054 PD78054Y
PD78058F PD78058FY
µ
µ
µ
µ
PD780058 PD780058Y
µµ
PD78070A PD78070AY
PD78078 PD78078Y
PD780018AY
µ
µ
µ
µ
µ
Control
PD78075B
µ
PD780065
µ
µ
PD78044H
PD780232
80-pin
80-pin For panel control. On-chip VFD C/D. Display output total: 53
PD78044F with N-ch open-drain I/O. Display output total: 34
µ
µ
PD78044F
80-pin Basic subseries for driving VFD. Display output total: 34
µ
µ
120-pin
PD780308 with enhanced display function and timer. Segment signal output: 40 pins max.
PD780318
PD780328
120-pin
120-pin
PD780308 with enhanced display function and timer. Segment signal output: 32 pins max.
PD780308 with enhanced display function and timer. Segment signal output: 24 pins max.
µ
µ
PD780338
µ
µ
PD780308 with enhanced display function and timer. Segment signal output: 40 pins max.
µ
µ
µ
On-chip CAN controller
Specialized for CAN controller function
80-pin
PD780703AY
µ
PD780702Y
µ
64-pin PD780816
µ
PD780344 with enhanced A/D converter
100-pin
100-pin
µ
PD780344 PD780344Y
PD780354 PD780354Y
µ
µ
µ
µ
<R>
Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some
documents, but the functions of the two are the same.
27
CHAPTER 1 OUTLINE (
µ
PD780308 SUBSERIES)
User’s Manual U11377EJ3V0UD
The major functional differences between the subseries are shown below.
• Subseries without the suffix Y
Function ROM Timer 8-bit 10-bit 8-bit Serial Interface I/O
External
Subseries Name Capacity 8-bit 16-bit Watch WDT A/D A/D D/A
Expansion
Control
µ
PD78075B
32 KB to 40 KB
4 ch 1 ch 1 ch 1 ch 8 ch – 2 ch 3 ch (UART: 1 ch) 88 1.8 V Yes
µ
PD78078
48 KB to 60 KB
µ
PD78070A – 61 2.7 V
µ
PD780058
24 KB to 60 KB
2 ch
3 ch (time-division UART: 1 ch)
68 1.8 V
µ
PD78058F
48 KB to 60 KB
3 ch (UART: 1 ch) 69 2.7 V
µ
PD78054
16 KB to 60 KB
2.0 V
µ
PD780065
40 KB to 48 KB
– 4 ch (UART: 1 ch) 60 2.7 V
µ
PD780078
48 KB to 60 KB
2 ch – 8 ch 3 ch (UART: 2 ch) 52 1.8 V
µ
PD780034A
8 KB to 32 KB
1 ch 3 ch (UART: 1 ch) 51
µ
PD780024A
8 ch –
µ
PD780034AS
–4 ch 39 –
µ
PD780024AS
4 ch –
µ
PD78014H 8 ch 2 ch 53 Yes
µ
PD78018F
8 KB to 60 KB
µ
PD78083
8 KB to 16 KB
– – 1 ch (UART: 1 ch) 33 –
Inverter
µ
PD780988
16 KB to 60 KB
3 ch Note – 1 ch – 8 ch – 3 ch (UART: 2 ch) 47 4.0 V Yes
control
VFD
µ
PD780208
32 KB to 60 KB
2 ch 1 ch 1 ch 1 ch 8 ch – – 2 ch 74 2.7 V –
drive
µ
PD780232
16 KB to 24 KB
3 ch – – 4 ch 40 4.5 V
µ
PD78044H
32 KB to 48 KB
2 ch 1 ch 1 ch 8 ch 1 ch 68 2.7 V
µ
PD78044F
16 KB to 40 KB
2 ch
LCD
µ
PD780354
24 KB to 32 KB
4 ch 1 ch 1 ch 1 ch – 8 ch – 3 ch (UART: 1 ch) 66 1.8 V –
drive
µ
PD780344 8 ch –
µ
PD780338
48 KB to 60 KB
3 ch 2 ch – 10 ch 1 ch 2 ch (UART: 1 ch) 54
µ
PD780328 62
µ
PD780318 70
µ
PD780308
48 KB to 60 KB
2 ch 1 ch 8 ch – –
3 ch (time-division UART: 1 ch)
57 2.0 V
µ
PD78064B 32 KB 2 ch (UART: 1 ch)
µ
PD78064
16 KB to 32 KB
Bus
µ
PD780948 60 KB 2 ch 2 ch 1 ch 1 ch 8 ch – – 3 ch (UART: 1 ch) 79 4.0 V Yes
interface
µ
PD78098B
40 KB to 60 KB
1 ch 2 ch 69 2.7 V –
supported
µ
PD780816
32 KB to 60 KB
2 ch 12 ch – 2 ch (UART: 1 ch) 46 4.0 V
Meter control
µ
PD780958
48 KB to 60 KB
4 ch 2 ch – 1 ch – – – 2 ch (UART: 1 ch) 69 2.2 V –
Dashboard
µ
PD780852
32 KB to 40 KB
3 ch 1 ch 1 ch 1 ch 5 ch – – 3 ch (UART: 1 ch) 56 4.0 V –
control
µ
PD780828B
32 KB to 60 KB
59
Note 16-bit timer: 2 channels
10-bit timer: 1 channel
VDD
MIN.
Value
28
CHAPTER 1 OUTLINE (
µ
PD780308 SUBSERIES)
User’s Manual U11377EJ3V0UD
1.7 Block Diagram
Remarks 1. The internal ROM capacity differs depending on the product.
2. Pin connection in parentheses is intended for the
µ
PD78P0308.
TO0/P30
TI00/INTP0/P00
TI01/INTP1/P01
TO1/P31
TI1/P33
TO2/P32
TI2/P34
SI0/SB0/P25
SO0/SB1/P26
SCK0/P27
SI3/P110
SO3/P111
SCK3/P112
AV
SS
AV
REF
INTP0/P00 to
INTP5/P05
BUZ/P36
PCL/P35
16-bit timer/
event counter
8-bit timer/
event counter 1
8-bit timer/
event counter 2
Watchdog timer
Watch timer
Serial
interface 0
Serial
interface 3
A/D converter
Interrupt
control
Buzzer output
Clock output
control
78K/0
CPU core
ROM
RAM
V
DD0,
V
DD1
V
SS0,
V
SS1
IC
(V
PP
)
Port 0
Port 1
Port 2
Port 3
Port 7
Port 8
Port 9
Port 10
Port 11
P00
P01 to P05
P07
P10 to P17
P25 to P27
P30 to P37
P70 to P72
P80 to P87
P90 to P97
P100 to P103
P110 to P117
S0 to S23
S24/P97 to
S31/P90
S32/P87 to
S39/P80
COM0 to COM3
V
LC0
to V
LC2
BIAS
f
LCD
RESET
X1
X2
XT1/P07
XT2
LCD
controller/
driver
System
control
Serial
interface 2
RxD/P114
TxD/P113
SCK2/ASCK/P72
SI2/RxD/P70
SO2/TxD/P71
ANI0/P10 to
ANI7/P17
29
CHAPTER 1 OUTLINE (
µ
PD780308 SUBSERIES)
User’s Manual U11377EJ3V0UD
1.8 Outline of Function
ROM
Mask ROM PROM
48 KB 60 KB 60 KBNote
High-speed RAM 1024 bytes
Expansion RAM 1024 bytes
LCD RAM 40 × 4 bits
General-purpose register 8 bits × 8 × 4 banks
With main system clock selected 0.4
µ
s/0.8
µ
s/1.6
µ
s/3.2
µ
s/6.4
µ
s/12.8
µ
s (@ 5.0 MHz)
With subsystem clock selected 122
µ
s (@ 32.768 kHz)
Instruction set • 16-bit operation
• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulate (set, reset, test, and Boolean operation)
• BCD adjust, etc.
I/O port (including alternate-function pins • Total: 57
for segment signal output) • CMOS input: 2
• CMOS I/O: 55
A/D converter 8-bit resolution × 8 channels
LCD controller/driver • Segment signal output: Max. 40
• Common signal output: Max. 4
• Bias: 1/2, 1/3 bias switching possible
Serial interface • 3-wire serial I/O/SBI/2-wire serial I/O mode selection possible: 1 channel
• 3-wire serial I/O mode/UART mode selection possible: 1 channel
• 3-wire serial I/O mode: 1 channel
Timer • 16-bit timer/event counter: 1 channel
• 8-bit timer/event counter: 2 channels
• Watch timer: 1 channel
• Watchdog timer: 1 channel
Timer output Three outputs (14-bit PWM output enable: 1)
Clock output 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz,
2.5 MHz, 5.0 MHz (@ 5.0 MHz with main system clock)
32.768 kHz (@ 32.768 kHz with subsystem clock)
Buzzer output 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (@ 5.0 MHz with main system clock)
Note The capacity of the internal PROM can be changed using the internal memory size switching register (IMS).
Item
Part Number
Internal
memory
µ
PD780306
µ
PD780308
µ
PD78P0308
Minimum
instruction
execution
time
30
CHAPTER 1 OUTLINE (
µ
PD780308 SUBSERIES)
User’s Manual U11377EJ3V0UD
Vectored Maskable Internal: 13
interrupt External: 6
source Non-maskable Internal: 1
Software 1
Test input Internal: 1
External: 1
Power supply voltage VDD = 2.0 to 5.5 V
Operating ambient temperature TA = –40 to +85°C
Package • 100-pin plastic LQFP (Fine pitch) (14 × 14)
• 100-pin plastic QFP (14 × 20)
1.9 Mask Options
The mask ROM versions (
µ
PD780306, 780308) provide mask options. By specifying this mask option at the time
of ordering, split resistors which enable to generate LCD drive voltage suited to each bias method type can be
incorporated. Using this mask option reduces the number of components to add to the device, resulting in board space
saving.
The mask options provided in the
µ
PD780308 Subseries are shown in Table 1-1.
Table 1-1. Mask Options of Mask ROM Versions
Pin Names Mask Options
VLC0 to VLC2 Split resistor can be incorporated.
Item
Part Number
µ
PD780306
µ
PD780308
µ
PD78P0308
31
User’s Manual U11377EJ3V0UD
CHAPTER 2 OUTLINE (
µ
PD780308Y SUBSERIES)
2.1 Features
●●On-chip high-capacity ROM and RAM
Note The capacity of internal PROM can be changed by means of the internal memory size switching register
(IMS).
●●Minimum instruction execution time changeable from high speed (0.4
µ
s: @ 5.0 MHz operation with main system
clock) to ultra-low speed (122
µ
s: @ 32.768 kHz operation with subsystem clock)
●●Instruction set suited to system control
• Bit manipulation possible in all address spaces
• Multiply and divide instructions
●●Fifty-seven I/O ports (including alternate-function pins for segment signal output)
●●LCD controller/driver
• Segment signal output: Max. 40
• Common signal output: Max. 4
• Bias: 1/2, 1/3 bias switching possible
• Power supply voltage: VDD = 2.0 to 5.5 V (can operate in all modes)
●●8-bit resolution A/D converter: 8 channels
●●Serial interface: 3 channels
• 3-wire serial I/O/2-wire serial I/O/I2C bus mode: 1 channel
• 3-wire serial I/O/UART mode: 1 channel
• 3-wire serial I/O mode: 1 channel
●●Timer: 5 channels
• 16-bit timer/event counter: 1 channel
• 8-bit timer/event counter: 2 channels
• Watch timer: 1 channel
• Watchdog timer: 1 channel
●●Twenty-one vectored interrupt sources
●●Two test inputs
●●Two types of on-chip clock oscillators (main system clock and subsystem clock)
●●Power supply voltage: VDD = 2.0 to 5.5 V
Program Memory
(ROM)
Part Number
Type
1024 bytes
48 KB
60 KB
60 KB
Note
Internal High-Speed RAM Internal Expansion RAM LCD RAM
1024 bytes 40 × 4 bits
µ
PD780306Y
µ
PD780308Y
µ
PD78P0308Y
Data Memory
32
CHAPTER 2 OUTLINE (
µ
PD780308Y SUBSERIES)
User’s Manual U11377EJ3V0UD
2.2 Applications
Cellular phones, CD players, cameras, meters, audio equipment, etc.
2.3 Ordering Information
Part Number Package Internal ROM
µ
PD780306YGC-×××-8EU 100-pin plastic LQFP (Fine pitch) (14 × 14) Mask ROM
µ
PD780306YGC-×××-8EU-A 100-pin plastic LQFP (Fine pitch) (14 × 14) Mask ROM
µ
PD780306YGF-×××-3BA 100-pin plastic QFP (14 × 20) Mask ROM
µ
PD780306YGF-×××-3BA-A 100-pin plastic QFP (14 × 20) Mask ROM
µ
PD780308YGC-×××-8EU 100-pin plastic LQFP (Fine pitch) (14 × 14) Mask ROM
µ
PD780308YGC-×××-8EU-A 100-pin plastic LQFP (Fine pitch) (14 × 14) Mask ROM
µ
PD780308YGF-×××-3BA 100-pin plastic QFP (14 × 20) Mask ROM
µ
PD780308YGF-×××-3BA-A 100-pin plastic QFP (14 × 20) Mask ROM
µ
PD78P0308YGC-8EU 100-pin plastic LQFP (Fine pitch) (14 × 14) One-time PROM
µ
PD78P0308YGC-8EU-A 100-pin plastic LQFP (Fine pitch) (14 × 14) One-time PROM
µ
PD78P0308YGF-3BA 100-pin plastic QFP (14 × 20) One-time PROM
µ
PD78P0308YGF-3BA-A 100-pin plastic QFP (14 × 20) One-time PROM
Remarks 1. ××× indicates ROM code suffix.
2. Products with -A at the end of the part number are lead-free products.
2.4 Quality Grade
Part Number Package Quality Grade
µ
PD780306YGC-×××-8EU 100-pin plastic LQFP (Fine pitch) (14 × 14) Standard
µ
PD780306YGC-×××-8EU-A 100-pin plastic LQFP (Fine pitch) (14 × 14) Standard
µ
PD780306YGF-×××-3BA 100-pin plastic QFP (14 × 20) Standard
µ
PD780306YGF-×××-3BA-A 100-pin plastic QFP (14 × 20) Standard
µ
PD780308YGC-×××-8EU 100-pin plastic LQFP (Fine pitch) (14 × 14) Standard
µ
PD780308YGC-×××-8EU-A 100-pin plastic LQFP (Fine pitch) (14 × 14) Standard
µ
PD780308YGF-×××-3BA 100-pin plastic QFP (14 × 20) Standard
µ
PD780308YGF-×××-3BA-A 100-pin plastic QFP (14 × 20) Standard
µ
PD78P0308YGC-8EU 100-pin plastic LQFP (Fine pitch) (14 × 14) Standard
µ
PD78P0308YGC-8EU-A 100-pin plastic LQFP (Fine pitch) (14 × 14) Standard
µ
PD78P0308YGF-3BA 100-pin plastic QFP (14 × 20) Standard
µ
PD78P0308YGF-3BA-A 100-pin plastic QFP (14 × 20) Standard
Remarks 1. ××× indicates ROM code suffix.
2. Products with -A at the end of the part number are lead-free products.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Electronics Corporation to know the specification of the quality grade on the device and its
recommended applications.
33
CHAPTER 2 OUTLINE (
µ
PD780308Y SUBSERIES)
User’s Manual U11377EJ3V0UD
2.5 Pin Configuration (Top View)
(1) Normal operating mode
100-pin plastic LQFP (Fine pitch) (14 × 14)
Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1.
2. Connect the AVSS pin to VSS0.
Remarks 1. Pin connection in parentheses is intended for the
µ
PD78P0308Y.
2. When using the
µ
PD780308Y Subseries in an application field where the noise generated from
the microcontroller must be reduced, it is recommended to take noise reduction measures by
supplying separate power to VDD0 and VDD1, and connecting VSS0 and VSS1 to separate ground
lines.
75
74
73
72
71
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
70
1
2
3
4
5
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
6
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
P70/SI2/RxD
P27/SCK0/SCL
P26/SO0/SB1/SDA1
P25/SI0/SB0/SDA0
P80/S39
P82/S37
P83/S36
P84/S35
P85/S34
P86/S33
P87/S32
P90/S31
P91/S30
P92/S29
P93/S28
P94/S27
P95/S26
P96/S25
P97/S24
S23
S22
S21
P81/S38
S20
S19
P11/ANI1
P12/ANI2
P13/ANI3
P14/ANI4
P15/ANI5
P17/ANI7
VDD0
AVREF
P100
P101
VSS1
P102
P103
P30/TO0
P31/TO1
P32/TO2
P33/TI1
P34/TI2
P35/PCL
P36/BUZ
P37
COM0
P16/ANI6
COM1
COM2
P10/ANI0
AVSS
P117
P116
P115
P114/RxD
P113/TxD
P112/SCK3
P111/SO3
P110/SI3
P05/INTP5
P04/INTP4
P03/INTP3
P02/INTP2
P01/INTP1/TI01
P00/INTP0/TI00
RESET
XT2
XT1/P07
VDD1
X1
X2
IC (VPP)
P72/SCK2/ASCK
P71/SO2/TxD
COM3
BIAS
VLC0
VLC1
VLC2
VSS0
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
34
CHAPTER 2 OUTLINE (
µ
PD780308Y SUBSERIES)
User’s Manual U11377EJ3V0UD
100-pin plastic QFP (14 × 20)
Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1.
2. Connect the AVSS pin to VSS0.
Remarks 1. Pin connection in parentheses is intended for the
µ
PD78P0308Y.
2. When using the
µ
PD780308Y Subseries in an application field where the noise generated from
the microcontroller must be reduced, it is recommended to take noise reduction measures by
supplying separate power to VDD0 and VDD1, and connecting VSS0 and VSS1 to separate ground
lines.
31 32 35 3633 34 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 96 9598 97 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P26/SO0/SB1/SDA1
P27/SCK0/SCL
P70/SI2/RxD
P72/SCK2/ASCK
IC (V
PP
)
X2
X1
V
DD1
XT1/P07
XT2
RESET
P00/INTP0/TI00
P02/INTP2
P03/INTP3
P04/INTP4
P05/INTP5
P110/SI3
P111/SO3
P112/SCK3
P113/TxD
P114/RxD
P115
P116
P117
AV
SS
P10/ANI0
P11/ANI1
P12/ANI2
P01/INTP1/TI01
P71/SO2/TxD
P25/SI0/SB0/SDA
0
P80/S39
P81/S38
P82/S37
P83/S36
P84/S35
P85/S34
P86/S33
P87/S32
P90/S31
P91/S30
P92/S29
P93/S28
P94/S27
P95/S26
P96/S25
P97/S24
S23
S22
S21
S20
S19
S18
S16
S15
S14
S13
S12
S11
S10
S9
S8
S6
S5
S4
S3
S2
S1
S0
V
SS0
V
LC2
V
LC1
V
LC0
BIAS
COM3
COM2
COM1
COM0
S7
S17
P13/ANI3
P14/ANI4
P15/ANI5
P16/ANI6
P17/ANI7
V
DD0
AV
REF
P100
P101
V
SS1
P102
P103
P30/TO0
P31/TO1
P32/TO2
P33/TI1
P34/TI2
P35/PCL
P36/BUZ
P37
35
CHAPTER 2 OUTLINE (
µ
PD780308Y SUBSERIES)
User’s Manual U11377EJ3V0UD
ANI0 to ANI7: Analog input RESET: Reset
ASCK: Asynchronous serial clock RxD: Receive data
AVREF: Analog reference voltage S0 to S39: Segment output
AVSS: Analog ground SB0, SB1: Serial bus
BIAS: LCD power supply bias control SCK0, SCK2, SCK3: Serial clock
BUZ: Buzzer clock SCL: Serial clock
COM0 to COM3: Common output SDA0, SDA1: Serial data
INTP0 to INTP5: Interrupt from peripherals SI0, SI2, SI3: Serial input
IC: Internally connected SO0, SO2, SO3: Serial output
P00 to P05, P07: Port 0 TI00, TI01: Timer input
P10 to P17: Port 1 TI1, TI2: Timer input
P25 to P27: Port 2 TO0 to TO2: Timer output
P30 to P37: Port 3 TxD: Transmit data
P70 to P72: Port 7 VDD0, VDD1: Power supply
P80 to P87: Port 8 VLC0 to VLC2: LCD power supply
P90 to P97: Port 9 VPP: Programming power supply
P100 to P103: Port 10 VSS0, VSS1: Ground
P110 to P117: Port 11 X1, X2: Crystal (main system clock)
PCL: Programmable clock XT1, XT2: Crystal (subsystem clock)
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(2) PROM programming mode
100-pin plastic LQFP (Fine pitch) (14 × 14)
Cautions 1. (L): Independently connect to VSS via a pull-down resistor.
2. VSS: Connect to the ground.
3. RESET: Set to the low level.
4. Open: Do not connect anything.
(L)
(L)
(L)
(L)
CE
OE
A9
RESET
Open
V
DD
PGM
V
PP
Open
A0
A1
A2
A3
A4
A5
A6
A7
A8
A16
A10
A11
A12
A13
A14
A15
75
74
73
72
71
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
70
1
2
3
4
5
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
6
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
(L)
V
DD
V
DD
D0
D1
V
SS
D2
D3
D4
D5
D6
D7
(L)
(L)
(L)
(L)
(L)
(L)
(L)
(L)
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User’s Manual U11377EJ3V0UD
100-pin plastic QFP (14 × 20)
Cautions 1. (L): Independently connect to VSS via a pull-down resistor.
2. VSS: Connect to the ground.
3. RESET: Set to the low level.
4. Open: Do not connect anything.
A0 to A16: Address bus RESET: Reset
CE: Chip enable VDD: Power supply
D0 to D7: Data bus VPP: Programming power supply
OE: Output enable VSS: Ground
PGM: Program
(L)
A0
A1
A2
A3
A4
A5
A6
A7
A8
A16
A10
A11
A12
A13
A14
A15
(L)
VPP
Open
VDD
Open
RESET
A9
PGM
OE
CE
VSS
VDD
VDD
D0
D1
D3
D2
D4
D5
D6
D7
31 32 35 3633 34 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 96 9598 97 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
(L)
(L)
(L)
(L)
(L)
(L)
(L)
(L)
(L)
(L)
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2.6 78K0 Series Lineup
The products in the 78K0 Series are listed below. The names enclosed in boxes are subseries name.
PD78083
PD78018F PD78018FY
PD78014H EMI-noise reduced version of the PD78018F
Basic subseries for control
On-chip UART, capable of operating at low voltage (1.8 V)
µ
µ
µ
µ
42/44-pin
64-pin
64-pin
52-pin 52-pin version of the PD780024A
µ
µ
PD780024AS
µ
52-pin 52-pin version of the PD780034A
PD780034AS
PD78054 with IEBus
TM
controller
PD78054 with enhanced serial I/O
PD78078Y with enhanced serial I/O and limited functions
PD78054 with timer and enhanced external interface
64-pin
64-pin
80-pin
80-pin
80-pin EMI-noise reduced version of the PD78054
PD78018F with UART and D/A converter, and enhanced I/O
PD780034A
PD780988
PD780034AY
µ
µ
µ
64-pin
PD780024A with expanded RAM
PD780024A with enhanced A/D converter
µ
µ
µ
µ
On-chip inverter controller and UART. EMI-noise reduced.
PD78064
PD78064B
PD780308
100-pin
100-pin
100-pin PD780308Y
PD78064Y
80-pin
78K0
Series
LCD drive
PD78064 with enhanced SIO, and expanded ROM and RAM
EMI-noise reduced version of the PD78064
Basic subseries for driving LCDs, on-chip UART
Bus interface supported
µ
µµ
µ
µ
µ
µ
µ
µ
PD78018F with enhanced serial I/O
µ
µ
80-pin
100-pin
100-pin
Products in mass production Products under development
Y subseries products are compatible with I
2
C bus.
ROMless version of the PD78078
µ
100-pin
µ
µ
100-pin EMI-noise reduced version of the PD78078
µ
Inverter control
PD780208100-pin
VFD drive
PD78044F with enhanced I/O and VFD C/D. Display output total: 53
µ
µ
PD78098B
µ
100-pin
PD780024A PD780024AY
µµ
µ
80-pin
80-pin PD780852
PD780828B
µ
µ
For automobile meter driver. On-chip CAN controller
100-pin PD780958
µ
For industrial meter control
On-chip automobile meter controller/driver
Meter control
80-pin On-chip IEBus controller
80-pin
On-chip controller compliant with J1850 (Class 2)
PD780833Y
µ
PD780948 On-chip CAN controller
µ
64-pin PD780078 PD780078Y
µµ
PD780034A with timer and enhanced serial I/O
PD78054 PD78054Y
PD78058F PD78058FY
µ
µ
µ
µ
PD780058 PD780058Y
µµ
PD78070A PD78070AY
PD78078 PD78078Y
PD780018AY
µ
µ
µ
µ
µ
Control
PD78075B
µ
PD780065
µ
µ
PD78044H
PD780232
80-pin
80-pin For panel control. On-chip VFD C/D. Display output total: 53
PD78044F with N-ch open-drain I/O. Display output total: 34
µ
µ
PD78044F
80-pin Basic subseries for driving VFD. Display output total: 34
µ
µ
120-pin
PD780308 with enhanced display function and timer. Segment signal output: 40 pins max.
PD780318
PD780328
120-pin
120-pin
PD780308 with enhanced display function and timer. Segment signal output: 32 pins max.
PD780308 with enhanced display function and timer. Segment signal output: 24 pins max.
µ
µ
PD780338
µ
µ
PD780308 with enhanced display function and timer. Segment signal output: 40 pins max.
µ
µ
µ
On-chip CAN controller
Specialized for CAN controller function
80-pin
PD780703AY
µ
PD780702Y
µ
64-pin PD780816
µ
PD780344 with enhanced A/D converter
100-pin
100-pin
µ
PD780344 PD780344Y
PD780354 PD780354Y
µ
µ
µ
µ
<R>
Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some
documents, but the functions of the two are the same.
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CHAPTER 2 OUTLINE (
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The major functional differences between the subseries are shown below.
• Subseries with the suffix Y
Function ROM Timer 8-bit 10-bit 8-bit Serial Interface I/O VDD
External
Subseries Name Capacity 8-bit 16-bit
Watch
WDT A/D A/D D/A
MIN. Value Expansion
Control
µ
PD78078Y
48 KB to 60 KB
4 ch 1 ch 1 ch 1 ch 8 ch −2 ch 3 ch (UART: 1 ch, 88 1.8 V Yes
µ
PD78070AY −I2C: 1 ch) 61 2.7 V
µ
PD780018AY
48 KB to 60 KB
−3 ch (I2C: 1 ch) 88
µ
PD780058Y
24 KB to 60 KB
2 ch 2 ch 3 ch (time-division 68 1.8 V
UART: 1 ch, I
2
C: 1 ch)
µ
PD78058FY
48 KB to 60 KB
3 ch (UART: 1 ch, 69 2.7 V
µ
PD78054Y
16 KB to 60 KB
I2C: 1 ch) 2.0 V
µ
PD780078Y
48 KB to 60 KB
2 ch −8 ch −4 ch (UART: 2 ch, 52 1.8 V
I2C: 1 ch)
µ
PD780034AY
8 KB to 32 KB
1 ch 3 ch (UART: 1 ch, 51
µ
PD780024AY 8 ch −I2C: 1 ch)
µ
PD78018FY
8 KB to 60 KB
2 ch (I2C: 1 ch) 53
LCD
µ
PD780354Y
24 KB to 32 KB
4 ch 1 ch 1 ch 1 ch −8 ch −4 ch (UART: 1 ch, 66 1.8 V −
drive
µ
PD780344Y 8 ch −I2C: 1 ch)
µ
PD780308Y
48 KB to 60 KB
2 ch 3 ch (time-division 57 2.0 V
UART: 1 ch, I
2
C: 1 ch)
µ
PD78064Y
16 KB to 32 KB
2 ch (UART: 1 ch,
I2C: 1 ch)
Bus
µ
PD780702Y 60 KB 3 ch 2 ch 1 ch 1 ch 16 ch −−4 ch (UART: 1 ch, 67 3.5 V −
interface
µ
PD780703AY 59.5 KB I2C: 1 ch)
supported
µ
PD780833Y 60 KB 65 4.5 V
Remark The functions of the subseries without the suffix Y and the subseries with the suffix Y are the same, except
for the serial interface (if a subseries without the suffix Y is available).
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User’s Manual U11377EJ3V0UD
2.7 Block Diagram
Remarks 1. The internal ROM capacity differs depending on the product.
2. Pin connection in parentheses is intended for the
µ
PD78P0308Y.
TO0/P30
TI00/INTP0/P00
TI01/INTP1/P01
TO1/P31
TI1/P33
TO2/P32
TI2/P34
SDA0/SI0/SB0/P25
SDA1/SO0/SB1/P26
SCL/SCK0/P27
SI3/P110
SO3/P111
SCK3/P112
AV
SS
AV
REF
INTP0/P00 to
INTP5/P05
BUZ/P36
PCL/P35
16-bit timer/
event counter
8-bit timer/
event counter 1
8-bit timer/
event counter 2
Watchdog timer
Watch timer
Serial
interface 0
Serial
interface 3
A/D converter
Interrupt
control
Buzzer output
Clock output
control
78K/0
CPU core
ROM
RAM
V
DD0,
V
DD1
V
SS0,
V
SS1
IC
(V
PP
)
Port 0
Port 1
Port 2
Port 3
Port 7
Port 8
Port 9
Port 10
Port 11
P00
P01 to P05
P07
P10 to P17
P25 to P27
P30 to P37
P70 to P72
P80 to P87
P90 to P97
P100 to P103
P110 to P117
S0 to S23
S24/P97 to
S31/P90
S32/P87 to
S39/P80
COM0 to COM3
V
LC0
to V
LC2
BIAS
f
LCD
RESET
X1
X2
XT1/P07
XT2
LCD
controller/
driver
System
control
Serial
interface 2
RxD/P114
TxD/P113
SCK2/ASCK/P72
SI2/RxD/P70
SO2/TxD/P71
ANI0/P10 to
ANI7/P17
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2.8 Outline of Function
ROM
Mask ROM PROM
48 KB 60 KB 60 KBNote
High-speed RAM 1024 bytes
Expansion RAM 1024 bytes
LCD RAM 40 × 4 bits
General-purpose register 8 bits × 8 × 4 banks
With main system clock selected 0.4
µ
s/0.8
µ
s/1.6
µ
s/3.2
µ
s/6.4
µ
s/12.8
µ
s (@ 5.0 MHz)
With subsystem clock selected 122
µ
s (@ 32.768 kHz)
Instruction set • 16-bit operation
• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulate (set, reset, test, and Boolean operation)
• BCD adjust, etc.
I/O port (including alternate-function pins • Total: 57
for segment signal output) • CMOS input: 2
• CMOS I/O: 55
A/D converter 8-bit resolution × 8 channels
LCD controller/driver • Segment signal output: Max. 40
• Common signal output: Max. 4
• Bias: 1/2, 1/3 bias switching possible
Serial interface
• 3-wire serial I/O/2-wire serial I/O/I
2
C bus mode selection possible:
1 channel
• 3-wire serial I/O mode/UART mode selection possible: 1 channel
• 3-wire serial I/O mode: 1 channel
Timer • 16-bit timer/event counter: 1 channel
• 8-bit timer/event counter: 2 channels
• Watch timer: 1 channel
• Watchdog timer: 1 channel
Timer output Three outputs (14-bit PWM output enable: 1)
Clock output 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz,
2.5 MHz, 5.0 MHz (@ 5.0 MHz with main system clock)
32.768 kHz (@ 32.768 kHz with subsystem clock)
Buzzer output 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (@ 5.0 MHz with main system clock)
Note The capacity of the internal PROM can be changed using the internal memory size switching register (IMS).
Item
Part Number
Internal
memory
µ
PD780306Y
µ
PD780308Y
µ
PD78P0308Y
Minimum
instruction
execution
time
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Vectored Maskable Internal: 13
interrupt External: 6
source Non-maskable Internal: 1
Software 1
Test input Internal: 1
External: 1
Power supply voltage VDD = 2.0 to 5.5 V
Operating ambient temperature TA = –40 to +85°C
Package • 100-pin plastic LQFP (14 × 14)
• 100-pin plastic QFP (14 × 20)
2.9 Mask Options
The mask ROM versions (
µ
PD780306Y, 780308Y) provide mask options. By specifying this mask option at the
time of ordering, split resistors which enable to generate LCD drive voltage suited to each bias method type can be
incorporated. Using this mask option reduces the number of components to add to the device, resulting in board space
saving.
The mask options provided in the
µ
PD780308Y Subseries are shown in Table 2-1.
Table 2-1. Mask Options of Mask ROM Versions
Pin Names Mask Options
VLC0 to VLC2 Split resistor can be incorporated.
Item
Part Number
µ
PD780306Y
µ
PD780308Y
µ
PD78P0308Y
43
User’s Manual U11377EJ3V0UD
Pin Name I/O Function After Reset
Alternate Function
P00 Input Port 0. Input only Input INTP0/TI00
P01 I/O 7-bit I/O port. Input/output mode can be specified Input INTP1/TI01
P02 in 1-bit units. INTP2
P03 If used as an input port, an internal INTP3
P04
pull-up resistor can be used by
INTP4
P05
software.
INTP5
P07Note 1 Input Input only Input XT1
P10 to P17 I/O Port 1. Input ANI0 to ANI7
8-bit I/O port.
Input/output mode can be specified in 1-bit units.
If used as an input port, an internal pull-up resistor can be used by
softwareNote 2.
I/O Port 2. Input
3-bit I/O port.
Input/output mode can be specified in 1-bit units.
If used as an input port, an internal pull-up resistor can be used by
software.
P30 I/O Port 3. Input TO0
P31 8-bit I/O port. TO1
P32 Input/output mode can be specified in 1-bit units. TO2
P33
If used as an input port, an internal pull-up resistor can be used by
TI1
P34
software.
TI2
P35 PCL
P36 BUZ
P37 —
Notes 1. When the P07/XT1 pin is used as an input port, set bit 6 (FRC) of the processor clock control register
(PCC) to 1 (do not use the internal feedback resistor to the subsystem clock oscillator).
2. When pins P10/ANI0 to P17/ANI7 are used as an analog input of the A/D converter, the internal pull-
up resistor is automatically disabled.
CHAPTER 3 PIN FUNCTION (
µ
PD780308 SUBSERIES)
3.1 Pin Function List
3.1.1 Normal operating mode pins
(1) Port pins (1/2)
P25
P27
P26
SI0/SB0
SO0/SB1
SCK0
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CHAPTER 3 PIN FUNCTION (
µ
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User’s Manual U11377EJ3V0UD
P70 SI2/RxD
P71 SO2/TxD
P72 SCK2/ASCK
(1) Port pins (2/2)
Pin Name I/O Function After Reset
Alternate Function
I/O Port 7. Input
3-bit I/O port.
Input/output mode can be specified in 1-bit units.
If used as an input port, an internal pull-up resistor can be used by
software.
P80 to P87 I/O Port 8. Input S39 to S32
8-bit I/O port.
Input/output mode can be specified in 1-bit units.
If used as an input port, an internal pull-up resistor can be used by
software.
I/O port/segment signal output can be specified in 2-bit units by LCD
display control register (LCDC).
I/O Port 9.
8-bit I/O port.
Input/output mode can be specified in 1-bit units.
If used as an input port, an internal pull-up resistor can be used by
software.
I/O port/segment signal output can be specified in 2-bit units by LCD
display control register (LCDC).
Port 10. Input —
4-bit I/O port.
Input/output mode can be specified in 1-bit units.
If used as an input port, an internal pull-up resistor can be used by
software.
LED can be driven directly.
P110
I/O Port 11. Input SI3
P111 8-bit I/O port. SO3
P112 Input/output mode can be specified in 1-bit units. SCK3
P113
If used as an input port, an internal pull-up resistor can be used by
TxD
P114
software.
RxD
P115 to P117
Falling edge can be detected.
—
P90 to P97 Input S31 to S24
P100 to P103
I/O
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CHAPTER 3 PIN FUNCTION (
µ
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User’s Manual U11377EJ3V0UD
(2) Non-port pins (1/2)
Pin Name I/O Function After Reset
Alternate Function
INTP0 Input External interrupt request inputs with specifiable valid edges (rising Input P00/TI00
INTP1 edge, falling edge, both rising and falling edges). P01/TI01
INTP2 P02
INTP3 P03
INTP4 P04
INTP5 P05
SI0 Input Serial interface serial data input. Input P25/SB0
SI2 P70/RxD
SI3 P110
SO0 Output Serial interface serial data output. Input P26/SB1
SO2 P71/TxD
SO3 P111
SB0 I/O Serial interface serial data input/output. Input P25/SI0
SB1 P26/SO0
SCK0 I/O Serial interface serial clock input/output. Input P27
SCK2 P72/ASCK
SCK3 P112
RxD Input Asynchronous serial interface serial data input. Input P70/SI2, P114
TxD Output Asynchronous serial interface serial data output. Input P71/SO2, P113
ASCK Input Asynchronous serial interface serial clock input. Input P72/SCK2
TI00 Input External count clock input to 16-bit timer (TM0). Input P00/INTP0
TI01 Capture trigger signal input to capture register (CR00). P01/INTP1
TI1 External count clock input to 8-bit timer (TM1). P33
TI2 External count clock input to 8-bit timer (TM2). P34
TO0 Output 16-bit timer (TM0) output (also used for 14-bit PWM output). Input P30
TO1 8-bit timer (TM1) output. P31
TO2 8-bit timer (TM2) output. P32
PCL Output Clock output (for main system clock and subsystem clock trimming). Input P35
BUZ Output Buzzer output. Input P36
S0 to S23 Output Segment signal output of LCD controller/driver. Output —
S24 to S31 Input P97 to P90
S32 to S39 P87 to P80
COM0 to COM3
Output Common signal output of LCD controller/driver Output —
VLC0 to VLC2 — LCD drive voltage (mask ROM versions can incorporate split resistor — —
(mask option)).
BIAS — Power supply for LCD drive. — —
ANI0 to ANI7
Input A/D converter analog input. Input P10 to P17
AVREF Input A/D converter reference voltage input (also used for analog power). — —
46
CHAPTER 3 PIN FUNCTION (
µ
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(2) Non-port pins (2/2)
Pin Name I/O Function After Reset
Alternate Function
AVSS — A/D converter ground potential. Same potential as VSS0.——
RESET Input System reset input. — —
X1 Input Crystal connection for main system clock oscillation. — —
X2 — ——
XT1 Input Crystal connection for subsystem clock oscillation. Input P07
XT2 — ——
VDD0 — Positive power supply to port. — —
VSS0 — Ground potential of port. — —
VDD1 — Positive power supply (except ports, analogs). — —
VSS1 — Ground potential (except ports, analogs). — —
VPP — High-voltage application for program write/verify. Connect directly to — —
VSS0 or VSS1 in normal operating mode.
IC — Internal connection. Connect directly to VSS0 or VSS1.——
3.1.2 PROM programming mode pins (
µ
PD78P0308 only)
Pin Name I/O Function
RESET Input PROM programming mode setting.
When +5 V or +12.5 V is applied to the VPP pin or a low level voltage is applied to the RESET pin,
the PROM programming mode is set.
VPP Input High-voltage application for PROM programming mode setting and program write/verify.
A0 to A16 Input Address bus.
D0 to D7 I/O Data bus.
CE Input PROM enable input/program pulse input.
OE Input Read strobe input to PROM.
PGM Input Program/program inhibit input in PROM programming mode.
VDD — Positive power supply.
VSS — Ground potential.
47
CHAPTER 3 PIN FUNCTION (
µ
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User’s Manual U11377EJ3V0UD
3.2 Description of Pin Functions
3.2.1 P00 to P05, P07 (Port 0)
These are 7-bit I/O ports. Besides serving as I/O ports, they function as an external interrupt request input, an
external count clock input to the timer, a capture trigger signal input, and crystal connection for subsystem clock
oscillation.
The following operating modes can be specified in 1-bit units.
(1) Port mode
P00 and P07 function as input-only ports and P01 to P05 function as I/O ports.
P01 to P05 can be specified as input or output ports in 1-bit units with port mode register 0 (PM0). When
they are used as input ports, internal pull-up resistors can be used by defining pull-up resistor option register
L (PUOL).
(2) Control mode
These ports function as an external interrupt request input, an external count clock input to the timer, and crystal
connection for subsystem clock oscillation.
(a) INTP0 to INTP5
INTP0 to INTP5 are external interrupt request input pins which can specify valid edges (rising edge, falling
edge, and both rising and falling edges). INTP0 or INTP1 becomes a 16-bit timer/event counter capture
trigger signal input pin with a valid edge input.
(b) TI00
Pin for external count clock input to 16-bit timer/event counter.
(c) TI01
Pin for capture trigger signal input to capture register (CR00) of 16-bit timer/event counter.
(d) XT1
Crystal connect pin for subsystem clock oscillation.
48
CHAPTER 3 PIN FUNCTION (
µ
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3.2.2 P10 to P17 (Port 1)
These are 8-bit I/O ports. Besides serving as I/O ports, they function as an A/D converter analog input.
The following operating modes can be specified in 1-bit units.
(1) Port mode
These ports function as 8-bit I/O ports. They can be specified as input or output ports in 1-bit units with port
mode register 1 (PM1). When they are used as input ports, internal pull-up resistors can be used by defining
pull-up resistor option register L (PUOL).
(2) Control mode
These ports function as A/D converter analog input pins (ANI0 to ANI7). The pull-up resistor is automatically
disabled when the pins are specified for analog input.
3.2.3 P25 to P27 (Port 2)
These are 3-bit I/O ports. Besides serving as I/O ports, they function as data I/O and clock I/O of the serial interface.
The following operating modes can be specified in 1-bit units.
(1) Port mode
These ports function as 3-bit I/O ports. They can be specified as input or output ports in 1-bit units with port
mode register 2 (PM2). When they are used as input ports, internal pull-up resistors can be used by defining
pull-up resistor option register L (PUOL).
(2) Control mode
These ports function as serial interface data I/O and clock I/O.
(a) SI0, SO0
Serial interface serial data I/O pins.
(b) SCK0
Serial interface serial clock I/O pins.
(c) SB0 and SB1
NEC Electronics standard serial bus interface I/O pins.
Caution When this port is used as a serial interface, the I/O and output latches must be set according
to the function used. For the setting, refer to Figure 15-4 Serial Operating Mode Register 0
Format.
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3.2.4 P30 to P37 (Port 3)
These are 8-bit I/O ports. Besides serving as I/O ports, they function as timer I/O, clock output, and buzzer output.
The following operating modes can be specified in 1-bit units.
(1) Port mode
These ports function as 8-bit I/O ports. They can be specified as input or output ports in 1-bit units with port
mode register 3 (PM3). When they are used as input ports, internal pull-up resistors can be used by defining
pull-up resistor option register L (PUOL).
(2) Control mode
These ports function as timer I/O, clock output, and buzzer output.
(a) TI1 and TI2
Pins for external count clock input to the 8-bit timer/event counter.
(b) TO0 to TO2
Timer output pins.
(c) PCL
Clock output pin.
(d) BUZ
Buzzer output pin.
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3.2.5 P70 to P72 (Port 7)
These are 3-bit I/O ports. Besides serving as I/O ports, they function as serial interface data I/O and clock I/O.
The following operating modes can be specified in 1-bit units.
(1) Port mode
These ports function as 3-bit I/O ports. They can be specified as input or output ports in 1-bit units with port
mode register 7 (PM7). When they are used as input ports, internal pull-up resistors can be used by defining
pull-up resistor option register L (PUOL).
(2) Control mode
These ports function as serial interface data I/O and clock I/O.
(a) SI2, SO2
Serial interface serial data I/O pins.
(b) SCK2
Serial interface serial clock I/O pin.
(c) RxD, TxD
Asynchronous serial interface serial data I/O pins.
(d) ASCK
Asynchronous serial interface serial clock input pin.
Caution When this port is used as a serial interface, the I/O and output latches must be set according
to the function used. For the setting, refer to Table 17-2 Serial Interface Channel 2 Operating
Mode Settings.
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3.2.6 P80 to P87 (Port 8)
These are 8-bit I/O ports. Besides serving as I/O ports, they function as segment signal output of LCD controller/
driver.
The following operating modes can be specified in 1-bit units.
(1) Port mode
These ports function as 8-bit I/O ports. They can be specified as input or output ports in 1-bit units with port
mode register 8 (PM8). When they are used as input ports, internal pull-up resistors can be used by defining
pull-up resistor option register H (PUOH).
(2) Control mode
These ports function as segment signal output pins (S32 to S39) of LCD controller/driver.
3.2.7 P90 to P97 (Port 9)
These are 8-bit I/O ports. Besides serving as I/O ports, they function as segment signal output of LCD controller/
driver.
The following operating modes can be specified in 1-bit units.
(1) Port mode
These ports function as 8-bit I/O ports. They can be specified as input or output ports in 1-bit units with port
mode register 9 (PM9). When they are used as input ports, internal pull-up resistors can be used by defining
pull-up resistor option register H (PUOH).
(2) Control mode
These ports function as segment signal output pins (S24 to S31) of LCD controller/driver.
3.2.8 P100 to P103 (Port 10)
These are 4-bit I/O ports. They can be specified as input or output ports in 1-bit units with port mode register 10
(PM10). When they are used as input ports, internal pull-up resistors can be used by defining pull-up resistor option
register H (PUOH).
LED can be driven directly.
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3.2.9 P110 to P117 (Port 11)
These are 8-bit I/O ports. Besides serving as I/O ports, they function as serial interface data I/O and clock I/O.
The following operating modes can be specified in 1-bit units.
(1) Port mode
These ports function as 8-bit I/O ports. They can be specified as input or output ports in 1-bit units with port
mode register 11 (PM11). When they are used as input ports, internal pull-up resistors can be used by defining
pull-up resistor option register H (PUOH).
When the falling edge is detected on a specified bit of this port, test input flag (KRIF) can be set to 1.
(2) Control mode
These ports function as serial interface data I/O and clock I/O.
(a) SI3, SO3
Serial interface serial data I/O pins.
(b) SCK3
Serial interface serial clock I/O pin.
(c) RxD, TxD
Asynchronous serial interface serial data I/O pins.
Caution When this port is used as a serial interface, the I/O and output latches must be set according
to the function used. For the setting, refer to Table 17-2 Serial Interface Channel 2 Operating
Mode Settings, and Figure 18-3 Serial Operating Mode Register 3 Format.
3.2.10 COM0 to COM3
These are LCD controller/driver common signal output pins. They output common signals under either of the
following conditions:
– when the static mode is selected (COM0 to COM3 outputs)
– when 2-time-division (COM0, COM1 outputs) or 3-time-division (COM0 to COM2 outputs) operation is performed
in 1/2 bias mode
– when 3-time-division (COM0 to COM2 outputs) or 4-time-division (COM0 to COM3 outputs) operation is
performed in 1/3 bias mode
3.2.11 VLC0 to VLC2
These are LCD-driving voltage pins. The mask ROM versions can have split resistors by mask option so that LCD
driving voltage can be supplied inside the VLC0 to VLC2 pins according to the required bias without connecting external
split resistors.
3.2.12 BIAS
This is a LCD driving power supply pin. This pin should be connected to the VLC0 pin to realize user-desired LCD
drive voltages to change resistance division ratios, or should be connected to external resistors together with the VLC0
to VLC2 pins and VSS1 pin to fine-adjust the LCD-driving power voltage.
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3.2.13 AVREF
This pin inputs the reference voltage for the on-chip A/D converter. This pin also functions to supply power to the
internal analog circuit. Supply power to this pin when using the A/D converter.
When not using the A/D converter, connect this pin to the VSS0 line.
3.2.14 AVSS
This is a ground potential pin of A/D converter. Always use the same voltage as that of the VSS0 pin even when
A/D converter is not used.
3.2.15 RESET
This is a low-level active system reset input pin.
3.2.16 X1 and X2
Crystal resonator connection pins for main system clock oscillation.
For external clock supply, input it to X1 and its inverted signal to X2.
3.2.17 XT1 and XT2
Crystal resonator connection pins for subsystem clock oscillation.
For external clock supply, input it to XT1 and its inverted signal to XT2.
3.2.18 VDD0, VDD1
VDD0 supplies positive power to the ports.
VDD1 supplies positive power to the circuits other than those of the ports.
3.2.19 VSS0, VSS1
VSS0 is the ground pin of the ports.
VSS1 is the ground pin of the circuits other than those of the ports.
3.2.20 VPP (
µ
PD78P0308 only)
High-voltage apply pin for PROM programming mode setting and program write/verify.
Connect directly to VSS0 or VSS1 in normal operating mode.
3.2.21 IC (Mask ROM version only)
The IC (Internally Connected) pin is provided to set the test mode to check the
µ
PD780308 Subseries at delivery.
Connect it directly to the VSS0 or VSS1 with the shortest possible wire in the normal operating mode.
When a voltage difference is produced between the IC pin and VSS0 or VSS1 pin because the wiring between those
two pins is too long or an external noise is input to the IC pin, the user’s program may not run normally.
●● Connect IC pins to VSS0 or VSS1 pins directly.
V
SS0, 1
IC
As short as possible
V
SS0
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I/O
Circuit Type
P00/INTP0/TI00 2 Input Connect to VSS0.
P01/INTP1/TI01 8-C I/O
Independently connect to V
SS0
via a resistor.
P02/INTP2
P03/INTP3
P04/INTP4
P05/INTP5
P07/XT1 16 Input Connect to VDD0.
P10/ANI0 to P17/ANI7 11-B I/O Independently connect to VDD0 or VSS0
P25/SI0/SB0 10-B via a resistor.
P26/SO0/SB1
P27/SCK0
P30/TO0 5-H
P31/TO1
P32/TO2
P33/TI1 8-C
P34/TI2
P35/PCL 5-H
P36/BUZ
P37
P70/SI2/RxD 8-C
P71/SO2/TxD 5-H
P72/SCK2/ASCK 8-C
P80/S39 to P87/S32 17-C
P90/S31 to P97/S24
P100 to P103 5-H
P110/SI3 8-C Independently connect to VDD0 via a
P111/SO3 resistor.
P112/SCK3
P113/TxD
P114/RxD
P115 to P117
S0 to S23 17-B Output Leave open.
COM0 to COM3 18-A
VLC0 to VLC2 ——
BIAS
Pin Name I/O Recommended Connection of Unused Pins
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 3-1 shows the I/O circuit types of pins and the recommended connections of unused pins.
Refer to Figure 3-1 for the configuration of the I/O circuit of each type.
Table 3-1. Pin I/O Circuit Types (1/2)
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Table 3-1. Pin I/O Circuit Types (2/2)
I/O
Circuit Type
RESET 2 Input —
XT2 16 —Leave open.
AVREF ——Connect to VSS0.
AVSS Connect to VSS0.
IC (mask ROM version) Connect directly to VSS0 or VSS1.
VPP (
µ
PD78P0308)
Pin Name I/O Recommended Connection of Unused Pins
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Figure 3-1. Pin I/O Circuit List (1/2)
Type 2
Schmitt-triggered input with hysteresis characteristics
IN
Type 5-H
Data
Output
disable
P-ch
IN/OUT
VDD0
N-ch
Input
enable
P-ch
VDD0
Pull-up
enable
Type 8-C
Type 10-B
Data P-ch
IN/OUT
VDD0
N-ch
P-ch
VDD0
Pull-up
enable
Open drain
Output
disable
Data
Output
disable
P-ch
IN/OUT
VDD0
N-ch
Input
enable
P-ch
VDD0
Pull-up
enable
Comparator
+
–
P-ch
VREF
(Threshold voltage)
Data
Output
disable
P-ch
IN/OUT
VDD0
N-ch
P-ch
VDD0
Pull-up
enable
Type 11-B
VSS0
VSS0
VSS0
VSS0
N-ch
AV SS
Type 16
Feedback
cut-off
P-ch
XT1 XT2
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Figure 3-1. Pin I/O Circuit List (2/2)
Type 17-B Type 17-C
VLC0
VLC1
SEG
data
VLC2
P-ch
N-ch
P-ch
N-ch
P-ch
N-ch
OUT
VLC0
VLC1
COM
data
VLC2
P-ch
N-ch
P-ch
N-ch
P-ch
N-ch OUT
N-ch
P-ch
VLC0
VLC1
SEG
data
VLC2
P-ch
N-ch P-ch
N-ch
P-ch
N-ch
P-ch
N-ch
Input
enable
Output
disable
Data
Pull-up
enable
VDD0
P-ch
IN/OUT
VDD0
Type 18-A
VSS1
VSS1 VSS1
VSS0
58 User’s Manual U11377EJ3V0UD
Pin Name I/O Function After Reset
Alternate Function
P00 Input Port 0. Input only Input INTP0/TI00
P01 I/O 7-bit I/O port. Input/output mode can be specified Input INTP1/TI01
P02 in 1-bit units. INTP2
P03 If used as an input port, an internal INTP3
P04
pull-up resistor can be used by
INTP4
P05
software.
INTP5
P07Note 1 Input Input only Input XT1
P10 to P17 I/O Port 1. Input ANI0 to ANI7
8-bit I/O port.
Input/output mode can be specified in 1-bit units.
If used as an input port, an internal pull-up resistor can be used by
softwareNote 2.
I/O Port 2. Input
3-bit I/O port.
Input/output mode can be specified in 1-bit units.
If used as an input port, an internal pull-up resistor can be used by
software.
P30 I/O Port 3. Input TO0
P31 8-bit I/O port. TO1
P32
Input/output mode can be specified in 1-bit units.
TO2
P33
If used as an input port, an internal pull-up resistor can be used by
TI1
P34
software.
TI2
P35 PCL
P36 BUZ
P37 —
Notes 1. When the P07/XT1 pin is used as an input port, set bit 6 (FRC) of the processor clock control register
(PCC) to 1 (do not use the internal feedback resistor to the subsystem clock oscillator).
2. When pins P10/ANI0 to P17/ANI7 are used as an analog input of the A/D converter, the internal pull-
up resistor is automatically disabled.
CHAPTER 4 PIN FUNCTION (
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4.1 Pin Function List
4.1.1 Normal operating mode pins
(1) Port pins (1/2)
P25
P26
P27
SI0/SB0/SDA0
SO0/SB1/SDA1
SCK0/SCL
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(1) Port pins (2/2)
Pin Name I/O Function After Reset
Alternate Function
I/O Port 7.
3-bit I/O port.
Input/output mode can be specified in 1-bit units.
If used as an input port, an internal pull-up resistor can be used by
software.
P80 to P87 I/O Port 8. Input S39 to S32
8-bit I/O port.
Input/output mode can be specified in 1-bit units.
If used as an input port, an internal pull-up resistor can be used by
software.
I/O port/segment signal output can be specified in 2-bit units by LCD
display control register (LCDC).
I/O Port 9.
8-bit I/O port.
Input/output mode can be specified in 1-bit units.
If used as an input port, an internal pull-up resistor can be used by
software.
I/O port/segment signal output can be specified in 2-bit units by LCD
display control register (LCDC).
Port 10. Input —
4-bit I/O port.
Input/output mode can be specified in 1-bit units.
If used as an input port, an internal pull-up resistor can be used by
software.
LED can be driven directly.
P110
I/O Port 11. Input SI3
P111 8-bit I/O port. SO3
P112
Input/output mode can be specified in 1-bit units.
SCK3
P113
If used as an input port, an internal pull-up resistor can be used by
TxD
P114
software.
RxD
P115 to P117
Falling edge can be detected.
—
P70 Input SI2/RxD
P71 SO2/TxD
P72 SCK2/ASCK
P90 to P97 Input S31 to S24
P100 to P103
I/O
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(2) Non-port pins (1/2)
Pin Name I/O Function After Reset
Alternate Function
INTP0 Input External interrupt request inputs with specifiable valid edges (rising edge, Input P00/TI00
INTP1 falling edge, both rising and falling edges). P01/TI01
INTP2 P02
INTP3 P03
INTP4 P04
INTP5 P05
SI0 Input Serial interface serial data input. Input P25/SB0/SDA0
SI2 P70/RxD
SI3 P110
SO0 Output Serial interface serial data output. Input P26/SB1/SDA1
SO2 P71/TxD
SO3 P111
SB0 I/O Serial interface serial data input/output. Input P25/SI0/SDA0
SB1 P26/SO0/SDA1
SDA0 P25/SI0/SB0
SDA1 P26/SO0/SB1
SCK0 I/O Serial interface serial clock input/output. Input P27/SCL
SCK2 P72/ASCK
SCK3 P112
SCL P27/SCK0
RxD Input Asynchronous serial interface serial data input. Input P70/SI2, P114
TxD Output Asynchronous serial interface serial data output. Input
P71/SO2, P113
ASCK Input Asynchronous serial interface serial clock input. Input P72/SCK2
TI00 Input External count clock input to 16-bit timer (TM0). Input P00/INTP0
TI01 Capture trigger signal input to capture register (CR00). P01/INTP1
TI1 External count clock input to 8-bit timer (TM1). P33
TI2 External count clock input to 8-bit timer (TM2). P34
TO0 Output 16-bit timer (TM0) output (also used for 14-bit PWM output). Input P30
TO1 8-bit timer (TM1) output. P31
TO2 8-bit timer (TM2) output. P32
PCL Output Clock output (for main system clock and subsystem clock trimming). Input P35
BUZ Output Buzzer output. Input P36
S0 to S23 Output Segment signal output of LCD controller/driver. Output —
S24 to S31 Input P97 to P90
S32 to S39 P87 to P80
COM0 to COM3
Output Common signal output of LCD controller/driver. Output —
VLC0 to VLC2 — LCD drive voltage (mask ROM versions can incorporate split resistor — —
(mask option)).
BIAS — Power supply for LCD drive. — —
ANI0 to ANI7
Input A/D converter analog input. Input P10 to P17
AVREF Input A/D converter reference voltage input (also used for analog power). — —
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(2) Non-port pins (2/2)
Pin Name I/O Function After Reset
Alternate Function
AVSS — A/D converter ground potential. Same potential as VSS0.——
RESET Input System reset input. — —
X1 Input Crystal connection for main system clock oscillation. — —
X2 — ——
XT1 Input Crystal connection for subsystem clock oscillation. Input P07
XT2 — ——
VDD0 — Positive power supply to port. — —
VSS0 — Ground potential of port. — —
VDD1 — Positive power supply (except ports, analogs). — —
VSS1 — Ground potential (except ports, analogs). — —
VPP — High-voltage application for program write/verify. Connect directly to — —
VSS0 or VSS1 in normal operating mode.
IC — Internal connection. Connect directly to VSS0 or VSS1.——
4.1.2 PROM programming mode pins (
µ
PD78P0308Y only)
Pin Name I/O Function
RESET Input PROM programming mode setting.
When +5 V or +12.5 V is applied to the VPP pin or a low level voltage is applied to the RESET pin,
the PROM programming mode is set.
VPP Input High-voltage application for PROM programming mode setting and program write/verify.
A0 to A16 Input Address bus.
D0 to D7 I/O Data bus.
CE Input PROM enable input/program pulse input.
OE Input Read strobe input to PROM.
PGM Input Program/program inhibit input in PROM programming mode.
VDD — Positive power supply.
VSS — Ground potential.
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4.2 Description of Pin Functions
4.2.1 P00 to P05, P07 (Port 0)
These are 7-bit I/O ports. Besides serving as I/O ports, they function as an external interrupt request input, an
external count clock input to the timer, a capture trigger signal input, and crystal connection for subsystem clock
oscillation.
The following operating modes can be specified in 1-bit units.
(1) Port mode
P00 and P07 function as input-only ports and P01 to P05 function as I/O ports.
P01 to P05 can be specified as input or output ports in 1-bit units with port mode register 0 (PM0). When
they are used as input ports, internal pull-up resistors can be used by defining pull-up resistor option register
L (PUOL).
(2) Control mode
These ports function as an external interrupt request input, an external count clock input to the timer, and crystal
connection for subsystem clock oscillation.
(a) INTP0 to INTP5
INTP0 to INTP5 are external interrupt request input pins which can specify valid edges (rising edge, falling
edge, and both rising and falling edges). INTP0 or INTP1 becomes a 16-bit timer/event counter capture
trigger signal input pin with a valid edge input.
(b) TI00
Pin for external count clock input to 16-bit timer/event counter.
(c) TI01
Pin for capture trigger signal input to capture register (CR00) of 16-bit timer/event counter.
(d) XT1
Crystal connect pin for subsystem clock oscillation.
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4.2.2 P10 to P17 (Port 1)
These are 8-bit I/O ports. Besides serving as I/O ports, they function as an A/D converter analog input.
The following operating modes can be specified in 1-bit units.
(1) Port mode
These ports function as 8-bit I/O ports. They can be specified as input or output ports in 1-bit units with port
mode register 1 (PM1). When they are used as input ports, internal pull-up resistors can be used by defining
pull-up resistor option register L (PUOL).
(2) Control mode
These ports function as A/D converter analog input pins (ANI0 to ANI7). The pull-up resistor is automatically
disabled when the pins are specified for analog input.
4.2.3 P25 to P27 (Port 2)
These are 3-bit I/O ports. Besides serving as I/O ports, they function as data I/O and clock I/O of the serial interface.
The following operating modes can be specified in 1-bit units.
(1) Port mode
These ports function as 3-bit I/O ports. They can be specified as input or output ports in 1-bit units with port
mode register 2 (PM2). When they are used as input ports, internal pull-up resistors can be used by defining
pull-up resistor option register L (PUOL).
(2) Control mode
These ports function as serial interface data I/O and clock I/O.
(a) SI0, SO0, SB0, SB1, SDA0, SDA1
Serial interface serial data I/O pins.
(b) SCK0, SCL
Serial interface serial clock I/O pins.
Caution When this port is used as a serial interface, the I/O and output latches must be set according
to the function used. For the setting, refer to Figure 16-4 Serial Operating Mode Register 0
Format.
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4.2.4 P30 to P37 (Port 3)
These are 8-bit I/O ports. Besides serving as I/O ports, they function as timer I/O, clock output, and buzzer output.
The following operating modes can be specified in 1-bit units.
(1) Port mode
These ports function as 8-bit I/O ports. They can be specified as input or output ports in 1-bit units with port
mode register 3 (PM3). When they are used as input ports, internal pull-up resistors can be used by defining
pull-up resistor option register L (PUOL).
(2) Control mode
These ports function as timer I/O, clock output, and buzzer output.
(a) TI1 and TI2
Pins for external clock input to the 8-bit timer/event counter.
(b) TO0 to TO2
Timer output pins.
(c) PCL
Clock output pin.
(d) BUZ
Buzzer output pin.
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4.2.5 P70 to P72 (Port 7)
These are 3-bit I/O ports. Besides serving as I/O ports, they function as serial interface data I/O and clock I/O.
The following operating modes can be specified in 1-bit units.
(1) Port mode
These ports function as 3-bit I/O ports. They can be specified as input or output ports in 1-bit units with port
mode register 7 (PM7). When they are used as input ports, internal pull-up resistors can be used by defining
pull-up resistor option register L (PUOL).
(2) Control mode
These ports function as serial interface data I/O and clock I/O.
(a) SI2, SO2
Serial interface serial data I/O pins.
(b) SCK2
Serial interface serial clock I/O pin.
(c) RxD, TxD
Asynchronous serial interface serial data I/O pins.
(d) ASCK
Asynchronous serial interface serial clock input pin.
Caution When this port is used as a serial interface, the I/O and output latches must be set according
to the function used. For the setting, refer to Table 17-2 Serial Interface Channel 2 Operating
Mode Settings.
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4.2.6 P80 to P87 (Port 8)
These are 8-bit I/O ports. Besides serving as I/O ports, they function as segment signal output of LCD controller/
driver.
The following operating modes can be specified in 1-bit units.
(1) Port mode
These ports function as 8-bit I/O ports. They can be specified as input or output ports in 1-bit units with port
mode register 8 (PM8). When they are used as input ports, internal pull-up resistors can be used by defining
pull-up resistor option register H (PUOH).
(2) Control mode
These ports function as segment signal output pins (S32 to S39) of LCD controller/driver.
4.2.7 P90 to P97 (Port 9)
These are 8-bit I/O ports. Besides serving as I/O ports, they function as segment signal output of LCD controller/
driver.
The following operating modes can be specified in 1-bit units.
(1) Port mode
These ports function as 8-bit I/O ports. They can be specified as input or output ports in 1-bit units with port
mode register 9 (PM9). When they are used as input ports, internal pull-up resistors can be used by defining
pull-up resistor option register H (PUOH).
(2) Control mode
These ports function as segment signal output pins (S24 to S31) of LCD controller/driver.
4.2.8 P100 to P103 (Port 10)
These are 4-bit I/O ports. They can be specified as input or output ports in 1-bit units with port mode register 10
(PM10). When they are used as input ports, internal pull-up resistors can be used by defining pull-up resistor option
register H (PUOH).
LED can be driven directly.
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µ
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4.2.9 P110 to P117 (Port 11)
These are 8-bit I/O ports. Besides serving as I/O ports, they function as serial interface data I/O and clock I/O.
The following operating modes can be specified in 1-bit units.
(1) Port mode
These ports function as 8-bit I/O ports. They can be specified as input or output ports in 1-bit units with port
mode register 11 (PM11). When they are used as input ports, internal pull-up resistors can be used by defining
pull-up resistor option register H (PUOH).
When the falling edge is detected on a specified bit of this port, test input flag (KRIF) can be set to 1.
(2) Control mode
These ports function as serial interface data I/O and clock I/O.
(a) SI3, SO3
Serial interface serial data I/O pins.
(b) SCK3
Serial interface serial clock I/O pin.
(c) RxD, TxD
Asynchronous serial interface serial data I/O pins.
Caution When this port is used as a serial interface, the I/O and output latches must be set according
to the function used. For the setting, refer to Table 17-2 Serial Interface Channel 2 Operating
Mode Settings, and Figure 18-3 Serial Operating Mode Register 3 Format.
4.2.10 COM0 to COM3
These are LCD controller/driver common signal output pins. They output common signals under either of the
following conditions:
– when the static mode is selected (COM0 to COM3 outputs)
– when 2-time-division (COM0, COM1 outputs) or 3-time-division (COM0 to COM2 outputs) operation is performed
in 1/2 bias mode
– when 3-time-division (COM0 to COM2 outputs) or 4-time-division (COM0 to COM3 outputs) operation is
performed in 1/3 bias mode
4.2.11 VLC0 to VLC2
These are LCD-driving voltage pins. The mask ROM versions can have split resistors by mask option so that LCD
driving voltage can be supplied inside the VLC0 to VLC2 pins according to the required bias without connecting external
split resistors.
4.2.12 BIAS
This is a LCD driving power supply pin. This pin should be connected to the VLC0 pin to realize user-desired LCD
drive voltages to change resistance division ratios, or should be connected to external resistors together with the VLC0
to VLC2 pins and VSS1 pin to fine-adjust the LCD-driving power voltage.
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µ
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4.2.13 AVREF
This pin inputs the reference voltage for the on-chip A/D converter. This pin also functions to supply power to the
internal analog circuit. Supply power to this pin when using the A/D converter.
When not using the A/D converter, connect this pin to the VSS0 line.
4.2.14 AVSS
This is a ground potential pin of A/D converter. Always use the same voltage as that of the VSS0 pin even when
A/D converter is not used.
4.2.15 RESET
This is a low-level active system reset input pin.
4.2.16 X1 and X2
Crystal resonator connection pins for main system clock oscillation.
For external clock supply, input it to X1 and its inverted signal to X2.
4.2.17 XT1 and XT2
Crystal resonator connection pins for subsystem clock oscillation.
For external clock supply, input it to XT1 and its inverted signal to XT2.
4.2.18 VDD0, VDD1
VDD0 supplies positive power to the ports.
VDD1 supplies positive power to the circuits other than those of the ports.
4.2.19 VSS0, VSS1
VSS0 is the ground pin of the ports.
VSS1 is the ground pin of the circuits other than those of the ports.
4.2.20 VPP (
µ
PD78P0308Y only)
High-voltage apply pin for PROM programming mode setting and program write/verify.
Connect directly to VSS0 or VSS1 in normal operating mode.
4.2.21 IC (Mask ROM version only)
The IC (Internally Connected) pin is provided to set the test mode to check the
µ
PD780308Y Subseries at delivery.
Connect it directly to the VSS0 or VSS1 with the shortest possible wire in the normal operating mode.
When a voltage difference is produced between the IC pin and VSS0 or VSS1 pin because the wiring between those
two pins is too long or an external noise is input to the IC pin, the user’s program may not run normally.
● ● Connect IC pins to VSS0 or VSS1 pins directly.
VSS0, 1 IC
As short as possible
VSS0
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µ
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User’s Manual U11377EJ3V0UD
I/O
Circuit Type
P00/INTP0/TI00 2 Input Connect to VSS0.
P01/INTP1/TI01 8-C I/O
Independently connect to V
SS0
via a resistor.
P02/INTP2
P03/INTP3
P04/INTP4
P05/INTP5
P07/XT1 16 Input Connect to VDD0.
P10/ANI0 to P17/ANI7 11-B I/O Independently connect to VDD0 or VSS0
P25/SI0/SB0/SDA0 10-B via a resistor.
P26/SO0/SB1/SDA1
P27/SCK0/SCL
P30/TO0 5-H
P31/TO1
P32/TO2
P33/TI1 8-C
P34/TI2
P35/PCL 5-H
P36/BUZ
P37
P70/SI2/RxD 8-C
P71/SO2/TxD 5-H
P72/SCK2/ASCK 8-C
P80/S39 to P87/S32 17-C
P90/S31 to P97/S24
P100 to P103 5-H
P110/SI3 8-C Independently connect to VDD0 via a
P111/SO3 resistor.
P112/SCK3
P113/TxD
P114/RxD
P115 to P117
S0 to S23 17-B Output Leave open.
COM0 to COM3 18-A
VLC0 to VLC2 ——
BIAS
Pin Name I/O Recommended Connection of Unused Pins
4.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 4-1 shows the I/O circuit types of pins and the recommended connections of unused pins.
Refer to Figure 4-1 for the configuration of the I/O circuit of each type.
Table 4-1. Pin I/O Circuit Types (1/2)
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µ
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Table 4-1. Pin I/O Circuit Types (2/2)
I/O
Circuit Type
RESET 2 Input —
XT2 16 —Leave open.
AVREF ——Connect to VSS0.
AVSS Connect to VSS0.
IC (mask ROM version) Connect directly to VSS0 or VSS1.
VPP (
µ
PD78P0308Y)
Pin Name I/O Recommended Connection of Unused Pins
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µ
PD780308Y SUBSERIES)
User’s Manual U11377EJ3V0UD
Figure 4-1. Pin I/O Circuit List (1/2)
Type 2
Schmitt-triggered input with hysteresis characteristics
IN
Type 5-H
Data
Output
disable
P-ch
IN/OUT
VDD0
N-ch
Input
enable
P-ch
VDD0
Pull-up
enable
Type 8-C
Type 10-B
Data P-ch
IN/OUT
VDD0
N-ch
P-ch
VDD0
Pull-up
enable
Open drain
Output
disable
Data
Output
disable
P-ch
IN/OUT
VDD0
N-ch
Input
enable
P-ch
VDD0
Pull-up
enable
Comparator
+
–
P-ch
VREF
(Threshold voltage)
Data
Output
disable
P-ch
IN/OUT
VDD0
N-ch
P-ch
VDD0
Pull-up
enable
Type 11-B
VSS0
VSS0
VSS0
VSS0
N-ch
AV SS
Type 16
Feedback
cut-off
P-ch
XT1 XT2
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µ
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Figure 4-1. Pin I/O Circuit List (2/2)
Type 17-B Type 17-C
VLC0
VLC1
SEG
data
VLC2
P-ch
N-ch
P-ch
N-ch
P-ch
N-ch
OUT
VLC0
VLC1
COM
data
VLC2
P-ch
N-ch
P-ch
N-ch
P-ch
N-ch OUT
N-ch
P-ch
VLC0
VLC1
SEG
data
VLC2
P-ch
N-ch P-ch
N-ch
P-ch
N-ch
P-ch
N-ch
Input
enable
Output
disable
Data
Pull-up
enable
VDD0
P-ch
IN/OUT
VDD0
Type 18-A
VSS1
VSS1 VSS1
VSS0
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CHAPTER 5 CPU ARCHITECTURE
5.1 Memory Spaces
The
µ
PD780308 and 780308Y Subseries can access a 64 KB memory space. Figures 5-1 to 5-3 show memory
maps.
Figure 5-1. Memory Map (
µ
PD780306, 780306Y)
0000H
Data memory
space
General-purpose registers
32 × 8 bits
Internal ROM
49152 × 8 bits
BFFFH
1000H
0FFFH
0800H
07FFH
0080H
007FH
0040H
003FH
0000H
CALLF entry area
CALLT table area
Vector table area
Program area
Program area
LCD RAM
40 × 4 bits
Reserved
Program
memory
space
C000H
BFFFH
FA58H
FA57H
FA80H
FA7FH
FEE0H
FEDFH
FF00H
FEFFH
FFFFH
Internal high-speed RAM
1024 × 8 bits
Special function
registers (SFRs)
256 × 8 bits
Reserved
FB00H
FAFFH
Reserved
Internal expansion RAM
1024 × 8 bits
F800H
F7FFH
F400H
F3FFH
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Figure 5-2. Memory Map (
µ
PD780308, 780308Y)
0000H
Data memory
space
General-purpose registers
32 × 8 bits
Internal ROM
61440 × 8 bits
EFFFH
1000H
0FFFH
0800H
07FFH
0080H
007FH
0040H
003FH
0000H
CALLF entry area
CALLT table area
Vector table area
Program area
Program area
LCD RAM
40 × 4 bits
Reserved
Program
memory
space
F000H
EFFFH
FA58H
FA57H
FA80H
FA7FH
FEE0H
FEDFH
FF00H
FEFFH
FFFFH
Internal high-speed RAM
1024 × 8 bits
Special function
registers (SFRs)
256 × 8 bits
Reserved
FB00H
FAFFH
Reserved
Internal expansion RAM
1024 × 8 bits
F800H
F7FFH
F400H
F3FFH
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Figure 5-3. Memory Map (
µ
PD78P0308, 78P0308Y)
0000H
Data memory
space
General-purpose registers
32 × 8 bits
Internal PROM
61440 × 8 bits
EFFFH
1000H
0FFFH
0800H
07FFH
0080H
007FH
0040H
003FH
0000H
CALLF entry area
CALLT table area
Vector table area
Program area
Program area
LCD RAM
40 × 4 bits
Reserved
Program
memory
space
F000H
EFFFH
FA58H
FA57H
FA80H
FA7FH
FEE0H
FEDFH
FF00H
FEFFH
FFFFH
Internal high-speed RAM
1024 × 8 bits
Special function
registers (SFRs)
256 × 8 bits
Reserved
FB00H
FAFFH
Reserved
Internal expansion RAM
1024 × 8 bits
F800H
F7FFH
F400H
F3FFH
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5.1.1 Internal program memory space
The internal program memory space stores program data and table data. This space is generally accessed with
program counter (PC).
The
µ
PD780308, 780308Y Subseries has internal ROM (or PROM) and the capacity of the memory varies
depending on the part number.
Table 5-1. Internal ROM Capacity
Part Number Internal ROM
Type Capacity
µ
PD780306, 780306Y Mask ROM 49152 × 8 bits
µ
PD780308, 780308Y 61440 × 8 bits
µ
PD78P0308, 78P0308Y PROM
The internal program memory is divided into the following three areas.
(1) Vector table area
The 64-byte area 0000H to 003FH is reserved as a vector table area. The RESET input and program start
addresses for branch upon generation of each interrupt request are stored in the vector table area. Of the
16-bit address, lower 8 bits are stored at even addresses and higher 8 bits are stored at odd addresses.
Table 5-2. Vector Table
Vector Table Address Interrupt Source
0000H RESET input
0004H INTWDT
0006H INTP0
0008H INTP1
000AH INTP2
000CH INTP3
000EH INTP4
0010H INTP5
0014H INTCSI0
0018H INTSER
001AH INTSR/INTCSI2
001CH INTST
001EH INTTM3
0020H INTTM00
0022H INTTM01
0024H INTTM1
0026H INTTM2
0028H INTAD
002AH INTCSI1
003EH BRK
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(2) CALLT instruction table area
The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT).
(3) CALLF instruction entry area
The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).
5.1.2 Internal data memory space
The
µ
PD780308 and 780308Y Subseries units incorporate the following RAMs.
(1) Internal high-speed RAM
The internal high-speed RAM space consists of 1024 × 8 bits, or addresses FB00H to FEFFH. In this area,
four banks of general-purpose registers, each bank consisting of eight 8-bit registers, are allocated in the 32-
byte area FEE0H to FEFFH.
The internal high-speed RAM can also be used as a stack.
(2) Internal expansion RAM
Internal expansion RAM is allocated to the 1024-byte area of addresses F400H to F7FFH.
(3) LCD display RAM
Addresses FA58H to FA7FH of 40 × 4 bits are allocated for LCD display RAM, However, this area can also
be used as general-purpose RAM.
5.1.3 Special-function register (SFR) area
An on-chip peripheral hardware special-function register (SFR) is allocated in the area FF00H to FFFFH (refer
to Table 5-3).
Caution Do not access addresses where the SFR is not assigned.
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5.1.4 Data memory addressing
Addressing is to specify the address of the instruction to be executed next or the address of a register or memory
to be manipulated when an instruction is executed.
The address of the instruction to be executed next is specified by the program counter (for details, refer to 5.3
Instruction Address Addressing).
To specify the address of the memory to be manipulated when an instruction is executed, the
µ
PD780308 and
780308Y Subseries are provided with many addressing modes to improve operability. Especially at addresses
corresponding to data memory area (FB00H to FFFFH), particular addressing modes are possible to meet the
functions of the special function registers (SFRs) and general-purpose registers. This area is between FB00H and
FFFFH. Figures 5-4 to 5-6 show the data memory addressing modes.
For details of each addressing, refer to 5.4 Operand Address Addressing.
Figure 5-4. Data Memory Addressing (
µ
PD780306, 780306Y)
0000H
Internal ROM
49152 × 8 bits
LCD RAM
40 × 4 bits
Internal expansion RAM
1024 × 8 bits
C000H
BFFFH
FA58H
FA57H
FA80H
FA7FH
FEE0H
FEDFH
FF00H
FEFFH
FFFFH
Internal high-speed RAM
1024 × 8 bits
Reserved
FB00H
FAFFH
FF20H
FF1FH
FE20H
FE1FH
Special function
registers (SFRs)
256 × 8 bits SFR addressing
Register addressing
Short direct
addressing
Direct addressing
Register indirect
addressing
Based addressing
Based indexed
addressing
F800H
F7FFH
Reserved
F400H
F3FFH
Reserved
General-purpose registers
32 × 8 bits
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Figure 5-5. Data Memory Addressing (
µ
PD780308, 780308Y)
0000H
General-purpose registers
32 × 8 bits
Internal ROM
61440 × 8 bits
LCD RAM
40 × 4 bits
F000H
EFFFH
FA58H
FA57H
FA80H
FA7FH
FEE0H
FEDFH
FF00H
FEFFH
FFFFH
Internal high-speed RAM
1024 × 8 bits
Reserved
FB00H
FAFFH
FF20H
FF1FH
FE20H
FE1FH
Special function
registers (SFRs)
256 × 8 bits SFR addressing
Register addressing
Short direct
addressing
Direct addressing
Register indirect
addressing
Based addressing
Based indexed
addressing
F800H
F7FFH
Reserved
F400H
F3FFH
Reserved
Internal expansion RAM
1024 × 8 bits
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Figure 5-6. Data Memory Addressing (
µ
PD78P0308, 78P0308Y)
0000H
General-purpose registers
32 ×8 bits
Internal PROM
61440 ×8 bits
LCD RAM
40 ×4 bits
Internal expansion RAM
1024 × 8 bits
F000H
EFFFH
FA58H
FA57H
FA80H
FA7FH
FEE0H
FEDFH
FF00H
FEFFH
FFFFH
Internal high-speed RAM
1024 ×8 bits
Reserved
FB00H
FAFFH
FF20H
FF1FH
FE20H
FE1FH
Special function
registers (SFRs)
256 ×8 bits SFR addressing
Register addressing
Short direct
addressing
Direct addressing
Register indirect
addressing
Based addressing
Based indexed
addressing
F800H
F7FFH
Reserved
Reserved
F400H
F3FFH
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5.2 Processor Registers
The
µ
PD780308 and 780308Y Subseries units incorporate the following processor registers.
5.2.1 Control registers
The control registers control the program sequence, statuses and stack memory. The control registers consist
of a program counter (PC), a program status word (PSW), and a stack pointer (SP).
(1) Program counter (PC)
The program counter is a 16-bit register which holds the address information of the next program to be
executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction
to be fetched. When a branch instruction is executed, immediate data and register contents are set.
RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.
Figure 5-7. Program Counter Configuration
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution.
Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW
instruction execution and are automatically reset upon execution of the RETB, RETI and POP PSW
instructions.
RESET input sets the PSW to 02H.
Figure 5-8. Program Status Word Configuration
(a) Interrupt enable flag (IE)
This flag controls the interrupt request acknowledge operations of the CPU.
When IE = 0, interrupt requests are disabled (DI), and all interrupts except the non-maskable interrupt
are disabled.
When IE = 1, the interrupts are enabled. At this time, acknowledging interrupt requests is controlled with
an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority
specification flag.
This flag is reset (to 0) upon DI instruction execution or interrupt acknowledgment and is set (to 1) upon
EI instruction execution.
(b) Zero flag (Z)
When the operation result is zero, this flag is set (to 1). It is reset (to 0) in all other cases.
(c) Register bank select flags (RBS0 and RBS1)
These are 2-bit flags to select one of the four register banks.
In these flags, the 2-bit information which indicates the register bank selected by SEL RBn instruction
execution is stored.
15 0
PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0PC
70
IE Z RBS1 AC RBS0 0 ISP CYPSW
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(d) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (to 1). It is reset (to 0)
in all other cases.
(e) In-service priority flag (ISP)
This flag manages the priority of acknowledgeable maskable vectored interrupt requests.
When ISP= 0, the vector interrupts assigned a low priority with the priority specify flag registers (PR0L,
PR0H, and PR1L) (refer to 20.3 (3) Priority specify flag registers (PR0L, PR0H, and PR1L)) are
acknowledge disabled. Actual acknowledgment is controlled with the interrupt enable flag (IE).
(f) Carry flag (CY)
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out
value upon rotate instruction execution and functions as a bit accumulator during bit manipulation
instruction execution.
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM
area (FB00H to FEFFH) can be set as the stack area.
Figure 5-9. Stack Pointer Configuration
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from
the stack memory.
Each stack operation saves/resets data as shown in Figures 5-10 and 5-11.
Caution Since RESET input makes SP contents indeterminate, be sure to initialize the SP before using
the stack.
Figure 5-10. Data to Be Saved to Stack Memory
15 0
SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0SP
<R>
Interrupt and
BRK instruction
PSW
PC15 to PC8
PC15 to PC8
PC7 to PC0
Register pair lower
SP SP _ 2
SP _ 2
Register pair higher
CALL, CALLF, and
CALLT instructions
PUSH rp instruction
SP _ 1
SP
SP SP _ 2
SP _ 2
SP _ 1
SP
PC7 to PC0
SP _ 3
SP _ 2
SP _ 1
SP
SP SP _ 3
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Figure 5-11. Data to Be Reset from Stack Memory
5.2.2 General-purpose registers
A general-purpose register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It consists
of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L and H).
Each register can also be used as an 8-bit register. Two 8-bit registers can be used in pairs as a 16-bit register
(AX, BC, DE and HL).
They can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE and HL) and absolute names
(R0 to R7 and RP0 to RP3).
Register banks to be used for instruction execution are set with the CPU control instruction (SEL RBn). Because
of the 4-register bank configuration, an efficient program can be created by switching between a register for normal
processing and a register for interruption for each bank.
RETI and RETB
instructions
PSW
PC15 to PC8
PC15 to PC8
PC7 to PC0
Register pair lower
SP SP + 2
SP
Register pair higher
RET instructionPOP rp instruction
SP + 1
PC7 to PC0
SP SP + 2
SP
SP + 1
SP + 2
SP
SP + 1
SP SP + 3
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Figure 5-12. General-Purpose Register Configuration
(a) Absolute name
(b) Function name
BANK0
BANK1
BANK2
BANK3
FEFFH
FEF8H
FEF7H
FEE0H
RP3
RP2
RP1
RP0
R7
15 0 7 0
R6
R5
R4
R3
R2
R1
R0
16-bit processing 8-bit processing
FEE0H
FEEFH
FEE8H
FEE7H
BANK0
BANK1
BANK2
BANK3
FEFFH
FEF8H
FEF7H
FEE0H
HL
DE
BC
AX
H
15 0 7 0
L
D
E
B
C
A
X
16-bit processing 8-bit processing
FEE0H
FEEFH
FEE8H
FEE7H
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5.2.3 Special-function register (SFR)
Unlike a general-purpose register, each special-function register has special functions.
It is allocated in the FF00H to FFFFH area.
The special-function register can be manipulated like the general-purpose register, with the operation, transfer and
bit manipulation instructions. Manipulatable bit units, 1, 8 and 16, depend on the special-function register type.
Each manipulation bit unit can be specified as follows.
•1-bit manipulation
Describe the symbol reserved with assembler for the 1-bit manipulation instruction operand (sfr.bit).
This manipulation can also be specified with an address.
•8-bit manipulation
Describe the symbol reserved with assembler for the 8-bit manipulation instruction operand (sfr).
This manipulation can also be specified with an address.
•16-bit manipulation
Describe the symbol reserved with assembler for the 16-bit manipulation instruction operand (sfrp).
When addressing an address, describe an even address.
Table 5-3 gives a list of special-function registers. The meaning of items in the table is as follows.
•Symbol
There are symbols indicating the addresses of the special function registers.
These symbols are reserved words in the RA78K0, and are defined as an sfr variable using the #pragma sfr
directive in the CC78K0. When using the RA78K0, ID78K0, or SD78K0, symbols can be written as an instruction
operand.
•R/W
Indicates whether the corresponding special-function register can be read or written.
R/W: Read/write enable
R: Read only
W: Write only
•Manipulatable bit units
“√” indicates the manipulatable bit unit (1, 8, or 16). “—” indicates a bit unit for which manipulation is not possible.
•After reset
Indicates each register status upon RESET input.
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FF00H Port 0 P0 R/W √√ — 00H
FF01H Port 1 P1 √√ —
FF02H Port 2 P2 √√ —
FF03H Port 3 P3 √√ —
FF07H Port 7 P7 √√ —
FF08H Port 8 P8 √√ —
FF09H Port 9 P9 √√ —
FF0AH Port 10 P10 √√ —
FF0BH Port 11 P11 √√ —
FF10H
FF11H
FF12H
FF13H
FF14H
FF15H
FF16H Compare register 10 CR10 — √—
FF17H Compare register 20 CR20 — √—
FF18H 8-bit timer register 1 TM1 — √
FF19H 8-bit timer register 2 TM2 — √
FF1AH Serial I/O shift register 0 SIO0 — √—
FF1FH A/D conversion result register ADCR R — √—
FF20H Port mode register 0 PM0 √√ —
FF21H Port mode register 1 PM1 √√ —
FF22H Port mode register 2 PM2 √√ —
FF23H Port mode register 3 PM3 √√ —
FF27H Port mode register 7 PM7 √√ —
FF28H Port mode register 8 PM8 √√ —
FF29H Port mode register 9 PM9 √√ —
FF2AH Port mode register 10 PM10 √√ —
FF2BH Port mode register 11 PM11 √√ —
FF40H Timer clock select register 0 TCL0 √√ — 00H
FF41H Timer clock select register 1 TCL1 — √—
FF42H Timer clock select register 2 TCL2 — √—
FF43H Timer clock select register 3 TCL3 — √— 88H
FF44H Timer clock select register 4 TCL4 — √—
FF47H Sampling clock select register SCS — √— 00H
FF48H 16-bit timer mode control register TMC0 √√ —
Table 5-3. Special-Function Register List (1/3)
8 Bits
1 Bit 16 Bits
Capture/compare register 00 CR00 — — √Undefined
Capture/compare register 01 CR01 — — √
16-bit timer register TM0 R — — √0000H
R/W Undefined
TMS R 0000H
√
R/W Undefined
R/W FFH
Address Special-Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit After Reset
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FF49H 8-bit timer mode control register TMC1 R/W √√—00H
FF4AH Watch timer mode control register TMC2 √√—
FF4CH Capture/compare control register 0 CRC0 √√—04H
FF4EH 16-bit timer output control register TOC0 √√ —00H
FF4FH 8-bit timer output control register TOC1 √√ —
FF60H Serial operating mode register 0 CSIM0 √√ —
FF61H Serial bus interface control register SBIC √√ —
FF62H Slave address register SVA —√—Undefined
FF63H Interrupt timing specify register SINT √√ —00H
FF6CH Serial operating mode register 3 CSIM3 √√ —
FF6DH Serial I/O shift register 3 SIO3 —√—Undefined
FF70H
Asynchronous serial interface mode register
ASIM √√ —00H
FF71H
Asynchronous serial interface status register
ASIS R —√—
FF72H Serial operating mode register 2 CSIM2 R/W √√ —
FF73H Baud rate generator control register BRGC —√—
FF74H Transmit shift register TXS SIO2 W —√—FFH
Receive buffer register RXB R
FF75H Serial interface pin select register SIPS R/W √√ —00H
FF80H A/D converter mode register ADM √√ —01H
FF84H A/D converter input select register ADIS —√—00H
FFB0H LCD display mode register LCDM √√ —
FFB2H LCD display control register LCDC √√ —
FFB8H Key return mode register KRM √√ —02H
FFE0H Interrupt request flag register 0L IF0 IF0L √√ √00H
FFE1H Interrupt request flag register 0H IF0H √√
FFE2H Interrupt request flag register 1L IF1L √√ —
FFE4H Interrupt mask flag register 0L MK0 MK0L √√ √FFH
FFE5H Interrupt mask flag register 0H MK0H √√
FFE6H Interrupt mask flag register 1L MK1L √√ —
FFE8H Priority order specify flag register 0L PR0 PR0L √√ √
FFE9H Priority order specify flag register 0H PR0H √√
FFEAH Priority order specify flag register 1L PR1L √√ —
FFECH External interrupt mode register 0 INTM0 —√—00H
FFEDH External interrupt mode register 1 INTM1 —√—
FFF0H Internal memory size switching register IMS —√—Note
FFF2H Oscillation mode select register OSMS W —√—00H
FFF3H Pull-up resistor option register H PUOH R/W √√ —
Table 5-3. Special-Function Register List (2/3)
Note The value after reset depends on products.
µ
PD780306, 780306Y: CCH,
µ
PD780308, 780308Y: CFH,
µ
PD78P0308, 78P0308Y: CFH
Address Special-Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit After Reset
8 Bits
1 Bit 16 Bits
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FFF4H Internal expansion RAM size switching IXS W —√—0AH
register
FFF7H Pull-up resistor option register L PUOL R/W √√ —00H
FFF9H Watchdog timer mode register WDTM √√ —
FFFAH
Oscillation stabilization time select register
OSTS —√—04H
FFFBH Processor clock control register PCC √√ —
Table 5-3. Special-Function Register List (3/3)
8 Bits
1 Bit 16 Bits
Address Special-Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit After Reset
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5.3 Instruction Address Addressing
An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each
byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is
executed. When a branch instruction is executed, the branch destination information is set to the PC and branched
by the following addressing (for details of instructions, refer to 78K/0 Series Instructions User’s Manual (U12326E)).
5.3.1 Relative addressing
[Function]
The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the
start address of the following instruction is transferred to the program counter (PC) and branched. The
displacement value is treated as signed two's complement data (–128 to +127) and bit 7 becomes a sign bit. In
other words, relative addressing consists in relative branching from the start address of the following instruction
to the –128 to +127 range.
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.
[Illustration]
15 0
PC
+
15 0
876
S
15 0
PC
α
jdisp8
When S = 0, all bits of αare 0.
When S = 1, all bits of αare 1.
PC indicates the start address
of the instruction
after the BR instruction.
...
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5.3.2 Immediate addressing
[Function]
Immediate data in the instruction word is transferred to the program counter (PC) and branched.
This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed.
CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space. The CALLF !addr11
instruction is branched to the 0800H to 0FFFH area.
[Illustration]
In the case of CALL !addr16 and BR !addr16 instructions
In the case of CALLF !addr11 instruction
15 0
PC
87
70
CALL or BR
Low Addr.
High Addr.
15 0
PC
87
70
fa
10 to 8
11 10
00001
643
CALLF
fa
7 to 0
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5.3.3 Table indirect addressing
[Function]
Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the
immediate data of an operation code are transferred to the program counter (PC) and branched.
Table indirect addressing is carried out when the CALLT [addr5] instruction is executed.
This instruction references the address stored in the memory table from 40H to 7FH, and allows branching to
the entire memory space.
[Illustration]
15 1
15 0
PC
70
Low Addr.
High Addr.
Memory (Table)
Effective address+1
Effective address 01
00000000
87
87
65 0
0
111
765 10
ta
4 to 0
Operation code
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5.3.4 Register addressing
[Function]
Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC)
and branched.
This function is carried out when the BR AX instruction is executed.
[Illustration]
70
rp
07
AX
15 0
PC
87
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5.4 Operand Address Addressing
The following various methods are available to specify the register and memory (addressing) which undergo
manipulation during instruction execution.
5.4.1 Implied addressing
[Function]
The register which functions as an accumulator (A and AX) in the general-purpose register is automatically
(implicity) addressed.
Of the
µ
PD780308 and 780308Y Subseries instruction words, the following instructions employ implied
addressing.
Instruction Register to Be Specified by Implied Addressing
MULU A register for multiplicand and AX register for product storage
DIVUW AX register for dividend and quotient storage
ADJBA/ADJBS A register for storage of numeric values which become decimal correction targets
ROR4/ROL4 A register for storage of digit data which undergoes digit rotation
[Operand format]
Because implied addressing can be automatically employed with an instruction, no particular operand format is
necessary.
[Description example]
In the case of MULU X
With an 8-bit × 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example,
the A and AX registers are specified by implied addressing.
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5.4.2 Register addressing
[Function]
The general-purpose register to be specified is accessed as an operand with the register bank select flag (RBS0
and RBS1) and with the register specify code (Rn and RPn) in an operation code.
Register addressing is carried out when an instruction with the following operand format is executed. When an
8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.
[Operand format]
Identifier Description
r X, A, C, B, E, D, L, H
rp AX, BC, DE, HL
'r' and 'rp' can be described with function names (X, A, C, B, E, D, L, H, AX, BC, DE and HL) as well as absolute
names (R0 to R7 and RP0 to RP3).
[Description example]
MOV A, C; when selecting C register as r
Operation code 01100010
INCW DE; when selecting DE register pair as rp
Operation code 10000100
Register specify code
Register specify code
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5.4.3 Direct addressing
[Function]
This addressing is to directly address the memory indicated by the immediate data in the instruction word.
[Operand format]
Identifier Description
addr16 Label or 16-bit immediate data
[Description example]
MOV A, !FE00H; when setting !addr16 to FE00H
Operation code 10001110 OP code
00000000 00H
11111110 FFH
[Illustration]
Memory
07
addr16 (lower)
addr16 (upper)
OP code
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5.4.4 Short direct addressing
[Function]
The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.
This addressing is applied to a fixed 256-byte space of FE20H to FF1FH. An internal high-speed RAM and a
special-function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
The SFR area (FF00H to FF1FH) to which short direct addressing is applied, is a part of the entire SFR area.
Ports which are frequency accessed in a program, and compare registers and capture registers of timers/event
counters are mapped to this area and these SFRs can be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH,
bit 8 is set to 1. Refer to the [Illustration] on the next page.
[Operand format]
Identifier Description
saddr Label or FE20H to FF1FH immediate data
saddrp Label or FE20H to FF1FH immediate data (even address only)
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[Description example]
MOV0 FE30H, #50H; when setting saddr to FE30H and immediate data to 50H
Operation code 00010001 OP code
00110000 30H (saddr-offset)
01010000 50H (immediate data)
[Illustration]
When 8-bit immediate data is 20H to FFH, α = 0
When 8-bit immediate data is 00H to 1FH, α = 1
15 0
Short direct memory
Effective address 1111111
87
07
OP code
saddr-offset
α
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5.4.5 Special-function register (SFR) addressing
[Function]
The memory-mapped special-function register (SFR) is addressed with 8-bit immediate data in an instruction
word.
This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR
mapped at FF00H to FF1FH can be accessed with short direct addressing.
[Operand format]
Identifier Description
sfr Special-function register name
sfrp 16-bit manipulatable special-function register name (even address only)
[Description example]
MOV PM0, A; when selecting PM0 (FF20H) as sfr
Operation code 11110110 OP code
00100000 20H (sfr-offset)
[Illustration]
15 0
SFR
Effective address 1111111
87
07
OP code
sfr-offset
1
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5.4.6 Register indirect addressing
[Function]
This addressing is to address a memory area to be manipulated by using as an operand address the contents
of a register pair specified by the register bank select flags (RBS0 and RBS1) and the register pair specification
code in the operation code.
[Operand format]
Identifier Description
—[DE], [HL]
[Description example]
MOV A, [DE]; when selecting [DE] as register pair
Operation code 10000101
[Illustration]
15 08
D
7
E
07
7 0
A
DE
Memory
The contents of the
memory addressed
are transferred.
The memory address
specified with the
register pair DE
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5.4.7 Based addressing
[Function]
This addressing is to address the memory by using the result of adding 8-bit immediate data to the contents of
the HL register pair that is used as a base register. The HL register pair to be accessed is in the register bank
specified with the register bank select flags (RBS0 and RBS1). Addition is performed by expanding the offset
data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out
for all the memory spaces.
[Operand format]
Identifier Description
—[HL + byte]
[Description example]
MOV A, [HL + 10H]; when setting byte to 10H
Operation code 10101110
00010000
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5.4.8 Based indexed addressing
[Function]
This addressing is to address the memory by using the result of adding the contents of the B or C register specified
in the instruction word to the contents of the HL register that is used as a base register. The H, B, and C registers
accessed are in the register bank specified by the register bank select flags (RBS0 and RBS1). The addition
is executed with the contents of the B or C register extended to 16 bits as a positive number. A carry from the
16th bit is ignored. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier Description
—[HL + B], [HL + C]
[Description example]
In the case of MOV A, [HL + B]
Operation code 10101011
5.4.9 Stack addressing
[Function]
The stack area is indirectly addressed with the stack pointer (SP) contents.
This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions
are executed or the register is saved/reset upon generation of an interrupt request.
Stack addressing enables to address the internal high-speed RAM area only.
[Description example]
In the case of PUSH DE
Operation code 10110101
102 User’s Manual U11377EJ3V0UD
CHAPTER 6 PORT FUNCTIONS
6.1 Port Functions
The
µ
PD780308 and 780308Y Subseries units incorporate two input ports and 55 I/O ports. Figure 6-1 shows
the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied
control operations. Besides port functions, the ports can also serve as on-chip hardware I/O pins.
Figure 6-1. Port Types
Port 9
Port 0
Port 10
Port 1
Port 2
P00
P90
P97
P100
P103
P10
P07
P17
P25
P27
Port 3
P110
P117
Port 11
P30
P37
Port 8
P80
P87
P05
Port 7
P70
P72
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Table 6-1. Port Functions (
µ
PD780308 Subseries)
Pin Name Function
Alternate Function
P00 Port 0. Input only INTP0/TI00
P01 7-bit I/O port.
Input/output mode can be specified in 1-bit
INTP1/TI01
P02 units. If used as an input port, an internal INTP2
P03 pull-up resistor can be used by software. INTP3
P04 INTP4
P05 INTP5
P07 Input only XT1
P10 to P17 Port 1. ANI0 to ANI7
8-bit I/O port. Input/output mode can be specified in 1-bit units.
If used as an input port, an internal pull-up resistor can be used by software.
P25 Port 2. SI0/SB0
P26 3-bit I/O port. Input/output mode can be specified in 1-bit units. SO0/SB1
P27 If used as an input port, an internal pull-up resistor can be used by software. SCK0
P30 Port 3. TO0
P31 8-bit I/O port. Input/output mode can be specified in 1-bit units. TO1
P32 If used as an input port, an internal pull-up resistor can be used by software. TO2
P33 TI1
P34 TI2
P35 PCL
P36 BUZ
P37 —
P70 Port 7. SI2/RxD
P71 3-bit I/O port. Input/output mode can be specified in 1-bit units. SO2/TxD
P72 If used as an input port, an internal pull-up resistor can be used by software. SCK2/ASCK
P80 to P87 Port 8. S39 to S32
8-bit I/O port. Input/output mode can be specified in 1-bit units.
If used as an input port, an internal pull-up resistor can be used by software.
This port can be used as a segment signal output port or an I/O port in 2-bit units
by setting LCD display control register (LCDC).
P90 to P97 Port 9. S31 to S24
8-bit I/O port. Input/output mode can be specified in 1-bit units.
If used as an input port, an internal pull-up resistor can be used by software.
This port can be used as a segment signal output port or an I/O port in 2-bit units
by setting LCD display control register (LCDC).
P100 to P103 Port 10. —
4-bit I/O port. Input/output mode can be specified in 1-bit units.
If used as an input port, an internal pull-up resistor can be used by software.
This port can directly drive LEDs.
P110 Port 11. SI3
P111 8-bit I/O port. Input/output mode can be specified in 1-bit units. SO3
P112 If used as an input port, an internal pull-up resistor can be used by software. SCK3
P113
Falling edge detection is possible.
TxD
P114 RxD
P115 to P117 —
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Table 6-2. Port Functions (
µ
PD780308Y Subseries)
Pin Name Function
Alternate Function
P00 Port 0. Input only INTP0/TI00
P01 7-bit I/O port.
Input/output mode can be specified in 1-bit
INTP1/TI01
P02 units. If used as an input port, an internal INTP2
P03 pull-up resistor can be used by software. INTP3
P04 INTP4
P05 INTP5
P07 Input only XT1
P10 to P17 Port 1. ANI0 to ANI7
8-bit I/O port. Input/output mode can be specified in 1-bit units.
If used as an input port, an internal pull-up resistor can be used by software.
P25 Port 2. SI0/SB0/SDA0
P26 3-bit I/O port. Input/output mode can be specified in 1-bit units. SO0/SB1/SDA1
P27 If used as an input port, an internal pull-up resistor can be used by software. SCK0/SCL
P30 Port 3. TO0
P31 8-bit I/O port. Input/output mode can be specified in 1-bit units. TO1
P32 If used as an input port, an internal pull-up resistor can be used by software. TO2
P33 TI1
P34 TI2
P35 PCL
P36 BUZ
P37 —
P70 Port 7. SI2/RxD
P71 3-bit I/O port. Input/output mode can be specified in 1-bit units. SO2/TxD
P72 If used as an input port, an internal pull-up resistor can be used by software. SCK2/ASCK
P80 to P87 Port 8. S39 to S32
8-bit I/O port. Input/output mode can be specified in 1-bit units.
If used as an input port, an internal pull-up resistor can be used by software.
This port can be used as a segment signal output port or an I/O port in 2-bit units
by setting LCD display control register (LCDC).
P90 to P97 Port 9. S31 to S24
8-bit I/O port. Input/output mode can be specified in 1-bit units.
If used as an input port, an internal pull-up resistor can be used by software.
This port can be used as a segment signal output port or an I/O port in 2-bit units
by setting LCD display control register (LCDC).
P100 to P103 Port 10. —
4-bit I/O port. Input/output mode can be specified in 1-bit units.
If used as an input port, an internal pull-up resistor can be used by software.
This port can directly drive LEDs.
P110 Port 11. SI3
P111 8-bit I/O port. Input/output mode can be specified in 1-bit units. SO3
P112 If used as an input port, an internal pull-up resistor can be used by software. SCK3
P113
Falling edge detection is possible.
TxD
P114 RxD
P115 to P117 —
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CHAPTER 6 PORT FUNCTIONS
User’s Manual U11377EJ3V0UD
6.2 Port Configuration
A port consists of the following hardware.
Table 6-3. Port Configuration
Item Configuration
Control register Port mode register (PMm: m = 0 to 3, 7 to 11)
Pull-up resistor option register (PUOH, PUOL)
Key return mode register (KRM)
Port Total: 57 ports (2 inputs, 55 inputs/outputs)
Pull-up resistor
Total: 55 (software specifiable: 55)
6.2.1 Port 0
Port 0 is a 7-bit I/O port with output latch. P01 to P05 pins can specify the input mode/output mode in 1-bit units
with port mode register 0. P00 and P07 pins are input-only ports. When P01 to P05 pins are used as input ports,
an internal pull-up resistor can be used to them in 5-bit units with pull-up resistor option register L.
Alternate functions include external interrupt request input, external count clock input to the timer and crystal
connection for subsystem clock oscillation.
RESET input sets port 0 to input mode.
Figures 6-2 and 6-3 show block diagrams of port 0.
Caution Because port 0 also serves for external interrupt request input, when the port function output
mode is specified and the output level is changed, the interrupt request flag is set. Thus, when
the output mode is used, set the interrupt mask flag to 1.
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Figure 6-2. P00 and P07 Block Diagram
Figure 6-3. P01 to P05 Block Diagram
PUO: Pull-up resistor option register
PM: Port mode register
RD: Port 0 read signal
WR: Port 0 write signal
P00/INTP0/TI00,
P07/XT1
RD
Internal bus
P-ch
WRPM
WRPORT
RD
WRPUO
VDD0
P01/INTP1/TI01,
P02/INTP2
P05/INTP5
Selector
PUO0
Output latch
(P01 to P05)
PM01 to PM05
Internal bus
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CHAPTER 6 PORT FUNCTIONS
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6.2.2 Port 1
Port 1 is an 8-bit I/O port with output latch. P10 to P17 pins can specify the input mode/output mode in 1-bit units
with port mode register 1. When P10 to P17 pins are used as input ports, an internal pull-up resistor can be used
to them in 8-bit units with pull-up resistor option register L.
Alternate functions include an A/D converter analog input.
RESET input sets port 1 to input mode.
Figure 6-4 shows a block diagram of port 1.
Caution A pull-up resistor cannot be used for pins used as A/D converter analog input.
Figure 6-4. P10 to P17 Block Diagram
PUO: Pull-up resistor option register
PM: Port mode register
RD: Port 1 read signal
WR: Port 1 write signal
P-ch
WRPM
WRPORT
RD
WRPUO
VDD0
P10/ANI0
P17/ANI7
Selector
PUO1
Output latch
(P10 to P17)
PM10 to PM17
Internal bus
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CHAPTER 6 PORT FUNCTIONS
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6.2.3 Port 2 (
µ
PD780308 Subseries)
Port 2 is a 3-bit I/O port with output latch. P25 to P27 pins can specify the input mode/output mode in 1-bit units
with port mode register 2. When P25 to P27 pins are used as input ports, an internal pull-up resistor can be used
to them in 3-bit units with pull-up resistor option register L.
Alternate functions include serial interface data I/O and clock I/O.
RESET input sets port 2 to input mode.
Figures 6-5 and 6-6 show the block diagrams of port 2.
Cautions 1. When used as a serial interface, set the I/O and output latch according to its functions. For
the setting method, refer to Figure 15-4 Serial Operating Mode Register 0 Format.
2. When reading the pin state in SBI mode, set PM2n to 1 (n = 5, 6) (refer to the description of
(10) Identifying busy status of slave in 15.4.3 SBI mode operation).
Figure 6-5. P25, P26 Block Diagram (
µ
PD780308 Subseries)
PUO: Pull-up resistor option register
PM: Port mode register
RD: Port 2 read signal
WR: Port 2 write signal
P-ch
WR
PM
WR
PORT
RD
WR
PUO
V
DD0
Selector
PUO2
Output latch
(P25 and P26)
PM25 and PM26
Internal bus
Alternate function
P25/SI0/SB0,
P26/SO0/SB1
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CHAPTER 6 PORT FUNCTIONS
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Figure 6-6. P27 Block Diagram (
µ
PD780308 Subseries)
PUO: Pull-up resistor option register
PM: Port mode register
RD: Port 2 read signal
WR: Port 2 write signal
P-ch
WRPM
WRPORT
RD
WRPUO
VDD0
Selector
PUO2
Output latch
(P27)
PM27
Internal bus
Alternate function
P27/SCK0
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6.2.4 Port 2 (
µ
PD780308Y Subseries)
Port 2 is a 3-bit I/O port with output latch. P25 to P27 pins can specify the input mode/output mode in 1-bit units
with port mode register 2. When P25 to P27 pins are used as input ports, an internal pull-up resistor can be used
to them in 3-bit units with pull-up resistor option register L.
Alternate functions include serial interface data I/O and clock I/O.
RESET input sets port 2 to input mode.
Figures 6-7 and 6-8 show the block diagrams of port 2.
Caution When used as a serial interface, set the I/O and output latch according to its functions. For the
setting method, refer to Figure 16-4 Serial Operating Mode Register 0 Format.
Figure 6-7. P25, P26 Block Diagram (
µ
PD780308Y Subseries)
PUO: Pull-up resistor option register
PM: Port mode register
RD: Port 2 read signal
WR: Port 2 write signal
P-ch
WRPM
WRPORT
RD
WRPUO
VDD0
Selector
PUO2
Output latch
(P25 and P26)
PM25 and PM26
Internal bus
Alternate function
P25/SI0/SB0/SDA0,
P26/SO0/SB1/SDA1
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Figure 6-8. P27 Block Diagram (
µ
PD780308Y Subseries)
PUO: Pull-up resistor option register
PM: Port mode register
RD: Port 2 read signal
WR: Port 2 write signal
P-ch
WRPM
WRPORT
RD
WRPUO
VDD0
Selector
PUO2
Output latch
(P27)
PM27
Internal bus
Alternate function
P27/SCK0/SCL
112
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6.2.5 Port 3
Port 3 is an 8-bit I/O port with output latch. P30 to P37 pins can specify the input mode/output mode in 1-bit units
with port mode register 3. When P30 to P37 pins are used as input ports, an internal pull-up resistor can be used
to them in 8-bit units with pull-up resistor option register L.
Alternate functions include timer I/O, clock output and buzzer output.
RESET input sets port 3 to input mode.
Figure 6-9 shows a block diagram of port 3.
Figure 6-9. P30 to P37 Block Diagram
PUO: Pull-up resistor option register
PM: Port mode register
RD: Port 3 read signal
WR: Port 3 write signal
P-ch
WR
PM
WR
PORT
RD
WR
PUO
V
DD0
Selector
PUO3
Output latch
(P30 to P37)
PM30 to PM37
Internal bus
Alternate function
P30/TO0
P32/TO2,
P33/TI1,
P34/TI2,
P35/PCL,
P36/BUZ,
P37
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6.2.6 Port 7
Port 7 is a 3-bit I/O port with output latch. P70 to P72 pins can specify the input mode/output mode in 1-bit units
with port mode register 7. When P70 to P72 pins are used as input ports, an internal pull-up resistor can be used
to them in 3-bit units with pull-up resistor option register L.
Alternate functions include serial interface channel 2 data I/O and clock I/O.
RESET input sets port 7 to input mode.
Figures 6-10 and 6-11 show the block diagrams of port 7.
Caution When used as a serial interface, set the I/O and output latch according to its functions. For the
setting method, refer to Table 17-2 Serial Interface Channel 2 Operating Mode Settings.
Figure 6-10. P70 Block Diagram
PUO: Pull-up resistor option register
PM: Port mode register
RD: Port 7 read signal
WR: Port 7 write signal
P-ch
WR
PM
WR
PORT
RD
WR
PUO
V
DD0
Selector
PUO7
Output latch
(P70)
PM70
Internal bus
P70/SI2/RxD
114
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Figure 6-11. P71 and P72 Block Diagram
PUO: Pull-up resistor option register
PM: Port mode register
RD: Port 7 read signal
WR: Port 7 write signal
P-ch
WR
PM
WR
PORT
RD
WR
PUO
V
DD0
Selector
PUO7
Output latch
(P71 and P72)
PM71 and PM72
Internal bus
Alternate function
P71/SO2/TxD,
P72/SCK2/ASCK
115
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6.2.7 Port 8
Port 8 is an 8-bit I/O port with output latch. P80 to P87 pins can specify the input mode/output mode in 1-bit units
with port mode register 8. When P80 to P87 pins are used as input ports, an internal pull-up resistor can be used
to them in 8-bit units with pull-up resistor option register H.
Alternate functions include LCD controller/driver segment signal output.
RESET input sets port 8 to input mode.
Figure 6-12 shows a block diagram of port 8.
Figure 6-12. P80 to P87 Block Diagram
PUO: Pull-up resistor option register
PM: Port mode register
RD: Port 8 read signal
WR: Port 8 write signal
P-ch
WRPM
WRPORT
RD
WRPUO
VDD0
Selector
PUO8
Output latch
(P80 to P87)
PM80 to PM87
Internal bus
P80/S39
P87/S32
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6.2.8 Port 9
Port 9 is an 8-bit I/O port with output latch. P90 to P97 pins can specify the input mode/output mode in 1-bit units
with port mode register 9. When P90 to P97 pins are used as input ports, an internal pull-up resistor can be used
to them in 8-bit units with pull-up resistor option register H.
Alternate functions include LCD controller/driver segment signal output.
RESET input sets port 9 to input mode.
Figure 6-13 shows a block diagram of port 9.
Figure 6-13. P90 to P97 Block Diagram
PUO: Pull-up resistor option register
PM: Port mode register
RD: Port 9 read signal
WR: Port 9 write signal
P-ch
WRPM
WRPORT
RD
WRPUO
VDD0
Selector
PUO9
Output latch
(P90 to P97)
PM90 to PM97
Internal bus
P90/S31
P97/S24
117
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6.2.9 Port 10
Port 10 is a 4-bit I/O port with output latch. P100 to P103 pins can specify the input mode/output mode in 1-bit
units with port mode register 10. When P100 to P103 pins are used as input ports, an internal pull-up resistor can
be used to them in 4-bit units with pull-up resistor option register H.
RESET input sets port 10 to input mode.
Figure 6-14 shows a block diagram of port 10.
Figure 6-14. P100 to P103 Block Diagram
PUO: Pull-up resistor option register
PM: Port mode register
RD: Port 10 read signal
WR: Port 10 write signal
P-ch
WR
PM
WR
PORT
RD
WR
PUO
V
DD0
Selector
PUO10
Output latch
(P100 to P103)
PM100 to PM103
Internal bus
P100 to P103
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6.2.10 Port 11
Port 11 is an 8-bit I/O port with output latch. P110 to P117 pins can specify the input mode/output mode in 1-bit
units with port mode register 11. When P110 to P117 pins are used as input ports, an internal pull-up resistor can
be used to them in 8-bit units with pull-up resistor option register H.
Alternate functions include serial interface data I/O and clock I/O.
When this function is not used, the test input flag (KRIF) can be set to 1 when the falling edge is detected on this
port.
RESET input sets port 11 to input mode.
Figures 6-15 to 6-17 show the block diagrams of port 11, and Figure 6-18 shows the falling edge detector,
respectively.
Caution When used as a serial interface, set the I/O and output latch according to its functions. For the
setting method, refer to Table 17-2 Serial Interface Channel 2 Operating Mode Settings and Figure
18-3 Serial Operating Mode Register 3 Format.
Figure 6-15. P110, P114 to P117 Block Diagram
PUO: Pull-up resistor option register
PM: Port mode register
RD: Port 11 read signal
WR: Port 11 write signal
P-ch
WRPM
WRPORT
RD
WRPUO
VDD0
Selector
PUO11
Output latch
(P110, P114 to P117)
PM110, PM114 to PM117
Internal bus
P110/SI3
P114/RxD
P115 to P117
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Figure 6-16. P111 Block Diagram
PUO: Pull-up resistor option register
PM: Port mode register
RD: Port 11 read signal
WR: Port 11 write signal
P-ch
WRPM
WRPORT
RD
WRPUO
VDD0
Selector
PUO11
Output latch
(P111)
PM111
Internal bus
Alternate function
P111/SO3
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Figure 6-17. P112 and P113 Block Diagram
PUO: Pull-up resistor option register
PM: Port mode register
RD: Port 11 read signal
WR: Port 11 write signal
Figure 6-18. Block Diagram of Falling Edge Detector
Note Selector that selects a pin used to input the falling edge
P-ch
WR
PM
WR
PORT
RD
WR
PUO
V
DD0
Selector
PUO11
Output latch
(P112 and P113)
PM112 and PM113
Internal bus
Alternate function
P112/SCK3,
P113/TxD
Standby release signal
KRIF setting signal
P110/SI3
P111/SO3
P112/SCK3
P113/T
X
D
P114/R
X
D
P115
P116
P117
Falling edge
detector
KRMK
Selector
Note
Key return mode register (KRM)
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6.3 Port Function Control Registers
The following three types of registers control the ports.
•Port mode registers (PM0 to PM3, PM7 to PM11)
•Pull-up resistor option register (PUOH, PUOL)
•Key return mode register (KRM)
(1) Port mode registers (PM0 to PM3, PM7 to PM11)
These registers are used to set port input/output in 1-bit units.
PM0 to PM3 and PM7 to PM11 are independently set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets registers to FFH.
When port pins are used as the alternate-function pins, set the port mode register and output latch according
to Table 6-4.
Cautions 1. Pins P00 and P07 are input-only pins.
2. As port 0 has an alternate function as external interrupt request input, when the port
function output mode is specified and the output level is changed, the interrupt
request flag is set. When the output mode is used, therefore, the interrupt mask flag
should be set to 1 beforehand.
3. Port 11 has a falling edge detection function. Do not specify the pin of this port to
input the falling edge in a mode other than port mode. For how to set this port to
falling edge input, refer to Figure 6-21 Key Return Mode Register Format.
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Table 6-4. Port Mode Register and Output Latch Settings When Using Alternate Functions
P00 INTP0 Input 1 (Fixed) None
TI00 Input 1 (Fixed) None
P01 INTP1 Input 1 ×
TI01 Input 1 ×
P02 to P05 INTP2 to INTP5 Input 1 ×
P07Note 1 XT1 Input 1 (Fixed) None
P10 to P17Note 1 ANI0 to ANI7 Input 1 ×
P30 to P32 TO0 to TO2 Output 0 0
P33, P34 TI1, TI2 Input 1 ×
P35 PCL Output 0 0
P36 BUZ Output 0 0
P80 to P87 S39 to S32 Output ×Note 2
P90 to P97 S31 to S24 Output ×Note 2
Alternate Functions
Name
P××PM××
I/O
Pin Name
Notes 1. If these ports are read out when these pins are used in the alternate function mode, undefined values
are read.
2. When the P80 to P87 and P90 to P97 pins are used for alternate functions, set the function by the
LCD display control register (LCDC).
Caution When port 2, port 7, and port 11 are used for serial interface, the I/O latch or output latch must
be set according to their function. For the setting methods, see Figure 15-4 Serial Operating Mode
Register 0 Format, Figure 16-4 Serial Operating Mode Register 0 Format, Table 17-2 Serial
Interface Channel 2 Operating Mode Settings, and Figure 18-3 Serial Operating Mode Register
3 Format.
Remark ×: don’t care
PM××: port mode register
P××: port output latch
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Figure 6-19. Port Mode Register Format
PM0
PM1
PM2
11PM03 PM02 PM01 1
76543210Symbol
PM3
PM8
FF20H
FF21H
FF22H
FF23H
FF28H
FFH
FFH
FFH
FFH
FFH
R/W
R/W
R/W
R/W
R/W
Address
After
Reset R/W
PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10
PM27 PM26 PM25 1 1 1 1 1
PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30
PM87 PM86 PM85 PM84 PM83 PM82 PM81 PM80
PM9
PM7
FF29H
FF27H
FFH
FFH
R/W
R/W
PM97 PM96 PM95 PM94 PM93 PM92 PM91 PM90
1 1 1 1 1 PM72 PM71 PM70
PM05 PM04
PM11
PM10
PMmn Pmn Pin I/O Mode Selection (m = 0 to 3, 7 to 11 : n = 0 to 7)
0
1
Output mode (output buffer ON)
Input mode (output buffer OFF)
FF2AH
FF2BH
FFH
FFH
R/W
R/W
PM112 PM111 PM110
1111
PM101 PM100
PM115 PM114 PM113PM117 PM116
PM103 PM102
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(2) Pull-up resistor option register (PUOH, PUOL)
This register is used to set whether to use an internal pull-up resistor at each port or not. A pull-up resistor
is internally used at bits which are set to the input mode at a port where internal pull-up resistor use has been
specified with PUOH, PUOL. No internal pull-up resistors can be used to the bits set to the output mode or
to the bits used as an analog input pin, irrespective of PUOH or PUOL setting.
PUOH and PUOL are set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Cautions 1. P00 and P07 pins do not incorporate a pull-up resistor.
2. When ports 1, 8, and 9 are used as alternate-function pins, an internal pull-up resistor
cannot be used even if 1 is set in PUOm (m = 1, 8, 9).
Figure 6-20. Pull-Up Resistor Option Register Format
Caution Zeros must be set to bits 4 to 7 of PUOH and bits 4 to 6 of PUOL.
PUO7 PUO2 PUO1 PUO0PUOL
PUOm Pm Internal Pull-up Resistor Selection (m = 0 to 3, 7 to 11)
0
1
Internal pull-up resistor not used
Internal pull-up resistor used
FFF7H 00H R/W
7654
PUO3
76 32 0
1
00
PUO11 PUO10
0
PUOH FFF3H 00H R/W
7654Symbol Address
After
Reset R/W
0
76 32 0
1
PUO9 PUO8
0
0
0
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(3) Key return mode register (KRM)
This register sets enabling/disabling of standby function release by a key return signal (falling edge detection
of port 11), and selects the port 11 falling edge input.
KRM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets KRM to 02H.
Figure 6-21. Key Return Mode Register Format
Caution When falling edge detection of port 11 is used, KRIF should be cleared to 0 (not cleared to
0 automatically).
KRIF Key Return Signal Detection Flag
0
1
Not detected
Detected (falling edge detection of port 11)
000KRM FFB8H
76 543 2Symbol 1
0KRMK KRIF
0Address
After
Reset R/W
02H R/W
KRMK Standby Mode Control by Key Return Signal
0
1
Standby mode release enabled
Standby mode release disabled
KRM3
Selection of Port 11 Falling Edge Input
0
0
P117
KRM2
0
1
1
1
0
1
P114 to P117
P112 to P117
P110 to P117
KRM3 KRM2
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6.4 Port Function Operations
Port operations differ depending on whether the input or output mode is set, as shown below.
6.4.1 Writing to I/O port
(1) Output mode
A value is written to the output latch by a transfer instruction, and the output latch contents are output from
the pin.
Once data is written to the output latch, it is retained until data is written to the output latch again.
(2) Input mode
A value is written to the output latch by a transfer instruction, but since the output buffer is OFF, the pin status
does not change.
Once data is written to the output latch, it is retained until data is written to the output latch again.
Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated
the port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output
pins, the output latch contents for pins specified as input are undefined, even for bits other
than the manipulated bit.
6.4.2 Reading from I/O port
(1) Output mode
The output latch contents are read by a transfer instruction. The output latch contents do not change.
(2) Input mode
The pin status is read by a transfer instruction. The output latch contents do not change.
6.4.3 Operations on I/O port
(1) Output mode
An operation is performed on the output latch contents, and the result is written to the output latch. The output
latch contents are output from the pins.
Once data is written to the output latch, it is retained until data is written to the output latch again.
(2) Input mode
The output latch contents are undefined, but since the output buffer is OFF, the pin status does not change.
Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated
the port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output
pins, the output latch contents for pins specified as input are undefined, even for bits other
than the manipulated bit.
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User’s Manual U11377EJ3V0UD
CHAPTER 7 CLOCK GENERATOR
7.1 Clock Generator Functions
The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two
types of system clock oscillators are available.
(1) Main system clock oscillator
This circuit oscillates at frequencies of 1 to 5.0 MHz. Oscillation can be stopped by executing the STOP
instruction or setting the processor clock control register (PCC).
(2) Subsystem clock oscillator
The circuit oscillates at a frequency of 32.768 kHz. Oscillation cannot be stopped. If the subsystem clock
oscillator is not used, not using the internal feedback resistance can be set by the processor clock control
register (PCC). This enables to decrease power consumption in the STOP mode.
7.2 Clock Generator Configuration
The clock generator consists of the following hardware.
Table 7-1. Clock Generator Configuration
Item Configuration
Control register Processor clock control register (PCC)
Oscillation mode select register (OSMS)
Oscillator Main system clock oscillator
Subsystem clock oscillator
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Figure 7-1. Clock Generator Block Diagram
Subsystem
clock
oscillator
Main
system
clock
oscillator
X2
X1
XT2
XT1/P07
FRC
STOP
MCC FRC CLS CSS PCC2 PCC1
Internal bus
Standby
controller
To INTP0
sampling clock
2
fXX 22
fXX 23
fXX 24
fXX
Prescaler
Clock to
peripheral
hardware
Prescaler
Oscillation mode
select register
Watch timer,
clock output
function
fXX
CPU clock
(fCPU)
Scaler
Selector
fX
fXT
2
fX
MCS
Processor clock control register
2
fXT
PCC0
3
Selector
1/2
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7.3 Clock Generator Control Register
The clock generator is controlled by the following two registers:
•Processor clock control register (PCC)
•Oscillation mode select register (OSMS)
(1) Processor clock control register (PCC)
The PCC sets whether to use CPU clock selection, the ratio of division, main system clock oscillator operation/
stop and subsystem clock oscillator internal feedback resistor.
The PCC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets the PCC to 04H.
Figure 7-2. Subsystem Clock Feedback Resistor
FRC
P-ch
Feedback resistor
XT1 XT2
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Figure 7-3. Processor Clock Control Register Format
Notes 1. Bit 5 is a read-only bit.
2. When the CPU is operating on the subsystem clock, MCC should be used to stop the main
system clock oscillation. A STOP instruction should not be used.
Caution Bit 3 must be set to 0.
Remarks 1. fX: Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency
3. MCS: Bit 0 of oscillation mode select register
MCC FRC CLS CSS PCC2 PCC1 PCC0PCC
CLS
0
1
Main system clock
Subsystem clock
FFFBH 04H R/W
Note 1
7654Symbol Address
After
Reset R/W
0
76 32 0
1
CSS
0
0
PCC2 CPU CIock (f
CPU
) Selection
PCC1 PCC0
CPU Clock Status
0
0
0
1
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
f
XT
/2
Setting prohibitedOther than above
FRC
0
1
Internal feedback resistor used
Internal feedback resistor not used
Subsystem Clock Feedback Resistor Selection
MCC
0
1
Oscillation possible
Oscillation stopped
Main System Clock Oscillation Control
Note 2
R/W
R/W
R/W
R
f
X
/2
f
X
/2
2
f
X
/2
3
f
X
/2
4
f
X
f
X
/2
2
f
X
/2
3
f
X
/2
4
f
X
/2
5
f
X
/2
MCS = 1 MCS = 0
0
1
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The fastest instruction of the
µ
PD780308 and 780308Y Subseries is executed with two CPU clocks. Therefore,
the relation between the CPU clock (fCPU) and the minimum instruction execution time is as shown in Table 7-2.
Table 7-2. Relation Between CPU Clock and Minimum Instruction Execution Time
CPU Clock (fCPU) Minimum Instruction Execution Time: 2/fCPU
fX0.4
µ
s
fX/2 0.8
µ
s
fX/221.6
µ
s
fX/233.2
µ
s
fX/246.4
µ
s
fX/2512.8
µ
s
fXT/2 122
µ
s
fX = 5.0 MHz, fXT = 32.768 kHz
fX: Main system clock oscillation frequency
fXT: Subsystem clock oscillation frequency
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(2) Oscillation mode select register (OSMS)
This register specifies whether the clock output from the main system clock oscillator without passing through
the scaler is used as the main system clock, or the clock output via the scaler is used as the main system
clock.
OSMS is set with an 8-bit memory manipulation instruction.
RESET input clears OSMS to 00H.
Figure 7-4. Oscillation Mode Select Register Format
Cautions 1. As shown in Figure 7-5 below, writing data (including same data as previous) to OSMS cause
delay of main system clock cycle up to 2/fX during the write operation. Therefore, if this
register is written during the operation, in peripheral hardware which operates with the main
system clock, a temporary error occurs in the count clock cycle of timer, etc. In addition,
because the oscillation mode is changed by this register, the clocks for peripheral hardware
as well as that for the CPU are switched.
Figure 7-5. Main System Clock Waveform due to Writing to OSMS
2. When writing “1” to MCS, VDD must be 2.7 V or higher before the write execution.
Remark fXX: Main system clock frequency (fX or fX/2)
fX: Main system clock oscillation frequency
MCS Main System Clock Scaler Control
0
1
Scaler used
Scaler not used
000 0OSMS FFF2H
76 543 2Symbol 1
0 MCS
0
0
Address
After
Reset R/W
00H W
0
Write to OSMS
(MCS 0)
f
XX
Max. 2/f
X
Operating at f
XX
= f
X
/2 (MCS = 0) Operating at f
XX
= f
X
/2 (MCS = 0)
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7.4 System Clock Oscillator
7.4.1 Main system clock oscillator
The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 5.0 MHz)
connected to the X1 and X2 pins.
External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the X1 pin
and an antiphase clock signal to the X2 pin.
Figure 7-6 shows an external circuit of the main system clock oscillator.
Figure 7-6. External Circuit of Main System Clock Oscillator
(a) Crystal and ceramic oscillation (b) External clock
Caution Do not execute the STOP instruction and do not set MCC to 1 if an external clock is used. This
is because the X2 pin is connected to VDD1 via a pull-up resistor.
Crystal
or
ceramic resonator
IC
X1
X2
X1
PD74HCU04
µ
X2
External
clock
V
SS1
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7.4.2 Subsystem clock oscillator
The subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1
and XT2 pins.
External clocks can be input to the subsystem clock oscillator. In this case, input a clock signal to the XT1 pin
and an antiphase clock signal to the XT2 pin.
Figure 7-7 shows an external circuit of the subsystem clock oscillator.
Figure 7-7. External Circuit of Subsystem Clock Oscillator
(a) Crystal oscillation (b) External clock
Caution 1. When using the main system clock oscillator and subsystem clock oscillator, wire as follows
in the area enclosed by broken lines in Figures 7-6 and 7-7 to avoid an adverse effect from
wiring capacitance.
●Keep the wiring length as short as possible.
●Do not cross the wiring with other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
●Always make the ground point of the oscillator capacitor the same potential as VSS1. Do
not ground the capacitor to a ground pattern through which a high current flows.
●Do not fetch signals from the oscillator.
Note that the subsystem clock oscillator is designed as a low-amplitude circuit for reducing
power consumption.
Figure 7-8 shows examples of incorrect resonator connection.
Figure 7-8. Examples of Incorrect Resonator Connection (1/2)
(a) Wiring of connection (b) Signal conductors intersect
circuits is too long each other
Remark When using a subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors
in series on the XT2 side.
IC X2 X1
VSS1
X2 X1
PORTn
(n = 0 to 3, 7 to 11)
IC
VSS1
External
clock XT1
XT2
PD74HCU04
µ
XT1
XT2
32.768
kHz
IC
VSS1
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Figure 7-8. Examples of Incorrect Resonator Connection (2/2)
(c) High fluctuating current is too near a (d) Current flows through the ground line
signal conductor of the oscillator (potential at points A, B,
and C fluctuates)
(e) Signals are fetched (f) Signal conductors of the main and subsystem
clocks are parallel and near each other
Remark When using a subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors
in series on the XT2 side.
Caution 2. In Figure 7-8 (f), XT1 and X1 are wired in parallel. Thus, the crosstalk noise of X1 may
increase with XT1, resulting in malfunctioning. To prevent that from occurring, it is
recommended to wire XT1 and X1 so that they are not in parallel.
IC X2 X1
VSS1
IC X2 X1 XT1 XT2
XT1 and X1 are wiring in parallel
VSS1
IC X2 X1
High
current
VSS1
IC X2
AB C
Pmn
V
DD0
High
current
X1
V
SS1
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7.4.3 Scaler
The scaler divides the main system clock oscillator output (fXX) and generates various clocks.
7.4.4 When no subsystem clocks are used
If it is not necessary to use subsystem clocks for low power consumption operations and clock operations,
connect the XT1 and XT2 pins as follows.
XT1 : Connect to VDD0
XT2 : Leave open
In this state, however, some current may leak via the internal feedback resistor of the subsystem clock oscillator
when the main system clock stops. To minimize leakage current, the above internal feedback resistance can be
removed with bit 6 (FRC) of the processor clock control register (PCC). In this case also, connect the XT1 and XT2
pins as described above.
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7.5 Clock Generator Operations
The clock generator generates the following types of clocks and controls the CPU operating mode including
the standby mode.
•Main system clock fXX
•Subsystem clock fXT
•CPU clock fCPU
•Clock to peripheral hardware
The following clock generator functions and operations are determined with the processor clock control register
(PCC) and the oscillation mode select register (OSMS).
(a) Upon generation of the RESET signal, the lowest speed mode of the main system clock (12.8
µ
s when operated
at 5.0 MHz) is selected (PCC = 04H, OSMS = 00H). Main system clock oscillation stops while low level is
applied to the RESET pin.
(b) With the main system clock selected, one of the six CPU clock types (0.4
µ
s. 0.8
µ
s, 1.6
µ
s, 3.2
µ
s, 6.4
µ
s,
12.8
µ
s @ 5.0 MHz) can be selected by setting the PCC and OSMS.
(c) With the main system clock selected, two standby modes, the STOP and HALT modes, are available. In a
system that does not use the subsystem clock, the power consumption in the STOP mode can be further
reduced by specifying not to use the internal feedback resistor by using bit 6 (FRC) of PCC.
(d) The PCC can be used to select the subsystem clock and to operate the system with low current consumption
(122
µ
s when operated at 32.768 kHz).
(e) With the subsystem clock selected, main system clock oscillation can be stopped with the PCC. The HALT
mode can be used. However, the STOP mode cannot be used. (Subsystem clock oscillation cannot be
stopped.)
(f) The main system clock is divided and supplied to the peripheral hardware. The subsystem clock is supplied
to the 16-bit timer/event counter, the watch timer, and clock output functions only. Thus, 16-bit timer/event
counter (when selecting watch timer output for count clock operating with subsystem clock), the watch function,
and the clock output function can also be continued in the standby state. However, since all other peripheral
hardware operates with the main system clock, the peripheral hardware also stops if the main system clock
is stopped (except external input clock operation).
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7.5.1 Main system clock operations
When operated with the main system clock (with bit 5 (CLS) of the processor clock control register (PCC) set to
0), the following operations are carried out by PCC setting.
(a) Because the operation guarantee instruction execution speed depends on the power supply voltage, the
minimum instruction execution time can be changed by bit 0 to bit 2 (PCC0 to PCC2) of the PCC.
(b) If bit 7 (MCC) of the PCC is set to 1 when operated with the main system clock, the main system clock oscillation
does not stop. When bit 4 (CSS) of the PCC is set to 1 and the operation is switched to subsystem clock
operation (CLS = 1) after that, the main system clock oscillation stops (see Figure 7-9).
Figure 7-9. Main System Clock Stop Function (1/2)
(a) Operation when MCC is set after setting CSS with main system clock operation
(b) Operation when MCC is set in case of main system clock operation
MCC
CSS
CLS
Main system clock oscillation
Subsystem clock oscillation
CPU clock
MCC
CSS
CLS
Main system clock oscillation
Subsystem clock oscillation
CPU clock
L
L
Oscillation does not stop.
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Figure 7-9. Main System Clock Stop Function (2/2)
(c) Operation when CSS is set after setting MCC with main system clock operation
7.5.2 Subsystem clock operations
When operated with the subsystem clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 1),
the following operations are carried out.
(a) The minimum instruction execution time remains constant (122
µ
s when operated at 32.768 kHz) irrespective
of bit 0 to bit 2 (PCC0 to PCC2) of the PCC.
(b) Watchdog timer counting stops.
Caution Do not execute the STOP instruction while the subsystem clock is in operation.
MCC
CSS
CLS
Main system clock oscillation
Subsystem clock oscillation
CPU clock
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7.6 Changing System Clock and CPU Clock Settings
7.6.1 Time required for switchover between system clock and CPU clock
The system clock and CPU clock can be switched over by means of bit 0 to bit 2 (PCC0 to PCC2) and bit 4 (CSS)
of the processor clock control register (PCC).
The actual switchover operation is not performed directly after writing to the PCC, but operation continues on the
pre-switchover clock for several instructions (see Table 7-3).
Determination as to whether the system is operating on the main system clock or the subsystem clock is performed
by bit 5 (CLS) of the PCC register.
Table 7-3. Maximum Time Required for CPU Clock Switchover
Set Values after Switchover
Set Values before Switchover
MCS CSS PCC2 PCC1 PCC0
CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0
00000001001000110100 1×××
×0 0 0 0 8 instructions 4 instructions 2 instructions 1 instruction 1 instruction
001
16 instructions
4 instructions 2 instructions 1 instruction 1 instruction
010
16 instructions
8 instructions 2 instructions 1 instruction 1 instruction
011
16 instructions
8 instructions 4 instructions 1 instruction 1 instruction
100
16 instructions
8 instructions 4 instructions 2 instructions 1 instruction
11 ×××
fX/2fXT instruction fX/4fXT instruction fX/8fXT instruction
fX/16fXT instruction fX/32fXT instruction
(77 instructions) (39 instructions) (20 instructions) (10 instructions) (5 instructions)
0
fX/4fXT instruction fX/8fXT instruction
fX/16fXT instruction fX/32fXT instruction fX/64fXT instruction
(39 instructions) (20 instructions) (10 instructions) (5 instructions) (3 instructions)
Caution Selection of the CPU clock cycle scaling factor (PCC0 to PCC2) and switchover from the main
system clock to the subsystem clock (changing CSS from 0 to 1) should not be performed
simultaneously. Simultaneous setting is possible, however, for selection of the CPU clock cycle
scaling factor (PCC0 to PCC2) and switchover from the subsystem clock to the main system clock
(changing CSS from 1 to 0).
Remarks 1. One instruction is the minimum instruction execution time with the pre-switchover CPU clock.
2. Figures in parentheses apply to operation with fX = 5.0 MHz and fXT = 32.768 kHz.
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(1) The CPU is reset by setting the RESET signal to low level after power-on. After that, when reset is released
by setting the RESET signal to high level, main system clock starts oscillation. At this time, oscillation
stabilization time (217/fX) is secured automatically.
After that, the CPU starts executing the instruction at the minimum speed of the main system clock (12.8
µ
s when
operated at 5.0 MHz).
(2) After the lapse of a sufficient time for the VDD voltage to increase to enable operation at maximum speeds,
the processor clock control register (PCC) and oscillation mode select register (OSMS) are rewritten and the
maximum-speed operation is carried out.
(3) Upon detection of a decrease of the VDD voltage due to an interrupt request signal, the main system clock
is switched to the subsystem clock (which must be in an oscillation stable state).
(4) Upon detection of VDD voltage reset due to an interrupt request signal, 0 is set to bit 7 of PCC (MCC) and
oscillation of the main system clock is started. After the lapse of time required for stabilization of oscillation,
the PCC and OSMS are rewritten and the maximum-speed operation is resumed.
Caution When subsystem clock is being operated while main system clock was stopped, if switching to
the main system clock is made again, be sure to switch after securing oscillation stable time by
software.
7.6.2 System clock and CPU clock switching procedure
This section describes switching procedure between system clock and CPU clock.
Figure 7-10. System Clock and CPU Clock Switching
V
DD
RESET
Interrupt
request
signal
System clock
CPU clock
Wait (26.2 ms : 5.0 MHz)
Internal reset operation
Minimum
speed
operation
Maximum speed
operation
Subsystem clock
operation
f
XX
f
XX
f
XT
f
XX
High-speed
operation
142 User’s Manual U11377EJ3V0UD
CHAPTER 8 16-BIT TIMER/EVENT COUNTER
8.1 Outline of Internal Timer of
µ
PD780308 and 780308Y Subseries
This chapter explains the 16-bit timer/event counter. Before that, the internal timer of the
µ
PD780308 and 780308Y
Subseries and related functions are briefly explained below.
(1) 16-bit timer/event counter (TM0)
TM0 can be used for an interval timer, PWM output, pulse widths measurement (infrared ray remote control
receive function), external event counter, square wave output of any frequency or one-shot pulse output.
(2) 8-bit timers/event counters 1 and 2 (TM1 and TM2)
TM1 and TM2 can be used to serve as an interval timer and an external event counter and to output square
waves with any selected frequency. Two 8-bit timer/event counters can be used as one 16-bit timer/event
counter (see CHAPTER 9 8-BIT TIMER/EVENT COUNTER).
(3) Watch timer (TM3)
This timer can set a flag every 0.5 sec. and simultaneously generates interrupt requests at the preset time
intervals (see CHAPTER 10 WATCH TIMER).
(4) Watchdog timer (WDTM)
WDTM can perform the watchdog timer function or generate non-maskable interrupt requests, maskable
interrupt requests and RESET at the preset time intervals (see CHAPTER 11 WATCHDOG TIMER).
(5) Clock output controller
This circuit supplies other devices with the divided main system clock and the subsystem clock (see CHAPTER
12 CLOCK OUTPUT CONTROLLER).
(6) Buzzer output controller
This circuit outputs the buzzer frequency obtained by dividing the main system clock (see CHAPTER 13
BUZZER OUTPUT CONTROLLER).
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Table 8-1. Timer/Event Counter Types and Functions
Interval timer 2 channelsNote 1 2 channels 1 channelNote 2 1 channelNote 3
External event counter √√——
Timer output √√——
PWM output √———
Pulse width measurement √———
Square-wave output √√——
One-shot pulse output √———
Interrupt request √√√√
Test input — — √—
Notes 1. When capture/compare registers 00 and 01 (CR00, CR01) are specified as compare registers.
2. Watch timer can perform both watch timer and interval timer functions at the same time.
3. Watchdog timer can perform either the watchdog timer function or the interval timer function.
16-bit Timer/ 8-bit Timer/Event
Event Counter Counter
Function
Type
Watch Timer Watchdog Timer
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8.2 16-bit Timer/Event Counter Functions
The 16-bit timer/event counter (TM0) has the following functions.
• Interval timer
• PWM output
• Pulse width measurement
• External event counter
• Square-wave output
• One-shot pulse output
(1) Interval timer
TM0 generates interrupt requests at the preset time interval.
Table 8-2. 16-bit Timer/Event Counter Interval Times
Minimum Interval Time Maximum Interval Time Resolution
MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0
2 × TI00 input cycle 216 × TI00 input cycle TI00 input edge cycle
—2 × 1/fX—2
16 × 1/fX— 1/fX
(400 ns) (13.1 ms) (200 ns)
2 × 1/fX22 × 1/fX216 × 1/fX217 × 1/fX1/fX2 × 1/fX
(400 ns) (800 ns) (13.1 ms) (26.2 ms) (200 ns) (400 ns)
22 × 1/fX23 × 1/fX217 × 1/fX218 × 1/fX2 × 1/fX22 × 1/fX
(800 ns) (1.6
µ
s) (26.2 ms) (52.4 ms) (400 ns) (800 ns)
23 × 1/fX24 × 1/fX218 × 1/fX219 × 1/fX22 × 1/fX23 × 1/fX
(1.6
µ
s) (3.2
µ
s) (52.4 ms) (104.9 ms) (800 ns) (1.6
µ
s)
2 × watch timer output cycle 216 × watch timer output cycle Watch timer output edge cycle
Remarks 1. fX: Main system clock oscillation frequency
2. MCS: Oscillation mode select register bit 0
3. Values in parentheses when operated at fX = 5.0 MHz
(2) PWM output
TM0 can generate 14-bit resolution PWM output.
(3) Pulse width measurement
TM0 can measure the pulse width of an externally input signal.
(4) External event counter
TM0 can measure the number of pulses of an externally input signal.
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(5) Square-wave output
TM0 can output a square wave with any selected frequency.
Table 8-3. 16-bit Timer/Event Counter Square-Wave Output Ranges
Minimum Pulse Width Maximum Pulse Width Resolution
MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0
2 × TI00 input cycle 216 × TI00 input cycle TI00 input edge cycle
—2 × 1/fX—2
16 × 1/fX— 1/fX
(400 ns) (13.1 ms) (200 ns)
2 × 1/fX22 × 1/fX216 × 1/fX217 × 1/fX1/fX2 × 1/fX
(400 ns) (800 ns) (13.1 ms) (26.2 ms) (200 ns) (400 ns)
22 × 1/fX23 × 1/fX217 × 1/fX218 × 1/fX2 × 1/fX22 × 1/fX
(800 ns) (1.6
µ
s) (26.2 ms) (52.4 ms) (400 ns) (800 ns)
23 × 1/fX24 × 1/fX218 × 1/fX219 × 1/fX22 × 1/fX23 × 1/fX
(1.6
µ
s) (3.2
µ
s) (52.4 ms) (104.9 ms) (800 ns) (1.6
µ
s)
2 × watch timer output cycle 216 × watch timer output cycle Watch timer output edge cycle
Remarks 1. fX: Main system clock oscillation frequency
2. MCS: Oscillation mode select register bit 0
3. Values in parentheses when operated at fX = 5.0 MHz
(6) One-shot pulse output
TM0 is able to output one-shot pulse which can set any width of output pulse.
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8.3 16-bit Timer/Event Counter Configuration
The 16-bit timer/event counter consists of the following hardware.
Table 8-4. 16-bit Timer/Event Counter Configuration
Item Configuration
Timer register 16 bits × 1 (TM0)
Register Capture/compare register: 16 bits × 2 (CR00, CR01)
Timer output 1 (TO0)
Control register Timer clock select register 0 (TCL0)
16-bit timer mode control register (TMC0)
Capture/compare control register 0 (CRC0)
16-bit timer output control register (TOC0)
Port mode register 3 (PM3)
External interrupt mode register 0 (INTM0)
Sampling clock select register (SCS)Note
Note For details, refer to Figure 20-1 Basic Configuration of Interrupt Function.
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Figure 8-1. 16-bit Timer/Event Counter Block Diagram
Notes 1. Edge detector
2. The configuration of the 16-bit timer/event counter output controller is shown in Figure 8-2.
Remark fXX = fX/2 (MCS = 0), fXX = fX (MCS = 1)
TCL06 TCL05 TCL04
Timer clock
select
register 0
3
Internal bus
Capture/compare
control register 0
CRC02 CRC01 CRC00
Selector
TI01/
P01/INTP1
INTTM3
2f
XX
f
XX
f
XX
/2
f
XX
/2
2
Selector
16-bit capture/compare
register 01 (CR01)
Internal bus
16-bit capture/compare
register 00 (CR00)
Clear
Match
Clear circuit
TMC03 TMC02 TMC01 OVF0 OSPT OSPETOC04 LVS0 LV R 0 TOC01 TO E0
16-bit timer mode
control register 16-bit timer output
control register
2
PWM pulse
output
controller
16-bit timer/event
counter output
controller
Note 2
TMC01 to TMC03
INTP0
INTTM01
TO0/P30
INTP1
INTTM00
Match
TMC01 to TMC03
3
16-bit timer register (TM0)
TI00/P00/
INTP0
Note 1
CRC02
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Figure 8-2. 16-bit Timer/Event Counter Output Controller Block Diagram
Remark The circuitry enclosed by the dotted line is the output controller.
PWM pulse
output controller
Edge
detector
TI00/P00/
INTP0
OSPT
16-bit timer output
control register
OSPE TOC04 LVS0 LVR0 TOC01 TOE0
Selector
Selector
INV
S
R
Q
3
Level
inversion
CRC02
INTTM01
CRC00
INTTM00
One-shot pulse
output controller
2
ES11 ES10
External interrupt
mode register 0
16-bit timer mode
control register
TMC03 TMC02 TMC01
P30 output
latch PM30
Port mode
register 3
TO0/P30
Internal bus
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(1) Capture/compare register 00 (CR00)
CR00 is a 16-bit register which has the functions of both a capture register and a compare register. Whether
it is used as a capture register or as a compare register is set by bit 0 (CRC00) of capture/compare control
register 0.
When CR00 is used as a compare register, the value set in the CR00 is constantly compared with the 16-
bit timer register (TM0) count value, and an interrupt request (INTTM00) is generated if they match. When
TM0 is set to interval timer operation, this register is used to hold the interval time. When the PWM output
operation is specified, it is used as a register that specifies a pulse width.
When CR00 is used as a capture register, it is possible to select the valid edge of the INTP0/TI00 pin or the
INTP1/TI01 pin as the capture trigger. Setting of the INTP0/TI00 or INTP1/TI01 valid edge is performed by
means of external interrupt mode register 0.
If CR00 is specified as a capture register and capture trigger is specified to be the valid edge of the INTP0/
TI00 pin, the situation is as shown in the following table.
Table 8-5. INTP0/TI00 Pin Valid Edge and CR00 Capture Trigger Valid Edge
ES11 ES10 INTP0/TI00 Pin Valid Edge CR00 Capture Trigger Valid Edge
0 0 Falling edge Rising edge
0 1 Rising edge Falling edge
1 0 Setting prohibited
1 1 Both rising and falling edges No capture operation
CR00 is set by a 16-bit memory manipulation instruction.
After RESET input, the value of CR00 is undefined.
Cautions 1. Set the data of PWM (14 bits) to the higher 4 bits of CR00. At this time, clear the lower
2 bits to 00.
2. Set a value other than 0000H to CR00. Therefore, when the 16-bit timer/event counter
is used as an event counter, the 1-pulse count operation cannot be performed.
3. If the new value of CR00 is less than the value of the 16-bit timer register (TM0), TM0
continues counting. When an overflow occurs, it counts again from 0. Therefore, if the
new value (M) of CR00 is less than the old value (N), the timer must be restarted after
changing the value of CR00.
(2) Capture/compare register 01 (CR01)
CR01 is a 16-bit register which has the functions of both a capture register and a compare register. Whether
it is used as a capture register or a compare register is set by bit 2 (CRC02) of capture/compare control register
0.
When CR01 is used as a compare register, the value set in the CR01 is constantly compared with the 16-
bit timer register (TM0) count value, and an interrupt request (INTTM01) is generated if they match.
When CR01 is used as a capture register, it is possible to select the valid edge of the INTP0/TI00 pin as the
capture trigger. Setting of the INTP0/TI00 valid edge is performed by means of external interrupt mode register
0 (INTM0).
CR01 is set with a 16-bit memory manipulation instruction.
After RESET input, the value of CR01 is undefined.
Caution If the valid edge of the TI00/P00 pin is input while CR01 is read, CR01 does not perform the
capture operation, but retains data. However, the interrupt request flag (PIF0) is set when
the valid edge is detected.
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(3) 16-bit timer register (TM0)
TM0 is a 16-bit register which counts the count pulses.
TM0 is read by a 16-bit memory manipulation instruction. When TM0 is read, capture/compare register 01
(CR01) should first be set as a capture register.
RESET input clears TM0 to 0000H.
Caution Because reading of the value of TM0 is performed via CR01, the previously set value of CR01
is lost.
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8.4 16-bit Timer/Event Counter Control Registers
The following seven types of registers are used to control the 16-bit timer/event counter.
•Timer clock select register 0 (TCL0)
•16-bit timer mode control register (TMC0)
•Capture/compare control register 0 (CRC0)
•16-bit timer output control register (TOC0)
•Port mode register 3 (PM3)
•External interrupt mode register 0 (INTM0)
•Sampling clock select register (SCS)
(1) Timer clock select register 0 (TCL0)
This register is used to set the count clock of the 16-bit timer register (TM0).
TCL0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TCL0 value to 00H.
Remark TCL0 has the function of setting the PCL output clock in addition to that of setting the count clock
of the 16-bit timer register.
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Figure 8-3. Timer Clock Select Register 0 Format
Cautions 1. Setting of the TI00/INTP0 pin valid edge is performed by external interrupt mode register
0, and selection of the sampling clock frequency is performed by the sampling clock
select register.
2. When enabling PCL output, set TCL00 to TCL03, then set 1 in CLOE with a 1-bit memory
manipulation instruction.
3. To read the count value when TI00 has been specified as the TM0 count clock, the value
should be read from TM0, not from capture/compare register 01 (CR01).
4. When rewriting TCL0 to other data, stop the timer operation beforehand.
CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00
76543210Symbol
TCL0
TCL03 TCL02 TCL01 TCL00
0000f
XT
(32.768 kHz)
0101f
X
(5.0 MHz) f
X
/2 (2.5 MHz)
0110f
X
/2
(2.5 MHz) f
X
/2
2
(1.25 MHz)
0111f
X
/2
2
(1.25 MHz) f
X
/2
3
(625 kHz)
1000f
X
/2
3
(625 kHz) f
X
/2
4
(313 kHz)
1001f
X
/2
4
(313 kHz) f
X
/2
5
(156 kHz)
1010f
X
/2
5
(156 kHz) f
X
/2
6
(78.1 kHz)
1011f
X
/2
6
(78.1 kHz) f
X
/2
7
(39.1 kHz)
1100f
X
/2
7
(39.1 kHz) f
X
/2
8
(19.5 kHz)
MCS = 1
PCL Output Clock Selection
MCS = 0
FF40H 00H R/W
Address After Reset R/W
Other than above Setting prohibited
TCL06 TCL05 TCL04
0 0 0 TI00 (Valid edge specifiable)
0 0 1 Setting prohibited f
X
(5.0 MHz)
010f
X
(5.0 MHz) f
X
/2 (2.5 MHz)
011f
X
/2 (2.5 MHz) f
X
/2
2
(1.25 MHz)
100f
X
/2
2
(1.25 MHz) f
X
/2
3
(625 kHz)
1 1 1 Watch timer output (INTTM3)
MCS = 1
16-bit Timer Register Count Clock Selection
MCS = 0
Other than above Setting prohibited
CLOE
1 Output enabled
PCL Output Control
0 Output disabled
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Remarks 1. fX: Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency
3. TI00: 16-bit timer/event counter input pin
4. TM0: 16-bit timer register
5. MCS: Bit 0 of oscillation mode select register
6. Figures in parentheses apply to operation with fX = 5.0 MHz of fXT = 32.768 kHz.
(2) 16-bit timer mode control register (TMC0)
This register sets the 16-bit timer operating mode, the 16-bit timer register clear mode and output timing, and
detects an overflow.
TMC0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TMC0 value to 00H.
Caution The 16-bit timer register starts operation at the moment a value other than 0, 0, 0 (operation
stop mode) is set in TMC01 to TMC03, respectively. Set 0, 0, 0 in TMC01 to TMC03 to stop
the operation.
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Figure 8-4. 16-bit Timer Mode Control Register Format
Cautions 1. Switch the clear mode and the T00 output timing after stopping the timer operation
(by setting TMC01 to TMC03 to 0, 0, 0).
2. Set the valid edge of the TI00/INTP0 pin with external interrupt mode register 0 and
select the sampling clock frequency with a sampling clock select register.
3. When using the PWM mode, set the PWM mode and then set data to CR00.
4. If clear & start mode on match between TM0 and CR00 is selected, when the set value
of CR00 is FFFFH and the TM0 value changes from FFFFH to 0000H, OVF0 flag is set to
1.
0000
TMC03 TMC02 TMC01
OVF0
76543210Symbol
TMC0 FF48H 00H R/W
Address After Reset R/W
OVF0 16-bit Timer Register Overflow Detection
0 Overflow not detected
1 Overflow detected
TMC03 TMC02 TMC01
Operating Mode
Clear Mode Selection TO0 Output Timing Selection Interrupt Generation
000
Operation stop
(TM0 cleared to 0) No change Not generated
001
PWM mode
(free running) PWM pulse output
010
011
100
101
110
111
Free running mode
Match between TM0 and
CR00 or match between
TM0 and CR01
Match between TM0 and
CR00, match between
TM0 and CR01 or TI00
valid edge
Match between TM0 and
CR00 or match between
TM0 and CR01
Match between TM0 and
CR00, match between
TM0 and CR01 or TI00
valid edge
Match between TM0 and
CR00 or match between
TM0 and CR01
Match between TM0 and
CR00, match between
TM0 and CR01 or TI00
valid edge
Clear & start on TI00
valid edge
Clear & start on match
between TM0 and CR00
Generated on match
between TM0 and CR00,
and match between TM0
and CR01
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Remark TO0: 16-bit timer/event counter output pin
TI00: 16-bit timer/event counter input pin
TM0: 16-bit timer register
CR00: Capture/compare register 00
CR01: Capture/compare register 01
(3) Capture/compare control register 0 (CRC0)
This register controls the operation of the capture/compare registers 00 and 01 (CR00, CR01).
CRC0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CRC0 value to 04H.
Figure 8-5. Capture/Compare Control Register 0 Format
Cautions 1. Timer operation must be stopped before setting CRC0.
2. When clear & start mode on a match between TM0 and CR00 is selected with the 16-
bit timer mode control register, CR00 should not be specified as a capture register.
0000
0 CRC02 CRC01
CRC00
76543210Symbol
CRC0 FF4CH 04H R/W
Address After Reset R/W
CRC02
CR01 Operating Mode Selection
0 Operates as compare register
1 Operates as capture register
CRC01
CR00 Capture Trigger Selection
0 Captures on valid edge of TI01
1 Captures on valid edge of TI00
CRC00
CR00 Operating Mode Selection
0 Operates as compare register
1 Operates as capture register
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(4) 16-bit timer output control register (TOC0)
This register controls the operation of the 16-bit timer/event counter output controller. It sets R-S type flip-
flop (LV0) setting/resetting, the active level in PWM mode, inversion enabling/disabling in modes other than
PWM mode, 16-bit timer/event counter timer output enabling/disabling, one-shot pulse output operation
enabling/disabling, and output trigger for a one-shot pulse by software. TOC0 is set with a 1-bit or 8-bit memory
manipulation instruction. RESET input clears TOC0 value to 00H.
Figure 8-6. 16-bit Timer Output Control Register Format
Cautions 1. Timer operation must be stopped before setting TOC0 (except OSPT).
2. If LVS0 and LVR0 are read after data is set, they will be 0.
3. OSPT is cleared automatically after data setting, and will therefore be 0 if read.
TOC04
In PWM Mode In Other Modes
Active Level Selection Timer Output F/F Control by Match of CR00 and TM0
Active high
Active low
Inversion operation disabled
Inversion operation enabled
Timer output F/F set (1)
Setting prohibited
0 OSPT OSPE TOC04
LVS0 LVR0 TOC01
TOE0
TOC0 FF4EH 00H R/W
Address After Reset R/W
OSPT Control of One-Shot Pulse Output Trigger by Software
0 One-shot pulse trigger not used
1 One-shot pulse trigger used
OSPE One-Shot Pulse Output Operation Control
0 Continuous pulse output
1 One-shot pulse output
TOC04
Timer Output F/F Control by Match of CR01 and TM0
0 Inversion operation disabled
1 Inversion operation enabled
LVS0 16-bit Timer/Event Counter Timer Output F/F Status Setting
0 No change
0 Timer output F/F reset (0)
0
1
TOE0 16-bit Timer/Event Counter Output Control
0 Output disabled (port mode)
1 Output enabled
76543210Symbol
LVR0
0
1
1
1
0
1
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(5) Port mode register 3 (PM3)
This register sets port 3 input/output in 1-bit units.
When using the P30/TO0 pin for timer output, set PM30 and output latch of P30 to 0.
PM3 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM3 value to FFH.
Figure 8-7. Port Mode Register 3 Format
PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30
PM3 FF23H FFH R/W
Address After Reset R/W
PM3n P3n Pin I/O Mode Selection (n = 0 to 7)
0 Output mode (output buffer ON)
1 Input mode (output buffer OFF)
76543210Symbol
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(6) External interrupt mode register 0 (INTM0)
This register is used to set INTP0 to INTP2 valid edges.
INTM0 is set with an 8-bit memory manipulation instruction.
RESET input clears INTM0 value to 00H.
Figure 8-8. External Interrupt Mode Register 0 Format
Caution Be sure to set bits 1 to 3 (TMC01 to TMC03) of the 16-bit timer mode control register to 0,
0, 0, and stop the timer operation before setting the valid edge of the INTP0/TI00 pin.
ES31 ES30 ES21 ES20
ES11 ES10 0
0
INTM0 FFECH 00H R/W
Address After Reset R/W
ES31 INTP2 Valid Edge Selection
0 Falling edge
0 Rising edge
76543210Symbol
1 Setting prohibited
1Both falling and rising edges
ES30
0
1
0
1
ES21 INTP1 Valid Edge Selection
0 Falling edge
0 Rising edge
1 Setting prohibited
1Both falling and rising edges
ES20
0
1
0
1
ES11 INTP0 Valid Edge Selection
0 Falling edge
0 Rising edge
1 Setting prohibited
1Both falling and rising edges
ES10
0
1
0
1
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(7) Sampling clock select register (SCS)
This register sets clocks which undergo clock sampling of valid edges to be input to INTP0. When remote
controlled reception is carried out using INTP0, digital noise is eliminated with sampling clock.
SCS is set with an 8-bit memory manipulation instruction.
RESET input clears SCS value to 00H.
Figure 8-9. Sampling Clock Select Register Format
Caution fXX/2N is the clock supplied to the CPU, and fXX/25, fXX/26, and fXX/27 are clocks supplied to
peripheral hardware. fXX/2N is stopped in HALT mode.
Remarks 1. N: Value set in bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC)
(N = 0 to 4)
2. fXX: Main system clock frequency (fX or fX/2)
3. fX: Main system clock oscillation frequency
4. MCS: Bit 0 of oscillation mode select register
5. Figures in parentheses apply to operation with fX = 5.0 MHz.
SCS1 INTP0 Sampling Clock Selection
MCS = 1 MCS = 0
f
XX
/2
N
f
X
/2
7
(39.1 kHz)
f
X
/2
6
(78.1 kHz)
f
X
/2
8
(19.5 kHz)
0 0 0 0 0 0 SCS1 SCS0
SCS FF47H 00H R/W
Address After Reset R/W
0
0
76543210Symbol
f
X
/2
7
(39.1 kHz)
f
X
/2
5
(156.3 kHz)
f
X
/2
6
(78.1 kHz)
1
1
SCS0
0
1
0
1
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8.5 16-bit Timer/Event Counter Operations
8.5.1 Interval timer operations
Setting the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) as shown
in Figure 8-10 allows operation as an interval timer. Interrupt requests are generated repeatedly using the count value
set in 16-bit capture/compare register 00 (CR00) beforehand as the interval.
When the count value of the 16-bit timer register (TM0) matches the value set to CR00, counting continues with
the TM0 value cleared to 0 and the interrupt request signal (INTTM00) is generated.
Count clock of the 16-bit timer/event counter can be selected with bits 4 to 6 (TCL04 to TCL06) of timer clock select
register 0 (TCL0).
For the operation to be performed when the value of the compare register is changed during timer count operation,
refer to 8.6 16-bit Timer/Event Counter Operating Precautions (3).
Figure 8-10. Control Register Settings for Interval Timer Operation
(a) 16-bit timer mode control register (TMC0)
(b) Capture/compare control register 0 (CRC0)
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the interval timer. See
the description of the respective control registers for details.
0 0 0 0 0 0/1 0/1 0
CRC02 CRC01 CRC00
CRC0
CR00 set as compare register
0000110/10
TMC03 TMC02 TMC01 OVF0
TMC0
Clear & start on match of TM0 and CR00
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Figure 8-11. Interval Timer Configuration Diagram
Figure 8-12. Interval Timer Operation Timings
Remark Interval time = (N + 1) × t: N = 0001H to FFFFH
16-bit capture/compare register 00 (CR00)
16-bit timer register (TM0)
Selector
f
XX
/2
2
f
XX
/2
f
XX
2f
XX
INTTM3
TI00/P00/INTP0
OVF0
Clear circuit
INTTM00
t
Count clock
TM0 count value
CR00
INTTM00
TO0
Interval time Interval time Interval time
0000 0001 N 0000 0001 N 0000 0001 N
Count start Clear Clear
NN NN
Interrupt request
acknowledge
Interrupt request
acknowledge
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Table 8-6. 16-bit Timer/Event Counter Interval Times
Minimum Interval Time Maximum Interval Time Resolution
MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0
000 2 × TI00 input cycle 216 × TI00 input cycle TI00 input edge cycle
0 0 1 Setting 2 × 1/fXSetting 216 × 1/fXSetting 1/fX
prohibited (400 ns) prohibited (13.1 ms) prohibited (200 ns)
0102 × 1/fX22 × 1/fX216 × 1/fX217 × 1/fX1/fX2 × 1/fX
(400 ns) (800 ns) (13.1 ms) (26.2 ms) (200 ns) (400 ns)
0112
2 × 1/fX23 × 1/fX217 × 1/fX218 × 1/fX2 × 1/fX22 × 1/fX
(800 ns) (1.6
µ
s) (26.2 ms) (52.4 ms) (400 ns) (800 ns)
1002
3 × 1/fX24 × 1/fX218 × 1/fX219 × 1/fX22 × 1/fX23 × 1/fX
(1.6
µ
s) (3.2
µ
s) (52.4 ms) (104.9 ms) (800 ns) (1.6
µ
s)
1112 × watch timer output cycle 216 × watch timer output cycle Watch timer output edge cycle
Other than above Setting prohibited
Remarks 1. fX: Main system clock oscillation frequency
2. MCS: Bit 0 of oscillation mode select register
3. Figures in parentheses apply to operation with fX = 5.0 MHz
8.5.2 PWM output operations
Setting the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and the 16-bit
timer output control register (TOC0) as shown in Figure 8-13 allows operation as PWM output. Pulses with the duty
rate determined by the value set in 16-bit capture/compare register 00 (CR00) beforehand are output from the TO0/
P30 pin.
Set the active level width of the PWM pulse to the higher 14 bits of CR00. Select the active level with bit 1 (TOC01)
of TOC0.
This PWM pulse has a 14-bit resolution. The pulse can be converted to an analog voltage by integrating it with
an external low-pass filter (LPF). The PWM pulse is formed by a combination of the basic cycle determined by 28/
Φ and the sub-cycle determined by 214/Φ so that the time constant of the external LPF can be shortened. Count clock
Φ can be selected with bits 4 to 6 (TCL04 to TCL06) of timer clock select register 0 (TCL0).
PWM output enable/disable can be selected with bit 0 (TOE0) of TOC0.
Cautions 1. PWM operation mode should be selected before setting CR00.
2. Be sure to write 0 to bits 0 and 1 of CR00.
3. Do not select PWM operation mode for external clock input from the TI00/P00 pin.
TCL06 TCL05 TCL04
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Figure 8-13. Control Register Settings for PWM Output Operation
(a) 16-bit timer mode control register (TMC0)
(b) Capture/compare control register 0 (CRC0)
(c) 16-bit timer output control register (TOC0)
Remarks 1. 0/1: Setting 0 or 1 allows another function to be used simultaneously with PWM output.
See the description of the respective control registers for details.
2. ×: don't care
TMC0 01000000
OVF0
TMC01TMC02TMC03
PWM mode
CRC00CRC01CRC02
CRC0 00/10/100000
CR00 set as compare register
TOE0TOC01LVR0LVS0TOC04OSPEOSPT
TOC0 10/1×××××0
TO0 output enabled
Specifies active level
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By integrating 14-bit resolution PWM pulses with an external low-pass filter, they can be converted to an analog
voltage and used for electronic tuning and D/A converter applications, etc.
The analog output voltage (VAN) used for D/A conversion with the configuration shown in Figure 8-14 is as follows.
VAN = VREF ×
216
VREF: External switching circuit reference voltage
Figure 8-14. Example of D/A Converter Configuration with PWM Output
Capture/compare register 00 (CR00) value
Figure 8-15 shows an example in which PWM output is converted to an analog voltage and used in a voltage
synthesizer type TV tuner.
Figure 8-15. TV Tuner Application Circuit Example
PD780308, 780308Y
µ
TO0/P30
V
SS0
8.2 k
Ω
8.2 k
Ω
100 pF
22 k
Ω
+110 V
2SC
2352
47 k
Ω
47 k
Ω
47 k
Ω
0.22 F
µ
0.22 F
µ
0.22 F
µ
Electronic
tuner
GND
PC574J
µ
V
SS0
Switching circuit
TO0/P30
PWM
signal
VREF
Low-pass filter Analog output (VAN)
PD780308, 780308Y
µ
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8.5.3 PPG output operations
Setting the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) as shown
in Figure 8-16 allows operation as PPG (Programmable Pulse Generator) output.
In the PPG output operation, square waves are output from the TO0/P30 pin with the pulse width and the cycle
that correspond to the count values set beforehand in 16-bit capture/compare register 01 (CR01) and in 16-bit capture/
compare register 00 (CR00), respectively.
Figure 8-16. Control Register Settings for PPG Output Operation
(a) 16-bit timer mode control register (TMC0)
(b) Capture/compare control register 0 (CRC0)
(c) 16-bit timer output control register (TOC0)
Caution Values in the following range should be set in CR00 and CR01:
0000H ≤ CR01 < CR00 ≤ FFFFH
Remark ×: don't care
TMC0 00110000
OVF0
TMC01TMC02TMC03
Clear & start on match of TM0 and CR00
CRC0 0×000000
CRC00CRC01CRC02
CR00 set as compare register
CR01 set as compare register
TOC0 110/10/11000
TOE0
TOC01LVR0LVS0
Inversion of output on match of TM0 and CR00
TOC04OSPEOSPT
TO0 output enabled
Specified TO0 output F/F initial value
Inversion of output on match of TM0 and CR01
One-shot pulse output disabled
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8.5.4 Pulse width measurement operations
It is possible to measure the pulse width of the signals input to the TI00/P00 pin and TI01/P01 pin using the
16-bit timer register (TM0).
There are two measurement methods: measuring with TM0 used in free-running mode, and measuring by
restarting the timer in synchronization with the edge of the signal input to the TI00/P00 pin.
(1) Pulse width measurement with free-running counter and one capture register
When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8-17),
and the edge specified by external interrupt mode register 0 (INTM0) is input to the TI00/P00 pin, the value
of TM0 is taken into 16-bit capture/compare register 01 (CR01) and an external interrupt request signal (INTP0)
is set.
Any of three edge specifications can be selected—rising, falling, or both edges—by means of bits 2 and 3
(ES10 and ES11) of INTM0.
For valid edge detection, sampling is performed at the interval selected by means of the sampling clock select
register (SCS), and a capture operation is only performed when a valid level is detected twice, thus eliminating
noise with a short pulse width.
Figure 8-17. Control Register Settings for Pulse Width Measurement with
Free-Running Counter and One Capture Register
(a) 16-bit timer mode control register (TMC0)
(b) Capture/compare control register 0 (CRC0)
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
See the description of the respective control registers for details.
CRC0 00/1100000
CRC00CRC01CRC02
CR00 set as compare register
CR01 set as capture register
TMC0 00/1100000
OVF0TMC01TMC02TMC03
Free-running mode
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Figure 8-18. Configuration Diagram for Pulse Width Measurement by Free-Running Counter
Figure 8-19. Timing of Pulse Width Measurement Operation by Free-Running Counter
and One Capture Register (with Both Edges Specified)
Selector
f
XX
/2
2
f
XX
/2
f
XX
2f
XX
INTTM3
16-bit timer register (TM0)
16-bit capture/compare
register 01 (CR01)
OVF0
INTP0
Internal bus
TI00/P00/INTP0
Count clock
TM0 count value
TI00 pin input
CR01 captured value
INTP0
OVF0
0000 0001 D0 D1 FFFF 0000 D2 D3
D0 D1 D2 D3
(D1 – D0) ×t (10000H – D1 + D2) ×t (D3 – D2) ×t
t
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(2) Measurement of two pulse widths with free-running counter
When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8-20),
it is possible to simultaneously measure the pulse widths of the two signals input to the TI00/P00 pin and the
TI01/P01 pin.
When the edge specified by bits 2 and 3 (ES10 and ES11) of external interrupt mode register 0 (INTM0) is
input to the TI00/P00 pin, the value of TM0 is taken into 16-bit capture/compare register 01 (CR01) and an
external interrupt request signal (INTP0) is set.
Also, when the edge specified by bits 4 and 5 (ES20 and ES21) of INTM0 is input to the TI01/P01 pin, the
value of TM0 is taken into 16-bit capture/compare register 00 (CR00) and an external interrupt request signal
(INTP1) is set.
Any of three edge specifications can be selected—rising, falling, or both edges—as the valid edges for the
TI00/P00 pin and the TI01/P01 pin by means of bits 2 and 3 (ES10 and ES11) and bits 4 and 5 (ES20 and
ES21) of INTM0, respectively.
For TI00/P00 pin valid edge detection, sampling is performed at the interval selected by means of the sampling
clock select register (SCS), and a capture operation is only performed when a valid level is detected twice,
thus eliminating noise with a short pulse width.
Figure 8-20. Control Register Settings for Two Pulse Width Measurements with Free-Running Counter
(a) 16-bit timer mode control register (TMC0)
(b) Capture/compare control register 0 (CRC0)
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
See the description of the respective control registers for details.
CRC0 10100000
CRC00CRC01CRC02
CR00 set as capture register
Captured in CR00 on valid edge of TI01/P01 Pin
CR01 set as capture register
TMC0 00/1100000
OVF0TMC01TMC02TMC03
Free-running mode
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Figure 8-21. Timing of Pulse Width Measurement Operation with
Free-Running Counter (with Both Edges Specified)
Count clock
TM0 count value
TI00 pin input
CR01 captured value
INTP0
TI01 pin input
t
CR00 captured value
INTP1
OVF0
(D1 – D0) ×t(10000H – D1 + D2) ×t
(10000H – D1 + (D2 + 1)) ×t
(D3 – D2) ×t
0000 0001 D0 D1 0000 D3D2FFFF
D0 D1 D3D2
D1
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(3) Pulse width measurement with free-running counter and two capture registers
When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8-22),
it is possible to measure the pulse width of the signal input to the TI00/P00 pin.
When the edge specified by bits 2 and 3 (ES10 and ES11) of external interrupt mode register 0 (INTM0) is
input to the TI00/P00 pin, the value of TM0 is taken into 16-bit capture/compare register 01 (CR01) and an
external interrupt request signal (INTP0) is set.
Also, on the inverse edge input of that of the capture operation into CR01, the value of TM0 is taken into 16-
bit capture/compare register 00 (CR00).
Either of two edge specifications can be selected—rising or falling—as the valid edges for the TI00/P00 pin
by means of bits 2 and 3 (ES10 and ES11) of INTM0.
For TI00/P00 pin valid edge detection, sampling is performed at the interval selected by means of the sampling
clock select register (SCS), and a capture operation is only performed when a valid level is detected twice,
thus eliminating noise with a short pulse width.
Caution If the valid edge of the TI00/P00 pin is specified to be both rising and falling edges, 16-bit
capture/compare register 00 (CR00) cannot perform the capture operation.
Figure 8-22. Control Register Settings for Pulse Width Measurement with
Free-Running Counter and Two Capture Registers
(a) 16-bit timer mode control register (TMC0)
(b) Capture/compare control register 0 (CRC0)
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
See the description of the respective control registers for details.
TMC0 00/1100000
OVF0TMC01TMC02TMC03
Free-running mode
CRC0 11100000
CRC00CRC01CRC02
CR00 set as capture register
Captured in CR00 on invalid edge of
TI00/P00 pin
CR01 set as capture register
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Figure 8-23. Timing of Pulse Width Measurement Operation by Free-Running
Counter and Two Capture Registers (with Rising Edge Specified)
Count clock
TM0 count value
TI00 pin input
CR01 captured value
CR00 captured value
INTP0
OVF0
(D1 – D0)×t (10000H – D1 + D2)×t (D3 – D2)×t
D1 D3
D0 D2
D3D20000FFFFD1D00000 0001
t
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(4) Pulse width measurement by means of restart
When input of a valid edge to the TI00/P00 pin is detected, the count value of the 16-bit timer register (TM0)
is taken into 16-bit capture/compare register 01 (CR01), and then the pulse width of the signal input to the
TI00/P00 pin is measured by clearing TM0 and restarting the count (see register settings in Figure 8-24).
The edge specification can be selected from two types, rising and falling edges by INTM0 bits 2 and 3 (ES10
and ES11).
In a valid edge detection, the sampling is performed by a cycle selected by the sampling clock select register
(SCS), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise
with a short pulse width.
Caution If the valid edge of the TI00/P00 pin is specified to be both rising and falling edges, 16-bit
capture/compare register 00 (CR00) cannot perform the capture operation.
Figure 8-24. Control Register Settings for Pulse Width Measurement by Means of Restart
(a) 16-bit timer mode control register (TMC0)
(b) Capture/compare control register 0 (CRC0)
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
See the description of the respective control registers for details.
Figure 8-25. Timing of Pulse Width Measurement Operation by
Means of Restart (with Rising Edge Specified)
TMC0 00/1010000
OVF0
TMC01TMC02TMC03
Clear & start with valid ed
g
e of TI00/P00 pin
Count clock
TM0 count value
TI00 pin input
CR01 captured value
CR00 captured value
INTP0
t
0000 0001 D0 0000 0001 D1 00010000D2
D0 D2
D1
D1 ×t
D2 ×t
CRC0 11100000
CRC00CRC01CRC02
CR00 set as capture register
Captured in CR00 on invalid
edge of TI00/P00 pin
CR01 set as capture register
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8.5.5 External event counter operation
The external event counter counts the number of external clock pulses to be input to the TI00/P00 pin with the
16-bit timer register (TM0).
TM0 is incremented each time the valid edge specified with external interrupt mode register 0 (INTM0) is input.
When the TM0 counted value matches the 16-bit capture/compare register 00 (CR00) value, TM0 is cleared to
0 and the interrupt request signal (INTTM00) is generated.
Set a value other than 0000H to CR00 (the 1-pulse count operation cannot be performed).
The rising edge, the falling edge or both edges can be selected with bits 2 and 3 (ES10 and ES11) of INTM0.
Because operation is carried out only after the valid edge is detected twice by sampling at the interval selected
with the sampling clock select register (SCS), noise with short pulse widths can be eliminated.
Figure 8-26. Control Register Settings in External Event Counter Mode
(a) 16-bit timer mode control register (TMC0)
(b) Capture/compare control register 0 (CRC0)
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the external event
counter. See the description of the respective control registers for details.
TMC0 00/1110000
OVF0TMC01TMC02TMC03
Clear & start with match of TM0 and CR00
CRC0 00/10/100000
CRC00CRC01CRC02
CR00 set as compare register
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Figure 8-27. External Event Counter Configuration Diagram
Figure 8-28. External Event Counter Operation Timings (with Rising Edge Specified)
Caution When reading the external event counter count value, TM0 should be read.
16-bit capture/compare
register 00 (CR00)
Clear INTTM00
INTP0
16-bit timer register (TM0)
16-bit capture/compare
register 01 (CR01)
Internal bus
TI00 valid edge OVF0
TI00 pin input
TM0 count value
CR00
INTTM00
N
0000 0001 0002 0003 0004 0005 N – 1 N 0000 0001 0002 0003
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8.5.6 Square-wave output operation
A square wave of any frequency is output at the interval specified by the count value set in advance to 16-bit capture/
compare register 00 (CR00).
The TO0/P30 pin output status is reversed at intervals of the count value preset to CR00 by setting bit 0 (TOE0)
and bit 1 (TOC01) of the 16-bit timer output control register (TOC0) to 1. This enables a square wave with any selected
frequency to be output.
Figure 8-29. Control Register Settings in Square-Wave Output Mode
(a) 16-bit timer mode control register (TMC0)
(b) Capture/compare control register 0 (CRC0)
(c) 16-bit timer output control register (TOC0)
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with square-wave output.
See the description of the respective control registers for details.
TMC0 00/1110000
OVF0TMC01TMC02TMC03
Clear & start on match of TM0 and CR00
CRC0 00/10/100000
CRC00CRC01CRC02
CR00 set as compare register
TOC0 110/10/10000
TOE0TOC01LVR0OSPT OSPE TOC04 LVS0
TO0 output enabled
Inversion of output on match of TM0 and CR00
Specified TO0 output F/F initial value
No inversion of output on match of TM0 and CR01
One-shot pulse output disabled
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Figure 8-30. Square-Wave Output Operation Timing
Table 8-7. 16-bit Timer/Event Count Square-Wave Output Ranges
Minimum Pulse Width Maximum Pulse Width Resolution
MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0
2 × TI00 input cycle 216 × TI00 input cycle TI00 input edge cycle
—2 × 1/fX—216 × 1/fX—1/fX
(400 ns) (13.1 ms) (200 ns)
2 × 1/fX22 × 1/fX216 × 1/fX217 × 1/fX1/fX2 × 1/fX
(400 ns) (800 ns) (13.1 ms) (26.2 ms) (200 ns) (400 ns)
22 × 1/fX23 × 1/fX217 × 1/fX218 × 1/fX2 × 1/fX22 × 1/fX
(800 ns) (1.6
µ
s) (26.2 ms) (52.4 ms) (400 ns) (800 ns)
23 × 1/fX24 × 1/fX218 × 1/fX219 × 1/fX22 × 1/fX23 × 1/fX
(1.6
µ
s) (3.2
µ
s) (52.4 ms) (104.9 ms) (800 ns) (1.6
µ
s)
2 × watch timer output cycle 216 × watch timer output cycle Watch timer output edge cycle
Remarks 1. fX: Main system clock oscillation frequency
2. MCS: Oscillation mode select register bit 0
3. Values in parentheses when operated at fX = 5.0 MHz
TI00 pin input
TM0 count value
CR00
INTTM00
TO0 pin output
0000 0001 0002 N – 1 N 0000 0001 0002 N – 1 N 0000
N
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8.5.7 One-shot pulse output operation
It is possible to output one-shot pulses synchronized with a software trigger or an external trigger (TI00/P00 pin
input).
(1) One-shot pulse output using software trigger
If the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and the 16-bit
timer output control register (TOC0) are set as shown in Figure 8-31, and 1 is set in bit 6 (OSPT) of TOC0
by software, a one-shot pulse is output from the TO0/P30 pin.
By setting 1 in OSPT, the 16-bit timer/event counter is cleared and started, and output is activated by the count
value set beforehand in 16-bit capture/compare register 01 (CR01). Thereafter, output is inactivated by the
count value set beforehand in 16-bit capture/compare register 00 (CR00).
TM0 continues to operate after one-shot pulse is output. To stop TM0, 00H must be set to TMC0.
Caution When outputting one-shot pulse, do not set 1 in OSPT. When outputting one-shot pulse
again, execute after the INTTM00, or interrupt match signal with CR00, is generated.
Figure 8-31. Control Register Settings for One-Shot Pulse Output Operation Using Software Trigger
(a) 16-bit timer mode control register (TMC0)
(b) Capture/compare control register 0 (CRC0)
(c) 16-bit timer output control register (TOC0)
Caution Values in the following range should be set in CR00 and CR01.
0000H ≤ CR01 < CR00 ≤ FFFFH
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with one-shot pulse output.
See the description of the respective control registers for details.
TMC0 00110000
OVF0TMC01TMC02TMC03
Clear & start with match of TM0 and CR00
CRC0 00/1000000
CRC00CRC01CRC02
CR00 set as compare register
CR01 set as compare register
TOC0 110/10/11100
TOE0TOC01LVR0OSPT OSPE TOC04 LVS0
TO0 output enabled
Inversion of output on match of TM0 and CR00
Specified TO0 output F/F initial value
Inversion of output on match of TM0 and CR01
One-shot pulse output mode
Set 1 in case of output
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Figure 8-32. Timing of One-Shot Pulse Output Operation Using Software Trigger
Caution The 16-bit timer register starts operation at the moment a value other than 0, 0, 0 (operation
stop mode) is set to TMC01 to TMC03, respectively.
Count clock
TM0 count value
CR01 set value
CR00 set value
INTTM01
OSPT
INTTM00
TO0 pin output
0000 0001 N N + 1 0000 N – 1 N M – 1 M 0000 0001 0002
N
M
N
M
N
M
N
M
Set 0CH to TMC0
(TM0 count start)
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(2) One-shot pulse output using external trigger
If the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and the 16-bit
timer output control register (TOC0) are set as shown in Figure 8-33, a one-shot pulse is output from the TO0/
P30 pin with a TI00/P00 valid edge as an external trigger.
Any of three edge specifications can be selected—rising, falling, or both edges — as the valid edges for the
TI00/P00 pin by means of bits 2 and 3 (ES10 and ES11) of external interrupt mode register 0 (INTM0).
When a valid edge is input to the TI00/P00 pin, the 16-bit timer/event counter is cleared and started, and output
is activated by the count values set beforehand in 16-bit capture/compare register 01 (CR01). Thereafter,
output is inactivated by the count value set beforehand in 16-bit capture/compare register 00 (CR00).
Caution When outputting one-shot pulses, external trigger is ignored if generated again.
Figure 8-33. Control Register Settings for One-Shot Pulse Output Operation Using External Trigger
(a) 16-bit timer mode control register (TMC0)
(b) Capture/compare control register 0 (CRC0)
(c) 16-bit timer output control register (TOC0)
Caution Values in the following range should be set in CR00 and CR01.
0000H ≤ CR01 < CR00 ≤ FFFFH
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with one-shot pulse output.
See the description of the respective control registers for details.
TMC0 00010000
OVF0TMC01TMC02TMC03
Clear & start with valid edge of TI00/P00 pin
CRC0 00/1000000
CRC00CRC01CRC02
CR00 set as compare register
CR01 set as compare re
g
ister
TOC0 110/10/11100
TOE0TOC01LVR0LVS0OSPT OSPE TOC04
TO0 output enabled
Inversion of output on match of TM0 and CR00
Specified TO0 output F/F initial value
Inversion of output on match of TM0 and CR01
One-shot pulse output mode
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Figure 8-34. Timing of One-Shot Pulse Output Operation Using
External Trigger (with Rising Edge Specified)
Caution The 16-bit timer register starts operation at the moment a value other than 0, 0, 0 (operation
stop mode) is set to TMC01 to TMC03, respectively.
Count clock
TM0 count value
CR01 set value
CR00 set value
INTTM01
TI00 pin input
INTTM00
TO0 pin output
0000 0001 0000 NN
+
1N
+
2M
–
2M
–
1MM
+
1M
+
2M
+
3
N
M
N
M
N
M
N
M
Set 08H to TMC0
(TM0 count start)
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8.6 16-bit Timer/Event Counter Operating Precautions
(1) Timer start errors
An error with a maximum of one clock may occur concerning the time required for a match signal to be
generated after timer start. This is because the 16-bit timer register (TM0) is started asynchronously with the
count pulse.
Figure 8-35. 16-bit Timer Register Start Timing
(2) 16-bit compare register setting
Set a value other than 0000H to 16-bit capture/compare register 00 (CR00).
Thus, when using the 16-bit capture/compare register as event counter, one-pulse count operation cannot
be carried out.
(3) Operation after compare register change during timer count operation
If the value after 16-bit capture/compare register 00 (CR00) is changed is smaller than that of the 16-bit timer
register (TM0), TM0 continues counting, overflows and then restarts counting from 0. Thus, if the value (M)
after CR00 change is smaller than that (N) before change, it is necessary to restart the timer after changing
CR00.
Figure 8-36. Timings After Change of Compare Register During Timer Count Operation
Remark N > X > M
Timer start
Count pulse
TM0 count value 0000H 0001H 0002H 0003H 0004H
Count pulse
CR00
TM0 count value X – 1 X FFFFH 0000H 0001H 0002H
MN
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(4) Capture register data retention timings
If the valid edge of the TI00/P00 pin is input during 16-bit capture/compare register 01 (CR01) read, CR01
holds data without carrying out capture operation. However, the interrupt request flag (PIF0) is set upon
detection of the valid edge.
Figure 8-37. Capture Register Data Retention Timing
(5) Valid edge setting
Set the valid edge of the TI00/INTP0 pin after setting bits 1 to 3 (TMC01 to TMC03) of the 16-bit timer mode
control register to 0, 0 and 0, respectively, and then stopping timer operation. Valid edge setting is carried
out with bits 2 and 3 (ES10 and ES11) of external interrupt mode register 0.
(6) Re-trigger of one-shot pulse
(a) One-shot pulse output using software
When outputting one-shot pulse, do not set 1 in bit 6 (OSPT) of 16-bit timer output control register (TOC0).
When outputting one-shot pulse again, execute it after the INTTM00, or interrupt match signal with 16-
bit capture/compare register 00 (CR00), is generated.
(b) One-shot pulse output using external trigger
When outputting one-shot pulses, external trigger is ignored if generated again.
Count pulse
TM0 count
value
Edge input
Interrupt
request flag
Capture
read signal
CR01
captured
value
Capture operation
ignored
X N + 1
N N + 1 N + 2 M M + 1 M + 2
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(7) Operation of OVF0 flag
OVF0 flag is set to 1 in the following case.
The clear & start mode on match between TM0 and CR00 is selected.
↓
CR00 is set to FFFFH.
↓
When TM0 is counted up from FFFFH to 0000H.
Figure 8-38. Operation Timing of OVF0 Flag
Count pulse
CR00
TM0
OVF0
INTTM00
FFFFH
FFFEH FFFFH 0000H 0001H
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9.1 8-bit Timer/Event Counter Functions
For the 8-bit timer/event counter, two modes are available. One is a mode for two-channel 8-bit timer/event counter
to be used separately (the 8-bit timer/event counter mode) and the other is a mode for the 8-bit timer/event counter
to be used as 16-bit timer/event counter (the 16-bit timer/event counter mode).
9.1.1 8-bit timer/event counter mode
8-bit timer/event counters 1 and 2 (TM1 and TM2) have the following functions.
• Interval timer
• External event counter
• Square-wave output
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CHAPTER 9 8-BIT TIMER/EVENT COUNTER
(1) 8-bit interval timer
Interrupt requests are generated at the preset time intervals.
Table 9-1. 8-bit Timer/Event Counter Interval Times
Minimum Interval Time Maximum Interval Time Resolution
MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0
2 × 1/fX22 × 1/fX29 × 1/fX210 × 1/fX2 × 1/fX22 × 1/fX
(400 ns) (800 ns) (102.4
µ
s) (204.8
µ
s) (400 ns) (800 ns)
22 × 1/fX23 × 1/fX210 × 1/fX211 × 1/fX22 × 1/fX23 × 1/fX
(800 ns) (1.6
µ
s) (204.8
µ
s) (409.6
µ
s) (800 ns) (1.6
µ
s)
23 × 1/fX24 × 1/fX211 × 1/fX212 × 1/fX23 × 1/fX24 × 1/fX
(1.6
µ
s) (3.2
µ
s) (409.6
µ
s) (819.2
µ
s) (1.6
µ
s) (3.2
µ
s)
24 × 1/fX25 × 1/fX212 × 1/fX213 × 1/fX24 × 1/fX25 × 1/fX
(3.2
µ
s) (6.4
µ
s) (819.2
µ
s) (1.64 ms) (3.2
µ
s) (6.4
µ
s)
25 × 1/fX26 × 1/fX213 × 1/fX214 × 1/fX25 × 1/fX26 × 1/fX
(6.4
µ
s) (12.8
µ
s) (1.64 ms) (3.28 ms) (6.4
µ
s) (12.8
µ
s)
26 × 1/fX27 × 1/fX214 × 1/fX215 × 1/fX26 × 1/fX27 × 1/fX
(12.8
µ
s) (25.6
µ
s) (3.28 ms) (6.55 ms) (12.8
µ
s) (25.6
µ
s)
27 × 1/fX28 × 1/fX215 × 1/fX216 × 1/fX27 × 1/fX28 × 1/fX
(25.6
µ
s) (51.2
µ
s) (6.55 ms) (13.1 ms) (25.6
µ
s) (51.2
µ
s)
28 × 1/fX29 × 1/fX216 × 1/fX217 × 1/fX28 × 1/fX29 × 1/fX
(51.2
µ
s) (102.4
µ
s) (13.1 ms) (26.2 ms) (51.2
µ
s) (102.4
µ
s)
29 × 1/fX210 × 1/fX217 × 1/fX218 × 1/fX29 × 1/fX210 × 1/fX
(102.4
µ
s) (204.8
µ
s) (26.2 ms) (52.4 ms) (102.4
µ
s) (204.8
µ
s)
211 × 1/fX212 × 1/fX219 × 1/fX220 × 1/fX211 × 1/fX212 × 1/fX
(409.6
µ
s) (819.2
µ
s) (104.9 ms) (209.7 ms) (409.6
µ
s) (819.2
µ
s)
Remarks 1. fX: Main system clock oscillation frequency
2. MCS: Oscillation mode select register bit 0
3. Values in parentheses when operated at fX = 5.0 MHz.
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(2) External event counter
The number of pulses of an externally input signal can be measured.
(3) Square-wave output
A square wave with any selected frequency can be output.
Table 9-2. 8-bit Timer/Event Counter Square-Wave Output Ranges
Minimum Pulse Width Maximum Pulse Width Resolution
MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0
2 × 1/fX22 × 1/fX29 × 1/fX210 × 1/fX2 × 1/fX22 × 1/fX
(400 ns) (800 ns) (102.4
µ
s) (204.8
µ
s) (400 ns) (800 ns)
22 × 1/fX23 × 1/fX210 × 1/fX211 × 1/fX22 × 1/fX23 × 1/fX
(800 ns) (1.6
µ
s) (204.8
µ
s) (409.6
µ
s) (800 ns) (1.6
µ
s)
23 × 1/fX24 × 1/fX211 × 1/fX212 × 1/fX23 × 1/fX24 × 1/fX
(1.6
µ
s) (3.2
µ
s) (409.6
µ
s) (819.2
µ
s) (1.6
µ
s) (3.2
µ
s)
24 × 1/fX25 × 1/fX212 × 1/fX213 × 1/fX24 × 1/fX25 × 1/fX
(3.2
µ
s) (6.4
µ
s) (819.2
µ
s) (1.64 ms) (3.2
µ
s) (6.4
µ
s)
25 × 1/fX26 × 1/fX213 × 1/fX214 × 1/fX25 × 1/fX26 × 1/fX
(6.4
µ
s) (12.8
µ
s) (1.64 ms) (3.28 ms) (6.4
µ
s) (12.8
µ
s)
26 × 1/fX27 × 1/fX214 × 1/fX215 × 1/fX26 × 1/fX27 × 1/fX
(12.8
µ
s) (25.6
µ
s) (3.28 ms) (6.55 ms) (12.8
µ
s) (25.6
µ
s)
27 × 1/fX28 × 1/fX215 × 1/fX216 × 1/fX27 × 1/fX28 × 1/fX
(25.6
µ
s) (51.2
µ
s) (6.55 ms) (13.1 ms) (25.6
µ
s) (51.2
µ
s)
28 × 1/fX29 × 1/fX216 × 1/fX217 × 1/fX28 × 1/fX29 × 1/fX
(51.2
µ
s) (102.4
µ
s) (13.1 ms) (26.2 ms) (51.2
µ
s) (102.4
µ
s)
29 × 1/fX210 × 1/fX217 × 1/fX218 × 1/fX29 × 1/fX210 × 1/fX
(102.4
µ
s) (204.8
µ
s) (26.2 ms) (52.4 ms) (102.4
µ
s) (204.8
µ
s)
211 × 1/fX212 × 1/fX219 × 1/fX220 × 1/fX211 × 1/fX212 × 1/fX
(409.6
µ
s) (819.2
µ
s) (104.9 ms) (209.7 ms) (409.6
µ
s) (819.2
µ
s)
Remarks 1. fX: Main system clock oscillation frequency
2. MCS: Oscillation mode select register bit 0
3. Values in parentheses when operated at fX = 5.0 MHz.
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9.1.2 16-bit timer/event counter mode
(1) 16-bit interval timer
Interrupt requests can be generated at the preset time intervals.
Table 9-3. Interval Times When 8-bit Timer/Event Counter
Is Used as 16-bit Timer/Event Counter
Minimum Interval Time Maximum Interval Time Resolution
MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0
2 × 1/fX22 × 1/fX217 × 1/fX218 × 1/fX2 × 1/fX22 × 1/fX
(400 ns) (800 ns) (26.2 ms) (52.4 ms) (400 ns) (800 ns)
22 × 1/fX23 × 1/fX218 × 1/fX219 × 1/fX22 × 1/fX23 × 1/fX
(800 ns) (1.6
µ
s) (52.4 ms) (104.9 ms) (800 ns) (1.6
µ
s)
23 × 1/fX24 × 1/fX219 × 1/fX220 × 1/fX23 × 1/fX24 × 1/fX
(1.6
µ
s) (3.2
µ
s) (104.9 ms) (209.7 ms) (1.6
µ
s) (3.2
µ
s)
24 × 1/fX25 × 1/fX220 × 1/fX221 × 1/fX24 × 1/fX25 × 1/fX
(3.2
µ
s) (6.4
µ
s) (209.7 ms) (419.4 ms) (3.2
µ
s) (6.4
µ
s)
25 × 1/fX26 × 1/fX221 × 1/fX222 × 1/fX25 × 1/fX26 × 1/fX
(6.4
µ
s) (12.8
µ
s) (419.4 ms) (838.9 ms) (6.4
µ
s) (12.8
µ
s)
26 × 1/fX27 × 1/fX222 × 1/fX223 × 1/fX26 × 1/fX27 × 1/fX
(12.8
µ
s) (25.6
µ
s) (838.9 ms) (1.7 s) (12.8
µ
s) (25.6
µ
s)
27 × 1/fX28 × 1/fX223 × 1/fX224 × 1/fX27 × 1/fX28 × 1/fX
(25.6
µ
s) (51.2
µ
s) (1.7 s) (3.4 s) (25.6
µ
s) (51.2
µ
s)
28 × 1/fX29 × 1/fX224 × 1/fX225 × 1/fX28 × 1/fX29 × 1/fX
(51.2
µ
s) (102.4
µ
s) (3.4 s) (6.7 s) (51.2
µ
s) (102.4
µ
s)
29 × 1/fX210 × 1/fX225 × 1/fX226 × 1/fX29 × 1/fX210 × 1/fX
(102.4
µ
s) (204.8
µ
s) (6.7 s) (13.4 s) (102.4
µ
s) (204.8
µ
s)
211 × 1/fX212 × 1/fX227 × 1/fX228 × 1/fX211 × 1/fX212 × 1/fX
(409.6
µ
s) (819.2
µ
s) (26.8 s) (53.7 s) (409.6
µ
s) (819.2
µ
s)
Remarks 1. fX: Main system clock oscillation frequency
2. MCS: Oscillation mode select register bit 0
3. Values in parentheses when operated at fX = 5.0 MHz.
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(2) External event counter
The number of pulses of an externally input signal can be measured.
(3) Square-wave output
A square wave with any selected frequency can be output.
Table 9-4. Square-Wave Output Ranges When 8-bit Timer/Event
Counter Is Used as 16-bit Timer/Event Counter
Minimum Pulse Width Maximum Pulse Width Resolution
MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0
2 × 1/fX22 × 1/fX217 × 1/fX218 × 1/fX2 × 1/fX22 × 1/fX
(400 ns) (800 ns) (26.2 ms) (52.4 ms) (400 ns) (800 ns)
22 × 1/fX23 × 1/fX218 × 1/fX219 × 1/fX22 × 1/fX23 × 1/fX
(800 ns) (1.6
µ
s) (52.4 ms) (104.9 ms) (800 ns) (1.6
µ
s)
23 × 1/fX24 × 1/fX219 × 1/fX220 × 1/fX23 × 1/fX24 × 1/fX
(1.6
µ
s) (3.2
µ
s) (104.9 ms) (209.7 ms) (1.6
µ
s) (3.2
µ
s)
24 × 1/fX25 × 1/fX220 × 1/fX221 × 1/fX24 × 1/fX25 × 1/fX
(3.2
µ
s) (6.4
µ
s) (209.7 ms) (419.4 ms) (3.2
µ
s) (6.4
µ
s)
25 × 1/fX26 × 1/fX221 × 1/fX222 × 1/fX25 × 1/fX26 × 1/fX
(6.4
µ
s) (12.8
µ
s) (419.4 ms) (838.9 ms) (6.4
µ
s) (12.8
µ
s)
26 × 1/fX27 × 1/fX222 × 1/fX223 × 1/fX26 × 1/fX27 × 1/fX
(12.8
µ
s) (25.6
µ
s) (838.9 ms) (1.7 s) (12.8
µ
s) (25.6
µ
s)
27 × 1/fX28 × 1/fX223 × 1/fX224 × 1/fX27 × 1/fX28 × 1/fX
(25.6
µ
s) (51.2
µ
s) (1.7 s) (3.4 s) (25.6
µ
s) (51.2
µ
s)
28 × 1/fX29 × 1/fX224 × 1/fX225 × 1/fX28 × 1/fX29 × 1/fX
(51.2
µ
s) (102.4
µ
s) (3.4 s) (6.7 s) (51.2
µ
s) (102.4
µ
s)
29 × 1/fX210 × 1/fX225 × 1/fX226 × 1/fX29 × 1/fX210 × 1/fX
(102.4
µ
s) (204.8
µ
s) (6.7 s) (13.4 s) (102.4
µ
s) (204.8
µ
s)
211 × 1/fX212 × 1/fX227 × 1/fX228 × 1/fX211 × 1/fX212 × 1/fX
(409.6
µ
s) (819.2
µ
s) (26.8 s) (53.7 s) (409.6
µ
s) (819.2
µ
s)
Remarks 1. fX: Main system clock oscillation frequency
2. MCS: Oscillation mode select register bit 0
3. Values in parentheses when operated at fX = 5.0 MHz.
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9.2 8-bit Timer/Event Counter Configuration
The 8-bit timer/event counter consists of the following hardware.
Table 9-5. 8-bit Timer/Event Counter Configuration
Item Configuration
Timer register 8 bits × 2 (TM1, TM2)
Register Compare register: 8 bits × 2 (CR10, CR20)
Timer output 2 (TO1, TO2)
Control register Timer clock select register 1 (TCL1)
8-bit timer mode control register 1 (TMC1)
8-bit timer output control register (TOC1)
Port mode register 3 (PM3)Note
Note For details, refer to Figure 6-9 P30 to P37 Block Diagram.
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Figure 9-1. 8-bit Timer/Event Counter Block Diagram
Note Refer to Figures 9-2 and 9-3 for details of 8-bit timer/event counter output controllers 1 and 2, respectively.
Remark fXX = fX/2 (MCS = 0), fXX = fX (MCS = 1)
Selector
Clear
Selector
Selector
f
XX
/2 to f
XX
/2
9
f
XX
/2
11
TI1/P33
f
XX
/2 to f
XX
/2
9
f
XX
/2
11
TI2/P34
4
TMC
12 TCE2 TCE1
Internal bus
8-bit timer/
event counter
output
controller 2
Note
INTTM1
TO2/P32
INTTM2
TO1/P31
4
TCL
17
TCL
16
TCL
15
TCL
14
TCL
13
TCL
12
TCL
11
TCL
10
Timer clock
select register 1
Selector
Selector
8-bit compare
register 10
(CR10)
Match
8-bit timer
register 1
(TM1)
4
8-bit timer
register 2
(TM2)
Match
8-bit compare
register 20
(CR20)
Clear
LVS2 LVR2 TOC
15 TOE2 LVS1 LVR1 TOC
11 TOE1
8-bit timer output
control register
Internal bus
8-bit timer mode
control register
8-bit timer/
event counter
output
controller 1
Note
4
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Figure 9-2. Block Diagram of 8-bit Timer/Event Counter Output Controller 1
Remark The section in the broken line is an output controller.
Figure 9-3. Block Diagram of 8-bit Timer/Event Counter Output Controller 2
Remarks 1. The section in the broken line is an output controller.
2. fSCK: Serial clock frequency
LVR1
LVS1
TOC11
INTTM1
R
S
INV
Q
P31
output latch
TOE1
PM31
TO1/P31
Level F/F
(LV1)
LVR2
LVS2
TOC15
INTTM2
R
S
INV
Level F/F
(LV2) fSCK
P32
output latch
PM32
TOE2
TO2/P32
Q
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(1) Compare registers 10 and 20 (CR10, CR20)
These are 8-bit registers to compare the value set to CR10 to the 8-bit timer register 1 (TM1) count value,
and the value set to CR20 to the 8-bit timer register 2 (TM2) count value, and, if they match, generate an
interrupt request (INTTM1 and INTTM2, respectively).
When TM1 and TM2 are set to interval timer operation, these registers are used to hold the interval time. When
the PWM output operation is specified, they are used as registers that specify a pulse width.
CR10 and CR20 are set with an 8-bit memory manipulation instruction. They cannot be set with a 16-bit
memory manipulation instruction. When the compare register is used as an 8-bit timer/event counter, the 00H
to FFH values can be set. When the compare register is used as a 16-bit timer/event counter, the 0000H to
FFFFH values can be set.
RESET input makes CR10 and CR20 undefined.
Caution When using the compare register as 16-bit timer/event counter, be sure to set data after
stopping timer operation.
(2) 8-bit timer registers 1, 2 (TM1, TM2)
These are 8-bit registers to count count pulses.
When TM1 and TM2 are used in the 8-bit timer × 2-channel mode, they are read with an 8-bit memory
manipulation instruction. When TM1 and TM2 are used in 16-bit timer × 1-channel mode, the 16-bit timer (TMS)
is read with a 16-bit memory manipulation instruction.
RESET input clears TM1 and TM2 to 00H.
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9.3 8-bit Timer/Event Counter Control Registers
The following four types of registers are used to control the 8-bit timer/event counter.
•Timer clock select register 1 (TCL1)
•8-bit timer mode control register 1 (TMC1)
•8-bit timer output control register (TOC1)
•Port mode register 3 (PM3)
(1) Timer clock select register 1 (TCL1)
This register sets count clocks of 8-bit timer registers 1 and 2.
TCL1 is set with an 8-bit memory manipulation instruction.
RESET input clears TCL1 to 00H.
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Figure 9-4. Timer Clock Select Register 1 Format
Caution When rewriting TCL1 to other data, stop the timer operation beforehand.
Remarks 1. fX: Main system clock oscillation frequency
2. TI1: 8-bit timer register 1 input pin
3. TI2: 8-bit timer register 2 input pin
4. MCS: Oscillation mode select register bit 0
5. Figures in parentheses apply to operation with fX = 5.0 MHz
TCL17 TCL16 TCL15 TCL14 TCL13 TCL12 TCL11 TCL10
76543210Symbol
TCL1 FF41H 00H R/W
Address After Reset R/W
TCL13 TCL12 TCL11 TCL10
0 0 0 0 TI1 falling edge
0 0 0 1 TI1 rising edge
0110
0111
fX/2 (2.5 MHz) fX/22(1.25 MHz)
1000
fX/22 (1.25 MHz) fX/23(625 kHz)
1001
fX/23(625 kHz) fX/24(313 kHz)
1010
fX/24(313 kHz) fX/25(156 kHz)
1011
fX/25(156 kHz) fX/26(78.1 kHz)
1100
fX/26(78.1 kHz) fX/27(39.1 kHz)
1101
fX/27(39.1 kHz) fX/28(19.5 kHz)
1110
fX/28(19.5 kHz) fX/29(9.8 kHz)
1111
fX/29(9.8 kHz) fX/210 (4.9 kHz)
MCS = 1
8-bit Timer Register 1 Count Clock Selection
MCS = 0
Other than above Setting prohibited
fX/211 (2.4 kHz) fX/212 (1.2 kHz)
TCL17 TCL16 TCL15 TCL14
0 0 0 0 TI2 falling edge
0 0 0 1 TI2 rising edge
0110
0111
fX/2 (2.5 MHz) fX/22(1.25 MHz)
1000
fX/22 (1.25 MHz) fX/23(625 kHz)
1001
fX/23(625 kHz) fX/24(313 kHz)
1010
fX/24(313 kHz) fX/25(156 kHz)
1011
fX/25(156 kHz) fX/26(78.1 kHz)
1100
fX/26(78.1 kHz) fX/27(39.1 kHz)
1101
fX/27(39.1 kHz) fX/28(19.5 kHz)
1110
fX/28(19.5 kHz) fX/29(9.8 kHz)
1111
fX/29(9.8 kHz) fX/210 (4.9 kHz)
MCS = 1
8-bit Timer Register 2 Count Clock Selection
MCS = 0
Other than above Setting prohibited
fX/211 (2.4 kHz) fX/212 (1.2 kHz)
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(2) 8-bit timer mode control register (TMC1)
This register enables/stops operation of 8-bit timer registers 1 and 2 and sets the operating mode of 8-bit timer
registers 1 and 2.
TMC1 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TMC1 to 00H.
Figure 9-5. 8-bit Timer Mode Control Register Format
Cautions 1. Switch the operating mode after stopping timer operation.
2. When used as 16-bit timer register, TCE1 should be used for operation enable/stop.
00000
TMC12
TCE2 TCE1
TMC1 FF49H 00H R/W
Address After Reset R/W
TMC12
Operating Mode Selection
0 8-bit timer register × 2 channel mode (TM1, TM2)
1 16-bit timer register × 1 channel mode (TMS)
TCE2 8-bit Timer Register 2 Operation Control
0 Operation stop (TM2 clear to 0)
1 Operation enable
TCE1 8-bit Timer Register 1 Operation Control
0 Operation stop (TM1 clear to 0)
1 Operation enable
76543210Symbol
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(3) 8-bit timer output control register (TOC1)
This register controls operation of 8-bit timer/event counter output controllers 1 and 2.
It sets/resets the R-S flip-flops (LV1 and LV2) and enables/disables inversion and timer output of 8-bit timer
registers 1 and 2.
TOC1 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TOC1 to 00H.
Figure 9-6. 8-bit Timer Output Control Register Format
Cautions 1. Be sure to set TOC1 after stopping timer operation.
2. LVS1, LVS2, LVR1 and LVR2 are 0 when read after data setting to them.
Timer output F/F set (to 1)
Setting prohibited
LVS2 LVR2
TOC15
TOE2
LVS1 LVR1 TOC11
TOE1
TOC1 FF4FH 00H R/W
Address After Reset R/W
TOC15
8-bit Timer/Event Counter 2 Timer Output F/F Control
0 Inverted operation disable
1 Inverted operation enable
TOE2 8-bit Timer/Event Counter 2 Output Control
0 Output disable (port mode)
1 Output enable
LVS1 8-bit Timer/Event Counter 1 Timer Output F/F Status Set
0 Unchanged
0 Timer output F/F reset (to 0)
76543210Symbol
LVR1
0
1
1
1
0
1
TOC11 8-bit Timer/Event Counter 1 Timer Output F/F Control
0 Inverted operation disable
1 Inverted operation enable
TOE1 8-bit Timer/Event Counter 1 Outptut Control
0 Output disable (port mode)
1 Output enable
Timer output F/F set (to 1)
Setting prohibited
LVS2 8-bit Timer/Event Counter 2 Timer Output F/F Status Set
0 Unchanged
0 Timer output F/F reset (to 0)
LVR2
0
1
1
1
0
1
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(4) Port mode register 3 (PM3)
This register sets port 3 input/output in 1-bit units.
When using the P31/TO1 and P32/TO2 pins for timer output, set PM31, PM32, and output latches of P31 and
P32 to 0.
PM3 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM3 to FFH.
Figure 9-7. Port Mode Register 3 Format
PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30
PM3 FF23H FFH R/W
Address After Reset R/W
PM3n P3n Pin I/O Mode Selection (n = 0 to 7)
0 Output mode (output buffer ON)
1 Input mode (output buffer OFF)
76543210Symbol
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9.4 8-bit Timer/Event Counter Operations
9.4.1 8-bit timer/event counter mode
(1) Interval timer operations
The 8-bit timer/event counter operates as an interval timer which generates interrupt requests repeatedly at
intervals of the count value preset to 8-bit compare registers 10 and 20 (CR10 and CR20).
When the count values of 8-bit timer registers 1 and 2 (TM1 and TM2) match the values set to CR10 and CR20,
counting continues with the TM1 and TM2 values cleared to 0 and the interrupt request signals (INTTM1 and
INTTM2) are generated.
Count clock of TM1 can be selected with bits 0 to 3 (TCL10 to TCL13) of timer clock select register 1 (TCL1).
Count clock of TM2 can be selected with bits 4 to 7 (TCL14 to TCL17) of timer clock select register 1 (TCL1).
For the operation to be performed when the value of the compare register is changed during timer count
operation, refer to 9.5 8-bit Timer/Event Counter Precautions (3).
Figure 9-8. Interval Timer Operation Timings
Remark Interval time = (N + 1) × t: N = 00H to FFH
Count clock
TM1 count value
INTTM1
CR10
TO1
Interval time Interval time Interval time
Interrupt request
acknowledge
Interrupt request
acknowledge
NNNN
Count start Clear Clear
t
00 01 N 00 01 N 00 01 N
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Table 9-6. 8-bit Timer/Event Counter 1 Interval Time
Minimum Interval Time Maximum Interval Time Resolution
MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0
0000 TI1 input cycle 28 × TI1 input cycle TI1 input edge cycle
0001 TI1 input cycle 28 × TI1 input cycle TI1 input edge cycle
2 × 1/fX22 × 1/fX29 × 1/fX210 × 1/fX2 × 1/fX22 × 1/fX
(400 ns) (800 ns) (102.4
µ
s) (204.8
µ
s) (400 ns) (800 ns)
22 × 1/fX23 × 1/fX210 × 1/fX211 × 1/fX22 × 1/fX23 × 1/fX
(800 ns) (1.6
µ
s) (204.8
µ
s) (409.6
µ
s) (800 ns) (1.6
µ
s)
23 × 1/fX24 × 1/fX211 × 1/fX212 × 1/fX23 × 1/fX24 × 1/fX
(1.6
µ
s) (3.2
µ
s) (409.6
µ
s) (819.2
µ
s) (1.6
µ
s) (3.2
µ
s)
24 × 1/fX25 × 1/fX212 × 1/fX213 × 1/fX24 × 1/fX25 × 1/fX
(3.2
µ
s) (6.4
µ
s) (819.2
µ
s) (1.64 ms) (3.2
µ
s) (6.4
µ
s)
25 × 1/fX26 × 1/fX213 × 1/fX214 × 1/fX25 × 1/fX26 × 1/fX
(6.4
µ
s) (12.8
µ
s) (1.64 ms) (3.28 ms) (6.4
µ
s) (12.8
µ
s)
26 × 1/fX27 × 1/fX214 × 1/fX215 × 1/fX26 × 1/fX27 × 1/fX
(12.8
µ
s) (25.6
µ
s) (3.28 ms) (6.55 ms) (12.8
µ
s) (25.6
µ
s)
27 × 1/fX28 × 1/fX215 × 1/fX216 × 1/fX27 × 1/fX28 × 1/fX
(25.6
µ
s) (51.2
µ
s) (6.55 ms) (13.1 ms) (25.6
µ
s) (51.2
µ
s)
28 × 1/fX29 × 1/fX216 × 1/fX217 × 1/fX28 × 1/fX29 × 1/fX
(51.2
µ
s) (102.4
µ
s) (13.1 ms) (26.2 ms) (51.2
µ
s) (102.4
µ
s)
29 × 1/fX210 × 1/fX217 × 1/fX218 × 1/fX29 × 1/fX210 × 1/fX
(102.4
µ
s) (204.8
µ
s) (26.2 ms) (52.4 ms) (102.4
µ
s) (204.8
µ
s)
211 × 1/fX212 × 1/fX219 × 1/fX220 × 1/fX211 × 1/fX212 × 1/fX
(409.6
µ
s) (819.2
µ
s) (104.9 ms) (209.7 ms) (409.6
µ
s) (819.2
µ
s)
Other than above Setting prohibited
Remarks 1. fX: Main system clock oscillation frequency
2. TCL10 to TCL13: Bits 0 to 3 of timer clock select register 1 (TCL1)
3. MCS: Oscillation mode select register bit 0
4. Values in parentheses when operated at fX = 5.0 MHz.
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
TCL13 TCL12 TCL11 TCL10
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Table 9-7. 8-bit Timer/Event Counter 2 Interval Time
Minimum Interval Time Maximum Interval Time Resolution
MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0
0000 TI2 input cycle 28 × TI2 input cycle TI2 input edge cycle
0001 TI2 input cycle 28 × TI2 input cycle TI2 input edge cycle
2 × 1/fX22 × 1/fX29 × 1/fX210 × 1/fX2 × 1/fX22 × 1/fX
(400 ns) (800 ns) (102.4
µ
s) (204.8
µ
s) (400 ns) (800 ns)
22 × 1/fX23 × 1/fX210 × 1/fX211 × 1/fX22 × 1/fX23 × 1/fX
(800 ns) (1.6
µ
s) (204.8
µ
s) (409.6
µ
s) (800 ns) (1.6
µ
s)
23 × 1/fX24 × 1/fX211 × 1/fX212 × 1/fX23 × 1/fX24 × 1/fX
(1.6
µ
s) (3.2
µ
s) (409.6
µ
s) (819.2
µ
s) (1.6
µ
s) (3.2
µ
s)
24 × 1/fX25 × 1/fX212 × 1/fX213 × 1/fX24 × 1/fX25 × 1/fX
(3.2
µ
s) (6.4
µ
s) (819.2
µ
s) (1.64 ms) (3.2
µ
s) (6.4
µ
s)
25 × 1/fX26 × 1/fX213 × 1/fX214 × 1/fX25 × 1/fX26 × 1/fX
(6.4
µ
s) (12.8
µ
s) (1.64 ms) (3.28 ms) (6.4
µ
s) (12.8
µ
s)
26 × 1/fX27 × 1/fX214 × 1/fX215 × 1/fX26 × 1/fX27 × 1/fX
(12.8
µ
s) (25.6
µ
s) (3.28 ms) (6.55 ms) (12.8
µ
s) (25.6
µ
s)
27 × 1/fX28 × 1/fX215 × 1/fX216 × 1/fX27 × 1/fX28 × 1/fX
(25.6
µ
s) (51.2
µ
s) (6.55 ms) (13.1 ms) (25.6
µ
s) (51.2
µ
s)
28 × 1/fX29 × 1/fX216 × 1/fX217 × 1/fX28 × 1/fX29 × 1/fX
(51.2
µ
s) (102.4
µ
s) (13.1 ms) (26.2 ms) (51.2
µ
s) (102.4
µ
s)
29 × 1/fX210 × 1/fX217 × 1/fX218 × 1/fX29 × 1/fX210 × 1/fX
(102.4
µ
s) (204.8
µ
s) (26.2 ms) (52.4 ms) (102.4
µ
s) (204.8
µ
s)
211 × 1/fX212 × 1/fX219 × 1/fX220 × 1/fX211 × 1/fX212 × 1/fX
(409.6
µ
s) (819.2
µ
s) (104.9 ms) (209.7 ms) (409.6
µ
s) (819.2
µ
s)
Other than above Setting prohibited
Remarks 1. fX: Main system clock oscillation frequency
2. TCL10 to TCL13: Bits 0 to 3 of timer clock select register 1 (TCL1)
3. MCS: Oscillation mode select register bit 0
4. Values in parentheses when operated at fX = 5.0 MHz
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
TCL17 TCL16 TCL15 TCL14
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(2) External event counter operation
The external event counter counts the number of external clock pulses to be input to the TI1/P33 and TI2/
P34 pins with 8-bit timer registers 1 and 2 (TM1 and TM2).
TM1 and TM2 are incremented each time the valid edge specified with timer clock select register 1 (TCL1)
is input. Either the rising or falling edge can be selected.
When the TM1 and TM2 counted values match the values of 8-bit compare registers 10 and 20 (CR10 and
CR20), TM1 and TM2 are cleared to 0 and the interrupt request signals (INTTM1 and INTTM2) are generated.
Figure 9-9. External Event Counter Operation Timings (with Rising Edge Specified)
Remark N = 00H to FFH
TI1 pin input
TM1 count value
INTTM1
CR10
00 01 02 03 04 05 N – 1 N 00 01 02 03
N
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(3) Square-wave output operation
A square wave with any selected frequency is output at intervals of the value preset to 8-bit compare registers
10 and 20 (CR10 and CR20).
The TO1/P31 or TO2/P32 pin output status is reversed at intervals of the count value preset to CR10 or CR20
by setting bit 0 (TOE1) or bit 4 (TOE2) of the 8-bit timer output control register (TOC1) to 1. This enables
a square wave with any selected frequency to be output.
Table 9-8. 8-bit Timer/Event Counter Square-Wave Output Ranges
Minimum Pulse Width Maximum Pulse Width Resolution
MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0
2 × 1/fX22 × 1/fX29 × 1/fX210 × 1/fX2 × 1/fX22 × 1/fX
(400 ns) (800 ns) (102.4
µ
s) (204.8
µ
s) (400 ns) (800 ns)
22 × 1/fX23 × 1/fX210 × 1/fX211 × 1/fX22 × 1/fX23 × 1/fX
(800 ns) (1.6
µ
s) (204.8
µ
s) (409.6
µ
s) (800 ns) (1.6
µ
s)
23 × 1/fX24 × 1/fX211 × 1/fX212 × 1/fX23 × 1/fX24 × 1/fX
(1.6
µ
s) (3.2
µ
s) (409.6
µ
s) (819.2
µ
s) (1.6
µ
s) (3.2
µ
s)
24 × 1/fX25 × 1/fX212 × 1/fX213 × 1/fX24 × 1/fX25 × 1/fX
(3.2
µ
s) (6.4
µ
s) (819.2
µ
s) (1.64 ms) (3.2
µ
s) (6.4
µ
s)
25 × 1/fX26 × 1/fX213 × 1/fX214 × 1/fX25 × 1/fX26 × 1/fX
(6.4
µ
s) (12.8
µ
s) (1.64 ms) (3.28 ms) (6.4
µ
s) (12.8
µ
s)
26 × 1/fX27 × 1/fX214 × 1/fX215 × 1/fX26 × 1/fX27 × 1/fX
(12.8
µ
s) (25.6
µ
s) (3.28 ms) (6.55 ms) (12.8
µ
s) (25.6
µ
s)
27 × 1/fX28 × 1/fX215 × 1/fX216 × 1/fX27 × 1/fX28 × 1/fX
(25.6
µ
s) (51.2
µ
s) (6.55 ms) (13.1 ms) (25.6
µ
s) (51.2
µ
s)
28 × 1/fX29 × 1/fX216 × 1/fX217 × 1/fX28 × 1/fX29 × 1/fX
(51.2
µ
s) (102.4
µ
s) (13.1 ms) (26.2 ms) (51.2
µ
s) (102.4
µ
s)
29 × 1/fX210 × 1/fX217 × 1/fX218 × 1/fX29 × 1/fX210 × 1/fX
(102.4
µ
s) (204.8
µ
s) (26.2 ms) (52.4 ms) (102.4
µ
s) (204.8
µ
s)
211 × 1/fX212 × 1/fX219 × 1/fX220 × 1/fX211 × 1/fX212 × 1/fX
(409.6
µ
s) (819.2
µ
s) (104.9 ms) (209.7 ms) (409.6
µ
s) (819.2
µ
s)
Remarks 1. fX: Main system clock oscillation frequency
2. MCS: Oscillation mode select register bit 0
3. Values in parentheses when operated at fX = 5.0 MHz.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTER
Figure 9-10. Square Wave Output Operation Timing
Note The initial value of TO1 output can be set by using bits 2 and 3 (LVR1 and LVS1) of the 8-bit timer output
control register (TOC1).
Count clock
TM1 count value
CR10
TO1 pin output
Note
00 01 02 N – 1 N 00 01 02 N – 1 N 00
N
204 User’s Manual U11377EJ3V0UD
CHAPTER 9 8-BIT TIMER/EVENT COUNTER
9.4.2 16-bit timer/event counter mode
When bit 2 (TMC12) of 8-bit timer mode control register 1 (TMC1) is set to 1, the 16-bit timer/event counter mode
is set.
In this mode, the count clock is selected with bits 0 to 3 (TCL10 to TCL13) of timer clock select register 1 (TCL1).
The overflow signal of 8-bit timer/event counter 1 (TM1) is used as the count clock to 8-bit timer/event counter 2 (TM2).
In this mode, the count operation enable/disable is selected with bit 0 (TCE1) of TMC1.
(1) Interval timer operation
The 8-bit timer/event counter can operate as an interval timer which generates interrupt requests repeatedly
at intervals of the count value preset to 2-channel 8-bit compare registers (CR10 and CR20). To set a count
value, set the value of the higher 8 bits to CR20, and the value of the lower 8 bits to CR10. For the count
value that can be set (interval time), refer to Table 9-7.
When the 8-bit timer register 1 (TM1) and CR10 values match and the 8-bit timer register 2 (TM2) and CR20
values match, counting continues with the TM1 and TM2 values cleared to 0 and the interrupt request signal
(INTTM2) is generated. For the operation timing of the interval timer, refer to Figure 9-11.
The count clock can be selected with bits 0 to 3 (TCL10 to TCL13) of timer clock select register 1 (TCL1).
The overflow signal of TM1 is used as the count clock to TM2.
Figure 9-11. Interval Timer Operation Timing
Remark Interval time = (N + 1) × t: N = 0000H to FFFFH
Caution Even if the 16-bit timer/event counter mode is used, when the TM1 count value matches the
CR10 value, interrupt request (INTTM1) is generated and the F/F of 8-bit timer/event counter
output controller 1 is inverted. Thus, when using 8-bit timer/event counter as 16-bit interval
timer, set the INTTM1 mask flag TMMK1 to 1 to disable INTTM1 acknowledgment.
When reading the 16-bit timer (TMS) count value, use the 16-bit memory manipulation
instruction.
Count clock
TMS (TM1, TM2) count value
CR10, CR20
INTTM2
TO2
Interval time Interval time Interval time
Interrupt request
acknowledge
Interrupt request
acknowledge
NN NN
Count start Clear Clear
0000 0001 N 0000 0001 N 0000 0001 N
t
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CHAPTER 9 8-BIT TIMER/EVENT COUNTER
Table 9-9. Interval Times When 2-Channel 8-bit Timer/Event Counters
(TM1 and TM2) Are Used as 16-bit Timer/Event Counter
Minimum Interval Time Maximum Interval Time Resolution
MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0
0000 TI1 input cycle 28 × TI1 input cycle TI1 input edge cycle
0001 TI1 input cycle 28 × TI1 input cycle TI1 input edge cycle
2 × 1/fX22 × 1/fX217 × 1/fX218 × 1/fX2 × 1/fX22 × 1/fX
(400 ns) (800 ns) (26.2 ms) (52.4 ms) (400 ns) (800 ns)
22 × 1/fX23 × 1/fX218 × 1/fX219 × 1/fX22 × 1/fX23 × 1/fX
(800 ns) (1.6
µ
s) (52.4 ms) (104.9 ms) (800 ns) (1.6
µ
s)
23 × 1/fX24 × 1/fX219 × 1/fX220 × 1/fX23 × 1/fX24 × 1/fX
(1.6
µ
s) (3.2
µ
s) (104.9 ms) (209.7 ms) (1.6
µ
s) (3.2
µ
s)
24 × 1/fX25 × 1/fX220 × 1/fX221 × 1/fX24 × 1/fX25 × 1/fX
(3.2
µ
s) (6.4
µ
s) (209.7 ms) (419.4 ms) (3.2
µ
s) (6.4
µ
s)
25 × 1/fX26 × 1/fX221 × 1/fX222 × 1/fX25 × 1/fX26 × 1/fX
(6.4
µ
s) (12.8
µ
s) (419.4 ms) (838.9 ms) (6.4
µ
s) (12.8
µ
s)
26 × 1/fX27 × 1/fX222 × 1/fX223 × 1/fX26 × 1/fX27 × 1/fX
(12.8
µ
s) (25.6
µ
s) (838.9 ms) (1.7 s) (12.8
µ
s) (25.6
µ
s)
27 × 1/fX28 × 1/fX223 × 1/fX224 × 1/fX27 × 1/fX28 × 1/fX
(25.6
µ
s) (51.2
µ
s) (1.7 s) (3.4 s) (25.6
µ
s) (51.2
µ
s)
28 × 1/fX29 × 1/fX224 × 1/fX225 × 1/fX28 × 1/fX29 × 1/fX
(51.2
µ
s) (102.4
µ
s) (3.4 s) (6.7 s) (51.2
µ
s) (102.4
µ
s)
29 × 1/fX210 × 1/fX225 × 1/fX226 × 1/fX29 × 1/fX210 × 1/fX
(102.4
µ
s) (204.8
µ
s) (6.7 s) (13.4 s) (102.4
µ
s) (204.8
µ
s)
211 × 1/fX212 × 1/fX227 × 1/fX228 × 1/fX211 × 1/fX212 × 1/fX
(409.6
µ
s) (819.2
µ
s) (26.8 s) (53.7 s) (409.6
µ
s) (819.2
µ
s)
Other than above Setting prohibited
Remarks 1. fX: Main system clock oscillation frequency
2. TCL10 to TCL13: Bits 0 to 3 of timer clock select register 1 (TCL1)
3. MCS: Oscillation mode select register bit 0
4. Values in parentheses when operated at fX = 5.0 MHz.
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
TCL13 TCL12 TCL11 TCL10
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CHAPTER 9 8-BIT TIMER/EVENT COUNTER
(2) External event counter operations
The external event counter counts the number of external clock pulses to be input to the TI1/P33 pin with 2-
channel 8-bit timer registers 1 and 2 (TM1 and TM2).
TM1 is incremented each time the valid edge specified with timer clock select register 1 (TCL1) is input. When
TM1 overflows as a result, TM2 is incremented with the overflow signal used as its count clock. Either the
rising or falling edge can be selected.
When the TM1 and TM2 counted values match the values of 8-bit compare registers 10 and 20 (CR10 and
CR20), TM1 and TM2 are cleared to 0 and the interrupt request signal (INTTM2) is generated.
Figure 9-12. External Event Counter Operation Timings (with Rising Edge Specified)
Caution Even if the 16-bit timer/event counter mode is used, when the TM1 count value matches the
CR10 value, interrupt request (INTTM1) is generated and the F/F of 8-bit timer/event counter
output controller 1 is inverted. Thus, when using 8-bit timer/event counter as 16-bit interval
timer, set the INTTM1 mask flag TMMK1 to 1 to disable INTTM1 acknowledgment.
When reading the 16-bit timer (TMS) count value, use the 16-bit memory manipulation
instruction.
TI1 pin input
TM1, TM2 count value
CR10, CR20
INTTM2
0000 0001 0002 0003 0004 0005 N – 1 N 0000 0001 0002 0003
N
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CHAPTER 9 8-BIT TIMER/EVENT COUNTER
(3) Square-wave output operation
A square wave with any selected frequency is output at intervals of the value preset to 8-bit compare registers
10 and 20 (CR10 and CR20).
The TO2/P32 pin output status is reversed at intervals of the count value preset to CR10 and CR20 by setting
bit 4 (TOE2) of the 8-bit timer output control register (TOC1) to 1. This enables a square wave with any selected
frequency to be output.
Table 9-10. Square-Wave Output Ranges When 2-Channel 8-bit Timer/Event Counters
(TM1 and TM2) Are Used as 16-bit Timer/Event Counter
Minimum Pulse Width Maximum Pulse Width Resolution
MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0
2 × 1/fX22 × 1/fX217 × 1/fX218 × 1/fX2 × 1/fX22 × 1/fX
(400 ns) (800 ns) (26.2 ms) (52.4 ms) (400 ns) (800 ns)
22 × 1/fX23 × 1/fX218 × 1/fX219 × 1/fX22 × 1/fX23 × 1/fX
(800 ns) (1.6
µ
s) (52.4 ms) (104.9 ms) (800 ns) (1.6
µ
s)
23 × 1/fX24 × 1/fX219 × 1/fX220 × 1/fX23 × 1/fX24 × 1/fX
(1.6
µ
s) (3.2
µ
s) (104.9 ms) (209.7 ms) (1.6
µ
s) (3.2
µ
s)
24 × 1/fX25 × 1/fX220 × 1/fX221 × 1/fX24 × 1/fX25 × 1/fX
(3.2
µ
s) (6.4
µ
s) (209.7 ms) (419.4 ms) (3.2
µ
s) (6.4
µ
s)
25 × 1/fX26 × 1/fX221 × 1/fX222 × 1/fX25 × 1/fX26 × 1/fX
(6.4
µ
s) (12.8
µ
s) (419.4 ms) (838.9 ms) (6.4
µ
s) (12.8
µ
s)
26 × 1/fX27 × 1/fX222 × 1/fX223 × 1/fX26 × 1/fX27 × 1/fX
(12.8
µ
s) (25.6
µ
s) (838.9 ms) (1.7 s) (12.8
µ
s) (25.6
µ
s)
27 × 1/fX28 × 1/fX223 × 1/fX224 × 1/fX27 × 1/fX28 × 1/fX
(25.6
µ
s) (51.2
µ
s) (1.7 s) (3.4 s) (25.6
µ
s) (51.2
µ
s)
28 × 1/fX29 × 1/fX224 × 1/fX225 × 1/fX28 × 1/fX29 × 1/fX
(51.2
µ
s) (102.4
µ
s) (3.4 s) (6.7 s) (51.2
µ
s) (102.4
µ
s)
29 × 1/fX210 × 1/fX225 × 1/fX226 × 1/fX29 × 1/fX210 × 1/fX
(102.4
µ
s) (204.8
µ
s) (6.7 s) (13.4 s) (102.4
µ
s) (204.8
µ
s)
211 × 1/fX212 × 1/fX227 × 1/fX228 × 1/fX211 × 1/fX212 × 1/fX
(409.6
µ
s) (819.2
µ
s) (26.8 s) (53.7 s) (409.6
µ
s) (819.2
µ
s)
Remarks 1. fX: Main system clock oscillation frequency
2. MCS: Oscillation mode select register bit 0
3. Values in parentheses when operated at fX = 5.0 MHz.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTER
Figure 9-13. Square Wave Output Operation Timing
Count clock
TM1
TM2
TO20
Count starts
00H 01H
N
N + 1 FFH 00H FFH 00H
N
00H 01HFFH 00H 01H
N
00H 01H 02H M – 1
M
00H
CR10
CR20 M
Level inverted
Counter cleared
Interval time
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CHAPTER 9 8-BIT TIMER/EVENT COUNTER
9.5 8-bit Timer/Event Counter Precautions
(1) Timer start errors
An error with a maximum of one clock may occur concerning the time required for a match signal to be
generated after timer start. This is because 8-bit timer registers 1 and 2 (TM1 and TM2) are started
asynchronously with the count pulse.
Figure 9-14. 8-bit Timer Register Start Timing
(2) 8-bit compare registers 10 and 20 setting
8-bit compare registers 10 and 20 (CR10 and CR20) can be set to 00H.
Thus, when these 8-bit compare registers are used as event counters, one-pulse count operation can be
carried out.
When the 8-bit compare register is used as 16-bit timer/event counter, write data to CR10 and CR20 after
setting bit 0 (TCE1) of 8-bit timer mode control register 1 to 0 and stopping timer operation.
Figure 9-15. External Event Counter Operation Timing
Count pulse
TM1, TM2 count value 00H 01H 02H 03H 04H
Timer start
TI1, TI2 input
CR10, CR20
TM1, TM2 count value
TO1, TO2
Interrupt request flag
00H
00H 00H 00H 00H
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CHAPTER 9 8-BIT TIMER/EVENT COUNTER
(3) Operation after compare register change during timer count operation
If the values after 8-bit compare registers 10 and 20 (CR10 and CR20) are changed are smaller than those
of 8-bit timer registers 1 and 2 (TM1 and TM2), TM1 and TM2 continue counting, overflow and then restart
counting from 0. Thus, if the value (M) after CR10 and CR20 change is smaller than value (N) before the
change, it is necessary to restart the timer after changing CR10 and CR20.
Figure 9-16. Timing After Compare Register Change During Timer Count Operation
Remark N > X > M
Count pulse
CR10, CR20
TM1, TM2 count value X – 1 X FFH 00H 01H 02H
MN
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CHAPTER 10 WATCH TIMER
10.1 Watch Timer Functions
The watch timer has the following functions.
• Watch timer
• Interval timer
The watch timer and the interval timer can be used simultaneously.
(1) Watch timer
When the 32.768 kHz subsystem clock is used, a flag (WTIF) is set at 0.5 second or 0.25 second intervals.
When the 4.19 MHz (standard: 4.194304 MHz) main system clock is used, a flag (WTIF) is set at 0.5 second
or 0.25 second intervals.
Caution 0.5-second intervals cannot be generated with the 5.0 MHz main system clock. You should
switch to the 32.768 kHz subsystem clock to generate 0.5-second intervals.
(2) Interval timer
Interrupt requests (INTTM3) are generated at the preset time interval.
Table 10-1. Interval Timer Interval Time
When Operated at When Operated at When Operated at
fXX = 5.0 MHz fXX = 4.19 MHz fXT = 32.768 kHz
24 × 1/fW410
µ
s 488
µ
s 488
µ
s
25 × 1/fW819
µ
s 977
µ
s 977
µ
s
26 × 1/fW1.64 ms 1.95 ms 1.95 ms
27 × 1/fW3.28 ms 3.91 ms 3.91 ms
28 × 1/fW6.55 ms 7.81 ms 7.81 ms
29 × 1/fW13.1 ms 15.6 ms 15.6 ms
Remark fXX: Main system clock frequency (fX or fX/2)
fX: Main system clock oscillation frequency
fXT: Subsystem clock oscillation frequency
fW: Watch timer clock frequency (fXX/27 or fXT)
Interval Time
212
CHAPTER 10 WATCH TIMER
User’s Manual U11377EJ3V0UD
10.2 Watch Timer Configuration
The watch timer consists of the following hardware.
Table 10-2. Watch Timer Configuration
Item Configuration
Counter 5 bits × 1
Control register Timer clock select register 2 (TCL2)
Watch timer mode control register (TMC2)
10.3 Watch Timer Control Registers
The following two types of registers are used to control the watch timer.
• Timer clock select register 2 (TCL2)
• Watch timer mode control register (TMC2)
(1) Timer clock select register 2 (TCL2)
This register sets the watch timer count clock.
TCL2 is set with an 8-bit memory manipulation instruction.
RESET input clears TCL2 to 00H.
Remark Besides setting the watch timer count clock, TCL2 sets the watchdog timer count clock and buzzer
output frequency.
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CHAPTER 10 WATCH TIMER
User’s Manual U11377EJ3V0UD
Figure 10-1. Watch Timer Block Diagram
Remark fXX = fX/2 (MCS = 0), fXX = fX (MCS = 1)
TMC21
Prescaler
Selector
INTWT
5-bit
counter
fW
214
fW
213
INTTM3
To 16-bit timer/
event counter
Watch timer mode
control register
TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 TMC20
Internal bus
TCL24
Timer clock
select register 2
3
fW
24
fW
25
fW
26
fW
27
fW
28
fW
29
fW
fXX/27
fXT
Clear
Clear
Selector
Selector
Selector
To LCD
controller/driver
214
CHAPTER 10 WATCH TIMER
User’s Manual U11377EJ3V0UD
Figure 10-2. Timer Clock Select Register 2 Format
Caution When rewriting TCL2 to other data, stop the timer operation beforehand.
Remarks 1. fX: Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency
3. ×: don't care
4. MCS: Oscillation mode select register bit 0
5. Figures in parentheses apply to operation with fX = 5.0 MHz or fXT = 32.768 kHz.
TCL27
7
TCL26
6
TCL25 TCL24
4
0
3210
FF42H
Address
TCL2
Symbol
TCL22 TCL21 TCL20
5
00H
After
Reset
R/W
R/W
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
TCL22 TCL21 TCL20
MCS = 1
f
X
/2
3
(625 kHz)
f
X
/2
4
(313 kHz)
f
X
/2
5
(156 kHz)
f
X
/2
6
(78.1 kHz)
f
X
/2
7
(39.1 kHz)
f
X
/2
8
(19.5 kHz)
f
X
/2
9
(9.8 kHz)
f
X
/2
11
(2.4 kHz)
MCS = 0
f
X
/2
4
(313 kHz)
f
X
/2
5
(156 kHz)
f
X
/2
6
(78.1 kHz)
f
X
/2
7
(39.1 kHz)
f
X
/2
8
(19.5 kHz)
f
X
/2
9
(9.8 kHz)
f
X
/2
10
(4.9 kHz)
f
X
/2
12
(1.2 kHz)
Watchdog Timer Count Clock Selection
0
1
TCL24
f
XT
(32.768 kHz)
MCS = 1
f
X
/2
7
(39.1 kHz)
MCS = 0
f
X
/2
8
(19.5 kHz)
Watch Timer Count Clock Selection
0
1
1
1
1
×
0
0
1
1
×
0
1
0
1
TCL27 TCL26 TCL25
Buzzer output disable
Setting prohibited
MCS = 1
f
X
/2
9
(9.8 kHz)
f
X
/2
10
(4.9 kHz)
f
X
/2
11
(2.4 kHz)
MCS = 0
f
X
/2
10
(4.9 kHz)
f
X
/2
11
(2.4 kHz)
f
X
/2
12
(1.2 kHz)
Buzzer Output Frequency Selection
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CHAPTER 10 WATCH TIMER
User’s Manual U11377EJ3V0UD
(2) Watch timer mode control register (TMC2)
This register sets the watch timer operating mode, watch flag set time and prescaler interval time and enables/
disables prescaler and 5-bit counter operations.
TMC2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TMC2 to 00H.
Figure 10-3. Watch Timer Mode Control Register Format
Caution When the watch timer is used, the prescaler should not be cleared frequently.
Remark fW: Watch timer clock frequency (fXX/27 or fXT)
fXX: Main system clock frequency (fX or fX/2)
fX: Main system clock oscillation frequency
fXT: Subsystem clock oscillation frequency
0
7
TMC26
6
TMC25 TMC24
4
TMC23
3210
FF4AH
Address
TMC2
Symbol
TMC22 TMC21 TMC20
5
00H
After
Reset
R/W
R/W
0
1
TMC23
2
14
/f
W
(0.4 sec)
2
13
/f
W
(0.2 sec)
Watch Flag Set Time Selection
0
0
0
0
1
1
Other than above
0
0
1
1
0
0
0
1
0
1
0
1
TMC26 TMC25 TMC24
f
XX
= 5.0 MHz Operation
2
4
/f
W
(410 s)
2
5
/f
W
(819 s)
2
6
/f
W
(1.64 ms)
2
7
/f
W
(3.28 ms)
2
8
/f
W
(6.55 ms)
2
9
/f
W
(13.1 ms)
Setting prohibited
f
XX
= 4.19 MHz Operation
2
4
/f
W
(488 s)
2
5
/f
W
(977 s)
2
6
/f
W
(1.95 ms)
2
7
/f
W
(3.91 ms)
2
8
/f
W
(7.81 ms)
2
9
/f
W
(15.6 ms)
f
XT
= 32.768 kHz Operation
f
XX
= 5.0 MHz Operation f
XX
= 4.19 MHz Operation f
XT
= 32.768 kHz Operation
2
4
/f
W
(488 s)
2
5
/f
W
(977 s)
2
6
/f
W
(1.95 ms)
2
7
/f
W
(3.91 ms)
2
8
/f
W
(7.81 ms)
2
9
/f
W
(15.6 ms)
Prescaler Interval Time Selection
µ
µ
µ
µ
µ
µ
2
14
/f
W
(0.5 sec)
2
13
/f
W
(0.25 sec)
2
14
/f
W
(0.5 sec)
2
13
/f
W
(0.25 sec)
TMC22
0
1
5-bit Counter Operation Control
Clear after operation stop
Operation enable
TMC21
0
1
Prescaler Operation Control
Clear after operation stop
Operation enable
TMC20
0
1
Watch Operating Mode Selection
Fast feed operating mode (flag set at f
2
Normal operating mode (flag set at f
W
/
14
)
W
/2
5
)
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CHAPTER 10 WATCH TIMER
User’s Manual U11377EJ3V0UD
10.4 Watch Timer Operations
10.4.1 Watch timer operation
When the 32.768 kHz subsystem clock or 4.19 MHz main system clock is used, the timer operates as a watch
timer with a 0.5-second or 0.25-second interval.
The watch timer sets the test input flag (WTIF) to 1 at the constant time interval. The standby state (STOP mode/
HALT mode) can be cleared by setting WTIF to 1.
When bit 2 (TIMC22) of the watch timer mode control register is set to 0, the 5-bit counter is cleared and the count
operation stops.
For simultaneous operation of the interval timer, zero-second start can be achieved by setting TMC22 to 0
(maximum error: 26.2 ms when operated at fXX = 5.0 MHz).
10.4.2 Interval timer operation
The watch timer operates as interval timer which generates interrupt requests repeatedly at an interval of the preset
count value.
The interval time can be selected with bits 4 to 6 (TMC24 to TMC26) of the watch timer mode control register.
Table 10-3. Interval Timer Interval Time
When Operated at When Operated at When Operated at
fXX = 5.0 MHz fXX = 4.19 MHz fXT = 32.768 kHz
000 2
4 × 1/fW410
µ
s 488
µ
s 488
µ
s
001 2
5 × 1/fW819
µ
s 977
µ
s 977
µ
s
010 2
6 × 1/fW1.64 ms 1.95 ms 1.95 ms
011 2
7 × 1/fW3.28 ms 3.91 ms 3.91 ms
100 2
8 × 1/fW6.55 ms 7.81 ms 7.81 ms
101 2
9 × 1/fW13.1 ms 15.6 ms 15.6 ms
Other than above Setting prohibited
Remark fXX: Main system clock frequency (fX or fX/2)
fX: Main system clock oscillation frequency
fXT: Subsystem clock oscillation frequency
fW: Watch timer clock frequency (fXX/27 or fXT)
TMC26 TMC25 TMC24 Interval Time
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CHAPTER 11 WATCHDOG TIMER
11.1 Watchdog Timer Functions
The watchdog timer has the following functions.
• Watchdog timer
• Interval timer
Caution Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register
(WDTM).
(1) Watchdog timer mode
An inadvertent program loop is detected. Upon detection of the inadvertent program loop, a non-maskable
interrupt request or RESET can be generated.
Table 11-1. Watchdog Timer Inadvertent Program Loop Detection Times
Loop Detection Time MCS = 1 MCS = 0
211 × 1/fXX 211 × 1/fX (410
µ
s) 212 × 1/fX (819
µ
s)
212 × 1/fXX 212 × 1/fX (819
µ
s) 213 × 1/fX (1.64 ms)
213 × 1/fXX 213 × 1/fX (1.64 ms) 214 × 1/fX (3.28 ms)
214 × 1/fXX 214 × 1/fX (3.28 ms) 215 × 1/fX (6.55 ms)
215 × 1/fXX 215 × 1/fX (6.55 ms) 216 × 1/fX (13.1 ms)
216 × 1/fXX 216 × 1/fX (13.1 ms) 217 × 1/fX (26.2 ms)
217 × 1/fXX 217 × 1/fX (26.2 ms) 218 × 1/fX (52.4 ms)
219 × 1/fXX 219 × 1/fX (104.9 ms) 220 × 1/fX (209.7 ms)
Remarks 1. fXX: Main system clock frequency (fX or fX/2)
2. fX: Main system clock oscillation frequency
3. MCS: Oscillation mode select register bit 0
4. Figures in parentheses apply to operation with fX = 5.0 MHz.
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(2) Interval timer mode
Interrupt requests are generated at the preset time intervals.
Table 11-2. Interval Times
Interval Time MCS = 1 MCS = 0
211 × 1/fXX 211 × 1/fX (410
µ
s) 212 × 1/fX (819
µ
s)
212 × 1/fXX 212 × 1/fX (819
µ
s) 213 × 1/fX (1.64 ms)
213 × 1/fXX 213 × 1/fX (1.64 ms) 214 × 1/fX (3.28 ms)
214 × 1/fXX 214 × 1/fX (3.28 ms) 215 × 1/fX (6.55 ms)
215 × 1/fXX 215 × 1/fX (6.55 ms) 216 × 1/fX (13.1 ms)
216 × 1/fXX 216 × 1/fX (13.1 ms) 217 × 1/fX (26.2 ms)
217 × 1/fXX 217 × 1/fX (26.2 ms) 218 × 1/fX (52.4 ms)
219 × 1/fXX 219 × 1/fX (104.9 ms) 220 × 1/fX (209.7 ms)
Remarks 1. fXX: Main system clock frequency (fX or fX/2)
2. fX: Main system clock oscillation frequency
3. MCS: Oscillation mode select register bit 0
4. Figures in parentheses apply to operation with fX = 5.0 MHz.
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11.2 Watchdog Timer Configuration
The watchdog timer consists of the following hardware.
Table 11-3. Watchdog Timer Configuration
Item Configuration
Control register Timer clock select register 2 (TCL2)
Watchdog timer mode register (WDTM)
Figure 11-1. Watchdog Timer Block Diagram
Remark fXX = fX/2 (MCS = 0), fXX = fX (MCS = 1)
Prescaler
f
XX
2
4
f
XX
2
5
f
XX
2
6
f
XX
2
7
f
XX
2
8
f
XX
2
9
Selector
Watchdog timer mode register
Internal bus
Internal bus
TCL22 TCL21 TCL20
f
XX
/2
3
f
XX
2
11
Timer clock select register 2
3
WDTM4 WDTM3
8-bit counter
TMMK4
RUN
TMIF4
INTWDT
maskable
interrupt
request
INTWDT
non-maskable
interrupt
request
RESET
Controller
RUN
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11.3 Watchdog Timer Control Registers
The following two types of registers are used to control the watchdog timer.
•Timer clock select register 2 (TCL2)
•Watchdog timer mode register (WDTM)
(1) Timer clock select register 2 (TCL2)
This register sets the watchdog timer count clock.
TCL2 is set with an 8-bit memory manipulation instruction.
RESET input clears TCL2 to 00H.
Remark Besides setting the watchdog timer count clock, TCL2 sets the watch timer count clock and buzzer
output frequency.
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Figure 11-2. Timer Clock Select Register 2 Format
Caution When rewriting TCL2 to other data, stop the timer operation beforehand.
Remarks 1. fX: Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency
3. ×: don't care
4. MCS: Oscillation mode select register bit 0
5. Figures in parentheses apply to operation with fX = 5.0 MHz or fXT = 32.768 kHz.
TCL27
7
TCL26
6
TCL25 TCL24
4
0
3210
FF42H
Address
TCL2
Symbol
TCL22 TCL21 TCL20
5
00H
After
Reset
R/W
R/W
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
TCL22 TCL21 TCL20
MCS = 1
f
X
/2
3
f
X
/2
4
f
X
/2
5
f
X
/2
6
f
X
/2
7
f
X
/2
8
f
X
/2
9
f
X
/2
11
MCS = 0
f
X
/2
4
f
X
/2
5
f
X
/2
6
f
X
/2
7
f
X
/2
8
f
X
/2
9
f
X
/2
10
f
X
/2
12
Watchdog Timer Count Clock Selection
0
1
TCL24
f
XT
(32.768 kHz)
MCS = 1
f
X
/2
7
(39.1 kHz)
MCS = 0
f
X
/2
8
(19.5 kHz)
Watch Timer Count Clock Selection
0
1
1
1
1
×
0
0
1
1
×
0
1
0
1
TCL27 TCL26 TCL25
Buzzer output disable
Setting prohibited
MCS = 1
f
X
/2
9
(9.8 kHz)
f
X
/2
10
(4.9 kHz)
f
X
/2
11
(2.4 kHz)
MCS = 0
f
X
/2
10
(4.9 kHz)
f
X
/2
11
(2.4 kHz)
f
X
/2
12
(1.2 kHz)
Buzzer Output Frequency Selection
(625 kHz)
(313 kHz)
(156 kHz)
(78.1 kHz)
(39.1 kHz)
(19.5 kHz)
(9.8 kHz)
(2.4 kHz)
(313 kHz)
(156 kHz)
(78.1 kHz)
(39.1 kHz)
(19.5 kHz)
(9.8 kHz)
(4.9 kHz)
(1.2 kHz)
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(2) Watchdog timer mode register (WDTM)
This register sets the watchdog timer operating mode and enables/disables counting.
WDTM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears WDTM to 00H.
Figure 11-3. Watchdog Timer Mode Register Format
Notes 1. Once set to 1, WDTM3 and WDTM4 cannot be cleared to 0 by software.
2. Once set to 1, RUN cannot be cleared to 0 by software.
Thus, once counting starts, it can only be stopped by RESET input.
3. The watchdog timer starts operating as an interval timer as soon as RUN has been set to 1.
Cautions 1. When 1 is set in RUN so that the watchdog timer is cleared, the actual overflow time is
up to 0.5% shorter than the time set by timer clock select register 2.
2. To use watchdog timer modes 1 and 2, confirm that the interrupt request flag (TMIF4) is
0 and then set the WDTM4 to 1.
If WDTM4 is set while TMIF4 is 1, the non-maskable interrupt request occurs regardless
of the content of WDTM3.
Remark ×: don't care
RUN
7
0
6
0
WDTM4
4
WDTM3
3210
FFF9H
Address
WDTM
Symbol
000
5
00H
After
Reset
R/W
R/W
0
1
RUN
Counter is cleared and counting starts.
Watchdog Timer Operation Mode Selection
Note 1
Count stop
0
1
1
×
0
0
WDTM4WDTM3
Watchdog Timer Operation Mode Selection
Note 2
Watchdog timer mode 1 (Non-maskable interrupt occurs upon generation of an overflow.)
Watchdog timer mode 2 (Reset operation is activated upon generation of an overflow.)
Interval timer mode (Maskable interrupt occurs upon generation of an overflow.)
Note 3
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11.4 Watchdog Timer Operations
11.4.1 Watchdog timer operation
When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated
to detect any inadvertent program loop.
The watchdog timer count clock (inadvertent program loop detection time interval) can be selected with bits 0 to
2 (TCL20 to TCL22) of timer clock select register 2 (TCL2).
Watchdog timer starts by setting bit 7 (RUN) of WDTM to 1. After the watchdog timer is started, set RUN to 1
within the set loop detection time interval. The watchdog timer can be cleared and counting is started by setting RUN
to 1. If RUN is not set to 1 and the inadvertent program loop detection time is past, system reset or a non-maskable
interrupt request is generated according to the WDTM bit 3 (WDTM3) value.
The watchdog timer continues operating in the HALT mode but it stops in the STOP mode. Thus, set RUN to 1
before the STOP mode is set, clear the watchdog timer and then execute the STOP instruction.
Cautions 1. The actual loop detection time may be shorter than the set time by a maximum of
0.5%.
2. When the subsystem clock is selected for the CPU clock, the watchdog timer count operation
is stopped.
Table 11-4. Watchdog Timer Loop Detection Time
TCL22 TCL21 TCL20 Loop Detection Time MCS = 1 MCS = 0
000 2
11 × 1/fXX 211 × 1/fX (410
µ
s) 212 × 1/fX (819
µ
s)
001 2
12 × 1/fXX 212 × 1/fX (819
µ
s) 213 × 1/fX (1.64 ms)
010 2
13 × 1/fXX 213 × 1/fX (1.64 ms) 214 × 1/fX (3.28 ms)
011 2
14 × 1/fXX 214 × 1/fX (3.28 ms) 215 × 1/fX (6.55 ms)
100 2
15 × 1/fXX 215 × 1/fX (6.55 ms) 216 × 1/fX (13.1 ms)
101 2
16 × 1/fXX 216 × 1/fX (13.1 ms) 217 × 1/fX (26.2 ms)
110 2
17 × 1/fXX 217 × 1/fX (26.2 ms) 218 × 1/fX (52.4 ms)
111 2
19 × 1/fXX 219 × 1/fX (104.9 ms) 220 × 1/fX (209.7 ms)
Remarks 1. fXX: Main system clock frequency (fX or fX/2)
2. fX: Main system clock oscillation frequency
3. MCS: Oscillation mode select register bit 0
4. Figures in parentheses apply to operation with fX = 5.0 MHz.
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11.4.2 Interval timer operation
The watchdog timer operates as an interval timer which generates interrupt requests repeatedly at an interval of
the preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0.
The count clock (interval timer) can be selected by bits 0 to 2 (TCL20 to TCL22) of timer clock select register 2
(TCL2). The watchdog timer starts operating as an interval timer when bit 7 (RUN) of WDTM is set to 1.
When the watchdog timer is operated as interval timer, the interrupt mask flag (TMMK4) and priority specify flag
(TMPR4) are validated and the maskable interrupt request (INTWDT) can be generated. Among maskable interrupt
requests, the INTWDT default has the highest priority.
The interval timer continues operating in the HALT mode but it stops in the STOP mode. Thus, set bit 7 of WDTM
(RUN) to 1 before the STOP mode is set, clear the interval timer and then execute the STOP instruction.
Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (with the watchdog timer mode selected), the interval
timer mode is not set unless RESET input is applied.
2. The interval time just after setting with WDTM may be shorter than the set time by a maximum
of 0.5%.
3. When the subsystem clock is selected for the CPU clock, the watchdog timer count operation
is stopped.
Table 11-5. Interval Timer Interval Time
TCL22 TCL21 TCL20 Interval Time MCS = 1 MCS = 0
000 2
11 × 1/fXX 211 × 1/fX (410
µ
s) 212 × 1/fX (819
µ
s)
001 2
12 × 1/fXX 212 × 1/fX (819
µ
s) 213 × 1/fX (1.64 ms)
010 2
13 × 1/fXX 213 × 1/fX (1.64 ms) 214 × 1/fX (3.28 ms)
011 2
14 × 1/fXX 214 × 1/fX (3.28 ms) 215 × 1/fX (6.55 ms)
100 2
15 × 1/fXX 215 × 1/fX (6.55 ms) 216 × 1/fX (13.1 ms)
101 2
16 × 1/fXX 216 × 1/fX (13.1 ms) 217 × 1/fX (26.2 ms)
110 2
17 × 1/fXX 217 × 1/fX (26.2 ms) 218 × 1/fX (52.4 ms)
111 2
19 × 1/fXX 219 × 1/fX (104.9 ms) 220 × 1/fX (209.7 ms)
Remarks 1. fXX: Main system clock frequency (fX or fX/2)
2. fX: Main system clock oscillation frequency
3. MCS: Oscillation mode select register bit 0
4. Figures in parentheses apply to operation with fX = 5.0 MHz.
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User’s Manual U11377EJ3V0UD
CHAPTER 12 CLOCK OUTPUT CONTROLLER
12.1 Clock Output Controller Functions
The clock output controller is intended for carrier output during remote controlled transmission and clock output
for supply to peripheral LSI. Clocks selected with timer clock select register 0 (TCL0) are output from the PCL/P35
pin.
Follow the procedure below to output clock pulses.
(1) Select the clock pulse output frequency (with clock pulse output disabled) with bits 0 to 3 (TCL00 to TCL03)
of TCL0.
(2) Set the P35 output latch to 0.
(3) Set bit 5 (PM35) of port mode register 3 to 0 (set to output mode).
(4) Set bit 7 (CLOE) of TCL0 to 1.
Caution Clock output cannot be used when setting P35 output latch to 1.
Remark When clock output enable/disable is switched, the clock output controller does not output pulses with
small widths (see the portions marked with * in Figure 12-1).
Figure 12-1. Remote Controlled Output Application Example
CLOE
PCL/P35 pin output
**
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12.2 Clock Output Controller Configuration
The clock output controller consists of the following hardware.
Table 12-1. Clock Output Controller Configuration
Item Configuration
Control register Timer clock select register 0 (TCL0)
Port mode register 3 (PM3)
Figure 12-2. Clock Output Controller Block Diagram
Remark fXX = fX/2 (MCS = 0), fXX = fX (MCS = 1)
Internal bus
f
XX
f
XX
/2
f
XX
/2
2
f
XX
/2
3
f
XX
/2
4
f
XX
/2
5
f
XX
/2
6
f
XX
/2
7
f
XT
CLOE TCL03 TCL02 TCL01 TCL00 P35
output latch
Synchronizing
circuit
4
PM35
Selector
Timer clock select register 0 Port mode register 3
PCL /P35
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12.3 Clock Output Function Control Registers
The following two types of registers are used to control the clock output function.
•Timer clock select register 0 (TCL0)
•Port mode register 3 (PM3)
(1) Timer clock select register 0 (TCL0)
This register sets PCL output clock.
TCL0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TCL0 to 00H.
Remark Besides setting PCL output clock, TCL0 sets the 16-bit timer register count clock.
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Figure 12-3. Timer Clock Select Register 0 Format
Cautions 1. Setting of the TI00/INTP0 pin valid edge is performed by external interrupt mode register
0, and selection of the sampling clock frequency is performed by the sampling clock
select register.
2. When enabling PCL output, set TCL00 to TCL03, then set 1 in CLOE with a 1-bit memory
manipulation instruction.
3. To read the count value when TI00 has been specified as the TM0 count clock, the value
should be read from TM0, not from capture/compare register 01 (CR01).
4. When rewriting TCL0 to other data, stop the timer operation beforehand.
CLOE
7
TCL06
6
TCL05 TCL04
4
TCL03
3210
FF40H
Address
TCL0
Symbol
TCL02 TCL01 TCL00
5
00H
After
Reset
R/W
R/W
0
0
0
0
1
1
1
1
1
Other than above
0
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
TCL03 TCL02 TCL01
fXT (32.768 kHz)
Setting prohibited
MCS = 1
fX (5.0 MHz)
fX/2 (2.5 MHz)
fX/22 (1.25 MHz)
fX/23 (625 kHz)
fX/24 (313 kHz)
fX/25 (156 kHz)
fX/26 (78.1 kHz)
fX/27 (39.1 kHz)
MCS = 0
fX/2 (2.5 MHz)
fX/22 (1.25 MHz)
fX/23 (625 kHz)
fX/24 (313 kHz)
fX/25 (156 kHz)
fX/26 (78.1 kHz)
fX/27 (39.1 kHz)
fX/28 (19.5 kHz)
PCL Output Clock Selection
CLOE
0
1
PCL Output Control
Output disabled
Output enabled
0
0
0
0
1
1
Other than above
0
0
1
1
0
1
0
1
0
1
0
1
TCL06 TCL05 TCL04
TI00 (Valid edge specifiable)
Watch timer output (INTTM3)
Setting prohibited
MCS = 1
Setting prohibited
fX (5.0 MHz)
fX/2 (2.5 MHz)
fX/22 (1.25 MHz)
MCS = 0
fX (5.0 MHz)
fX/2 (2.5 MHz)
fX/22(1.25 MHz)
fX/23 (625 kHz)
16-bit Timer Register Count Clock Selection
TCL00
0
1
0
1
0
1
0
1
0
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CHAPTER 12 CLOCK OUTPUT CONTROLLER
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Remarks 1. fX: Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency
3. TI00: 16-bit timer/event counter input pin
4. TM0: 16-bit timer register
5. MCS: Oscillation mode select register bit 0
6. Figures in parentheses apply to operation with fX = 5.0 MHz or fXT = 32.768 kHz.
(2) Port mode register 3 (PM3)
This register sets port 3 input/output in 1-bit units.
When using the P35/PCL pin for clock output function, set PM35 and output latch of P35 to 0.
PM3 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM3 to FFH.
Figure 12-4. Port Mode Register 3 Format
PM37
7
PM36
6
PM35 PM34
4
PM33
3210
FF23H
Address
PM3
Symbol
PM32 PM31 PM30
5
FFH
After
Reset
R/W
R/W
PM3n
0
1
P3n Pin I/O Mode Selection (n = 0 to 7)
Output mode (output buffer ON)
Input mode (output buffer OFF)
230 User’s Manual U11377EJ3V0UD
CHAPTER 13 BUZZER OUTPUT CONTROLLER
13.1 Buzzer Output Controller Functions
The buzzer output controller outputs 1.2 kHz, 2.4 kHz, 4.9 kHz, or 9.8 kHz frequency square waves. The buzzer
frequency selected with timer clock select register 2 (TCL2) is output from the BUZ/P36 pin.
Follow the procedure below to output the buzzer frequency.
(1) Select the buzzer output frequency with bits 5 to 7 (TCL25 to TCL27) of TCL2.
(2) Set the P36 output latch to 0.
(3) Set bit 6 (PM36) of port mode register 3 to 0 (set to output mode).
Caution Buzzer output cannot be used when setting P36 output latch to 1.
13.2 Buzzer Output Controller Configuration
The buzzer output controller consists of the following hardware.
Table 13-1. Buzzer Output Controller Configuration
Item Configuration
Control register Timer clock select register 2 (TCL2)
Port mode register 3 (PM3)
Figure 13-1. Buzzer Output Controller Block Diagram
Remark fXX = fX/2 (MCS = 0), fXX = fX (MCS = 1)
Internal bus
fXX /29
fXX /210
fXX /211
TCL27 TCL26 TCL25
3
PM36
Selector
Timer clock select register 2 Port mode register 3
BUZ/P36
P36
output latch
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13.3 Buzzer Output Function Control Registers
The following two types of registers are used to control the buzzer output function.
•Timer clock select register 2 (TCL2)
•Port mode register 3 (PM3)
(1) Timer clock select register 2 (TCL2)
This register sets the buzzer output frequency.
TCL2 is set with an 8-bit memory manipulation instruction.
RESET input clears TCL2 to 00H.
Remark Besides setting the buzzer output frequency, TCL2 sets the watch timer count clock and the
watchdog timer count clock.
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Figure 13-2. Timer Clock Select Register 2 Format
Caution When rewriting TCL2 to other data, stop the timer operation beforehand.
Remarks 1. fX: Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency
3. ×: don't care
4. MCS: Oscillation mode select register bit 0
5. Figures in parentheses apply to operation with fX = 5.0 MHz or fXT = 32.768 kHz.
TCL27
7
TCL26
6
TCL25 TCL24
4
0
3210
FF42H
Address
TCL2
Symbol
TCL22 TCL21 TCL20
5
00H
After
Reset
R/W
R/W
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
TCL22 TCL21 TCL20
MCS = 1
f
X
/2
3
f
X
/2
4
f
X
/2
5
f
X
/2
6
f
X
/2
7
f
X
/2
8
f
X
/2
9
f
X
/2
11
MCS = 0
f
X
/2
4
f
X
/2
5
f
X
/2
6
f
X
/2
7
f
X
/2
8
f
X
/2
9
f
X
/2
10
f
X
/2
12
Watchdog Timer Count Clock Selection
0
1
TCL24
f
XT
(32.768 kHz)
MCS = 1
f
X
/2
7
(39.1 kHz)
MCS = 0
f
X
/2
8
(19.5 kHz)
Watch Timer Count Clock Selection
0
1
1
1
1
×
0
0
1
1
×
0
1
0
1
TCL27 TCL26 TCL25
Buzzer output disable
Setting prohibited
MCS = 1
f
X
/2
9
(9.8 kHz)
f
X
/2
10
(4.9 kHz)
f
X
/2
11
(2.4 kHz)
MCS = 0
f
X
/2
10
(4.9 kHz)
f
X
/2
11
(2.4 kHz)
f
X
/2
12
(1.2 kHz)
Buzzer Output Frequency Selection
(625 kHz)
(313 kHz)
(156 kHz)
(78.1 kHz)
(39.1 kHz)
(19.5 kHz)
(9.8 kHz)
(2.4 kHz)
(313 kHz)
(156 kHz)
(78.1 kHz)
(39.1 kHz)
(19.5 kHz)
(9.8 kHz)
(4.9 kHz)
(1.2 kHz)
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(2) Port mode register 3 (PM3)
This register sets port 3 input/output in 1-bit units.
When using the P36/BUZ pin for buzzer output function, set PM36 and output latch of P36 to 0.
PM3 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM3 to FFH.
Figure 13-3. Port Mode Register 3 Format
PM37
7
PM36
6
PM35 PM34
4
PM33
3210
FF23H
Address
PM3
Symbol
PM32 PM31 PM30
5
FFH
After
Reset
R/W
R/W
PM3n
0
1
P3n Pin I/O Mode Selection (n = 0 to 7)
Output mode (output buffer ON)
Input mode (output buffer OFF)
234 User’s Manual U11377EJ3V0UD
CHAPTER 14 A/D CONVERTER
14.1 A/D Converter Functions
The A/D converter converts an analog input into a digital value. It consists of 8 channels (ANI0 to ANI7) with an
8-bit resolution.
The conversion method is based on successive approximation and the conversion result is held in the 8-bit A/D
conversion result register (ADCR).
The following two ways are available to start A/D conversion.
(1) Hardware start
Conversion is started by trigger input (INTP3).
(2) Software start
Conversion is started by setting the A/D converter mode register.
Select one channel of analog input from ANI0 to ANI7 to execute A/D conversion. In the case of hardware start,
A/D conversion operation stops and an interrupt request (INTAD) is generated when the conversion operation ends.
In the case of software start, the conversion operation is repeated. Each time the conversion operation ends, INTAD
is generated.
14.2 A/D Converter Configuration
The A/D converter consists of the following hardware.
Table 14-1. A/D Converter Configuration
Item Configuration
Analog input 8 channels (ANI0 to ANI7)
Control register A/D converter mode register (ADM)
A/D converter input select register (ADIS)
External interrupt mode register 1 (INTM1)
Register Successive approximation register (SAR)
A/D conversion result register (ADCR)
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Figure 14-1. A/D Converter Block Diagram
Notes 1. Selector to select the number of channels to be used for analog input.
2. Selector to select the channel for A/D conversion.
3. Bits 0 and 1 of external interrupt mode register 1 (INTM1)
ANI0/P10
ANI1/P11
ANI2/P12
ANI3/P13
ANI4/P14
ANI5/P15
ANI6/P16
ANI7/P17
Selector
A/D converter mode register
3
Trigger enable
ES40, ES41
Note 3
Sample & hold circuit
3
CS
4
Internal bus
Internal bus
Edge
detector Controller
Series resistor string
Voltage
comparator
Tap selector
INTAD
INTP3
Successive
approximation
register (SAR)
Note 1 Note 2
ADM1 to ADM3
INTP3/P03
TRG FR1 FR0
ADM3 ADM2 ADM1
HSC A/D conversion
result register
(ADCR)
AV
REF
AV
SS
ADIS3
A/D converter input
select register
ADIS2
ADIS1
ADIS0
Selector
AV
SS
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(1) Successive approximation register (SAR)
This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from
the series resistor string and holds the result from the most significant bit (MSB).
When up to the least significant bit (LSB) is set (termination of A/D conversion), the SAR contents are
transferred to the A/D conversion result register.
(2) A/D conversion result register (ADCR)
This register holds the A/D conversion result. Each time A/D conversion terminates, the conversion result
is loaded from the successive approximation register.
ADCR is read with an 8-bit memory manipulation instruction.
RESET input makes ADCR undefined.
(3) Sample & hold circuit
The sample & hold circuit samples each analog input signal sequentially applied from the input circuit and
sends it to the voltage comparator. This circuit holds the sampled analog input voltage value during A/D
conversion.
(4) Voltage comparator
The voltage comparator compares the analog input to the series resistor string output voltage.
(5) Series resistor string
The series resistor string is connected between AVREF and AVSS and generates a voltage to be compared with
the analog input.
(6) ANI0 to ANI7 pins
These are 8-channel analog input pins to input analog signals to undergo A/D conversion to the A/D converter.
Pins other than those selected as analog input by the A/D converter input select register (ADIS) can be used
as I/O ports.
Caution Use ANI0 to ANI7 input voltages within the specified range. If a voltage higher than AVREF
or lower than AVSS is applied (even if within the absolute maximum ratings), the converted
value of the corresponding channel becomes indeterminate and may adversely affect the
converted values of other channels.
(7) AVREF pin
This pin inputs the A/D converter reference voltage.
It converts signals input to ANI0 to ANI7 into digital signals according to the voltage applied between AVREF
and AVSS.
The current flowing in the series resistor string can be reduced by setting the voltage to be input to the AVREF
pin to AVSS level in standby mode.
The AVREF pin also functions to supply analog power to the A/D converter. When using the A/D converter,
be sure to supply power to the AVREF pin.
Caution When making the voltage applied to the AVREF pin the same level as that of AVSS, be sure
to clear bit 7 (CS) of the A/D converter mode register (ADM) to 0.
(8) AVSS pin
This is a GND potential pin of the A/D converter. Keep it at the same potential as the VSS0 pin when not using
the A/D converter.
237
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14.3 A/D Converter Control Registers
The following three types of registers are used to control the A/D converter.
•A/D converter mode register (ADM)
•A/D converter input select register (ADIS)
•External interrupt mode register 1 (INTM1)
(1) A/D converter mode register (ADM)
This register sets the analog input channel for A/D conversion, conversion time, conversion start/stop and
external trigger.
ADM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets ADM to 01H.
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Figure 14-2. A/D Converter Mode Register Format
Notes 1. Set so that the A/D conversion time is 19.1
µ
s or more.
2. Setting prohibited because A/D conversion time is less than 19.1
µ
s.
Cautions 1. The following sequence is recommended for power consumption reduction of A/D
converter when the standby function is used: Clear bit 7 (CS) to 0 first to stop the
A/D conversion operation, and then execute the HALT or STOP instruction.
2. When restarting the stopped A/D conversion operation, start the A/D conversion
operation after clearing the interrupt request flag (ADIF) to 0.
Remarks 1. fX: Main system clock oscillation frequency
2. MCS: Oscillation mode select register bit 0
CS
7
TRG
6
FR1 FR0
4
ADM3
3210
FF80H
Address
ADM
Symbol
ADM2 ADM1 HSC
5
01H
After
Reset
R/W
R/W
ADM3
0
0
0
0
1
1
1
1
ADM2
0
0
1
1
0
0
1
1
ADM1
0
1
0
1
0
1
0
1
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
TRG
0
1
No external trigger (software starts)
Conversion started by external trigger (hardware starts)
FR1
0
0
1
1
FR0
0
1
0
0
A/D Conversion Time Selection
Note 1
f
X
= 5.0 MHz Operation
80/f
X
(Setting prohibitedNote 2
)
40/f
X
(Setting prohibitedNote 2
)
50/f
X
(Setting prohibitedNote 2
)
100/f
X
(20.0 s)
Setting prohibited
µ
160/f
X
(32.0 s)
80/f
X
(
Setting prohibited
Note 2
)
100/f
X
(20.0 s)
200/f
X
(40.0 s)
f
X
= 4.19 MHz Operation
80/f
X
(19.1 s)
40/f
X
(
Setting prohibited
Note 2
)
50/f
X
(
Setting prohibited
Note 2
)
100/f
X
(23.8 s)
160/f
X
(38.1 s)
80/f
X
(19.1 s)
100/f
X
(23.8 s)
200/f
X
(47.7 s)
µ
µ
µ
µµ
µ
µ
CS
0
1
Operation stop
Operation start
HSC
1
1
0
1
µµ
A/D Conversion Operation Control
External Trigger Selection
MCS = 1 MCS = 0 MCS = 1 MCS = 0
Other than above
Analog Input Channel Selection
239
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(2) A/D converter input select register (ADIS)
This register determines whether the ANI0/P10 to ANI7/P17 pins should be used for analog input channels
or ports. Pins other than those selected as analog input can be used as I/O ports.
ADIS is set with an 8-bit memory manipulation instruction.
RESET input clears ADIS to 00H.
Cautions 1. Set the analog input channel in the following order.
(1) Set the number of analog input channels with ADIS.
(2) Using A/D converter mode register (ADM), select one channel to undergo A/D
conversion from among the channels set for analog input with ADIS.
2. No internal pull-up resistor can be used to the channels set for analog input with ADIS,
irrespective of the value of bit 1 (PUO1) of pull-up resistor option register L.
Figure 14-3. A/D Converter Input Select Register Format
0
7
0
6
00
4
ADIS3
3210
FF84H
Address
ADIS
Symbol
ADIS2 ADIS1 ADIS0
5
00H
After
Reset
R/W
R/W
ADIS3
0
0
0
0
0
0
0
0
1
Other than above
No analog input channel (P10 to P17)
1 channel (ANI0, P11 to P17)
2 channel (ANI0, ANI1, P12 to P17)
3 channel (ANI0 to ANI2, P13 to P17)
4 channel (ANI0 to ANI3, P14 to P17)
5 channel (ANI0 to ANI4, P15 to P17)
6 channel (ANI0 to ANI5, P16, P17)
7 channel (ANI0 to ANI6, P17)
8 channel (ANI0 to ANI7)
Setting prohibited
ADIS2
0
0
0
0
1
1
1
1
0
ADIS1
0
0
1
1
0
0
1
1
0
ADIS0
0
1
0
1
0
1
0
1
0
Number of Analog Input Channel Selection
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(3) External interrupt mode register 1 (INTM1)
This register sets the valid edge for INTP3 to INTP5.
INTM1 is set with an 8-bit memory manipulation instruction.
RESET input clears INTM1 to 00H.
Figure 14-4. External Interrupt Mode Register 1 Format
0
7
0
6
ES61 ES60
4
ES51
3210
FFEDH
Address
INTM1
Symbol
ES50 ES41 ES40
5
00H
After
Reset
R/W
R/W
ES41
0
0
1
1
ES40
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both falling and rising edges
ES51
0
0
1
1
ES50
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both falling and rising edges
ES61
0
0
1
1
ES60
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both falling and rising edges
INTP5 Valid Edge Selection
INTP4 Valid Edge Selection
INTP3 Valid Edge Selection
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14.4 A/D Converter Operations
14.4.1 Basic operations of A/D converter
(1) Set the number of analog input channels with A/D converter input select register (ADIS).
(2) From among the analog input channels set with ADIS, select one channel for A/D conversion with A/D converter
mode register (ADM).
(3) The sample & hold circuit samples the voltage input to the selected analog input channel.
(4) Sampling for the specified period of time sets the sample & hold circuit to the hold state so that the circuit
holds the input analog voltage until termination of A/D conversion.
(5) Set bit 7 (CS) of the A/D converter mode register (ADM). Bit 7 of the successive approximation register (SAR)
is automatically set, and the series resistor string voltage tap is set to (1/2) AVREF by the tap selector.
(6) The voltage difference between the series resistor string voltage tap and analog input is compared with a
voltage comparator. If the analog input is greater than (1/2) AVREF, the MSB of SAR remains set. If the input
is smaller than (1/2) AVREF, the MSB is reset.
(7) Next, bit 6 of SAR is automatically set and the operation proceeds to the next comparison. In this case, the
series resistor string voltage tap is selected according to the preset value of bit 7 as described below.
• Bit 7 = 1 : (3/4) AVREF
• Bit 7 = 0 : (1/4) AVREF
The voltage tap and analog input voltage are compared and bit 6 of SAR is manipulated with the result as
follows.
• Analog input voltage ≥ Voltage tap : Bit 6 = 1
• Analog input voltage ≤ Voltage tap : Bit 6 = 0
(8) Comparison of this sort continues up to bit 0 of SAR.
(9) Upon completion of the comparison of 8 bits, any effective digital resultant value remains in SAR and the
resultant value is transferred to and latched in the A/D conversion result register (ADCR).
At the same time, the A/D conversion termination interrupt request (INTAD) can also be generated.
<R>
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Figure 14-5. A/D Converter Basic Operation
A/D conversion operations are performed continuously until bit 7 (CS) of ADM is reset (to 0) by software.
If a write to the ADM register is performed during an A/D conversion operation, the conversion operation is
initialized, and if the CS bit is set (to 1), conversion starts again from the beginning.
After RESET input, the value of ADCR is undefined.
SAR
ADCR
INTAD
A/D converter
operation
Sampling time
Sampling A/D conversion
Conversion
time
Undefined 80H C0H
or
40H
Conversion
result
Conversion
result
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14.4.2 Input voltage and conversion results
The relation between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion
result (the value stored in A/D conversion result register (ADCR)) is shown by the following expression.
ADCR = INT ( × 256 + 0.5)
or
(ADCR – 0.5) ×≤ VIN < (ADCR + 0.5) ×
INT( ): Function which returns integer parts of value in parentheses.
VIN: Analog input voltage
AVREF:AVREF pin voltage
ADCR: A/D conversion result register (ADCR) value
Figure 14-6 shows the relation between the analog input voltage and the A/D conversion result.
Figure 14-6. Relationships Between Analog Input Voltage and A/D Conversion Result
VIN
AVREF
AVREF
256
AVREF
256
1
512
1
256
3
512
2
256
5
512
3
256
507
512
254
256
509
512
255
256
511
512 1
255
254
253
3
2
1
0
A/D conversion
results
(ADCR)
Input voltage/AV
REF
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14.4.3 A/D converter operating mode
One analog input channel is selected from among ANI0 to ANI7 with the A/D converter input select register (ADIS)
and A/D converter mode register (ADM) and starts A/D conversion.
The following two ways are available to start A/D conversion.
•Hardware start: Conversion is started by trigger input (INTP3).
•Software start: Conversion is started by setting ADM.
The A/D conversion result is stored in the A/D conversion result register (ADCR) and the interrupt request signal
(INTAD) is simultaneously generated.
(1) A/D conversion by hardware start
When bit 6 (TRG) and bit 7 (CS) of A/D converter mode register (ADM) are set to 1, the A/D conversion standby
state is set. When the external trigger signal (INTP3) is input, the A/D conversion starts on the voltage applied
to the analog input pins specified with bits 1 to 3 (ADM1 to ADM3) of ADM.
Upon termination of the A/D conversion, the conversion result is stored in the A/D conversion result register
(ADCR) and the interrupt request signal (INTAD) is generated. After one A/D conversion operation is started
and terminated, another operation is not started until a new external trigger signal is input.
If data with CS set to 1 is written to ADM again during A/D conversion, the converter suspends its A/D
conversion operation and waits for a new external trigger signal to be input. When the external trigger input
signal is reinput, A/D conversion is carried out from the beginning.
If data with CS set to 0 is written to ADM during A/D conversion, the A/D conversion operation stops
immediately.
Figure 14-7. A/D Conversion by Hardware Start
Remarks 1. n = 0, 1, ... , 7
2. m = 0, 1, ... , 7
ADM rewrite
CS = 1, TRG = 1
Standby
state ANIn
INTP3
A/D conversion
ADCR
INTAD
ANIn ANIn ANIn ANIm ANIm
ANIn ANIn
Standby
state
Standby
state
ADM rewrite
CS = 1, TRG = 1
ANIm ANIm ANIm
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(2) A/D conversion by software start
When bit 6 (TRG) and bit 7 (CS) of A/D converter mode register (ADM) are set to 0 and 1, respectively, the
A/D conversion starts on the voltage applied to the analog input pins specified with bits 1 to 3 (ADM1 to
ADM3) of ADM.
Upon termination of the A/D conversion, the conversion result is stored in the A/D conversion result register
(ADCR) and the interrupt request signal (INTAD) is generated. After one A/D conversion operation is started
and terminated, the next A/D conversion operation starts immediately. The A/D conversion operation
continues repeatedly until new data is written to ADM.
If data with CS set to 1 is written to ADM again during A/D conversion, the converter suspends its A/D
conversion operation and starts A/D conversion on the newly written data.
If data with CS set to 0 is written to ADM during A/D conversion, the A/D conversion operation stops
immediately.
Figure 14-8. A/D Conversion by Software Start
Remarks 1. n = 0, 1, ... , 7
2. m = 0, 1, ... , 7
Conversion start
CS = 1, TRG = 0
A/D conversion
ADCR
INTAD
ANIn ANIn ANIm
ANIn ANIm ANImANInANIn
ADM rewrite
CS = 1, TRG = 0
ADM rewrite
CS = 0, TRG = 0
Conversion suspended
Conversion results are
not stored Stop
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14.5 A/D Converter Cautions
(1) Current consumption in standby mode
The A/D converter operates on the main system clock. Therefore, its operation stops in STOP mode or in
HALT mode with the subsystem clock. As a current still flows in the AVREF pin at this time, this current must
be cut in order to minimize the overall system power dissipation. In Figure 14-9, the power dissipation can
be reduced by outputting a low-level signal to the output port in standby mode. However, there is no precision
to the actual AVREF voltage, and therefore the conversion values themselves lack precision and can only be
used for relative comparison.
Figure 14-9. Example of Method of Reducing Current Consumption in Standby Mode
(2) Input range of ANI0 to ANI7
The input voltages of ANI0 to ANI7 should be within the specification range. In particular, if a voltage above
AVREF or below AVSS is input (even if within the absolute maximum rating range), the conversion value for that
channel will be indeterminate. The conversion values of the other channels may also be affected.
Series resistor string
V
DD0
AV
REF
AV
SS
Output port
AV
REF
= V
DD0
.
.
µ
PD780308, 780308Y
V
SS0
V
SS0
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(3) Noise countermeasures
In order to maintain 8-bit resolution, attention must be paid to noise on pins AVREF and ANI0 to ANI7. Since
the effect increases in proportion to the output impedance of the analog input source, it is recommended that
a capacitor be connected externally as shown in Figure 14-10 in order to reduce noise.
Figure 14-10. Analog Input Pin Disposition
(4) Pins ANI0/P10 to ANI7/P17
The analog input pins ANI0 to ANI7 also function as I/O port (PORT1) pins. When A/D conversion is performed
with any of pins ANI0 to ANI7 selected, be sure not to execute a PORT1 input instruction while conversion
is in progress, as this may reduce the conversion resolution.
Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/D conversion, the expected
A/D conversion value may not be obtainable due to coupling noise. Therefore, avoid applying pulses to pins
adjacent to the pin undergoing A/D conversion.
(5) AVREF pin input impedance
A series resistor string of approximately 10 kΩ is connected between the AVREF pin and the AVSS pin.
Therefore, if the output impedance of the reference voltage source is high, this will result in parallel connection
to the series resistor string between the AVREF pin and the AVSS pin, and there will be a large reference voltage
error.
ANI0 to ANI7
AV
REF
AV
SS
Reference
voltage input
C = 100 to 1000 pF
If there is possibility that noise whose
level is AV
REF
or higher or AV
SS
or lower may enter,
clamp with a diode with a small V
F
(0.3 V or less).
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(6) Interrupt request flag (ADIF)
The interrupt request flag (ADIF) is not cleared even if the A/D converter mode register (ADM) is changed.
Caution is therefore required since, if a change of analog input pin is performed during A/D conversion, the
A/D conversion result and conversion end interrupt request flag for the pre-change analog input may be set
just before the ADM rewrite, and when ADIF is read immediately after the ADM rewrite, ADIF may be set despite
the fact that the A/D conversion for the post-change analog input has not ended.
When the A/D conversion is stopped and then resumed, clear the ADIF before it is resumed.
Figure 14-11. A/D Conversion End Interrupt Generation Timing
A/D conversion
ADCR
INTAD
ANIn ANIn ANIm ANIm
ANIn ANIn ANIm ANIm
ADM rewrite
(Start of ANIn conversion)
ADM rewrite
(Start of ANIm conversion)
ADIF is set but ANIm
conversion has not ended
249
User’s Manual U11377EJ3V0UD
CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (
µ
PD780308 SUBSERIES)
The
µ
PD780308 Subseries incorporates three channels of serial interfaces. Differences between channels 0,
2, and 3 are as follows (refer to CHAPTER 17 SERIAL INTERFACE CHANNEL 2 for details of serial interface
channel 2, and CHAPTER 18 SERIAL INTERFACE CHANNEL 3 for details of serial interface channel 3,
respectively).
Table 15-1. Differences Between Channels 0, 2, and 3
Channel 2
External clock, baud
rate generator output
MSB/LSB switchable as
the start bit
Serial transfer end
interrupt request flag
(SRIF)
Serial Transfer Mode Channel 0
fXX/2, fXX/22, fXX/23,
fXX/24, fXX/25, fXX/26,
fXX/27, fXX/28, external
clock, TO2 output
MSB/LSB switchable as
the start bit
Serial transfer end
interrupt request flag
(CSIIF0)
Clock selection
Transfer method
Transfer end flag
SBI (serial bus interface)
2-wire serial I/O
UART
(Asynchronous serial interface)
Use possible
None
3-wire serial I/O
None
Use possible
Channel 3
fXX/2, fXX/22, fXX/23,
fXX/24, fXX/25, fXX/26,
fXX/27, fXX/28, external
clock
MSB/LSB switchable as
the start bit
Serial transfer end
interrupt request flag
(CSIIF3)
None
None
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CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (
µ
PD780308 SUBSERIES)
User’s Manual U11377EJ3V0UD
15.1 Serial Interface Channel 0 Functions
Serial interface channel 0 employs the following four modes.
• Operation stop mode
• 3-wire serial I/O mode
• SBI (serial bus interface) mode
• 2-wire serial I/O mode
Caution Do not change the operating mode (3-wire serial I/O, 2-wire serial I/O, or SBI) while serial interface
channel 0 is enabled. To change the operating mode, stop the serial operation once.
(1) Operation stop mode
This mode is used when serial transfer is not carried out. Power consumption can be reduced.
(2) 3-wire serial I/O mode (MSB-/LSB-first selectable)
This mode is used for 8-bit data transfer using three lines, one each for serial clock (SCK0), serial output (SO0)
and serial input (SI0). This mode enables simultaneous transmission/reception and therefore reduces the data
transfer processing time.
The start bit of transferred 8-bit data is switchable between MSB and LSB, so that devices can be connected
regardless of their start bit recognition.
This mode should be used when connecting with peripheral I/O devices or display controllers which incorporate
a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K Series.
(3) SBI (serial bus interface) mode (MSB-first)
This mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (SCK0) and
serial data bus (SB0 or SB1).
The SBI mode conforms to the NEC serial bus format, and transfers or receives three types of data:
“addresses”, “commands”, and “data”.
• Address: Data to select the target device for serial communication
• Command: Data to give an instruction to the target device
• Data: Data actually transferred
Actually, the master device outputs an “address” to the serial bus to select one of the slave devices with which
the master device is to communicate. After that, “commands” and “data” are transferred or received between
the master and slave devices. The receiver can automatically identify the received data as an “address”,
“command”, or “data” by hardware.
This function enables the I/O ports to be used effectively and the application program serial interface control
portions to be simplified.
In this mode, the wake-up function for handshake and the output function of acknowledge and busy signals
can also be used.
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CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (
µ
PD780308 SUBSERIES)
User’s Manual U11377EJ3V0UD
(4) 2-wire serial I/O mode (MSB-first)
This mode is used for 8-bit data transfer using two lines of serial clock (SCK0) and serial data bus (SB0 or
SB1).
This mode enables to cope with any one of the possible data transfer formats by controlling the SCK0 level
and the SB0 or SB1 output level. Thus, the handshake line previously necessary for connection of two or
more devices can be removed, resulting in the increased number of available I/O ports.
Figure 15-1. Serial Bus Interface (SBI) System Configuration Example
Master CPU
SCK0
SB0
SCK0
SB0
Slave CPU1
SCK0
SB0
Slave CPU2
SCK0
SB0
Slave CPUn
V
DD0
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CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (
µ
PD780308 SUBSERIES)
User’s Manual U11377EJ3V0UD
15.2 Serial Interface Channel 0 Configuration
Serial interface channel 0 consists of the following hardware.
Table 15-2. Serial Interface Channel 0 Configuration
Item Configuration
Register Serial I/O shift register 0 (SIO0)
Slave address register (SVA)
Control register Timer clock select register 3 (TCL3)
Serial operating mode register 0 (CSIM0)
Serial bus interface control register (SBIC)
Interrupt timing specify register (SINT)
Port mode register 2 (PM2)Note
Note Refer to Figure 6-5 P25, P26 Block Diagram (
µ
PD780308 Subseries)
and Figure 6-6 P27 Block Diagram (
µ
PD780308 Subseries).
253
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µ
PD780308 SUBSERIES)
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Figure 15-2. Serial Interface Channel 0 Block Diagram
Remarks 1. Output control performs selection between CMOS output and N-ch open-drain output.
2. fXX = fX/2 (MCS = 0), fXX = fX (MCS = 1)
P25
output
latch
CSIE0 COI WUP CSIM
04
CSIM
03
CSIM
02
CSIM
01
CSIM
00
Serial operating
mode register 0
Controller
Output
control
Selector
SI0/SB0/
P25
PM25
Output
control
SO0/SB1/
P26
PM26
Output
control
SCK0/
P27
PM27
Selector
P26 output
latch
CLD
P27
output latch
Internal bus
Internal bus
Bus release/
command/
acknowledge
detector
Serial clock
counter
Serial clock
controller
CLR
D
SET
Q
Match
Busy/
acknowledge
output circuit
Interrupt
request
signal
generator
ACKD
CMDD
RELD
WUP
Selector Selector
f
xx
/2 to f
xx
/2
8
INTCSI0
BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
CLD SIC
SVAM
CSIM01
CSIM00
CSIM01
CSIM00
Slave address
register (SVA)
Serial I/O shift
register 0 (SIO0)
TO2
Interrupt timing
specify register
TCL33 TCL32 TCL31 TCL30
4
Timer clock
select
register 3
Serial bus interface
control register
SVAM
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(1) Serial I/O shift register 0 (SIO0)
This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception
(shift operation) in synchronization with the serial clock.
SIO0 is set with an 8-bit memory manipulation instruction.
When bit 7 (CSIE0) of serial operating mode register 0 (CSIM0) is 1, writing data to SIO0 starts serial operation.
In transmission, data written to SIO0 is output to the serial output (SO0) or serial data bus (SB0/SB1). In
reception, data is read from the serial input (SI0) or SB0/SB1 to SIO0.
Note that, if a bus is driven in the SBI mode or 2-wire serial I/O mode, the bus pin must serve for both input
and output. Thus, in the case of a device for reception, write FFH to SIO0 in advance (except when address
reception is carried out by setting bit 5 (WUP) of CSIM0 to 1).
In the SBI mode, the busy state can be cleared by writing data to SIO0. In this case, bit 7 (BSYE) of the serial
bus interface control register (SBIC) is not cleared to 0.
RESET input makes SIO0 undefined.
(2) Slave address register (SVA)
This is an 8-bit register to set the slave address value for connection of a slave device to the serial bus.
SVA is set with an 8-bit memory manipulation instruction. This register is not used in the 3-wire serial I/O
mode.
The master device outputs a slave address for selection of a particular slave device to the connected slave
device. These two data (the slave address output from the master device and the SVA value) are compared
with an address comparator. If they match, the slave device has been selected. In that case, bit 6 (COI) of
serial operating mode register 0 (CSIM0) becomes 1.
By setting bit 4 (SVAM) of the interrupt timing specify register (SINT) to 1, the address can be compared using
the data of the LSB-masked higher 7 bits.
If no matching is detected in address reception, bit 2 (RELD) of the serial bus interface control register (SBIC)
is cleared to 0.
In the SBI mode, the wake-up function can be used by setting bit 5 (WUP) of CSIM0 to 1.
In this case, an interrupt request signal (INTCSI0) is generated only when the slave address output by the
master matches the value of SVA. This interrupt request indicates that the master has requested for
communication. If bit 5 (SIC) of the interrupt timing specify register (SINT) is set to 1, the wake-up function
cannot be used even if WUP is set to 1 (the interrupt request signal is generated when bus release is detected).
When using the wake-up function, clear SIC to 0.
When the device is used as the master or slave in the SBI or 2-wire serial I/O mode, detect an error by using
SVA.
RESET input makes SVA undefined.
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(3) SO0 latch
This latch holds SI0/SB0/P25 and SO0/SB1/P26 pin levels. It can be directly controlled by software. In the
SBI mode, this latch is set upon termination of the 8th serial clock.
(4) Serial clock counter
This counter counts the serial clocks to be output and input during transmission/reception and to check whether
8-bit data has been transmitted/received.
(5) Serial clock controller
This circuit controls serial clock supply to serial I/O shift register 0 (SIO0). When the internal system clock
is used, the circuit also controls clock output to the SCK0/P27 pin.
(6) Interrupt request signal generator
This circuit controls interrupt request signal generation. It generates the interrupt request signal in the following
cases.
•In the 3-wire serial I/O mode and 2-wire serial I/O mode
This circuit generates an interrupt request signal every eight serial clocks.
•In the SBI mode
When WUPNote is 0..... Generates an interrupt request signal every eight serial clocks.
When WUPNote is 1..... Generates an interrupt request signal when the serial I/O shift register 0 (SIO0)
value matches the slave address register (SVA) value after address reception.
Note WUP is wake-up function specify bit. It is bit 5 of serial operating mode register 0 (CSIM0). Clear
bit 5 (SIC) of the interrupt timing specify register to 0 when using the wake-up function (WUP =
1).
(7) Busy/acknowledge output circuit and bus release/command/acknowledge detector
These two circuits output and detect various control signals in the SBI mode.
These do not operate in the 3-wire serial I/O mode and 2-wire serial I/O mode.
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15.3 Serial Interface Channel 0 Control Registers
The following four types of registers are used to control serial interface channel 0.
•Timer clock select register 3 (TCL3)
•Serial operating mode register 0 (CSIM0)
•Serial bus interface control register (SBIC)
•Interrupt timing specify register (SINT)
(1) Timer clock select register 3 (TCL3)
This register sets the serial clock of serial interface channel 0.
TCL3 is set with an 8-bit memory manipulation instruction.
RESET input sets TCL3 to 88H.
Figure 15-3. Timer Clock Select Register 3 Format
Cautions 1. Set bit 4 to bit 6 to 0, and bit 7 to 1.
2. When rewriting TCL3 to other data, stop the serial transfer operation beforehand.
Remarks 1. fX: Main system clock oscillation frequency
2. MCS: Oscillation mode select register bit 0
3. Figures in parentheses apply to operation with fX = 5.0 MHz.
Serial Interface Channel 0 Serial Clock Selection
TCL33 TCL32 TCL31 TCL30
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
MCS = 1
Setting prohibited
f
X
/2
2
(1.25 MHz)
f
X
/2
3
(625 kHz)
f
X
/2
4
(313 kHz)
f
X
/2
5
(156 kHz)
f
X
/2
6
(78.1 kHz)
f
X
/2
7
(39.1 kHz)
f
X
/2
8
(19.5 kHz)
MCS = 0
f
X
/2
2
(1.25 MHz)
f
X
/2
3
(625 kHz)
f
X
/2
4
(313 kHz)
f
X
/2
5
(156 kHz)
f
X
/2
6
(78.1 kHz)
f
X
/2
7
(39.1 kHz)
f
X
/2
8
(19.5 kHz)
f
X
/2
9
(9.8 kHz)
Other than above Setting prohibited
65432107
Symbol
TCL3 1 0 0 0 TCL33 TCL32 TCL31 TCL30 FF43H 88H R/W
Address After Reset R/W
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(2) Serial operating mode register 0 (CSIM0)
This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop, wake-up
function and displays the address comparator match signal.
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM0 to 00H.
Caution Do not change the operating mode (3-wire serial I/O, 2-wire serial I/O, or SBI) while serial
interface channel 0 is enabled. To change the operating mode, stop the serial operation once.
Figure 15-4. Serial Operating Mode Register 0 Format (1/2)
Notes 1. Bit 6 (COI) is a read-only bit.
2. When CSIE0 = 0, COI becomes 0.
3. Clear bit 5 (SIC) of the interrupt timing specify register (SINT) to 0 when using the wake-up
function (WUP = 1).
65432107
Symbol
CSIM0 CSIE0 COI WUP
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
FF60H 00H R/W
Note 1
Address After Reset R/W
WUP
0
1
Wake-up Function Control
Note 3
Interrupt request signal generation with each serial transfer in any mode
Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1)
matches the slave address register data in SBI mode
R/W
COI
0
1
Slave Address Comparison Result Flag
Note 2
Slave address register not equal to serial I/O shift register 0 data
Slave address register equal to serial I/O shift register 0 data
R
CSIE0
0
1
Serial Interface Channel 0 Operation Control
Operation stopped
Operation enabled
R/W
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Figure 15-4. Serial Operating Mode Register 0 Format (2/2)
Notes 1. Can be used as P25 (CMOS I/O) when used only for transmission.
2. Can be used freely as port function.
Remark ×: don’t care
PM××: Port mode register
P××: Port output latch
SBI mode
CSIM01
0
1
Serial Interface Channel 0 Clock Selection
Input clock to SCK0 pin from off-chip
8-bit timer register 2 (TM2) output
0
0
SCK0 (CMOS
I/O)
R/W
1 Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
CSIM
04
0
1
CSIM00
×
0
1
R/W
CSIM
03
CSIM
02
PM25 P25 PM26 P26 PM27 P27
Operation
Mode Start Bit SIO/SB0/P25
Pin Function
SO0/SB1/P26
Pin Function
SCK0/P27
Pin Function
×
10
×
0
×
0
0
×
0
×
0
0
1
1
Note 2 Note 2
Note 2 Note 2
MSB P25 (CMOS
I/O)
SB0 (N-ch
open-drain
I/O)
SB1 (N-ch
open-drain
I/O)
P26 (CMOS
I/O)
1
MSB
LSB
1×0001
Note 1
3-wire serial
l/O mode
SI0
Note 1
(Input)
SO0
(CMOS output)
SCK0 (CMOS
I/O)
2-wire serial
l/O mode
0
SCK0 (N-ch
open-drain
I/O)
1
11
×
0
×
0
0
×
0
×
0
0
1
1
Note 2 Note 2
Note 2 Note 2
MSB P25 (CMOS
I/O)
SB0 (N-ch
open-drain
I/O)
SB1 (N-ch
open-drain
I/O)
P26 (CMOS
I/O)
Note 1
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(3) Serial bus interface control register (SBIC)
This register sets serial interface operation and displays statuses.
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SBIC to 00H.
Figure 15-5. Serial Bus Interface Control Register Format (1/2)
Notes 1. Bits 2, 3, and 6 (RELD, CMDD, and ACKD) are read-only bits.
2. The busy mode can be cancelled by start of serial interface transfer. However, the BSYE flag
is not cleared to 0.
Remark CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
65432107
Symbol
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT FF61H 00H R/WNote 1
Address After Reset R/W
ACKE Acknowledge Signal Output Control
0 Acknowledge signal automatic output disable (output with ACKT enable)
Acknowledge signal is output in synchronization with the 9th clock
falling edge of SCK0 (automatically output when ACKE = 1).
Before completion of
transfer
Acknowledge signal is output in synchronization with the falling edge of
SCK0 just after execution of the instruction to be set to 1
(automatically output when ACKE = 1).
However, not automatically cleared to 0 after acknowledge signal output.
After completion of
transfer
1
R/W
RACKD Acknowledge Detection
Clear Conditions (ACKD = 0)
•Falling edge of the SCK0 immediately after the busy
mode is released while executing the transfer
start instruction
• When CSIE0 = 0
• When RESET input is applied
Set Conditions (ACKD = 1)
• When acknowledge signal (ACK) is detected at the
rising edge of SCK0 clock after completion of
transfer
BSYE Synchronizing Busy Signal Output Control
0Disables busy signal which is output in synchronization with the falling edge of SCK0 clock just after
execution of the instruction to be cleared to 0.
R/W Note 2
1 Outputs busy signal at the falling edge of SCK0 clock following the acknowledge signal.
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Figure 15-5. Serial Bus Interface Control Register Format (2/2)
Remarks 1. Bits 0, 1, and 4 (RELD, CMDT, and ACKT) are 0 when they are read after data has been
set.
2. CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
RELT
Used for bus release signal output.
When RELT = 1, SO Iatch is set to 1. After SO latch setting, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
R/W
CMDT
Used for command signal output.
When CMDT = 1, SO Iatch is cleared to (0). After SO latch clearance, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
R/W
RRELD Bus Release Detection
Set Conditions (RELD =1)Clear Conditions (RELD = 0)
•When bus release signal (REL) is detected
• When transfer start instruction is executed
• If SIO0 and SVA values do not match in
address reception
• When CSIE0 = 0
• When RESET input is applied
RCMDD Command Detection
Clear Conditions (CMDD = 0)
• When transfer start instruction is executed
• When bus release signal (REL) is detected
• When CSIE0 = 0
• When RESET input is applied
Set Conditions (CMDD = 1)
• When command signal (CMD) is detected
ACKT
Acknowledge signal is output in synchronization with the falling edge clock of SCK0 just after execution
of the instruction to be set to 1, and after acknowledge signal output, is automatically cleared to 0.
Used as ACKE = 0. Also cleared to 0 upon start of serial interface transfer or when CSIE0 = 0.
R/W
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(4) Interrupt timing specify register (SINT)
This register sets the bus release interrupt and address mask functions and displays the SCK0 pin level status.
SINT is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SINT to 00H.
Figure 15-6. Interrupt Timing Specify Register Format
Notes 1. Bit 6 (CLD) is a read-only bit.
2. When CSIE0 = 0, CLD becomes 0.
3. When using the wake-up function in the SBI mode, set SIC to 0.
Caution Be sure to set bit 0 to bit 3 to 0.
Remark SVA: Slave address register
CSIIF0: Interrupt request flag corresponding to INTCSI0
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
65432107
Symbol
SINT 0 CLD SIC SVAM 0 0 0 0 FF63H 00H R/WNote 1
Address After Reset R/W
SVAM
0
1
SVA Bit to Be Used as Slave Address
Bits 0 to 7
Bits 1 to 7
CLD
0
1
SCK0 Pin LevelNote 2
Low level
High level
R/W
SIC
0
1
INTCSI0 Interrupt Cause SelectionNote 3
CSIIF0 is set upon termination of serial interface channel 0 transfer
CSIIF0 is set upon bus release detection or termination of serial interface channel 0 transfer
R/W
R
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15.4 Serial Interface Channel 0 Operations
The following four operating modes are available for serial interface channel 0.
•Operation stop mode
•3-wire serial I/O mode
•SBI mode
•2-wire serial I/O mode
15.4.1 Operation stop mode
Serial transfer is not carried out in the operation stop mode. Thus, power consumption can be reduced. Serial
I/O shift register 0 (SIO0) does not carry out shift operation either and thus it can be used as an ordinary 8-bit register.
In the operation stop mode, the P25/SI0/SB0, P26/SO0/SB1 and P27/SCK0 pins can be used as ordinary I/O ports.
(1) Register setting
The operation stop mode is set with serial operating mode register 0 (CSIM0).
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM0 to 00H.
65432107
Symbol
CSIM0 CSIE0 COI WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 FF60H 00H R/W
Address After Reset R/W
CSIE0
0
Serial Interface Channel 0 Operation Control
Operation stopped
Operation enabled
R/W
1
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15.4.2 3-wire serial I/O mode operation
The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate
a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K Series.
Communication is carried out with three lines of serial clock (SCK0), serial output (SO0), and serial input (SI0).
(1) Register setting
The 3-wire serial I/O mode is set with serial operating mode register 0 (CSIM0) and the serial bus interface
control register (SBIC).
(a) Serial operating mode register 0 (CSIM0)
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM0 to 00H.
Notes 1. Bit 6 (COI) is a read-only bit.
2. Be sure to set WUP to 0 when the 3-wire serial I/O mode is selected.
3. Can be used as P25 (CMOS I/O) when used only for transmission.
Remark ×: don’t care
PM××: Port mode register
P××: Port output latch
65432107
Symbol
CSIM0
CSIM01
0
1
Serial Interface Channel 0 Clock Selection
Input clock to SCK0 pin from off-chip
8-bit timer register 2 (TM2) output
0
SBI mode (See 15.4.3 SBI mode operation)
R/W
1 Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
CSIM
04
0
CSIM00
×
0
1
FF60H 00H R/W
Note 1
Address After Reset R/W
R/W
CSIM
03
CSIM
02
PM25 P25 PM26 P26 PM27 P27
Operation
Mode Start Bit SIO/SB0/P25
Pin Function
SO0/SB1/P26
Pin Function
SCK0/P27
Pin Function
×
10
WUP
0
1
Wake-up Function Control
Note 2
Interrupt request signal generation with each serial transfer in any mode
Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1)
matches the slave address register data in SBI mode
R/W
1
MSB
LSB
1×0001
Note 3
3-wire serial
l/O mode
SI0
Note 3
(Input)
SO0
(CMOS output)
SCK0 (CMOS
I/O)
2-wire serial I/O mode (See 15.4.4 2-wire serial I/O mode operation)
11
Note 3
CSIE0
0
Serial Interface Channel 0 Operation Control
Operation stopped
Operation enabled
R/W
1
CSIE0 COI WUP
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
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CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (
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(b) Serial bus interface control register (SBIC)
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SBIC to 00H.
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
65432107
Symbol
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
RELT When RELT = 1, SO Iatch is set to 1. After SO Iatch setting, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
R/W
FF61H 00H R/W
Address After Reset R/W
CMDT When CMDT = 1, SO Iatch is cleared to 0. After SO latch clearance, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
R/W
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(2) Communication operation
The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Each bit of data is transmitted
or received in synchronization with the serial clock.
Shift operation of serial I/O shift register 0 (SIO0) is carried out at the falling edge of the serial clock (SCK0).
The transmitted data is held in the SO0 latch and is output from the SO0 pin. The received data input to the
SI0 pin is latched in SIO0 at the rising edge of SCK0.
Upon termination of 8-bit transfer, SIO0 operation stops automatically and the interrupt request flag (CSIIF0)
is set.
Figure 15-7. 3-Wire Serial I/O Mode Timings
The SO0 pin is a CMOS output pin and outputs current SO0 latch statuses. Thus, the SO0 pin output status
can be manipulated by setting bit 0 (RELT) and bit 1 (CMDT) of the serial bus interface control register (SBIC).
However, do not carry out this manipulation during serial transfer.
Control the SCK0 pin output level in the output mode (internal system clock mode) by manipulating the P27
output latch (refer to 15.4.5 SCK0/P27 pin output manipulation).
(3) Other signals
Figure 15-8 shows RELT and CMDT operations.
Figure 15-8. RELT and CMDT Operations
RELT
CMDT
SO0 latch
SI0
SCK0 12345678
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SO0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
CSIIF0
Transfer start at the falling edge of SCK0
End of transfer
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(4) MSB/LSB switching as the start bit
The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB.
Figure 15-9 shows the configuration of serial I/O shift register 0 (SIO0) and internal bus. As shown in the figure,
MSB/LSB can be read/written in reverse form.
MSB/LSB switching as the start bit can be specified with bit 2 (CSIM02) of serial operating mode register 0
(CSIM0).
Figure 15-9. Circuit of Switching in Transfer Bit Order
Start bit switching is realized by switching the bit order for data write to SIO0. The SIO0 shift order remains
unchanged.
Thus, switching between MSB-first and LSB-first must be performed before writing data to the shift register.
(5) Transfer start
Serial transfer is started by setting transfer data to serial I/O shift register 0 (SIO0) when the following two
conditions are satisfied.
•Serial interface channel 0 operation control bit (CSIE0) = 1
•Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer.
Caution If CSIE0 is set to “1” after data write to SIO0, transfer does not start.
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0)
is set.
7
6
Internal bus
1
0
LSB-first
MSB-first Read/write gate
SI0 Shift register 0 (SIO0)
Read/write gate
SO0
SCK0
DQ
SO0 latch
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15.4.3 SBI mode operation
SBI (Serial Bus Interface) is a high-speed serial interface in compliance with the NEC serial bus format.
SBI uses a single master device and employs the clocked serial I/O format with the addition of a bus configuration
function. This function enables devices to communicate using only two lines. Thus, when making up a serial bus
with two or more microcontrollers and peripheral ICs, the number of ports to be used and the number of wires on
the board can be decreased.
The master device outputs three kinds of data to slave devices on the serial data bus: “addresses” to select a device
to be communicated with, “commands” to instruct the selected device, and “data” which is actually required.
The slave device can identify the received data into “address”, “command”, or “data”, by hardware. An application
program that controls serial interface channel 0 can be simplified by using this function.
The SBI function is incorporated into various devices including 75X/XL Series and 78K Series.
Figure 15-10 shows a serial bus configuration example when a CPU having a serial interface compliant with SBI
and peripheral ICs are used.
In SBI, the SB0 (SB1) serial data bus is an open-drain output pin and therefore the serial data bus line behaves
in the same way as the wired-OR configuration. In addition, a pull-up resistor must be connected to the serial data
bus line.
When the SBI mode is used, refer to (11) SBI mode precautions (d) described later.
Figure 15-10. Example of Serial Bus Configuration with SBI
Caution When exchanging the master CPU/slave CPU, a pull-up resistor is necessary for the serial clock
line (SCK0) as well because serial clock line (SCK0) input/output switching is carried out
asynchronously between the master and slave CPUs.
Master CPU
SCK0
SB0 (SB1)
SCK0
SB0 (SB1)
SCK0
SB0 (SB1)
SCK0
SB0 (SB1)
Slave CPU
Address 1
Slave CPU
Address 2
Slave IC
Address N
Serial clock
Serial data bus
•
•
•
•
•
•
V
DD0
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CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (
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(1) SBI functions
In the conventional serial I/O format, when a serial bus is configured by connecting two or more devices, many
ports and wiring are necessary, to provide chip select signal to identify command and data, and to judge the
busy state, because only the data transfer function is available. If these operations are to be controlled by
software, the software must be heavily loaded.
In SBI, a serial bus can be configured with two signal lines of serial clock SCK0 and serial data bus SB0 (SB1).
Thus, use of SBI leads to reduction in the number of microcontroller ports and that of wirings and routings
on the board.
The SBI functions are described below.
(a) Address/command/data identify function
Serial data is distinguished into addresses, commands, and data.
(b) Chip select function by address transmission
The master executes slave chip selection by address transmission.
(c) Wake-up function
The slave can easily judge address reception (chip select judgment) with the wake-up function (which
can be set/reset by software).
When the wake-up function is set, the interrupt request signal (INTCSI0) is generated upon reception of
a match address.
Thus, when communication is executed with two or more devices, the CPU except the selected slave
devices can operate regardless of under way serial communications.
(d) Acknowledge signal (ACK) control function
The acknowledge signal to check serial data reception is controlled.
(e) Busy signal (BUSY) control function
The busy signal to report the slave busy state is controlled.
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(2) SBI definition
The SBI serial data format and the signals to be used are defined as follows.
Serial data to be transferred with SBI consists of three kinds of data: “address”, “command”, and “data”.
Figure 15-11 shows the address, command, and data transfer timings.
Figure 15-11. SBI Transfer Timings
Remark The dotted line indicates the READY status.
The bus release signal and the command signal are output by the master device. BUSY is output by the slave
signal. ACK can be output by either the master or slave device (normally, the 8-bit data receiver outputs).
Serial clocks continue to be output by the master device from 8-bit data transfer start to BUSY reset.
SCK0
SB0 (SB1)
SCK0
SB0 (SB1)
SCK0
SB0 (SB1)
89
9
A7 A0 ACK BUSY
C7 C0 ACK BUSY READY
89
D7 D0 ACK BUSY READY
Address transfer
Command transfer
Data transfer
Bus release
signal
Command signal
Address
Command
Data
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(a) Bus release signal (REL)
The bus release signal is a signal with the SB0 (SB1) line which has changed from the low level to the
high level when the SCK0 line is at the high level (without serial clock output).
This signal is output by the master device.
Figure 15-12. Bus Release Signal
The bus release signal indicates that the master device is going to transmit an address to the slave device.
The slave device incorporates hardware to detect the bus release signal.
(b) Command signal (CMD)
The command signal is a signal with the SB0 (SB1) line which has changed from the high level to the
low level when the SCK0 line is at the high level (without serial clock output). This signal is output by
the master device.
Figure 15-13. Command Signal
The command signal indicates that the master is to transmit a command to the slave (however, the
command signal following the bus release signal indicates that an address is transmitted).
The slave device incorporates hardware to detect the command signal.
SCK0 H
SB0 (SB1)
SCK0 H
SB0 (SB1)
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(c) Address
An address is 8-bit data which the master device outputs to the slave device connected to the bus line
in order to select a particular slave device.
Figure 15-14. Addresses
8-bit data following bus release and command signals is defined as an “address”. In the slave device,
this condition is detected by hardware and whether or not 8-bit data matches the own specification number
(slave address) is checked by hardware. If the 8-bit data matches the slave address, the slave device
has been selected. After that, communication with the master device continues until a release instruction
is received from the master device.
Figure 15-15. Slave Selection with Address
SCK0
A7 A6 A5 A4 A3 A2 A1 A0
12345678
SB0 (SB1)
Address
Command signal
Bus release
signal
Master Slave 1 Not selected
Slave 2 Selected
Slave 3 Not selected
Slave 4 Not selected
Slave 2
address transmission
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(d) Command and data
The master device transmits commands to, and transmits/receives data to/from the slave device selected
by address transmission.
Figure 15-16. Commands
8-bit data following a command signal is defined as “command” data. 8-bit data without command signal
is defined as “data”. Command and data operation procedures are allowed to determine by user according
to communications specifications.
Figure 15-17. Data
SCK0
D7 D6 D5 D4 D3 D2 D1 D0
12345678
SB0 (SB1)
Data
SCK0
C7 C6 C5 C4 C3 C2 C1 C0
12345678
SB0 (SB1)
Command
Command signal
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[When output in synchronization with 9th clock SCK0]
Remark The dotted line indicates the READY status.
The acknowledge signal is one-shot pulse to be generated at the falling edge of SCK0 after 8-bit data
transfer. It can be positioned anywhere and can be synchronized with any clock SCK0.
After 8-bit data transmission, the transmitter checks whether the receiver has returned the acknowledge
signal. If the acknowledge signal is not returned for the preset period of time after data transmission, it
can be judged that data reception has not been carried out correctly.
(e) Acknowledge signal (ACK)
The acknowledge signal is used to check serial data reception between transmitter and receiver.
Figure 15-18. Acknowledge Signal
[When output in synchronization with 11th clock SCK0]
SCK0
SB0 (SB1)
891011
ACK
89
ACK
SCK0
SB0 (SB1)
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(f) Busy signal (BUSY) and ready signal (READY)
The BUSY signal is intended to report to the master device that the slave device is preparing for data
transmission/reception.
The READY signal is intended to report to the master device that the slave device is ready for data
transmission/reception.
Figure 15-19. BUSY and READY Signals
Remark The dotted line indicates the READY status.
In SBI, the slave device notifies the master device of the busy state by setting SB0 (SB1) line to the low
level.
The BUSY signal output follows the acknowledge signal output from the master or slave device. It is set/
reset at the falling edge of SCK0. When the BUSY signal is reset, the master device automatically
terminates the output of SCK0 serial clock.
When the BUSY signal is reset and the READY signal is set, the master device can start the next transfer.
READYACK
SCK0
SB0 (SB1)
BUSY
89
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(3) Register setting
The SBI mode is set with serial operating mode register 0 (CSIM0), the serial bus interface control register
(SBIC), and the interrupt timing specify register (SINT).
(a) Serial operating mode register 0 (CSIM0)
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM0 to 00H.
Notes 1. Bit 6 (COI) is a read-only bit.
2. COI is 0 when CSIE0 = 0.
3. Set bit 5 (SIC) of the interrupt timing specify register (SINT) to 1 when using the wake-up
function (WUP = 1).
4. These pins can be used freely as port pins.
Remark ×: don’t care
PM××: Port mode register
P××: Port output latch
SBI mode
65432107
Symbol
CSIM0 CSIE0 COI WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
CSIM01
0
1
Serial Interface Channel 0 Clock Selection
Input clock to SCK0 pin from off-chip
8-bit timer register 2 (TM2) output
0
R/W
1 Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
CSIM
04
0
1
CSIM00
×
0
1
FF60H 00H R/W
Note 1
Address After Reset R/W
R/W CSIM
03
CSIM
02
PM25 P25 PM26 P26 PM27 P27 Operation
Mode Start Bit SI0/SB0/P25
Pin Function
SO0/SB1/P26
Pin Function
SCK0/P27
Pin Function
×
10
×
0
×
0
0
×
0
×
0
0
1
1
Note 4 Note 4
Note 4 Note 4
MSB P25 (CMOS
I/O)
SB0 (N-ch
open-drain
I/O)
SB1 (N-ch
open-drain
I/O)
P26 (CMOS
I/O)
WUP
0
1
Wake-up Function Control
Note 3
Interrupt request signal generation with each serial transfer in any mode
Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1)
matches the slave address register data in SBI mode
R/W
11
3-wire serial I/O mode (See 15.4.2 3-wire serial I/O mode operation)
2-wire serial I/O mode (See 15.4.4 2-wire serial I/O mode operation)
COI
0
Slave Address Comparison Result Flag
Note 2
Slave address register not equal to serial I/O shift register 0 data
Slave address register equal to serial I/O shift register 0 data
R
1
CSIE0
0
Serial Interface Channel 0 Operation Control
Operation stopped
Operation enabled
R/W
1
SCK0 (CMOS
I/O)
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(b) Serial bus interface control register (SBIC)
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SBIC to 00H.
(continued)
Notes 1. Bits 2, 3, and 6 (RELD, CMDD, and ACKD) are read-only bits.
2. The busy mode can be cleared by start of serial interface transfer. However, the BSYE flag
is not cleared to 0.
Remarks 1. Bits 0, 1, and 4 (RELT, CMDT, and ACKT) are 0 when read after data setting.
2. CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
65432107
Symbol
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT FF61H 00H R/W
Note 1
Address After Reset R/W
ACKE Acknowledge Signal Output Control
0 Acknowledge signal automatic output disable (output with ACKT enable)
Acknowledge signal is output in synchronization with the 9th clock falling edge of
SCK0 (automatically output when ACKE = 1).
Before completion of
transfer
Acknowledge signal is output in synchronization with falling edge clock
of SCK0 just after execution of the instruction to be set to 1
(automatically output when ACKE = 1).
However, not automatically cleared to 0 after acknowledge signal output.
After completion of
transfer
1
R/W
BSYE Synchronizing Busy Signal Output Control
0Disables busy signal which is output in synchronization with the falling edge of SCK0 clock just after
execution of the instruction to be cleared (to 0).
R/W
Note2
1 Outputs busy signal at the falling edge of SCK0 clock following the acknowledge signal.
RACKD Acknowledge Detection
Clear Conditions (ACKD = 0)
• SCK0 fall immediately after the busy mode is
released during the transfer start instruction execution.
• When CSIE0 = 0
• When RESET input is applied
Set Conditions (ACKD = 1)
•When acknowledge signal (ACK) is detected at the
rising edge of SCK0 clock after completion of
transfer
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Remarks 1. Bits 0, 1, and 4 (RELT, CMDT, and ACKT) are 0 when read after data setting.
2. CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
RELT
Used for bus release signal output.
When RELT = 1, SO Iatch is set (to 1). After SO latch setting, automatically cleared (to 0).
Also cleared to 0 when CSIE0 = 0.
R/W
CMDT
Used for command signal output.
When CMDT = 1, SO Iatch is cleared (to 0). After SO latch clearance, automatically cleared (to 0).
Also cleared to 0 when CSIE0 = 0.
R/W
RRELD Bus Release Detection
Set Conditions (RELD = 1)Clear Conditions (RELD = 0)
•When bus release signal (REL) is detected
• When transfer start instruction is executed
• If SIO0 and SVA values do not match in address
reception
• When CSIE0 = 0
• When RESET input is applied
RCMDD Command Detection
Clear Conditions (CMDD = 0)
• When transfer start instruction is executed
• When bus release signal (REL) is detected
• When CSIE0 = 0
• When RESET input is applied
Set Conditions (CMDD = 1)
• When command signal (CMD) is detected
Acknowledge signal is output in synchronization with the falling edge clock of SCK0 just after execution
of the instruction to be set (to 1) and, after acknowledge signal output, is automatically cleared (to 0).
Used as ACKE = 0. Also cleared (to 0) upon start of serial interface transfer or when CSIE0 = 0.
R/W
ACKT
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(c) Interrupt timing specify register (SINT)
SINT is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SINT to 00H.
Notes 1. Bit 6 (CLD) is a read-only bit.
2. When CSIE0 = 0, CLD becomes 0.
3. When using the wake-up function in the SBI mode, set SIC to 0.
Caution Be sure to set bit 0 to bit 3 to 0.
Remark SVA: Slave address register
CSIIF0: Interrupt request flag corresponding to INTCSI0
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
65432107
Symbol
SINT 0 CLD SIC SVAM 0 0 0 0 FF63H 00H R/W
Note 1
Address After Reset R/W
SVAM
0
1
SVA Bit to Be Used as Slave Address
Bits 0 to 7
Bits 1 to 7
SIC
0
INTCSI0 Interrupt Cause Selection
Note 3
CSIIF0 is set upon termination of serial interface channel 0 transfer
CSIIF0 is set upon bus release detection or termination of serial interface channel 0 transfer
CLD
0
1
SCK0 Pin Level
Note 2
Low level
High level
R/W
R/W
R
1
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(4) Various signals
Figures 15-20 to 15-25 show various signals and serial bus interface control register (SBIC) flag operations
in SBI. Table 15-3 lists various signals in SBI.
Figure 15-20. RELT, CMDT, RELD, and CMDD Operations (Master)
Figure 15-21. RELD and CMDD Operations (Slave)
SCK0
SB0 (SB1)
RELT
CMDT
CMDD
RELD
SIO0
Slave address write to SIO0
(Transfer start instruction)
Write FFH to SIO0
(Transfer start instruction)
SIO0
SCK0
SB0 (SB1)
RELD
CMDD
Transfer start instruction
A7 A6 A1 A0
12 789
READY
A7 A6 A1 A0 ACK
Slave address When addresses match
When addresses do not match
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Figure 15-22. ACKT Operation
Caution Do not set ACKT before termination of transfer.
SCK0 6
SB0 (SB1)
ACKT
7 8 9
D2 D1 D0 ACK
When set during
this period
ACK signal is output for
a period of one clock
just after setting
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Figure 15-23. ACKE Operations
(a) When ACKE = 1 upon completion of transfer
(b) When set after completion of transfer
(c) When ACKE = 0 upon completion of transfer
(d) When “ACKE = 1” period is short
SB0 (SB1)
ACKE
12 789
D7 D6 D2 D1 D0 ACK
When ACKE = 1 at this point
ACK signal is output
at 9th clock
SCK0
SB0 (SB1)
ACKE
789
D1 D0 ACK
6
D2
If set during this period and ACKE = 1
at the fallin
g
ed
g
e of the next SCK0
ACK signal is output for
a period of one clock
just after setting
SCK0
SB0 (SB1)
ACKE
12 789
D7 D6 D2 D1 D0
When ACKE = 0 at this point
ACK signal is not output
SCK0
SB0 (SB1)
ACKE
If set and cleared during this period
and ACKE = 0 at the falling edge of SCK0
ACK signal is not output
D2 D1 D0
SCK0
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Figure 15-24. ACKD Operations
(a) When ACK signal is output at 9th clock of SCK0
(b) When ACK signal is output after 9th clock of SCK0
(c) Clear timing when transfer start is instructed in BUSY
Figure 15-25. BSYE Operation
SCK0
SB0 (SB1)
BSYE
789
ACK
6
When BSYE = 1 at this point
BUSY
If reset during this period and
BSYE = 0 at the falling edge of SCK0
D2 D1 D0
SCK0
SB0 (SB1)
ACKD
789
D1 D0 ACK
6
D2
Transfer start
instruction
SIO0
Transfer start
SB0 (SB1)
ACKD
ACK
9
SIO0
78
D1
6
D2 D0
Transfer start
instruction
Transfer start
SCK0
SCK0
SB0 (SB1)
ACKD
ACK
9
Transfer start
instruction
SIO0
78
D1
6
D2 D0 D6D7BUSY
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Table 15-3. Various Signals in SBI Mode (1/2)
Timing Chart
Definition
Signal Name Output
Device
Output
Condition Effects on Flag Meaning of Signal
CMD signal is output
to indicate that
transmit data is an
address.
i) Transmit data is an
address after REL
signal output.
ii) REL signal is not
output and transmit
data is a command.
Low-level signal to be
output to SB0 (SB1) during
one-clock period of SCK0
after completion of serial
reception
[Synchronous BUSY signal]
Low-level signal to be
output to SB0 (SB1)
following acknowledge
signal
1 BSYE = 0
2 Execution of
instruction for
data write to
SIO0
(transfer start
instruction)
Master/
slave
SB0 (SB1) rising edge
when SCK0 = 1
Master
Bus release
signal
(REL)
•RELT set •RELD set
•CMDD clear
•CMDD set
•CMDT set
Master
Command
signal
(CMD)
SB0 (SB1) falling edge
when SCK0 = 1
Acknowledge
signal
(ACK)
1 ACKE = 1
2 ACKT set •ACKD set Completion of
reception
Slave
Busy signal
(BUSY) •BSYE = 1 —
Serial receive disable
because of
processing
—Serial receive enable
Slave
Ready signal
(READY)
High-level signal to be
output to SB0 (SB1) before
serial transfer start and
after completion of serial
transfer
[Synchronous BUSY output]
SCK0 "H"
SB0 (SB1)
"H"
SB0 (SB1)
SCK0
SCK0
D0 READY
SB0 (SB1)
D0 READY
SB0 (SB1)
ACK BUSY
BUSYACK
9
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Timing Chart
Definition
Signal Name Output
Device
Output
Condition Effects on Flag Meaning of Signal
Synchronous clock to
output address/command/
data, ACK signal, synchro-
nous BUSY signal, etc.
Address/command/data are
transferred with the first
eight synchronous clocks.
8-bit data to be transferred
in synchronization with
SCK0 after output of only
CMD signal without REL
signal output
Master
Numeric values to be
processed with slave
or master device
Serial clock
(SCK0)
Timing of signal
output to serial data
bus
Address value of
slave device on the
serial bus
Address
(A7 to A0)
8-bit data to be transferred
in synchronization with
SCK0 after output of REL
and CMD signals
Master
Commands
(C7 to C0)
Instructions and
messages to the
slave device
Master/
slave
Data
(D7 to D0)
8-bit data to be transferred
in synchronization with
SCK0 without output of
REL and CMD signals
Table 15-3. Various Signals in SBI Mode (2/2)
When CSIE0 = 1,
execution of
instruction for
data write to
SIO0 (serial
transfer start
instruction)Note 2
Notes 1. When WUP = 0, CSIIF0 is set at the rising edge of the 9th clock of SCK0.
When WUP = 1, an address is received. Only when the address matches the slave address register (SVA) value, CSIIF0 is set.
2. In BUSY state, transfer starts after the READY state is set.
Master
CSIIF0 set (rising
edge of 9th clock
of SCK0)Note 1
SCK0
SB0 (SB1)
1278910
SCK0
SB0 (SB1)
1278
REL CMD
SCK0
SB0 (SB1)
1278
CMD
SCK0
SB0 (SB1)
1278
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(5) Pin configuration
The serial clock pin SCK0 and serial data bus pin SB0 (SB1) have the following configurations.
(a) SCK0 ............ Serial clock I/O pin
<1> Master ... CMOS and push-pull output
<2> Slave...... Schmitt input
(b) SB0 (SB1) .... Serial data I/O dual-function pin
Both master and slave devices have an N-ch open-drain output and a Schmitt input.
Because the serial data bus line has an N-ch open-drain output, an external pull-up resistor is necessary.
Figure 15-26. Pin Configuration
Caution Because the N-ch open-drain output pin must go into a high-impedance state at time of data
reception, write FFH to serial I/O shift register 0 (SIO0) in advance. The N-ch open-drain can
go into a high-impedance state at any time of transfer. However, when the wake-up function
specify bit (WUP) = 1, the N-ch transistor always goes into a high-impedance state. Thus,
it is not necessary to write FFH to SIO0 before reception.
SI0
SO0
SI0
SO0
(Clock input)
Clock output
Master device
Clock input
(Clock output)
Serial clock
SCK0 SCK0
R
L
Serial data bus
SB0 (SB1) SB0 (SB1)
N-ch open drain N-ch open drain
Slave device
V
SS0
V
SS0
V
DD0
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(6) Address match detection method
In the SBI mode, the master transmits a slave address to select a specific slave device.
Address match is automatically detected by hardware. If the slave address transmitted by the master matches
the address set to the slave address register (SVA) when the wake-up function specify bit (WUP) = 1, CSIIF0
is set.
If bit 5 (SIC) of the interrupt timing specify register (SINT) is set to 1, the wake-up function cannot be used
even if WUP is set to 1 (an interrupt request signal is generated when bus release is detected). To use the
wake-up function, therefore, clear SIC to 0.
Cautions 1. Slave selection/non-selection is detected by matching of the slave address received after
bus release (RELD = 1).
For this match detection, match interrupt (INTCSI0) of the address to be generated with
WUP = 1 is normally used. Thus, execute selection/non-selection detection by slave
address when WUP = 1.
2. When detecting selection/non-selection without the use of interrupt with WUP = 0, do so
by means of transmission/reception of the command preset by program instead of using
the address match detection method.
(7) Error detection
In the SBI mode, the serial bus SB0 (SB1) status being transmitted is fetched into the destination device, that
is, serial I/O shift register 0 (SIO0). Thus, transmit errors can be detected in the following way.
(a) Method of comparing SIO0 data before transmission to that after transmission
In this case, if two data differ from each other, a transmit error is judged to have occurred.
(b) Method of using the slave address register (SVA)
Transmit data is set to both SIO0 and SVA and is transmitted. After termination of transmission, COI bit
(match signal coming from the address comparator) of serial operating mode register 0 (CSIM0) is tested.
If “1”, normal transmission is judged to have been carried out. If “0”, a transmit error is judged to have
occurred.
(8) Communication operation
In the SBI mode, the master device selects normally one slave device as communication target from among
two or more devices by outputting an “address” to the serial bus.
After the communication target device has been determined, commands and data are transmitted/received
and serial communication is realized between the master and slave devices.
Figures 15-27 to 15-30 show data communication timing charts.
Shift operation of the shift register is carried out at the falling edge of serial clock (SCK0). Transmit data is
latched into the SO0 latch and is output with MSB set as the first bit from the SB0/P25 or SB1/P26 pin. Receive
data input to the SB0 (or SB1) pin at the rising edge of SCK0 is latched into the shift register.
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Figure 15-27. Address Transmission from Master Device to Slave Device (WUP = 1)
1 2 3 4 5 6 7 8 9SCK0 pin
A7 A6 A5 A4 A3 A2 A1 A0 ACK BUSYSB0 (SB1) pin
Program processing
Serial transmission INTCSI0
generation
ACKD
set
SCK0
stop
Hardware operation
WUP←0ACKT
set
Program processing
CMDD
set
INTCSI0
generation
ACK
output
Hardware operation
CMDT
set
RELT
set
CMDT
set
Write
to SIO0
Interrupt servicing
(preparation for the next serial transfer)
Master device processing (transmitter)
Transfer line
Slave device processing (receiver)
CMDD
clear
CMDD
set
RELD
set
Serial reception BUSY
output
READY
(When SVA = SIO0)
Address
BUSY
clear
BUSY
clear
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User’s Manual U11377EJ3V0UD
Figure 15-28. Command Transmission from Master Device to Slave Device
1 2 3 4 5 6 7 8 9SCK0 pin
C7 C6 C5 C4 C3 C2 C1 C0 ACK BUSYSB0 (SB1) pin
Program processing
Serial transmission INTCSI0
generation
ACKD
set
SCK0
stop
Hardware operation
ACKT
set
Program processing
INTCSI0
generation
ACK
output
Hardware operation
CMDT
set
Write
to SIO0
Interrupt servicing
(preparation for the next serial transfer)
Master device processing (transmitter)
Transfer line
Slave device processing (receiver)
CMDD
set Serial reception BUSY
output
READY
Command
BUSY
clear
BUSY
clear
SIO0
read
Command
analysis
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Figure 15-29. Data Transmission from Master Device to Slave Device
1 2 3 4 5 6 7 8 9SCK0 pin
D7 D6 D5 D4 D3 D2 D1 D0 ACK BUSYSB0 (SB1) pin
Program processing
Serial transmission INTCSI0
generation ACKD
set
SCK0
stop
Hardware operation
ACKT
set
Program processing
INTCSI0
generation ACK
output
Hardware operation
Write
to SIO0
Interrupt servicing
(preparation for the next serial transfer)
Master device processing (transmitter)
Transfer line
Slave device processing (receiver)
Serial reception BUSY
output
READY
Data
BUSY
clear
BUSY
clear
SIO0
read
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Figure 15-30. Data Transmission from Slave Device to Master Device
1 2 3 4 5 6 7 8 9SCK0 pin
D7 D6 D5 D4 D3 D2 D1 D0 ACK BUSYSB0 (SB1) pin
Program processing
Serial reception INTCSI0
generation ACK
output
Serial
reception
Hardware operation
Program processing
INTCSI0
generation ACKD
set
Hardware operation
FFH write
to SIO0
Master device processing (receiver)
Transfer line
Slave device processing (transmitter)
Serial transmission BUSY
output
READY
Data
BUSY
clear
Write
to SIO0
SCK0
stop
BUSY
clear
12
READYBUSY D7 D6
ACKT
set
SIO0
read Receive data processing
FFH write
to SIO0
Write
to SIO0
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(9) Transfer start
Serial transfer is started by setting transfer data to serial I/O shift register 0 (SIO0) when the following two
conditions are satisfied.
•Serial interface channel 0 operation control bit (CSIE0) = 1
•Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer.
Cautions 1. If CSIE0 is set to “1” after data write to SIO0, transfer does not start.
2. Because the N-ch transistor output pin must go into a high-impedance state for data
reception, write FFH to SIO0 in advance.
However, when the wake-up function specify bit (WUP) = 1, the N-ch transistor always
goes into a high-impedance state. Thus, it is not necessary to write FFH to SIO0 before
reception.
3. If data is written to SIO0 when the slave is busy, the data is not lost.
When the busy state is cleared and SB0 (or SB1) input is set to the high level (READY)
state, transfer starts.
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0)
is set.
For pins (SB0 or SB1) which are to be used for data input/output, be sure to carry out the following settings
before serial transfer of the 1st byte after RESET input.
<1> Set the P25 and P26 output latches to 1.
<2> Set bit 0 (RELT) of the serial bus interface control register (SBIC) to 1.
<3> Reset the P25 and P26 output latches from 1 to 0.
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(10) Identifying busy status of slave
When device is in the master mode, follow the procedure below to judge whether slave device is in the busy
state or not.
<1> Detect acknowledge signal (ACK) or interrupt request signal generation.
<2> Set the port mode register PM25 (or PM26) of the SB0/P25 (or SB1/P26) pin into the input mode.
<3> Read out the pin state (when the pin level is high, the READY state is set).
After the detection of the READY state, set the port mode register to 0 and return to the output mode.
(11) SBI mode precautions
(a) Slave selection/non-selection is detected by match detection of the slave address received after bus
release (RELD = 1).
For this match detection, match interrupt (INTCSI0) of the address to be generated with WUP = 1 is
normally used. Thus, execute selection/non-selection detection by slave address when WUP = 1.
(b) When detecting selection/non-selection without the use of interrupt with WUP = 0, do so by means of
transmission/reception of the command preset by program instead of using the address match detection
method.
(c) If WUP is set to 1 during BUSY signal output, BUSY is not cleared. In SBI, the BUSY signal continues
to be output after BUSY clear instruction generation to the falling edge of the next serial clock (SCK0).
Before setting WUP to 1, be sure to clear BUSY and then check that the SB0 (SB1) has become high-
level.
(d) For pins which are to be used for data input/output, be sure to carry out the following settings before serial
transfer of the 1st byte after RESET input.
<1> Set the P25 and P26 output latches to 1.
<2> Set bit 0 (RELT) of the serial bus interface control register to 1.
<3> Reset the P25 and P26 output latches from 1 to 0.
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15.4.4 2-wire serial I/O mode operation
The 2-wire serial I/O mode can cope with any communication format by program.
Communication is basically carried out with two lines of serial clock (SCK0) and serial data input/output (SB0 or
SB1).
Figure 15-31. Serial Bus Configuration Example Using 2-Wire Serial I/O Mode
Master
SCK0
Slave
SB0 (SB1)
SCK0
SB0 (SB1)
AV
DD0
AV
DD0
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(1) Register setting
The 2-wire serial I/O mode is set with serial operating mode register 0 (CSIM0), the serial bus interface control
register (SBIC), and the interrupt timing specify register (SINT).
(a) Serial operating mode register 0 (CSIM0)
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM0 to 00H.
Notes 1. Bit 6 (COI) is a read-only bit.
2. When CSIE0 = 0, COI becomes 0.
3. Be sure to set WUP to 0 when the 2-wire serial I/O mode is selected.
4. Can be used freely as port function.
Remark ×: don’t care
PM××: Port mode register
P××: Port output latch
65432107
Symbol
CSIM0 CSIE0 COI WUP
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
CSIM01
0
1
Serial Interface Channel 0 Clock Selection
Input clock to SCK0 pin from off-chip
8-bit timer register 2 (TM2) output
R/W
1 Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
CSIM
04
0
CSIM00
×
0
1
FF60H 00H R/W
Note 1
Address After Reset R/W
R/W
CSIM
03
CSIM
02
PM25 P25 PM26 P26 PM27 P27
Operation
Mode Start Bit SIO/SB0/P25
Pin Function
SO0/SB1/P26
Pin Function
SCK0/P27
Pin Function
×
10
WUP
0
1
Wake-up Function Control
Note 3
Interrupt request signal generation with each serial transfer in any mode
Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1)
matches the slave address register data in SBI mode
R/W
2-wire serial
l/O mode
0
1
11
×
0
×
0
0
×
0
×
0
0
1
1
Note 4 Note 4
Note 4 Note 4
MSB P25 (CMOS
I/O)
SB0 (N-ch
open-drain
I/O)
SB1 (N-ch
open-drain
I/O)
P26 (CMOS
I/O)
3-wire serial I/O mode (See 15.4.2 3-wire serial I/O mode operation)
SBI mode (See 15.4.3 SBI mode operation)
COI
0
Slave Address Comparison Result Flag
Note 2
Slave address register not equal to serial I/O shift register 0 data
Slave address register equal to serial I/O shift register 0 data
R
1
CSIE0
0
Serial Interface Channel 0 Operation Control
Operation stopped
Operation enabled
R/W
1
SCK0 (N-ch
open-drain
I/O)
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(b) Serial bus interface control register (SBIC)
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SBIC to 00H.
(c) Interrupt timing specify register (SINT)
SINT is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SINT to 00H.
Notes 1. Bit 6 (CLD) is a read-only bit.
2. When CSIE0 = 0, CLD becomes 0.
Caution Be sure to set bit 0 to bit 3 to 0.
Remark CSIIF0: Interrupt request flag corresponding to INTCSI0
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
65432107
Symbol
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
RELT When RELT = 1, SO Iatch is set to 1. After SO Iatch setting, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
R/W
FF61H 00H R/W
Address After Reset R/W
CMDT When CMDT = 1, SO Iatch is cleared to 0. After SO latch clearance, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
R/W
65432107
Symbol
SINT 0 CLD SIC 0 0 0 0 FF63H 00H R/WNote 1
Address After Reset R/W
CLD
0
1
SCK0 Pin LevelNote 2
Low level
High level
R
SIC
0
1
INTCSI0 Interrupt Cause Selection
CSIIF0 is set upon termination of serial interface channel 0 transfer
CSIIF0 is set upon bus release detection or termination of serial interface channel 0 transfer
R/W
SVAM
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(2) Communication operation
The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Each bit of data is transmitted
or received in synchronization with the serial clock.
Shift operation of serial I/O shift register 0 (SIO0) is carried out in synchronization with the falling edge of the
serial clock (SCK0). The transmit data is held in the SO0 latch and is output from the SB0/P25 (or SB1/P26)
pin on an MSB-first basis. The receive data input from the SB0 (or SB1) pin is latched into the shift register
at the rising edge of SCK0.
Upon termination of 8-bit transfer, the shift register operation stops automatically and the interrupt request
flag (CSIIF0) is set.
Figure 15-32. 2-Wire Serial I/O Mode Timings
The SB0 (SB1) pin specified for the serial data bus is an N-ch open-drain I/O and thus it must be externally
connected to a pull-up resistor. Because the N-ch transistor output pin must go into a high-impedance state
for data reception, write FFH to SIO0 in advance.
The SB0 (or SB1) pin generates the SO0 latch status and thus the SB0 (or SB1) pin output status can be
manipulated by setting bit 0 (RELT) and bit 1 (CMDT) of the serial bus interface control register (SBIC).
However, do not carry out this manipulation during serial transfer.
Control the SCK0 pin output level in the output mode (internal system clock mode) by manipulating the P27
output latch (refer to 15.4.5 SCK0/P27 pin output manipulation).
1234 5 6 7 8
SCK0
D7 D6 D5 D4 D3 D2 D1 D0
SB0 (SB1)
CSIIF0
Transfer start at the falling edge of SCK0
End of transfer
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(3) Other signals
Figure 15-33 shows RELT and CMDT operations.
Figure 15-33. RELT and CMDT Operations
(4) Transfer start
Serial transfer is started by setting transfer data to serial I/O shift register 0 (SIO0) when the following two
conditions are satisfied.
•Serial interface channel 0 operation control bit (CSIE0) = 1
•Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer.
Cautions 1. If CSIE0 is set to “1” after data write to SIO0, transfer does not start.
2. Because the N-ch transistor output pin must go into a high-impedance state for data
reception, write FFH to SIO0 in advance.
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0)
is set.
(5) Error detection
In the 2-wire serial I/O mode, the serial bus SB0 (SB1) status being transmitted is fetched into the destination
device, that is, serial I/O shift register 0 (SIO0). Thus, transmit error can be detected in the following way.
(a) Method of comparing SIO0 data before transmission to that after transmission
In this case, if two data differ from each other, a transmit error is judged to have occurred.
(b) Method of using the slave address register (SVA)
Transmit data is set to both SIO0 and SVA and is transmitted. After termination of transmission, COI bit
(match signal coming from the address comparator) of serial operating mode register 0 (CSIM0) is tested.
If “1”, normal transmission is judged to have been carried out. If “0”, a transmit error is judged to have
occurred.
RELT
CMDT
SO0 latch
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15.4.5 SCK0/P27 pin output manipulation
Because the SCK0/P27 pin incorporates an output latch, static output is also possible by software in addition to
normal serial clock output.
P27 output latch manipulation enables any value of SCK0 to be set by software (SI0/SB0 and SO0/SB1 pin to be
controlled with the RELT and CMDT bits of the serial bus interface control register (SBIC)).
SCK0/P27 pin output manipulating procedure is described below.
<1> Set serial operating mode register 0 (CSIM0) (SCK0 pin is set in the output mode and serial operation is
enabled). While serial transfer is suspended, SCK0 is set to 1.
<2> Manipulate the content of the P27 output latch by executing the bit manipulation instruction.
Figure 15-34. SCK0/P27 Pin Configuration
To internal
circuit
SCK0/P27 P27 output
latch
When CSIE0 = 1
and
CSIM01 and CSIM00 are 1 and 0, or 1 and 1.
SCK0 (1 when transfer stops)
From serial clock
controller
Set by bit
manipulation instruction
299User’s Manual U11377EJ3V0UD
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (
µ
PD780308Y SUBSERIES)
The
µ
PD780308Y Subseries incorporates three channels of serial interfaces. Differences between channels
0, 2, and 3 are as follows (refer to CHAPTER 17 SERIAL INTERFACE CHANNEL 2 for details of serial interface
channel 2, and CHAPTER 18 SERIAL INTERFACE CHANNEL 3 for details of serial interface channel 3,
respectively).
Table 16-1. Differences Between Channels 0, 2, and 3
Serial Transfer Mode Channel 0
fXX/2, fXX/22, fXX/23,
fXX/24, fXX/25, fXX/26,
fXX/27, fXX/28, external
clock, TO2 output
MSB/LSB switchable as
the start bit
Serial transfer end
interrupt request flag
(CSIIF0)
Clock selection
Transfer method
Transfer end flag
I2C bus (Inter IC Bus)
2-wire serial I/O
UART
(Asynchronous serial interface)
Use possible
None
3-wire serial I/O
Channel 2
External clock, baud
rate generator output
MSB/LSB switchable as
the start bit
Serial transfer end
interrupt request flag
(SRIF)
None
Use possible
Channel 3
fXX/2, fXX/22, fXX/23,
fXX/24, fXX/25, fXX/26,
fXX/27, fXX/28, external
clock
MSB/LSB switchable as
the start bit
Serial transfer end
interrupt request flag
(CSIIF3)
None
None
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16.1 Serial Interface Channel 0 Functions
Serial interface channel 0 employs the following four modes.
• Operation stop mode
• 3-wire serial I/O mode
• 2-wire serial I/O mode
•I
2C (Inter IC) bus mode
Caution Do not change the operating mode (3-wire serial I/O, 2-wire serial I/O, or I2C bus) while serial
interface channel 0 is enabled. To change the operating mode, stop the serial operation once.
(1) Operation stop mode
This mode is used when serial transfer is not carried out. Power consumption can be reduced.
(2) 3-wire serial I/O mode (MSB-/LSB-first selectable)
This mode is used for 8-bit data transfer using three lines, one each for serial clock (SCK0), serial output (SO0)
and serial input (SI0). This mode enables simultaneous transmission/reception and therefore reduces the data
transfer processing time.
The start bit of transferred 8-bit data is switchable between MSB and LSB, so that devices can be connected
regardless of their start bit recognition.
This mode should be used when connecting with peripheral I/O devices or display controllers which incorporate
a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K Series.
(3) 2-wire serial I/O mode (MSB-first)
This mode is used for 8-bit data transfer using two lines of serial clock (SCK0) and serial data bus (SB0 or
SB1).
This mode enables to cope with any one of the possible data transfer formats by controlling the SCK0 level
and the SB0 or SB1 output level. Thus, the handshake line previously necessary for connection of two or
more devices can be removed, resulting in the increased number of available I/O ports.
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(4) I2C (Inter IC) bus mode (MSB-first)
This mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (SCL) and
serial data bus (SDA0 or SDA1).
This mode is in compliance with the I2C bus format. In this mode, the transmitter outputs three kinds of data
onto the serial data bus: “start condition”, “data”, and “stop condition”, to be actually sent or received. The
receiver automatically distinguishes the received data into “start condition”, “data”, or “stop condition”, by
hardware.
Figure 16-1. Serial Bus Configuration Example Using I2C Bus
Master CPU
SCL
SDA0 (SDA1)
SCL
SDA0 (SDA1)
Slave CPU1
Slave CPU2
Slave CPUn
V
DD0
V
DD0
SCL
SDA0 (SDA1)
SCL
SDA0 (SDA1)
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16.2 Serial Interface Channel 0 Configuration
Serial interface channel 0 consists of the following hardware.
Table 16-2. Serial Interface Channel 0 Configuration
Item Configuration
Register Serial I/O shift register 0 (SIO0)
Slave address register (SVA)
Control register Timer clock select register 3 (TCL3)
Serial operating mode register 0 (CSIM0)
Serial bus interface control register (SBIC)
Interrupt timing specify register (SINT)
Port mode register 2 (PM2)Note
Note Refer to Figure 6-7 P25, P26 Block Diagram (
µ
PD780308Y
Subseries) and Figure 6-8 P27 Block Diagram (
µ
PD780308Y
Subseries).
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Figure 16-2. Serial Interface Channel 0 Block Diagram
Remarks 1. Output control performs selection between CMOS output and N-ch open-drain output.
2. fXX = fX/2 (MCS = 0), fXX = fX (MCS = 1)
(1) Serial I/O shift register 0 (SIO0)
This is an 8-bit register to carry out parallel-serial conversion and to carry out serial transmission/reception
(shift operation) in synchronization with the serial clock.
SIO0 is set with an 8-bit memory manipulation instruction.
When bit 7 (CSIE0) of serial operating mode register 0 (CSIM0) is 1, writing data to SIO0 starts serial operation.
In transmission, data written to SIO0 is output to the serial output (SO0) or serial data bus (SB0/SB1). In
reception, data is read from the serial input (SI0) or SB0/SB1 to SIO0.
CSIE0 COI WUP CSIM
04
CSIM
03
CSIM
02
CSIM
01
CSIM
00
Serial operating mode register 0
Controller
Output
control
Selector
SI0/SB0/
SDA0/P25
PM25
Output
control
SO0/SB1/
SDA1/P26
PM26
Output
control
SCK0/
SCL/P27
PM27
P25
output
latch
P26 output latch
CLD
P27
output latch
Internal bus
BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
Internal bus
Stop condition/
start condition/
acknowledge
detector
Serial clock
counter
Serial clock
controller
CLR
D
SET
Q
Match
Acknowledge
output circuit
Interrupt
request
signal
generator
ACKD
CMDD
RELD
WUP
Selector Selector
f
XX
/2 to f
XX
/2
8
INTCSI0
CSIM01
CSIM00
TO2
1/16
divider
CSIM01
CSIM00
Slave address
register (SVA)
Serial bus interface
control register
CLD SIC
SVAM
CLC WREL
WAT1 WAT0
Interrupt timing
specify register
2
Serial I/O shift
register 0 (SIO0)
4
TCL33 TCL32 TCL31 TCL30
Timer clock
select
register 3
Selector
BSYE
SVAM
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Note that, if a bus is driven in the I2C bus mode or 2-wire serial I/O mode, the bus pin must serve for both
input and output. Therefore, the transmission N-ch transistor of the device which will start reception of data
must be turned off beforehand. Consequently, write FFH to SIO0 in advance.
In the I2C bus mode, set SIO0 to FFH with bit 7 (BSYE) of the serial bus interface control register (SBIC) set
to 1.
RESET input makes SIO0 undefined.
Caution Do not execute an instruction that writes SIO0 while WUP (bit 5 of serial operating mode
register 0 (CSIM0)) is 1 in the I2C bus mode. Even if this instruction is not executed, data
can be received when the wake-up function is used (WUP = 1). For the details of the wake-
up function, refer to 16.4.4 (1) (c) Wake-up function.
(2) Slave address register (SVA)
This is an 8-bit register to set the slave address value for connection of a slave device to the serial bus.
SVA is set with an 8-bit memory manipulation instruction. This register is not used in the 3-wire serial I/O
mode.
The master device outputs a slave address for selection of a particular slave device to the connected slave
device. These two data (the slave address output from the master device and the SVA value) are compared
with an address comparator. If they match, the slave device has been selected. In that case, bit 6 (COI) of
serial operating mode register 0 (CSIM0) becomes 1.
By setting bit 4 (SVAM) of the interrupt timing specify register (SINT) to 1, the address can be compared using
the data of the LSB-masked higher 7 bits.
If no matching is detected in address reception, bit 2 (RELD) of the serial bus interface control register (SBIC)
is cleared to 0.
In the I2C bus mode, the wake-up function can be used by setting bit 5 (WUP) of CSIM0 to 1. In this case,
an interrupt request signal (INTCSI0) is generated when the slave address output by the master matches the
value of SVA (the interrupt request signal is also generated when the stop condition is detected). This interrupt
request indicates that the master has requested for communication. Note that SIC must be set to 1 when the
wake-up function is used.
When the device is used as the master or slave in the 2-wire serial I/O or I2C bus mode, detect an error by
using the slave address register (SVA).
RESET input makes SVA undefined.
(3) SO0 latch
This latch holds SI0/SB0/SDA0/P25 and SO0/SB1/SDA1/P26 pin levels. It can be directly controlled by
software.
(4) Serial clock counter
This counter counts the serial clocks to be output and input during transmission/reception and to check whether
8-bit data has been transmitted/received.
(5) Serial clock controller
This circuit controls serial clock supply to serial I/O shift register 0 (SIO0). When the internal system clock
is used, the circuit also controls clock output to the SCK0/SCL/P27 pin.
(6) Interrupt request signal generator
This circuit controls interrupt request signal generation. It generates interrupt request signals according to
the settings of interrupt timing specify register (SINT) bits 0 and 1 (WAT0, WAT1) and serial operating mode
register 0 (CSIM0) bit 5 (WUP), as shown in Table 16-3.
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(7) Acknowledge output circuit and stop condition/start condition/acknowledge detector
These two circuits output and detect various control signals in the I2C bus mode.
These do not operate in the 3-wire serial I/O mode and 2-wire serial I/O mode.
Table 16-3. Serial Interface Channel 0 Interrupt Request Signal Generation
Serial Transfer Mode
BSYE WUP WAT1 WAT0 ACKE
Description
3-wire or 2-wire serial I/O mode 0 0 0 0 0 An interrupt request signal is generated each time 8
serial clocks are counted.
Other than above Setting prohibited
I2C bus mode (transmit) 0 0 1 0 0 An interrupt request signal is generated each time 8
serial clocks are counted (8-clock wait).
Normally, during transmission the settings WAT21,
WAT0 = 1, 0, are not used. They are used only when
wanting to coordinate receive time and processing
systematically using software. ACK information is
generated by the receiving side, thus ACKE should be
set to 0 (disable).
1 1 0 An interrupt request signal is generated each time 9
serial clocks are counted (9-clock wait).
ACK information is generated by the receiving side,
thus ACKE should be set to 0 (disable).
Other than above Setting prohibited
I2C bus mode (receive) 1 0 1 0 0 An interrupt request signal is generated each time 8
serial clocks are counted (8-clock wait).
ACK information is output by manipulating ACKT by
software after an interrupt request is generated.
1 1 0/1 An interrupt request signal is generated each time 9
serial clocks are counted (9-clock wait).
To automatically generate ACK information, preset
ACKE to 1 before transfer start. However, in the case
of the master, set ACKE to 0 (disable) before receiving
the last data.
1 1 1 1 1 Generates an interrupt request signal when the
values of serial I/O shift register 0 (SIO0) and slave
address register (SVA) match, or when the stop
condition is detected, after an address has been
received.
To automatically generate ACK information, preset
ACKE to 1 (enable) before transfer start.
Other than above Setting prohibited
BSYE: Bit 7 of serial bus interface control register (SBIC)
ACKE: Bit 5 of serial bus interface control register (SBIC)
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16.3 Serial Interface Channel 0 Control Registers
The following four types of registers are used to control serial interface channel 0.
•Timer clock select register 3 (TCL3)
•Serial operating mode register 0 (CSIM0)
•Serial bus interface control register (SBIC)
•Interrupt timing specify register (SINT)
(1) Timer clock select register 3 (TCL3)
This register sets the serial clock of serial interface channel 0.
TCL3 is set with an 8-bit memory manipulation instruction.
RESET input sets TCL3 to 88H.
Figure 16-3. Timer Clock Select Register 3 Format
Cautions 1. Set bit 4 to bit 6 to 0, and bit 7 to 1.
2. When rewriting TCL3 to other data, stop the serial transfer operation beforehand.
Remarks 1. fX: Main system clock oscillation frequency
2. MCS: Oscillation mode select register bit 0
3. Figures in parentheses apply to operation with fX = 5.0 MHz.
Serial Interface Channel 0 Serial Clock Selection
TCL33 TCL32 TCL31 TCL30
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
MCS = 1
Setting prohibited
f
X
/2
6
(78.1 kHz)
f
X
/2
7
(39.1 kHz)
f
X
/2
8
(19.5 kHz)
f
X
/2
9
(9.77 kHz)
f
X
/2
10
(4.88 kHz)
f
X
/2
11
(2.44 kHz)
f
X
/2
12
(1.22 kHz)
MCS = 1
Setting prohibited
f
X
/2
2
(1.25 MHz)
f
X
/2
3
(625 kHz)
f
X
/2
4
(313 kHz)
f
X
/2
5
(156 kHz)
f
X
/2
6
(78.1 kHz)
f
X
/2
7
(39.1 kHz)
f
X
/2
8
(19.5 kHz)
Other than above Setting prohibited
65432107
Symbol
TCL3 1 0 0 0 TCL33 TCL32 TCL31 TCL30 FF43H 88H R/W
Address After Reset R/W
MCS = 0
f
X
/2
6
(78.1 kHz)
f
X
/2
7
(39.1 kHz)
f
X
/2
8
(19.5 kHz)
f
X
/2
9
(9.77 kHz)
f
X
/2
10
(4.88 kHz)
f
X
/2
11
(2.44 kHz)
f
X
/2
12
(1.22 kHz)
f
X
/2
13
(0.61 kHz)
MCS = 0
f
X
/2
2
(1.25 MHz)
f
X
/2
3
(625 kHz)
f
X
/2
4
(313 kHz)
f
X
/2
5
(156 kHz)
f
X
/2
6
(78.1 kHz)
f
X
/2
7
(39.1 kHz)
f
X
/2
8
(19.5 kHz)
f
X
/2
9
(9.8 kHz)
Serial Clock in I
2
C Bus Mode Serial Clock in 2-Wire or 3-Wire
Serial I/O Mode
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(2) Serial operating mode register 0 (CSIM0)
This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop, wake-up
function and displays the address comparator match signal.
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM0 to 00H.
Caution Do not change the operating mode (3-wire serial I/O, 2-wire serial I/O, or I2C bus) while serial
interface channel 0 is enabled. To change the operating mode, stop the serial operation once.
Figure 16-4. Serial Operating Mode Register 0 Format (1/2)
Notes 1. Bit 6 (COI) is a read-only bit.
2. When CSIE0 = 0, COI becomes 0.
3. Set bit 5 (SIC) of the interrupt timing specify register (SINT) to 1 when using the wake-up
function (WUP = 1). Do not execute an instruction that writes to serial I/O shift register 0 (SIO0)
while WUP = 1.
Remark ×: don’t care
PM××: Port mode register
P××: Port output latch
65432107
Symbol
CSIM0 CSIE0 COI WUP
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
FF60H 00H R/W
Note 1
Address After Reset R/W
WUP
0
1
Wake-up Function Control
Note 3
Interrupt request signal generation with each serial transfer in any mode
Interrupt request signal generation when the address received after detecting start condition
(when CMDD = 1) matches the slave address register data in I
2
C bus mode
R/W
COI
0
1
Slave Address Comparison Result Flag
Note 2
Slave address register not equal to serial I/O shift register 0 data
Slave address register equal to serial I/O shift register 0 data
R
CSIE0
0
1
Serial Interface Channel 0 Operation Control
Operation stopped
Operation enabled
R/W
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (
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Figure 16-4. Serial Operating Mode Register 0 Format (2/2)
Notes 1. Set bit 5 (SIC) of the interrupt timing specify register (SINT) to 1 when using the wake-up
function (WUP = 1). Do not execute an instruction that writes to serial I/O shift register 0 (SIO0)
while WUP = 1.
2. This pin can be used as P25 (CMOS I/O) only to transmit data.
3. These pins can be used freely as port pins.
4. In the I2C bus mode, the clock frequency becomes 1/16 of that output from TO2.
CSIM01
0
1
Serial Interface Channel 0 Clock Selection
Input clock to SCK0/SCL pin from off-chip
8-bit timer register 2 (TM2) output
Note 4
0
R/W
1 Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
CSIM
04
0
CSIM00
×
0
1
R/W
CSIM
03
CSIM
02
PM25 P25 PM26 P26 PM27 P27
Operation
Mode Start Bit SI0/SB0/SDA0/
P25 Pin Function
SO0/SB1/SDA1/
P26 Pin Function
SCK0/SCL/P27
Pin Function
×1
MSB
LSB
1×0001
Note 2
3-wire serial
l/O mode
SI0
Note 1
(Input)
SO0
(CMOS output)
SCK0 (CMOS
I/O)
2-wire serial
l/O mode
or
I
2
C bus mode
0SCK0/SCL
(N-ch open-
drain I/O)
1
11
×
0
×
0
0
×
0
×
0
0
1
1
Note 3 Note 3
Note 3 Note 3
MSB P25 (CMOS
I/O)
SB0/SDA0
(N-ch open-drain
I/O)
SB1/SDA1
(N-ch open-drain
I/O)
P26 (CMOS
I/O)
Note 2
309
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(3) Serial bus interface control register (SBIC)
This register sets serial bus interface operation and displays statuses.
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SBIC to 00H.
Figure 16-5. Serial Bus Interface Control Register Format (1/2)
Notes 1. Bits 2, 3, and 6 (RELD, CMDD, and ACKD) are read-only bits.
2. The busy mode can be cancelled by start of serial interface transfer or reception of address signal.
However, the BSYE flag is not cleared to 0.
3. When using the wake-up function, be sure to set BSYE to 1.
4. Setting should be performed before transfer.
5. If 8-clock wait mode is selected, the acknowledge signal at reception time must be output using
ACKT.
Remarks 1. Bits 0, 1, and 4 (RELT, CMDT, and ACKT) are 0 when read after data setting.
2. CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
65432107
Symbol
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT FF61H 00H R/W
Note 1
Address After Reset R/W
RCMDD Start Condition Detection
Clear Conditions (CMDD = 0)
• When transfer start instruction is executed
• When stop condition signal is detected
• When CSIE0 = 0
• When RESET input is applied
Set Conditions (CMDD = 1)
• When start condition signal is detected
ACKT
Keeps SDA0 (SDA1) low from set instruction (ACKT = 1) execution to the next falling edge of SCL.
Used to generate the ACK signal by software when 8-clock wait mode is selected.
Also cleared to 0 upon start of serial interface transfer or when CSIE0 = 0.
R/W
BSYE Control of N-ch Open-Drain Output for Transmission in I
2
C Bus Mode
Note 3
0Output enabled (transmission)
R/W
Note 2
1Output disabled (reception)
RACKD Acknowledge Detection
Clear Conditions (ACKD = 0)
• When CSIE0 = 0
• When RESET
• When transfer start instruction is executed
input is applied
Set Conditions (ACKD = 1)
• When acknowledge signal is detected at the
rising edge of SCL clock after completion of
transfer
ACKE Acknowledge Signal Automatic Output Control
Note 4
0Disables acknowledge signal automatic output. (However, output with ACKT is enabled)
Used for reception when 8-clock wait mode is selected or for transmission.
Note 5
Enables acknowledge signal automatic output.
Outputs acknowledge signal in synchronization with the falling edge of the 9th SCL clock cycle
(automatically output when ACKE = 1).
However, not automatically cleared to 0 after acknowledge signal output.
Used in reception with 9-clock wait mode selected.
1
R/W
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Figure 16-5. Serial Bus Interface Control Register Format (2/2)
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
RELT
Used for stop condition signal output.
When RELT = 1, SO Iatch is set to 1. After SO latch setting, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
R/W
CMDT
Used for start condition signal output.
When CMDT = 1, SO Iatch is cleared (to 0). After SO latch clearance, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
R/W
RRELD Stop Condition Detection
Set Conditions (RELD =1)Clear Conditions (RELD = 0)
•When stop condition signal is detected
• When transfer start instruction is executed
• If SIO0 and SVA values do not match in
address reception
• When CSIE0 = 0
• When RESET input is applied
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(4) Interrupt timing specify register (SINT)
This register controls interrupt, wait, and clock level, sets the address mask functions, and displays the SCK0/
SCL pin level status.
SINT is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SINT to 00H.
Figure 16-6. Interrupt Timing Specify Register Format (1/2)
Notes 1. Bit 6 (CLD) is a read-only bit.
2. When CSIE0 = 0, CLD becomes 0.
3. When using wake-up function in the I2C bus mode, set SIC to 1.
4. When not using the I2C bus mode, set CLC to 0.
Remark SVA: Slave address register
CSIIF0: Interrupt request flag corresponding to INTCSI0
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
65432107
Symbol
SINT 0 CLD SIC SVAM CLC WREL WAT1 WAT0 FF63H 00H R/WNote 1
Address After Reset R/W
CLD
0
1
SCK0/SCL Pin LevelNote 2
Low level
High level
R
SIC
0
INTCSI0 Interrupt Cause SelectionNote 3
CSIIF0 is set to 1 upon termination of serial interface channel 0 transfer
CSIIF0 is set to 1 upon stop condition detection or termination of serial interface channel 0 transfer
R/W
1
SVAM
0
1
SVA Bit to Be Used as Slave Address
Bits 0 to 7
Bits 1 to 7
R/W
Used in I2C bus mode.
Make SCL pin enter high-impedance state unless serial transfer is being performed (except for clock line
which is kept high).
Used to enable master device to generate start condition and stop condition signals.
CLC
0
1
Clock Level ControlNote 4
Used in I2C bus mode.
Make output level of SCL pin low unless serial transfer is being performed.
R/W
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Figure 16-6. Interrupt Timing Specify Register Format (2/2)
WAT1
0
1
Wait and Interrupt Control
Generates interrupt service request at rising edge of 8th SCK0 clock cycle (keeping clock output
in high impedance).
R/W WAT0
0
0Used in I
2
C bus mode (8-clock wait).
Generates interrupt service request at rising edge of 8th SCL clock cycle.
(In the case of master device, makes SCL output low to enter wait state after 8 clock pulses are
output. In the case of slave device, makes SCL output low to request wait state after 8 clock
pulses are input.)
11Used in I
2
C bus mode (9-clock wait).
Generates interrupt service request at rising edge of 9th SCL clock cycle.
(In the case of master device, makes SCL output low to enter wait state after 9 clock pulses are
output. In the case of slave device, makes SCL output low to request wait state after 9 clock
pulses are input.)
0 Setting prohibited
1
WREL
0Wait state has been cancelled.
Cancels wait state. Automatically cleared to 0 when the state is cancelled.
(Used to cancel wait state by means of WAT0 and WAT1.)
R/W
1
Wait Sate Cancellation Control
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16.4 Serial Interface Channel 0 Operations
The following four operating modes are available for serial interface channel 0.
•Operation stop mode
•3-wire serial I/O mode
•2-wire serial I/O mode
•I2C (Inter IC) bus mode
16.4.1 Operation stop mode
Serial transfer is not carried out in the operation stop mode. Thus, power consumption can be reduced. Serial
I/O shift register 0 (SIO0) does not carry out shift operation either and thus it can be used as ordinary 8-bit register.
In the operation stop mode, the P25/SI0/SB0/SDA0, P26/SO0/SB1/SDA1 and P27/SCK0/SCL pins can be used
as ordinary I/O ports.
(1) Register setting
The operation stop mode is set with serial operating mode register 0 (CSIM0).
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM0 to 00H.
65432107
Symbol
CSIM0 CSIE0 COI WUP
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
FF60H 00H R/W
Address After Reset R/W
CSIE0
0
Serial Interface Channel 0 Operation Control
Operation stopped
Operation enabled
R/W
1
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16.4.2 3-wire serial I/O mode operation
The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate
a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K Series.
Communication is carried out with three lines of serial clock (SCK0), serial output (SO0), and serial input (SI0).
(1) Register setting
The 3-wire serial I/O mode is set with serial operating mode register 0 (CSIM0) and the serial bus interface
control register (SBIC).
(a) Serial operating mode register 0 (CSIM0)
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM0 to 00H.
Notes 1. Bit 6 (COI) is a read-only bit.
2. Be sure to set WUP to 0 when the 3-wire serial I/O mode is selected.
3. Can be used as P25 (CMOS I/O) when used only for transmission.
Remark ×: don’t care
PM××: Port mode register
P××: Port output latch
65432107
Symbol
CSIM0 CSIE0 COI WUP
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
CSIM01
0
1
Serial Interface Channel 0 Clock Selection
Input clock to SCK0 pin from off-chip
8-bit timer register 2 (TM2) output
0
2-wire serial I/O mode (See 16.4.3 2-wire serial I/O mode operation)
R/W
1 Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
CSIM
04
0
CSIM00
×
0
1
FF60H 00H R/W
Note 1
Address After Reset R/W
R/W
CSIM
03
CSIM
02
PM25 P25 PM26 P26 PM27 P27
Operation
Mode Start Bit
SIO/SB0/SDA0
/P25 Pin Function
SO0/SB1/SDA1
/P26 Pin Function
SCK0/SCL/P27
Pin Function
×
11
WUP
0
1
Wake-up Function Control
Note 2
Interrupt request signal generation with each serial transfer in any mode
Interrupt request signal generation when the address received after detecting start condition
(when CMDD = 1) matches the slave address register data in I
2
C bus mode
R/W
1
MSB
LSB
1×0001
Note 3
3-wire serial
l/O mode
SI0
Note 3
(Input)
SO0
(CMOS output)
SCK0 (CMOS
I/O)
I
2
C bus mode (See 16.4.4 I
2
C bus mode operation)
Note 3
CSIE0
0
Serial Interface Channel 0 Operation Control
Operation stopped
Operation enabled
R/W
1
or
315
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (
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(b) Serial bus interface control register (SBIC)
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SBIC to 00H.
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
65432107
Symbol
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
RELT When RELT = 1, SO Iatch is set to 1. After SO Iatch setting, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
R/W
FF61H 00H R/W
Address After Reset R/W
CMDT When CMDT = 1, SO Iatch is cleared to 0. After SO latch clearance, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
R/W
316
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(2) Communication operation
The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Each bit of data is transmitted
or received in synchronization with the serial clock.
Shift operation of serial I/O shift register 0 (SIO0) is carried out at the falling edge of the serial clock (SCK0).
The transmitted data is held in the SO0 latch and is output from the SO0 pin. The received data input to the
SI0 pin is latched in SIO0 at the rising edge of SCK0.
Upon termination of 8-bit transfer, SIO0 operation stops automatically and the interrupt request flag (CSIIF0)
is set.
Figure 16-7. 3-Wire Serial I/O Mode Timings
The SO0 pin is a CMOS output pin and outputs current SO0 latch statuses. Thus, the SO0 pin output status
can be manipulated by setting bit 0 (RELT) and bit 1 (CMDT) of the serial bus interface control register (SBIC).
However, do not carry out this manipulation during serial transfer.
Control the SCK0 pin output level in the output mode (internal system clock mode) by manipulating the P27
output latch (refer to 16.4.7 SCK0/SCL/P27 pin output manipulation).
(3) Other signals
Figure 16-8 shows RELT and CMDT operations.
Figure 16-8. RELT and CMDT Operations
SI0
SCK0 12345678
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SO0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
CSIIF0
Transfer start at the falling edge of SCK0
End of transfer
RELT
CMDT
SO0 latch
317
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(4) MSB/LSB switching as the start bit
The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB.
Figure 16-9 shows the configuration of serial I/O shift register 0 (SIO0) and internal bus. As shown in the figure,
MSB/LSB can be read/written in reverse form.
MSB/LSB switching as the start bit can be specified with bit 2 (CSIM02) of serial operating mode register 0
(CSIM0).
Figure 16-9. Circuit of Switching in Transfer Bit Order
Start bit switching is realized by switching the bit order for data write to SIO0. The SIO0 shift order remains
unchanged.
Thus, switching between MSB-first and LSB-first must be performed before writing data to the shift register.
(5) Transfer start
Serial transfer is started by setting transfer data to serial I/O shift register 0 (SIO0) when the following two
conditions are satisfied.
•Serial interface channel 0 operation control bit (CSIE0) = 1
•Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer.
Caution If CSIE0 is set to “1” after data write to SIO0, transfer does not start.
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0)
is set.
7
6
Internal bus
1
0
LSB-first
MSB-first Read/write gate
SI0 Shift register 0 (SIO0)
Read/write gate
SO0
SCK0
DQ
SO0 latch
318
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (
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16.4.3 2-wire serial I/O mode operation
The 2-wire serial I/O mode can cope with any communication format by program.
Communication is basically carried out with two lines of serial clock (SCK0) and serial data input/output (SB0 or
SB1).
Figure 16-10. Serial Bus Configuration Example Using 2-Wire Serial I/O Mode
(1) Register setting
The 2-wire serial I/O mode is set with serial operating mode register 0 (CSIM0), the serial bus interface control
register (SBIC), and the interrupt timing specify register (SINT).
Master
SCK0
Slave
SB0 (SB1)
SCK0
SB0 (SB1)
VDD0VDD0
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (
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(a) Serial operating mode register 0 (CSIM0)
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM0 to 00H.
Notes 1. Bit 6 (COI) is a read-only bit.
2. When CSIE0 = 0, COI becomes 0.
3. Be sure to set WUP to 0 when the 2-wire serial I/O mode is selected.
4. Can be used freely as port function.
Remark ×: don’t care
PM××: Port mode register
P××: Port output latch
65432107
Symbol
CSIM0 CSIE0 COI WUP
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
CSIM01
0
1
Serial Interface Channel 0 Clock Selection
Input clock to SCK0 pin from off-chip
8-bit timer register 2 (TM2) output
R/W
1 Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
CSIM
04
0
CSIM00
×
0
1
FF60H 00H R/W
Note 1
Address After Reset R/W
R/W
CSIM
03
CSIM
02
PM25 P25 PM26 P26 PM27 P27
Operation
Mode Start Bit
SIO/SB0/SDA0
/P25 Pin Function
SO0/SB1/SDA1
/P26 Pin Function
SCK0/SCL/P27
Pin Function
×
WUP
0
1
Wake-up Function Control
Note 3
Interrupt request signal generation with each serial transfer in any mode
Interrupt request signal generation when the address received after detecting start condition
(when CMDD = 1) matches the slave address register data in I
2
C bus mode
R/W
2-wire serial
l/O mode
or
I
2
C bus mode
0
SCK0/SCL
(N-ch open-drain
I/O)
1
11
×
0
×
0
0
×
0
×
0
0
1
1
Note 4 Note 4
Note 4 Note 4
MSB P25 (CMOS
I/O)
SB0/SDA0
(N-ch open-drain
I/O)
SB1/SDA1
(N-ch open-drain
I/O)
P26 (CMOS
I/O)
3-wire serial I/O mode (See 16.4.2 3-wire serial I/O mode operation)
COI
0
Slave Address Comparison Result Flag
Note 2
Slave address register not equal to serial I/O shift register 0 data
Slave address register equal to serial I/O shift register 0 data
R
1
CSIE0
0
Serial Interface Channel 0 Operation Control
Operation stopped
Operation enabled
R/W
1
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (
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(b) Serial bus interface control register (SBIC)
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SBIC to 00H.
(c) Interrupt timing specify register (SINT)
SINT is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SINT to 00H.
Notes 1. Bit 6 (CLD) is a read-only bit.
2. When CSIE0 = 0, CLD becomes 0.
Caution Be sure to set bit 0 to bit 3 to 0 when 2-wire serial I/O mode is used.
Remark CSIIF0: Interrupt request flag corresponding to INTCSI0
65432107
Symbol
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
RELT When RELT = 1, SO Iatch is set to 1. After SO Iatch setting, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
R/W
FF61H 00H R/W
Address After Reset R/W
CMDT When CMDT = 1, SO Iatch is cleared to 0. After SO latch clearance, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
R/W
65432107
Symbol
SINT 0 CLD SIC CLC WREL WAT1 WAT0 FF63H 00H R/W
Note 1
Address After Reset R/W
SVAM
SIC
0
INTCSI0 Interrupt Cause Selection
CSIIF0 is set to 1 upon termination of serial interface channel 0 transfer
CSIIF0 is set to 1 upon stop condition detection or termination of serial interface channel 0 transfer
CLD
0
1
SCK0 Pin Level
Note 2
Low level
High level
R/W
R
1
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(2) Communication operation
The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Each bit of data is transmitted
or received in synchronization with the serial clock.
Shift operation of serial I/O shift register 0 (SIO0) is carried out in synchronization with the falling edge of the
serial clock (SCK0). The transmit data is held in the SO0 latch and is output from the SB0/SDA0/P25 (or SB1/
SDA1/P26) pin on an MSB-first basis. The receive data input from the SB0 (or SB1) pin is latched into the
shift register at the rising edge of SCK0.
Upon termination of 8-bit transfer, the shift register operation stops automatically and the interrupt request
flag (CSIIF0) is set.
Figure 16-11. 2-Wire Serial I/O Mode Timings
The SB0 (or SB1) pin specified for the serial data bus is an N-ch open-drain I/O and thus it must be externally
connected to a pull-up resistor. Because the N-ch transistor output pin must go into a high-impedance state
for data reception, write FFH to SIO0 in advance.
The SB0 (or SB1) pin generates the SO0 latch status and thus the SB0 (or SB1) pin output status can be
manipulated by setting the RELT and CMDT bits. However, do not carry out this manipulation during serial
transfer.
Control the SCK0 pin output level in the output mode (internal system clock mode) by manipulating the P27
output latch (refer to 16.4.7 SCK0/SCL/P27 pin output manipulation).
1234 5 6 7 8
SCK0
D7 D6 D5 D4 D3 D2 D1 D0
SB0 (SB1)
CSIIF0
Transfer start at the falling edge of SCK0
End of transfer
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(3) Other signals
Figure 16-12 shows RELT and CMDT operations.
Figure 16-12. RELT and CMDT Operations
(4) Transfer start
Serial transfer is started by setting transfer data to serial I/O shift register 0 (SIO0) when the following two
conditions are satisfied.
•Serial interface channel 0 operation control bit (CSIE0) = 1
•Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer
Cautions 1. If CSIE0 is set to “1” after data write to SIO0, transfer does not start.
2. Because the N-ch transistor output pin must go into a high-impedance state for data
reception, write FFH to SIO0 in advance.
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0)
is set.
(5) Error detection
In the 2-wire serial I/O mode, the serial bus SB0 (SB1) status being transmitted is fetched into the destination
device, that is, serial I/O shift register 0 (SIO0). Thus, transmit error can be detected in the following way.
(a) Method of comparing SIO0 data before transmission to that after transmission
In this case, if two data differ from each other, a transmit error is judged to have occurred.
(b) Method of using the slave address register (SVA)
Transmit data is set to both SIO0 and SVA and is transmitted. After termination of transmission, COI bit
(match signal coming from the address comparator) of serial operating mode register 0 (CSIM0) is tested.
If “1”, normal transmission is judged to have been carried out. If “0”, a transmit error is judged to have
occurred.
RELT
CMDT
SO0 latch
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16.4.4 I2C bus mode operation
The I2C bus mode is provided for when communication operations are performed between a single master device
and multiple slave devices. This mode configures a serial bus that includes only a single master device, and is
based on the clocked serial I/O format with the addition of bus configuration functions, which allows the master
device to communicate with a number of (slave) devices using only two lines: serial clock (SCL) line and serial data
bus (SDA0 or SDA1) line. Consequently, when the user plans to configure a serial bus which includes multiple
microcontrollers and peripheral devices, using this configuration results in reduction of the required number of port
pins and on-board wires.
In the I2C bus specification, the master sends start condition, data, and stop condition signals to slave devices
through the serial data bus, while slave devices automatically detect and distinguish the type of signals due to the
signal detection function incorporated as hardware. This simplifies I2C bus control sections in the application program.
An example of a serial bus configuration is shown in Figure 16-13. This system below is composed of CPUs and
peripheral ICs having serial interface hardware that complies with the I2C bus specification.
Note that pull-up resistors are required to connect to both serial clock line and serial data bus line, because open-
drain buffers are used for the serial clock pin (SCL) and the serial data bus pin (SDA0 or SDA1) on the I2C bus.
The signals used in the I2C bus mode are described in Table 16-4.
Figure 16-13. Example of Serial Bus Configuration Using I2C Bus
SCL
SDA0 (SDA1)
SCL
SDA0 (SDA1)
SCL
SDA0 (SDA1)
SCL
SDA
Slave IC
Slave CPU2
Slave CPU1
Master CPU
VDD0
Serial clock
Serial data bus
VDD0
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(1) I2C bus mode functions
In the I2C bus mode, the following functions are available.
(a) Automatic identification of serial data
Slave devices automatically detect and identifies start condition, data, and stop condition signals sent in
series through the serial data bus.
(b) Chip selection by specifying device addresses
The master device can select a specific slave device connected to the I2C bus and communicate with it by
sending in advance the address data corresponding to the destination device.
(c) Wake-up function
When address data is sent from the master device, slave devices compare it with the value registered in
their internal slave address registers. If the values in one of the slave devices match, the slave device
internally generates an interrupt request signal to terminate the current processing and communicates
with the master device (The interrupt request is also generated when the stop condition is detected).
Therefore, CPUs other than the selected slave device on the I2C bus can perform independent operations
during the serial communication.
(d) Acknowledge signal (ACK) control function
The master device and a slave device send and receive acknowledge signals to confirm that the serial
communication has been executed normally.
(e) Wait signal (WAIT) control function
When a slave device is preparing for data transmission or reception and requires more waiting time, the
slave device outputs a wait signal on the bus to inform the master device of the wait status.
(2) I2C bus definition
This section describes the format of serial data communications and functions of the signals used in the
I2C bus mode.
First, the transfer timings of the start condition, data, and stop condition signals, which are output onto the
signal data bus of the I2C bus, are shown in Figure 16-14.
Figure 16-14. I2C Bus Serial Data Transfer Timing
The start condition, slave address, and stop condition signals are output by the master. The acknowledge
signal (ACK) is output by either the master or the slave device (normally by the device which has received
the 8-bit data that was sent). A serial clock (SCL) is continuously supplied from the master device.
1 to 7 8 9 1 to 7 8 9 1 to 7 8 9
Address R/W ACK Data ACK Data ACK
SCL
Start
condition
SDA0 (SDA1)
Stop
condition
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(a) Start condition
When the SDA0 (SDA1) pin level is changed from high to low while the SCL pin is high, this transition is
recognized as the start condition signal. This start condition signal, which is created using the SCL and
SDA0 (or SDA1) pins, is output from the master device to slave devices to initiate a serial transfer. See
16.4.5 Cautions on use of I2C bus mode for details of the start condition output.
The start condition signal is detected by hardware incorporated in slave devices.
Figure 16-15. Start Condition
(b) Address
The 7 bits following the start condition signal are defined as an address.
The 7-bit address data is output by the master device to specify a specific slave from among those connected
to the bus line. Each slave device on the bus line must therefore have a different address.
Therefore, after a slave device detects the start condition, it compares the 7-bit address data received and
the data of the slave address register (SVA). After the comparison, only the slave device in which the
data are a match becomes the communication partner, and subsequently performs communication with
the master device until the master device sends a start condition or stop condition signal.
Figure 16-16. Address
(c) Transfer direction specification
The 1 bit that follows the 7-bit address data will be sent from the master device, and it is defined as the
transfer direction specification bit. If this bit is 0, it is the master device which will send data to the slave.
If it is 1, it is the slave device which will send data to the master.
Figure 16-17. Transfer Direction Specification
H
SCL
SDA0 (SDA1)
1234567
A6 A5 A4 A3 A2 A1 A0 R/W
Address
SCL
SDA0 (SDA1)
234567
A6 A5 A4 A3 A2 A1 A0 R/W
Transfer direction
specification
SCL 81
SDA0 (SDA1)
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(d) Acknowledge signal (ACK)
The acknowledge signal indicates that the transferred serial data has definitely been received. This signal
is used between the sending side and receiving side devices for confirmation of correct data transfer. In
principle, the receiving side device returns an acknowledge signal to the sending device each time it
receives 8-bit data. The only exception is when the receiving side is the master device and the 8-bit data
is the last transfer data; the master device outputs no acknowledge signal in this case.
The sending side that has transferred 8-bit data waits for the acknowledge signal which will be sent from
the receiving side. If the sending side device receives the acknowledge signal, which means a successful
data transfer, it proceeds to the next processing. If this signal is not sent back from the slave device, this
means that the data sent has not been received by the slave device, and therefore the master device
outputs a stop condition signal to terminate subsequent transmissions.
Figure 16-18. Acknowledge Signal
(e) Stop condition
If the SDA0 (SDA1) pin level changes from low to high while the SCL pin is high, this transition is defined
as a stop condition signal.
The stop condition signal is output from the master to the slave device to terminate a serial transfer.
The stop condition signal is detected by hardware incorporated in the slave device.
Figure 16-19. Stop Condition
1234567
A6 A5 A4 A3 A2 A1 A0 R/W
SCL
SDA0 (SDA1)
9
8
ACK
H
SCL
SDA0 (SDA1)
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(f) Wait signal (WAIT)
The wait signal is output by a slave device to inform the master device that the slave device is in wait state
due to preparing for transmitting or receiving data.
During the wait state, the slave device continues to output the wait signal by keeping the SCL pin low to
delay subsequent transfers. When the wait state is released, the master device can start the next transfer.
For the releasing operation of slave devices, see 16.4.5 Cautions on use of I2C bus mode.
Figure 16-20. Wait Signal
(a) Wait of 8 clock cycles
(b) Wait of 9 clock cycles
SCL of
master device
D2 D1 D0 ACK D7
Output by manipulating ACKT
6789 1 324
D6 D5 D4
Set low because slave device drives low,
though master device returns to Hi-Z state.
No wait is inserted after 9th clock cycle
(and before master device starts next transfer).
SCL of
slave device
SCL
SDA0 (SDA1)
SCL of
master device
Set low because slave device drives low,
though master device returns to Hi-Z state.
SCL of
slave device
SCL
D2 D1 D0 ACK D7
Output based on the value set in ACKE in advance
6789 23
D6 D5
1
SDA0 (SDA1)
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(3) Register setting
The I2C bus mode setting is performed by serial operating mode register 0 (CSIM0), the serial bus interface
control register (SBIC), and the interrupt timing specify register (SINT).
(a) Serial operating mode register 0 (CSIM0)
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM0 to 00H.
Notes 1. Bit 6 (COI) is a read-only bit.
2. When CSIE0 = 0, COI becomes 0.
3. Set bit 5 (SIC) of the interrupt timing specify register (SINT) to 1 when using the wake-up function
(WUP = 1). Do not execute an instruction that writes to serial I/O shift register 0 (SIO0) while WUP
= 1.
4. These pins can be used freely as port pins.
5. In the I2C bus mode, the clock frequency becomes 1/16 of that output from TO2.
Remark ×: don’t care
PM××: Port mode register
P××: Port output latch
2-wire
serial I/O
or
I2C bus mode
65432107
Symbol
CSIM0 CSIE0 COI WUP
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
CSIM01
0
1
Serial Interface Channel 0 Clock Selection
Input clock to SCL pin from off-chip
8-bit timer register 2 (TM2) outputNote 5
0
R/W
1 Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
CSIM
04
0
1
CSIM00
×
0
1
FF60H 00H R/WNote 1
Address After Reset R/W
R/W
CSIM
03
CSIM
02
PM25 P25 PM26 P26 PM27 P27
Operation
Mode Start Bit SI0/SB0/SDA0/
P25 Pin Function
SO0/SB1/SDA1/
P26 Pin Function
SCK0/SCL/P27
Pin Function
×
11
×
0
×
0
0
×
0
×
0
0
1
1
Note 4 Note 4
Note 4 Note 4
MSB P25 (CMOS
I/O)
SB0/SDA0
(N-ch open-drain
I/O)
SB1/SDA1
(N-ch open-drain
I/O)
P26 (CMOS
I/O)
WUP
0
1
Wake-up Function ControlNote 3
Interrupt request signal generation with each serial transfer in any mode
Interrupt request signal generation when the address received after start condition detection
(when CMDD = 1) matches the slave address register data in I
2
C bus mode
R/W
3-wire serial I/O mode (See 16.4.2 3-wire serial I/O mode operation)
COI
0
Slave Address Comparison Result FlagNote 2
Slave address register not equal to serial I/O shift register 0 data
Slave address register equal to serial I/O shift register 0 data
R
1
CSIE0
0
Serial Interface Channel 0 Operation Control
Operation stopped
Operation enabled
R/W
1
SCK0/SCL
(N-ch open-drain
I/O)
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(b) Serial bus interface control register (SBIC)
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SBIC to 00H.
(continued)
Notes 1. Bits 2, 3, and 6 (RELD, CMDD, and ACKD) are read-only bits.
2. The busy mode can be released by the start of a serial interface transfer or reception of an address
signal. However, the BSYE flag is not cleared to 0.
3. When using the wake-up function, be sure to set BSYE to 1.
4. This setting must be performed prior to transfer start.
5. In the 8-clock wait mode, use ACKT for output of the acknowledge signal after normal data reception.
Remark CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
65432107
Symbol
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT FF61H 00H R/WNote 1
Address After Reset R/W
RCMDD Start Condition Detection
Clear Conditions (CMDD = 0)
• When transfer start instruction is executed
• When stop condition is detected
• When CSIE0 = 0
• When RESET input is applied
Set Conditions (CMDD = 1)
• When start condition is detected
SDA0 (SDA1) is set to low after the set instruction execution (ACKT = 1) before the next SCL falling edge.
Used for generating an ACK signal by software if the 8-clock wait mode is selected. Cleared to 0 if CSIE0
= 0 when a transfer by the serial interface is started.
R/W
ACKE Acknowledge Signal Automatic Output ControlNote 4
0 Disabled (with ACKT enabled).
Used when receiving data in the 8-clock wait mode or when transmitting dataNote 5
Enabled.
After completion of transfer, acknowledge signal is output in synchronization with the 9th falling edge of SCL
clock (automatically output when ACKE = 1). However, not automatically cleared to 0 after acknowledge
signal output. Used for reception when the 9-clock wait mode is selected.
1
R/W
ACKT
BSYE Control of N-ch Open-Drain Output for Transmission in I2C Bus ModeNote 3
0Output enabled (transmission)
R/W Note 2
1 Output disabled (reception)
RACKD Acknowledge Detection
Clear Conditions (ACKD = 0)
• When transfer start instruction is executed
• When CSIE0 = 0
• When RESET input is applied
Set Conditions (ACKD = 1)
•When acknowledge signal is detected at the
rising edge of SCL clock after completion of
transfer
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RRELD Stop Condition Detection
Set Conditions (RELD = 1)Clear Conditions (RELD = 0)
•When stop condition is detected
• When transfer start instruction is executed
• If SIO0 and SVA values do not match in address
reception
• When CSIE0 = 0
• When RESET input is applied
RELT
Used for stop condition output.
When RELT = 1, SO Iatch is set to 1. After SO latch setting, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
R/W
CMDT
Use for start condition output.
When CMDT = 1, SO latch is cleared to 0. After clearing SO latch, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
R/W
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(c) Interrupt timing specify register (SINT)
SINT is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SINT to 00H.
(continued)
Notes 1. Bit 6 (CLD) is a read-only bit.
2. When CSIE0 = 0, CLD becomes 0.
3. When using the wake-up function in I2C bus mode, set SIC to 1.
Remark SVA: Slave address register
CSIIF0: Interrupt request flag corresponding to INTCSI0
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
65432107
Symbol
SINT 0 CLD SIC SVAM CLC WREL WAT1 WAT0 FF63H 00H R/W
Note 1
Address After Reset R/W
CLD
0
1
SCL Pin Level
Note 2
Low level
High level
R
SIC
0
INTCSI0 Interrupt Cause Selection
Note 3
CSIIF0 is set to 1 upon termination of serial interface channel 0 transfer
CSIIF0 is set to 1 upon stop condition detection or termination of serial interface channel 0 transfer
R/W
1
SVAM
0
1
SVA Bit to Be Used as Slave Address
Bits 0 to 7
Bits 1 to 7
R/W
WREL
0Wait state has been cancelled.
Cancels wait state. Automatically cleared to 0 when the state is cancelled.
(Used to cancel wait state by means of WAT0 and WAT1.)
R/W
1
Wait Sate Cancellation Control
Used in I
2
C bus mode.
Make SCL pin enter high-impedance state unless serial transfer is being performed (except for clock line
which is kept high).
Used to enable master device to generate start condition and stop condition signals.
CLC
0
1
Clock Level Control
Used in I
2
C bus mode.
Make output level of SCL pin low unless serial transfer is being performed.
R/W
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Note When the I2C bus mode is used, be sure to set 1 and 0, or 1 and 1 in WAT1 and WAT0, respectively.
WAT1
0
1
Wait and Interrupt Control
Note
Generates interrupt service request at rising edge of 8th SCK0 clock cycle (keeping clock output in
high impedance).
R/W WAT0
0
0Used in I
2
C bus mode (8-clock wait).
Generates interrupt service request at rising edge of 8th SCL clock cycle.
(In the case of master device, makes SCL output low to enter wait state after 8 clock pulses are
output. In the case of slave device, makes SCL output low to request wait state after 8 clock
pulses are input.)
11Used in I
2
C bus mode (9-clock wait).
Generates interrupt service request at rising edge of 9th SCL clock cycle.
(In the case of master device, makes SCL output low to enter wait state after 9 clock pulses are
output. In the case of slave device, makes SCL output low to request wait state after 9 clock
pulses are input.)
0 Setting prohibited
1
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(4) Various signals
A list of signals in the I2C bus mode is given in Table 16-4.
Table 16-4. Signals in I2C Bus Mode
Signal Name Description
Start condition Definition: SDA0 (SDA1) falling edge when SCL is highNote 1
Function: Indicates that serial communication starts and subsequent data are address data.
Signalled by: Master
Signalled when: CMDT is set.
Affected flag(s): CMDD (is set.)
Stop condition Definition: SDA0 (SDA1) rising edge when SCL is highNote 1
Function: Indicates end of serial transmission.
Signalled by: Master
Signalled when: RELT is set.
Affected flag(s): RELD (is set) and CMDD (is cleared)
Acknowledge signal (ACK) Definition: Low level of SDA0(SDA1) pin during one SCL clock cycle after serial reception
Function: Indicates completion of reception of 1 byte.
Signalled by: Master or slave
Signalled when: ACKT is set with ACKE = 1.
Affected flag(s): ACKD (is set.)
Wait (WAIT) Definition: Low-level signal output to SCL
Function: Indicates state in which serial reception is not possible.
Signalled by: Slave
Signalled when: WAT1, WAT0 = 1x.
Affected flag(s): None
Serial clock (SCL) Definition: Synchronization clock for output of various signals
Function: Serial communication synchronization signal.
Signalled by: Master
Signalled when: See Note 2 below.
Affected flag(s): CSIIF0. Also see Note 3 below.
Address (A6 to A0) Definition: 7-bit data synchronized with SCL immediately after start condition signal
Function: Indicates address value for specification of slave on serial bus.
Signalled by: Master
Signalled when: See Note 2 below.
Affected flag(s): CSIIF0. Also see Note 3 below.
Transfer direction (R/W) Definition: 1-bit data output in synchronization with SCL after address output
Function: Indicates whether data transmission or reception is to be performed.
Signalled by: Master
Signalled when: See Note 2 below.
Affected flag(s): CSIIF0. Also see Note 3 below.
Data (D7 to D0) Definition: 8-bit data synchronized with SCL, not immediately after start condition
Function: Contains data actually to be sent.
Signalled by: Master or slave
Signalled when: See Note 2 below.
Affected flag(s): CSIIF0. Also see Note 3 below.
Notes 1. The level of the serial clock can be controlled by CLC of the interrupt timing specify register (SINT).
2. Execution of instruction to write data to SIO0 when CSIE0 = 1 (serial transfer start directive). In the
wait state, the serial transfer operation will be started after the wait state is released.
3. If the 8-clock wait is selected when WUP = 0, CSIIF0 is set at the rising edge of the 8th clock cycle
of SCL. If the 9-clock wait is selected when WUP = 0, CSIIF0 is set at the rising edge of the 9th clock
cycle of SCL. If WUP = 1, CSIIF0 is set when an address is received and the address matches the
slave address register (SVA) value, or when the stop condition is detected.
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(5) Pin configurations
The configurations of the serial clock pin (SCL) and the serial data bus pins (SDA0, SDA1) are shown
below.
(a) SCL
Serial clock I/O pin.
<1> Master ..... N-ch open-drain output
<2> Slave ....... Schmitt input
(b) SDA0 (SDA1)
Serial data I/O dual-function pin.
Uses N-ch open-drain output and Schmitt-input buffers for both master and slave devices.
Note that pull-up resistors are required to connect to both serial clock line and serial data bus line, because
open-drain buffers are used for the serial clock pin (SCL) and the serial data bus pin (SDA0 or SDA1) on
the I2C bus.
Figure 16-21. Pin Configuration
Caution When data is received, the N-ch open-drain output pin must go into a high-impedance
state. Therefore, set bit 7 (BSYE) of the serial bus interface control register (SBIC) to 1,
and write FFH to serial I/O shift register 0 (SIO0).
However, do not write FFH to SIO0 before reception when the wake-up function is used
(when bit 5 (WUP) of serial operating mode register 0 (CSIM0) is set). Even if FFH is not
written to SIO0, the N-ch open-drain output pin always goes into a high-impedance state.
V
DD0
V
DD0
SCL
SDA0 (SDA1)
Master device
Clock output
(Clock input)
Data output
Data input
Slave devices
(Clock output)
Clock input
Data output
Data input
SCL
SDA0 (SDA1)
V
SS0
V
SS0
V
SS0
V
SS0
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(6) Address match detection method
In the I2C bus mode, the master can select a specific slave device by sending slave address data.
Address match detection is performed automatically by the slave device hardware. A slave device has a
slave address register (SVA), and compares its contents and the slave address sent from the master
device. If they match and the wake-up function specify (WUP) bit is then 1, interrupt request flag (CSIIF0)
is set (CSIIF0 is also set when the stop condition is detected).
Set SIC to 1 when using the wake-up function.
Caution Status detection of slave selection/non-selection is performed by a match detection of
reception data (address) after the start condition. This address match signal interrupt
(INTCSI0) generated during WUP = 1 is used as a match signal. Thus, perform the slave
selection/non-selection detection during WUP = 1.
(7) Error detection
In the I2C bus mode, transmission error detection can be performed by the following methods because the
serial bus SDA0 (SDA1) status during transmission is also taken into serial I/O shift register 0 (SIO0) of the
transmitting device.
(a) Comparison of SIO0 data before and after transmission
In this case, a transmission error is judged to have occurred if the two data values are different.
(b) Using the slave address register (SVA)
Transmit data is set in SIO0 and SVA before transmission is performed. After transmission, the COI bit
(match signal from the address comparator) of serial operating mode register 0 (CSIM0) is tested: "1"
indicates normal transmission, and "0" indicates a transmission error.
(8) Communication operation
In the I2C bus mode, the master selects the slave device to be communicated with from among multiple
devices by outputting address data onto the serial bus.
After the slave address data, the master sends the R/W bit which indicates the data transfer direction, and
starts serial communication with the selected slave device.
Data communication timing charts are shown in Figures 16-22 and 16-23.
In the transmitting device, serial I/O shift register 0 (SIO0) shifts transmission data to the SO latch in
synchronization with the falling edge of the serial clock (SCL), the SO0 latch outputs the data on an MSB-
first basis from the SDA0 or SDA1 pin to the receiving device.
In the receiving device, the data input from the SDA0 or SDA1 pin is taken into the SIO0 in synchronization
with the rising edge of SCL.
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Figure 16-22. Data Transmission from Master to Slave
(Both Master and Slave Selected 9-Clock Wait) (1/3)
(a) Start condition to address
Master device operation
Transfer line
Slave device operation
Write SIO0
COI
ACKD
CMDD
RELD
CLD
P27
WUP
BSYE
ACKE
CMDT
RELT
CLC
WREL
SIC
INTCSI0
SCL
SDA0
SIO0 Address SIO0 Data
L
H
L
L
L
L
L
L
2
A6
1 3456789 12345
A5 A4 A3 A2 A1 A0 W
ACK
D4D5D6D7
Write SIO0
COI
ACKD
CMDD
RELD
CLD
P27
WUP
BSYE
ACKE
CMDT
RELT
CLC
WREL
SIC
INTCSI0
SIO0 FFH
L
H
H
L
L
P25 L
PM25 L
PM27 L
H
L
L
D3
CSIE0 H
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Figure 16-22. Data Transmission from Master to Slave
(Both Master and Slave Selected 9-Clock Wait) (2/3)
(b) Data
Master device operation
Transfer line
Slave device operation
Write SIO0
COI
ACKD
CMDD
RELD
CLD
P27
WUP
BSYE
ACKE
CMDT
RELT
CLC
WREL
SIC
INTCSI0
SCL
SDA0
SIO0 Data SIO0 Data
L
H
L
L
L
L
L
L
2
D7
1 3456789 12345
D6 D5 D4 D3 D2 D1
ACK
D4D5D6D7
Write SIO0
COI
ACKD
CMDD
RELD
CLD
P27
WUP
BSYE
ACKE
CMDT
RELT
CLC
WREL
SIC
INTCSI0
SIO0 FFH
L
H
H
L
L
H
CSIE0 H
L
L
P25 L
PM25 L
PM27 L
L
L
L
FFH
D0 D3
SIO0
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Figure 16-22. Data Transmission from Master to Slave
(Both Master and Slave Selected 9-Clock Wait) (3/3)
(c) Stop condition
Master device operation
Transfer line
Slave device operation
Write SIO0
COI
ACKD
CMDD
RELD
CLD
P27
WUP
BSYE
ACKE
CMDT
RELT
CLC
WREL
SIC
INTCSI0
SCL
SDA0
SIO0 Data SIO0 Address
H
L
L
L
L
L
2
D6
1 3456789 1234
D5 D4 D3 D2 D1
D0
ACK
A4A5A6
Write SIO0
COI
ACKD
CMDD
RELD
CLD
P27
WUP
BSYE
ACKE
CMDT
RELT
CLC
WREL
SIC
INTCSI0
CSIE0
P25
PM25
PM27
H
H
L
H
L
L
SIO0 FFH
D7
SIO0 FFH
A3
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Figure 16-23. Data Transmission from Slave to Master
(Both Master and Slave Selected 9-Clock Wait) (1/3)
(a) Start condition to address
Master device operation
Transfer line
Slave device operation
Write SIO0
COI
ACKD
CMDD
RELD
CLD
P27
WUP
BSYE
ACKE
CMDT
RELT
CLC
WREL
SIC
INTCSI0
SCL
SDA0
SIO0 Address SIO0 FFH
L
H
L
L
L
L
2
A6
1 3456789 12345
A5 A4 A3 A2 A1 A0
ACK
D4D5D6D7
Write SIO0
COI
ACKD
CMDD
RELD
CLD
P27
WUP
BSYE
ACKE
CMDT
RELT
CLC
WREL
SIC
INTCSI0
L
L
L
P25 L
PM25 L
PM27 L
H
CSIE0 H
L
L
R
SIO0 Data
D3
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Figure 16-23. Data Transmission from Slave to Master
(Both Master and Slave Selected 9-Clock Wait) (2/3)
(b) Data
Master device operation
Transfer line
Write SIO0
COI
ACKD
CMDD
RELD
CLD
P27
WUP
BSYE
ACKE
CMDT
RELT
CLC
WREL
SIC
INTCSI0
SCL
SDA0
SIO0 FFH SIO0 FFH
L
H
L
H
H
L
L
L
2
D7
1 3456789 12345
D6 D5 D4 D3 D2 D1
ACK
D4D5D6D7
Write SIO0
COI
ACKD
CMDD
RELD
CLD
P27
WUP
BSYE
ACKE
CMDT
RELT
CLC
WREL
SIC
INTCSI0
L
L
L
L
L
P25 L
PM25 L
PM27 L
H
CSIE0 H
L
L
L
L
L
D0
D3
Slave device operation
SIO0 Data SIO0 Data
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Figure 16-23. Data Transmission from Slave to Master
(Both Master and Slave Selected 9-Clock Wait) (3/3)
(c) Stop condition
Master device operation
Transfer line
Write SIO0
COI
ACKD
CMDD
RELD
CLD
P27
WUP
BSYE
ACKE
CMDT
RELT
CLC
WREL
SIC
INTCSI0
SCL
SDA0
SIO0 FFH SIO0 Address
H
L
L
L
2
D6
1 3456789 1234
D5 D4 D3 D2 D1 D0
NAK
A4A5A6
Write SIO0
COI
ACKD
CMDD
RELD
CLD
P27
WUP
BSYE
ACKE
CMDT
RELT
CLC
WREL
SIC
INTCSI0
L
H
CSIE0 H
L
L
P25 L
PM25 L
PM27 L
D7
SIO0 Data
Slave device operation
A3
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(9) Start of transfer
A serial transfer is started by setting transfer data in serial I/O shift register 0 (SIO0) if the following two
conditions have been satisfied:
• Serial interface channel 0 operation control bit (CSIE0) = 1
• After an 8-bit serial transfer, the internal serial clock is stopped or SCL is low.
Cautions 1. Be sure to set CSIE0 to 1 before writing data in SIO0. Setting CSIE0 to 1 after writing data
in SIO0 does not initiate transfer operation.
2. When data is received, the N-ch open-drain output pin must go into a high-impedance
state. Therefore, set BSYE of the serial bus interface control register (SBIC) to 1, and write
FFH to SIO0.
However, do not write FFH to SIO0 before reception when the wake-up function is used
(when bit 5 (WUP) of serial operating mode register 0 (CSIM0) is set). Even if FFH is not
written to SIO0, the N-ch open-drain output pin always goes into a high-impedance state.
3. If data is written to SIO0 while the slave is in the wait state, that data is held. Transfer
is started when SCL is output after the wait state is cleared.
When an 8-bit data transfer ends, serial transfer is stopped automatically and the interrupt request flag
(CSIIF0) is set.
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16.4.5 Cautions on use of I2C bus mode
(1) Start condition output (master)
The SCL pin normally outputs a low-level signal when no serial clock is output. It is necessary to change
the SCL pin to high in order to output a start condition signal. Set 1 in CLC of the interrupt timing specify
register (SINT) to drive the SCL pin high.
After setting CLC, clear CLC to 0 and return the SCL pin to low. If CLC remains 1, no serial clock is output.
If it is the master device which outputs the start condition and stop condition signals, confirm that CLD is
set to 1 after setting CLC to 1; a slave device may have set SCL to low (wait state).
Figure 16-24. Start Condition Output
SCL
CLC
CMDT
CLD
SDA0 (SDA1)
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(2) Slave wait release (slave transmission)
The wait status of a slave is released by setting the WREL flag, which is bit 2 of the interrupt timing specify
register (SINT), or by executing a serial I/O shift register 0 (SIO0) write instruction.
If the slave sends data, the wait is immediately released by execution of an SIO0 write instruction and the
clock rises without the start transmission bit being output in the data line. Therefore, manipulate the P27
output latch through the program as shown in Figure 16-25 to transmit data correctly. At this time, control
the low-level width ("
a
" in Figure 16-25) of the first serial clock at the timing used for setting the P27 output
latch to 1 after execution of an SIO0 write instruction.
In addition, if the acknowledge signal from the master is not output (if data transmission from the slave is
completed), set 1 in the WREL flag of SINT and release the wait.
For these timings, see Figure 16-23.
Figure 16-25. Slave Wait Release (Transmission)
Writing
FFH
to SIO0
Setting
CSIIF0
Setting
ACKD
Serial reception
9
a
23
A0 R ACK D7 D6 D5
P27
output
latch 1
Setting
CSIIF0
ACK
output
Serial transmission
Write
data
to SIO0
P27
output
latch 0
Wait
release
Program processing
Hardware operation
SCL
Program processing
Hardware operation
Transfer line
Master device operation
Slave device operation
1
SDA0 (SDA1)
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(3) Slave wait release (slave reception)
The wait status of a slave is released by setting the WREL flag, which is bit 2 of the interrupt timing specify
register (SINT), or by executing a serial I/O shift register 0 (SIO0) write instruction.
When a slave receives data, if the SCL line immediately enters a high-impedance state due to a write to
SIO0, the slave may not receive the first bit of the data sent from the master. This is because SIO0 cannot
start operation if the SCL line is in a high-impedance state during execution of a write instruction to SIO0
(until the next instruction execution is started). Therefore, manipulate the P27 output latch through the
program as shown in Figure 16-26 to receive data correctly.
For these timings, see Figure 16-22.
Figure 16-26. Slave Wait Release (Reception)
(4) Reception completion of slave
During processing of reception completion by a slave device, confirm the statuses of bit 3 (CMDD) of the
serial bus interface control register (SBIC) and bit 6 (COI) of serial operating mode register 0 (CSIM0) (if
CMDD = 1). This procedure is necessary to use the wake-up function normally. If an uncertain amount of
data is sent from the master device, the slave device cannot determine whether the start condition signal
or the data will be sent from the master. This may disable use of the wake-up function.
Writing
data
to SIO0
Setting
CSIIF0
Setting
ACKD
Serial transmission
923
A0 W ACK D7 D6 D5
P27
output
latch 1
Setting
CSIIF0
ACK
output
Serial reception
Write
FFH
to SIO0
P27
output
latch 0
Wait
release
Program processing
Hardware operation
SCL
Program processing
Hardware operation
Transfer line
Master device operation
Slave device operation
1
SDA0 (SDA1)
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16.4.6 Restrictions when using I2C bus mode
The following restrictions are applied to the
µ
PD780308Y Subseries.
• Restrictions when
µ
PD780308Y Subseries is used as slave device in I2C bus mode
Subject:
µ
PD780306Y, 780308Y, 78P0308Y, IE-780308-R-EM
Description: If the wake-up function is executed in the serial transfer statusNote (by setting the
WUP flag (bit 5 of serial operating mode register 0 (CSIM0)) to 1), the data between
the other slave devices and the master device is identified as an address. If that
data matches the slave address of the
µ
PD780308Y Subseries, therefore, the
µ
PD780308Y participates in communication, destroying the communication data.
Note The serial transfer status is the status where the interrupt request flag (CSIIF0)
is set to 1 on completion of serial transfer after data has been written to serial
I/O shift register 0 (SIO0).
Preventive measures: The above problem can be avoided by modifying the program.
Before executing the wake-up function, execute the program shown below that
releases the serial transfer status. When executing the wake-up function, do not
execute the instruction that writes data to SIO0. Even if this instruction is not
executed, data can be received while the wake-up function is executed.
The program shown below is to release the serial transfer status. To release the
serial transfer status, it is necessary to stop serial interface channel 0 once (by
clearing the CSIE0 flag (bit 7 of serial operating mode register 0 (CSIM0)) to 0). If
serial interface channel 0 is stopped in the I2C bus mode, however, the SCL pin
outputs the high level and the SDA0 (SDA1) pin outputs the low level, affecting
communication of the I2C bus. To prevent the I2C bus from being influenced,
therefore, this program makes the SCL and SDA0 (SDA1) pins go into a high-
impedance state.
In this example, SDA0 (/P25) is used as a serial data input/output pin. To use
SDA1 (/P26) as the serial data input/output pin, change P2.5 and PM2.5 in the
program below to P2.6 and PM2.6, respectively.
For the timing of each signal when this program is executed, refer to Figure 16-22.
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• Example of program to release serial transfer status
SET1 P2.5; <1>
SET1 PM2.5; <2>
SET1 PM2.7; <3>
CLR1 CSIE0; <4>
SET1 CSIE0; <5>
SET1 RELT; <6>
CLR1 PM2.7; <7>
CLR1 P2.5; <8>
CLR1 PM2.5; <9>
<1> Prevents the SDA0 pin from outputting the low level when the I2C bus mode is restored by instruction
<5>. The SDA0 pin goes into a high-impedance state.
<2> Sets the P25(/SDA0) pin in the input mode to prevent the SDA0 line from being affected when the port
mode is set by instruction <4>. The input mode is set when instruction <2> is executed.
<3> Sets the P27(/SCL) pin in the input mode to prevent the SCL line from being affected when the port
mode is set by instruction <4>. The input mode is set when instruction <3> is executed.
<4> Changes the mode from the I2C bus mode to the port mode.
<5> Restores the I2C bus mode from the port mode.
<6> Prevents instruction <8> from causing the SDA0 pin to output the low level.
<7> Because the P27 pin must be set in the output mode in the I2C bus mode, sets the P27 pin in the
output mode.
<8> Because the output latch of the P25 pin must be cleared to 0 in the I2C bus mode, clears the output
latch of the P25 pin to 0.
<9> Because, in the I2C bus mode, the P25 pin must be set in the output mode, sets the P25 pin in the
output mode.
Remark RELT: bit 0 of serial bus interface control register (SBIC)
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16.4.7 SCK0/SCL/P27 pin output manipulation
The SCK0/SCL/P27 pin enables static output by manipulating software in addition to normal serial clock output.
The value of serial clocks can be set by software (SI0/SB0/SDA0 and SO0/SB1/SDA1 pins are controlled with the
RELT and CMDT bits of the serial bus interface control register (SBIC)).
The SCK0/SCL/P27 pin output should be manipulated as described below.
(1) In 3-wire serial I/O mode and 2-wire serial I/O mode
The SCK0/SCL/P27 pin output level is manipulated by the P27 output latch.
<1> Set serial operating mode register 0 (CSIM0) (SCK0 pin is set in the output mode and serial operation
is enabled). While serial transfer is suspended, SCK0 is set to 1.
<2> Manipulate the content of the P27 output latch by executing the bit manipulation instruction.
Figure 16-27. SCK0/SCL/P27 Pin Configuration
To internal
circuit
SCK0/SCL/P27 P27 output
latch
When CSIE0 = 1
and
CSIM01 and CSIM00 are 1 and 0, or 1 and 1.
SCK0 (1 when transfer stops)
From serial clock
controller
Set by bit
manipulation instruction
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(2) In I2C bus mode
The SCK0/SCL/P27 pin output level is manipulated by the CLC bit of the interrupt timing specify register
(SINT).
<1> Set serial operating mode register 0 (CSIM0) (SCL pin is set in the output mode and serial operation
is enabled). Set 1 to the P27 output latch. While serial transfer is suspended, SCL is set to 0.
<2> Manipulate the content of the CLC bit of SINT by executing the bit manipulation instruction.
Figure 16-28. SCK0/SCL/P27 Pin Configuration
Note The level of SCL signal follows the contents of logic circuit shown in Figure 16-29.
Figure 16-29. Logic Circuit of SCL Signal
Remarks 1. This figure shows the relationship of each signal, and does not show the internal circuit.
2. CLC: Bit 3 of interrupt timing specify register (SINT)
SCL
CLC (Set by bit manipulation instruction)
Serial clock
(Low level when transfer stops)
Wait request signal
To internal
circuit
SCK0/SCL/P27 P27 output
latch
When CSIE0 = 1
and
CSIM01 and CSIM00 are 1 and 0, or 1 and 1.
SCL
From serial clock
controller
Set 1
Note
350 User’s Manual U11377EJ3V0UD
CHAPTER 17 SERIAL INTERFACE CHANNEL 2
17.1 Serial Interface Channel 2 Functions
Serial interface channel 2 has the following three modes.
• Operation stop mode
• Asynchronous serial interface (UART) mode
• 3-wire serial I/O mode
(1) Operation stop mode
This mode is used when serial transfer is not carried out to reduce power consumption.
(2) Asynchronous serial interface (UART) mode
In this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is
possible.
A dedicated UART baud rate generator is incorporated, allowing communication over a wide range of baud
rates. In addition, the baud rate can be defined by scaling the input clock to the ASCK pin.
The MIDI standard baud rate (31.25 kbps) can be used by employing the dedicated UART baud rate generator.
Serial interface channel 2 has two data I/O pins (RxD and TxD) which can be selected by software. Note that
only one data I/O pin can be used at one time.
Caution When it is not necessary to change the data I/O pin, using the RxD/SI2/P70 and TxD/SO2/
P71 is recommended. If only port 11 (RxD/P114 and TxD/P113) is used as data I/O pin, the
function of port 7 is limited.
(3) 3-wire serial I/O mode (MSB-first/LSB-first switchable)
In this mode, 8-bit data transfer is performed using three lines: the serial clock (SCK2), and serial data lines
(SI2, SO2).
In the 3-wire serial I/O mode, simultaneous transmission and reception is possible, increasing the data transfer
processing speed.
Either the MSB or LSB can be specified as the start bit for an 8-bit data serial transfer, allowing connection
to devices using either as the start bit.
The 3-wire serial I/O mode is useful for connection to peripheral I/Os and display controllers, etc., which
incorporate a conventional synchronous clocked serial interface, such as the 75X/XL Series, 78K Series, 17K
Series, etc.
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17.2 Serial Interface Channel 2 Configuration
Serial interface channel 2 consists of the following hardware.
Table 17-1. Serial Interface Channel 2 Configuration
Item Configuration
Register Transmit shift register (TXS)
Receive shift register (RXS)
Receive buffer register (RXB)
Control register Serial operating mode register 2 (CSIM2)
Asynchronous serial interface mode register (ASIM)
Asynchronous serial interface status register (ASIS)
Baud rate generator control register (BRGC)
Serial interface pin select register (SIPS)
Port mode register 7 (PM7)Note
Note Refer to Figure 6-10 P70 Block Diagram and Figure 6-11 P71 and P72
Block Diagram.
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Figure 17-1. Serial Interface Channel 2 Block Diagram
Note See Figure 17-2 for the baud rate generator configuration.
Remark fXX = fX/2 (MCS = 0), fXX = fX (MCS = 1)
Internal bus
Asynchronous
serial interface
mode register
Asynchronous
serial interface
status register
Receive buffer
register
(RXB/SIO2)
Direction
controller
Receive shift
register (RXS)
Reception
controller INTSR/INTCSI2
CSIE2 CSIM
22 CSCK
INTSER
SCK output
controller
Baud rate generator
f
XX
to f
XX
/2
10
Internal bus
CSCK
SCK
INTST
Baud rate generator
control register
Serial operating
mode register 2
PE FE OVE
Transmission
controller
ISRM
ASCK/
SCK2/P72
PM72
Direction
controller
Transmit shift
register
(TXS/SIO2)
RXE PS1 PS0 CL SL ISRMTXE SCK
4 4
CSIE2
TXE
RXE
MDL3 MDL2 MDL1 MDL0 TPS3 TPS2 TPS1 TPS0
Selector
TxD/SO2/P71
PM71
TxD/P113
PM113
Selector
RxD/P114
RxD/SI2/P70
Selector
SIPS21SIPS20
Serial interface
pin select
register
Note
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CHAPTER 17 SERIAL INTERFACE CHANNEL 2
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Figure 17-2. Baud Rate Generator Block Diagram
TPS3 TPS2 TPS1 TPS0
Internal bus
MDL3 MDL2 MDL1 MDL0
Baud rate generator
control register
4
TXE
CSIE2
5-bit
counter
Selector
Selector
Decoder
1/2
Selector
Transmit
clock
1/2
Selector
Receive
clock
Match
Match
MDL0 to MDL3
5-bit
counter
RXE
Start bit detection
Selector f
XX
to f
XX
/2
10
TPS0 to TPS3
SCK
CSCK
ASCK/SCK2/P72
4
4
Start bit
sampling clock
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CHAPTER 17 SERIAL INTERFACE CHANNEL 2
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(1) Transmit shift register (TXS)
This register is used to set the transmit data. The data written in TXS is transmitted as serial data.
If the data length is specified as 7 bits, bits 0 to 6 of the data written in TXS are transferred as transmit data.
Writing data to TXS starts the transmit operation.
TXS is written to with an 8-bit memory manipulation instruction. It cannot be read.
TXS value is FFH after RESET input.
Caution TXS must not be written to during a transmit operation. TXS and the receive buffer register
(RXB) are allocated to the same address, and when a read is performed, the value of RXB
is read.
(2) Receive shift register (RXS)
This register is used to convert serial data input to the RxD pin to parallel data. When one byte of data is
received, the receive data is transferred to the receive buffer register (RXB).
RXS cannot be directly manipulated by a program.
(3) Receive buffer register (RXB)
This register holds receive data. Each time one byte of data is received, new receive data is transferred from
the receive shift register (RXS).
If the data length is specified as 7 bits, the receive data is transferred to bits 0 to 6 of RXB, and the MSB of
RXB is always set to 0.
RXB is read with an 8-bit memory manipulation instruction. It cannot be written to.
RXB value is FFH after RESET input.
Caution RXB and the transmit shift register (TXS) are allocated to the same address, and when a write
is performed, the value is written to TXS.
(4) Transmission controller
This circuit performs transmit operation control such as the addition of a start bit, parity bit and stop bit to data
written in the transmit shift register (TXS) in accordance with the contents set in the asynchronous serial
interface mode register (ASIM).
(5) Reception controller
This circuit controls receive operations in accordance with the contents set in the asynchronous serial interface
mode register (ASIM). It performs error checks for parity errors, etc., during a receive operation, and if an
error is detected, sets a value in the asynchronous serial interface status register (ASIS) in accordance with
the error contents.
355
CHAPTER 17 SERIAL INTERFACE CHANNEL 2
User’s Manual U11377EJ3V0UD
17.3 Serial Interface Channel 2 Control Registers
Serial interface channel 2 is controlled by the following five registers.
•Serial operating mode register 2 (CSIM2)
•Asynchronous serial interface mode register (ASIM)
•Asynchronous serial interface status register (ASIS)
•Baud rate generator control register (BRGC)
•Serial interface pin select register (SIPS)
(1) Serial operating mode register 2 (CSIM2)
This register is set when serial interface channel 2 is used in the 3-wire serial I/O mode.
CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM2 to 00H.
Figure 17-3. Serial Operating Mode Register 2 Format
Cautions 1. Ensure that bit 0 and bit 3 to bit 6 are set to 0.
2. When UART mode is selected, CSIM2 should be set to 00H.
65432107
Symbol
CSIM2 CSIE2 0 0 0 0 CSIM
22 CSCK 0 FF72H 00H R/W
Address After Reset R/W
CSCK
0
1
Clock Selection in 3-wire Serial I/O Mode
Input clock from off-chip to SCK2 pin
Dedicated baud rate generator output
CSIM22
0
1
First Bit Specification
MSB
LSB
CSIE2
0
1
Operation Control in 3-wire Serial I/O Mode
Operation stopped
Operation enabled
356
CHAPTER 17 SERIAL INTERFACE CHANNEL 2
User’s Manual U11377EJ3V0UD
(2) Asynchronous serial interface mode register (ASIM)
This register is set when serial interface channel 2 is used in the asynchronous serial interface mode.
ASIM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM to 00H.
Figure 17-4. Asynchronous Serial Interface Mode Register Format
Note When SCK is set to 1 and the baud rate generator output is selected, the ASCK pin can be used as
an I/O port.
Cautions 1. When the 3-wire serial I/O mode is selected, 00H should be set in ASIM.
2. The serial transmit/receive operation must be stopped before changing the operating
mode.
65432107
Symbol
ASIM TXE RXE PS1 PS0 CL SL ISRM SCK FF70H 00H R/W
Address After Reset R/W
SCK
0
1
Clock Selection in Asynchronous Serial Interface Mode
Input clock from off-chip to ASCK pin
Dedicated baud rate generator output
Note
ISRM
0
1
Control of Reception Completion Interrupt When Error Occurs
Reception completion interrupt generated when an error occurs
Reception completion interrupt not generated when an error occurs
SL Transmit Data Stop Bit Length Specification
CL
1
Character Length Specification
7 bits
8 bits
RXE
0
1
Receive Operation Control
Receive operation stopped
Receive operation enabled
TXE
0
1
Transmit Operation Control
Transmit operation stopped
Transmit operation enabled
PS1
0
1
0 1 bit
1 2 bits
0
Parity Bit Specification
No parity
Even parity
PS0
0
1
0 parity always added in transmission
No parity test in reception (parity errors do not occur)
01
1 Odd parity
0
357
CHAPTER 17 SERIAL INTERFACE CHANNEL 2
User’s Manual U11377EJ3V0UD
Table 17-2. Serial Interface Channel 2 Operating Mode Settings (1/2)
(1) Operation stop mode
(2) 3-wire serial I/O mode
Notes 1. Can be used freely as port function.
2. Can be used as P70 (CMOS I/O) when only transmitter is used.
Remark ×: don't care
P72/SCK2
/ASCK Pin
Functions
P71/SO2
/TxD Pin
Functions
P70/SI2
/RxD Pin
Functions
Shift
Clock
Start
Bit
TXE RXE SCK
CSIE2
CSIM22
CSCK
PM70
P70
PM71
P71
PM72
P72
ASIM CSIM2
0001
1
0
1
0
1
0
1
×
Note 2
×
Note 2
01
PM113
×
Note 1
P113
×
Note 1
PM114
×
Note 1
P114
×
Note 1
1
0
1
0
×
1
×
1
MSB
LSB
External
clock
Internal
clock
External
clock
Internal
clock
SI2
Note 2
SI2
Note 2
SO2
(CMOS
output)
SO2
(CMOS
output)
P113/TxD
Pin
Functions
P113
P114/RxD
Pin
Functions
P114
SCK2 input
SCK2 output
SCK2 input
SCK2 output
Other than above Setting prohibited
SIPS
SIPS21 SIPS20
××
P72/SCK2
/ASCK Pin
Functions
P71/SO2
/TxD Pin
Functions
P70/SI2
/RxD Pin
Functions
Shift
Clock
Start
Bit
TXE RXE SCK
CSIE2
CSIM22
CSCK
PM70
P70
PM71
P71
PM72
P72
ASIM CSIM2
00×0×× ×
Note 1
×
Note 1
×
Note 1
×
Note 1
PM113
×
Note 1
P113
×
Note 1
PM114
×
Note 1
P114
×
Note 1
×
Note1
×
Note 1
—— P70 P71
P113/TxD
Pin
Functions
P113
P114/RxD
Pin
Functions
P114 P72
Other than above Setting prohibited
SIPS
SIPS21 SIPS20
××
358
CHAPTER 17 SERIAL INTERFACE CHANNEL 2
User’s Manual U11377EJ3V0UD
Table 17-2. Serial Interface Channel 2 Operating Mode Settings (2/2)
(3) Asynchronous serial interface mode
Note Can be used freely as port function.
Remark ×: don’t care
PM××: Port mode register
P××: Port output latch
P72/SCK2
/ASCK Pin
Functions
P71/SO2
/TxD Pin
Functions
P70/SI2
/RxD Pin
Functions
Shift
Clock
Start
Bit
TXE RXE SCK
CSIE2
CSIM22
CSCK
PM70
P70
PM71
P71
PM72
P72
ASIM CSIM2
1
0
1
1
0
1
0
1
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
×
Note
×
Note
0
0
0
0
1
1
1
1
PM113
×
Note
×
Note
×
Note
×
Note
×
Note
×
Note
×
Note
1
×
Note
×
Note
×
×
P113
×
Note
PM114
×
Note
P114
×
Note
1
1
1
1
1
1
×
×
×
×
×
×
LSB
External
clock
Internal
clock
External
clock
Internal
clock
External
clock
Internal
clock
External
clock
Internal
clock
External
clock
Internal
clock
External
clock
Internal
clock
P70
RxD
P70
P70
(Input)
P70
(Input)
TxD
(CMOS
output)
P71
TxD
(CMOS
output)
High
output
P71
High
output
P113/TxD
Pin
Functions
P113
TxD
P113
TxD
P114/RxD
Pin
Functions
P114
P114
RxD
RxD
ASCK input
P72
ASCK input
P72
ASCK input
P72
ASCK input
P72
ASCK input
P72
ASCK input
P72
Other than above Setting prohibited
SIPS
SIPS21 SIPS20
0
0
0
1
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
×
×
×
1
1
0
0
×
Note
×
Note
×
Note
×
Note
×
Note
×
Note
×
Note
×
Note
×
Note
×
Note
×
Note
×
Note
1×
×
Note
×
Note
×
Note
×
Note
×
Note
×
Note
×
Note
×
Note
×
Note
×
Note
1
359
CHAPTER 17 SERIAL INTERFACE CHANNEL 2
User’s Manual U11377EJ3V0UD
(3) Asynchronous serial interface status register (ASIS)
This is a register which displays the type of error when a receive error occurs in the asynchronous serial
interface mode.
ASIS is read with an 8-bit memory manipulation instruction.
In 3-wire serial I/O mode, the contents of ASIS are undefined.
RESET input clears ASIS to 00H.
Figure 17-5. Asynchronous Serial Interface Status Register Format
Notes 1. Even if the stop bit length has been set as 2 bits by bit 2 (SL) of the asynchronous serial interface
mode register (ASIM), only single stop bit detection is performed during reception.
2. The receive buffer register (RXB) must be read when an overrun error occurs. Overrun errors will
continue to occur until RXB is read.
PE
65432107
Symbol
ASIS 0 0 0 0 0 FE OVE FF71H 00H R
Address After Reset R/W
OVE
0
1
Overrun Error Flag
Overrun error does not occur
Overrun error occurs
(When next receive operation is completed before data from receive buffer register is read)
Note 2
FE
0
1
Framing Error Flag
Framing error does not occur
Framing error occurs (When stop bit is not detected)
Note 1
PE
0
1
Parity Error Flag
Parity error does not occur
Parity error occurs (When transmit data parity does not match)
360
CHAPTER 17 SERIAL INTERFACE CHANNEL 2
User’s Manual U11377EJ3V0UD
(4) Baud rate generator control register (BRGC)
This register sets the serial clock for serial interface channel 2.
BRGC is set with an 8-bit memory manipulation instruction.
RESET input clears BRGC to 00H.
Figure 17-6. Baud Rate Generator Control Register Format (1/2)
Remarks 1. fX: Main system clock oscillation frequency
2. MCS: Oscillation mode select register bit 0
3. n: Value set in TPS0 to TPS3 (1 ≤ n ≤ 11)
4. Figures in parentheses apply to operation with fX = 5.0 MHz
65432107
Symbol
BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 FF73H 00H R/W
Address After Reset R/W
Selects Source Clock of 5-bit Counter
TPS3 TPS2 TPS1 TPS0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
MCS = 1
fX (5.0 MHz)
fX/210 (4.9 kHz)
fX/2 (2.5 MHz)
fX/22 (1.25 MHz)
fX/23 (625 kHz)
fX/24 (313 kHz)
fX/25 (156 kHz)
fX/26 (78.1 kHz)
fX/27 (39.1 kHz)
fX/28 (19.5 kHz)
fX/29 (9.8 kHz)
MCS = 0
fX/211 (2.4 kHz)
fX/2 (2.5 MHz)
fX/22 (1.25 MHz)
fX/23 (625 kHz)
fX/24 (313 kHz)
fX/25 (156 kHz)
fX/26 (78.1 kHz)
fX/27 (39.1 kHz)
fX/28 (19.5 kHz)
fX/29 (9.8 kHz)
fX/210 (4.9 kHz)
Other than above Setting prohibited
11
1
2
3
4
5
6
7
8
9
10
n
361
CHAPTER 17 SERIAL INTERFACE CHANNEL 2
User’s Manual U11377EJ3V0UD
Figure 17-6. Baud Rate Generator Control Register Format (2/2)
Note Can only be used in 3-wire serial I/O mode.
Caution When a write is performed to BRGC during a communication operation, baud rate generator
output is disrupted and communication cannot be performed normally.
Therefore, BRGC must not be written to during a communication operation.
Remarks 1. fSCK: 5-bit counter source clock
2. k: Value set in MDL0 to MDL3 (0 ≤ k ≤ 14)
Baud Rate Generator Input Clock SelectionMDL3 MDL2 MDL1 MDL0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
f
SCK
/16
f
SCK
/17
f
SCK
/18
f
SCK
/19
f
SCK
/20
f
SCK
/21
f
SCK
/22
f
SCK
/23
f
SCK
/24
f
SCK
/25
f
SCK
/26
f
SCK
/27
f
SCK
/28
f
SCK
/29
f
SCK
/30
f
SCKNote
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
—
k
362
CHAPTER 17 SERIAL INTERFACE CHANNEL 2
User’s Manual U11377EJ3V0UD
The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal
scaled from the clock input from the ASCK pin.
(a) Generation of baud rate transmit/receive clock by means of main system clock
The transmit/receive clock is generated by scaling the main system clock. The baud rate generated from
the main system clock is obtained with the following expression.
[Baud rate] = [Hz]
fX: Main system clock oscillation frequency
fXX: Main system clock frequency (fx or fx/2)
n: Value set in TPS0 to TPS3 (1 ≤ n ≤ 11)
k: Value set in MDL0 to MDL3 (0 ≤ k ≤14)
Table 17-3. Relationships Between Main System Clock and Baud Rate
fx = 5.0 MHz fx = 4.19 MHz
MCS = 1 MCS = 0 MCS = 1 MCS = 0
BRGC Set Value Error (%) BRGC Set Value Error (%) BRGC Set Value Error (%) BRGC Set Value Error (%)
75 –00H 1.73 0BH 1.14 EBH 1.14
110 06H 0.88 E6H 0.88 03H –2.01 E3H –2.01
150 00H 1.73 E0H 1.73 EBH 1.14 DBH 1.14
300 E0H 1.73 D0H 1.73 DBH 1.14 CBH 1.14
600 D0H 1.73 C0H 1.73 CBH 1.14 BBH 1.14
1200 C0H 1.73 B0H 1.73 BBH 1.14 ABH 1.14
2400 B0H 1.73 A0H 1.73 ABH 1.14 9BH 1.14
4800 A0H 1.73 90H 1.73 9BH 1.14 8BH 1.14
9600 90H 1.73 80H 1.73 8BH 1.14 7BH 1.14
19200 80H 1.73 70H 1.73 7BH 1.14 6BH 1.14
31250 74H 0 64H 0 71H –1.31 61H –1.31
38400 70H 1.73 60H 1.73 6BH 1.14 5BH 1.14
76800 60H 1.73 50H 1.73 5BH 1.14 ——
MCS: Oscillation mode select register (CSMS) bit 0
fXX
2n × (k + 16)
Baud
Rate
(bps)
363
CHAPTER 17 SERIAL INTERFACE CHANNEL 2
User’s Manual U11377EJ3V0UD
(b) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin
The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate
generated from the clock input from the ASCK pin is obtained with the following expression.
[Baud rate] = [Hz]
fASCK: Frequency of clock input to ASCK pin
k: Value set in MDL0 to MDL3 (0 ≤ k ≤ 14)
Table 17-4. Relationships Between ASCK Pin Input Frequency and Baud Rate (When BRGC Is Set to 00H)
Baud Rate (bps) ASCK Pin Input Frequency
75 2.4 kHz
110 3.52 kHz
150 4.8 kHz
300 9.6 kHz
600 19.2 kHz
1200 38.4 kHz
2400 76.8 kHz
4800 153.6 kHz
9600 307.2 kHz
19200 614.4 kHz
31250 1000.0 kHz
38400 1228.8 kHz
fASCK
2 × (k + 16)
364
CHAPTER 17 SERIAL INTERFACE CHANNEL 2
User’s Manual U11377EJ3V0UD
(5) Serial interface pin select register (SIPS)
This register selects I/O pins when serial interface channel 2 is used in the asynchronous serial interface mode.
SIPS is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SIPS to 00H.
To select I/O pins, the port mode register and the output latch of the port must be set. For details, refer to
Table 17-2 Serial Interface Channel 2 Operating Mode Settings.
Figure 17-7. Serial Interface Pin Select Register Format
Cautions 1. Select I/O pins after stopping serial transmission/reception.
2. Port 11 has a falling edge detection function. Do not specify the pin of this port used
in a mode other than port mode to input the falling edge. For how to set to input the falling
edge, refer to Figure 6-21 Key Return Mode Register Format.
65432107
Symbol
SIPS 0 0
SIPS21 SIPS20
0000FF75H 00H R/W
Address After Reset R/W
SIPS21
0
1
Selects I/O Pin of Asynchronous Serial Interface
Input pin: RxD/SI2/P70
Output pin: TxD/SO2/P71
Input pin: RxD/P114
Output pin: TxD/P113
SIPS20
0
1
Input pin: RxD/P114
Output pin: TxD/SO2/P71
01
1Input pin: RxD/SI2/P70
Output pin: TxD/P113
0
365
CHAPTER 17 SERIAL INTERFACE CHANNEL 2
User’s Manual U11377EJ3V0UD
17.4 Serial Interface Channel 2 Operation
The operating mode of serial interface channel 2 has the following three types.
•Operation stop mode
•Asynchronous serial interface (UART) mode
•3-wire serial I/O mode
17.4.1 Operation stop mode
In the operation stop mode, serial transfer is not performed, and therefore power consumption can be reduced.
In the operation stop mode, the P70/SI2/RxD, P71/SO2/TxD, P72/SCK2/ASCK, P113/TxD, and P114/RxD pins
can be used as normal I/O ports.
(1) Register setting
Operation stop mode settings are performed using serial operating mode register 2 (CSIM2) and the
asynchronous serial interface mode register (ASIM).
(a) Serial operating mode register 2 (CSIM2)
CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM2 to 00H.
Caution Ensure that bit 0 and bit 3 to bit 6 are set to 0.
CSIM
22
65432107
Symbol
CSIM2 CSIE2 0 0 0 0 CSCK 0 FF72H 00H R/W
Address After Reset R/W
CSIE2
0
1
Operation Control in 3-wire Serial I/O Mode
Operation stopped
Operation enabled
366
CHAPTER 17 SERIAL INTERFACE CHANNEL 2
User’s Manual U11377EJ3V0UD
(b) Asynchronous serial interface mode register (ASIM)
ASIM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM to 00H.
SL
65432107
Symbol
ASIM TXE RXE PS1 PS0 CL ISRM SCK FF70H 00H R/W
Address After Reset R/W
RXE
0
1
Receive Operation Control
Receive operation stopped
Receive operation enabled
TXE
0
1
Transmit Operation Control
Transmit operation stopped
Transmit operation enabled
367
CHAPTER 17 SERIAL INTERFACE CHANNEL 2
User’s Manual U11377EJ3V0UD
17.4.2 Asynchronous serial interface (UART) mode
In this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is possible.
A dedicated UART baud rate generator is incorporated, allowing communication over a wide range of baud rates.
In addition, the baud rate can be defined by scaling the input clock to the ASCK pin.
The MIDI standard baud rate (31.25 kbps) can be used by employing the dedicated UART baud rate generator.
Serial interface channel 2 has two data I/O pins (RxD and TxD) which can be selected by software. Note that only
one data I/O pin can be used at one time.
Caution When it is not necessary to change the data I/O pin, using the RxD/SI2/P70 and TxD/SO2/P71 is
recommended. If only port 11 (RxD/P114 and TxD/P113) is used as data I/O pin, the function of
port 7 is limited.
(1) Register setting
UART mode settings are performed using serial operating mode register 2 (CSIM2), the asynchronous serial
interface mode register (ASIM), the asynchronous serial interface status register (ASIS), the baud rate
generator control register (BRGC), and the serial interface pin select register (SIPS).
(a) Serial operating mode register 2 (CSIM2)
CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM2 to 00H.
When the UART mode is selected, 00H should be set in CSIM2.
Caution Ensure that bit 0 and bit 3 to bit 6 are set to 0.
65432107
Symbol
CSIM2 CSIE2 0 0 0 0 CSIM
22
CSCK 0
CSCK
0
1
Clock Selection in 3-wire Serial I/O Mode
Input clock from off-chip to SCK2 pin
Dedicated baud rate generator output
CSIM22
0
1
First Bit Specification
MSB
LSB
CSIE2
0
1
Operation Control in 3-wire Serial I/O Mode
Operation stopped
Operation enabled
FF72H 00H R/W
Address After Reset R/W
368
CHAPTER 17 SERIAL INTERFACE CHANNEL 2
User’s Manual U11377EJ3V0UD
(b) Asynchronous serial interface mode register (ASIM)
ASIM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM to 00H.
Note When SCK is set to 1 and the baud rate generator output is selected, the ASCK pin can be used
as an I/O port.
Caution The serial transmit/receive operation must be stopped before changing the operating
mode.
65432107
Symbol
ASIM TXE RXE PS1 PS0 CL SL ISRM SCK FF70H 00H R/W
Address After Reset R/W
SCK
0
1
Clock Selection in Asynchronous Serial Interface Mode
Input clock from off-chip to ASCK pin
Dedicated baud rate generator output
Note
ISRM
0
1
Control of Reception Completion Interrupt When Error Occurs
Reception completion interrupt generated when an error occurs
Reception completion interrupt not generated when an error occurs
SL Transmit Data Stop Bit Length Specification
CL
1
Character Length Specification
7 bits
8 bits
RXE
0
1
Receive Operation Control
Receive operation stopped
Receive operation enabled
TXE
0
1
Transmit Operation Control
Transmit operation stopped
Transmit operation enabled
PS1
0
1
0 1 bit
1 2 bits
0
Parity Bit Specification
No parity
Even parity
PS0
0
1
0 parity always added in transmission
No parity test in reception (parity errors do not occur)
01
1 Odd parity
0
369
CHAPTER 17 SERIAL INTERFACE CHANNEL 2
User’s Manual U11377EJ3V0UD
(c) Asynchronous serial interface status register (ASIS)
ASIS is read with an 8-bit memory manipulation instruction.
RESET input clears ASIS to 00H.
Notes 1. Even if the stop bit length has been set as 2 bits by bit 2 (SL) of the asynchronous serial
interface mode register (ASIM), only single stop bit detection is performed during reception.
2. The receive buffer register (RXB) must be read when an overrun error occurs. Overrun errors
will continue to occur until RXB is read.
PE
65432107
Symbol
ASIS 0 0 0 0 0 FE OVE FF71H 00H R
Address After Reset R/W
OVE
0
1
Overrun Error Flag
Overrun error does not occur
Overrun error occurs
(When next receive operation is completed before data from receive buffer register is read)Note 2
FE
0
1
Framing Error Flag
Framing error does not occur
Framing error occurs (When stop bit is not detected)Note 1
PE
0
1
Parity Error Flag
Parity error does not occur
Parity error occurs (When transmit data parity does not match)
370
CHAPTER 17 SERIAL INTERFACE CHANNEL 2
User’s Manual U11377EJ3V0UD
(d) Baud rate generator control register (BRGC)
BRGC is set with an 8-bit memory manipulation instruction.
RESET input clears BRGC to 00H.
(continued)
Remarks 1. fX: Main system clock oscillation frequency
2. MCS: Oscillation mode select register bit 0
3. n: Value set in TPS0 to TPS3 (1 ≤ n ≤ 11)
4. Figures in parentheses apply to operation with fX = 5.0 MHz.
65432107
Symbol
BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 FF73H 00H R/W
Address After Reset R/W
Selects Source Clock of 5-bit Counter
TPS3 TPS2 TPS1 TPS0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
MCS = 1
f
X
(5.0 MHz)
f
X
/2
10
(4.9 kHz)
f
X
/2 (2.5 MHz)
f
X
/2
2
(1.25 MHz)
f
X
/2
3
(625 kHz)
f
X
/2
4
(313 kHz)
f
X
/2
5
(156 kHz)
f
X
/2
6
(78.1 kHz)
f
X
/2
7
(39.1 kHz)
f
X
/2
8
(19.5 kHz)
f
X
/2
9
(9.8 kHz)
MCS = 0
f
X
/2
11
(2.4 kHz)
f
X
/2 (2.5 MHz)
f
X
/2
2
(1.25 MHz)
f
X
/2
3
(625 kHz)
f
X
/2
4
(313 kHz)
f
X
/2
5
(156 kHz)
f
X
/2
6
(78.1 kHz)
f
X
/2
7
(39.1 kHz)
f
X
/2
8
(19.5 kHz)
f
X
/2
9
(9.8 kHz)
f
X
/2
10
(4.9 kHz)
Other than above Setting prohibited
11
1
2
3
4
5
6
7
8
9
10
n
371
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Caution When a write is performed to BRGC during a communication operation, baud rate
generator output is disrupted and communication cannot be performed normally.
Therefore, BRGC must not be written to during a communication operation.
Remark fSCK: 5-bit counter source clock
k: Value set in MDL0 to MDL3 (0 ≤ k ≤14)
Baud Rate Generator Input Clock SelectionMDL3 MDL2 MDL1 MDL0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
fSCK/16
fSCK/17
fSCK/18
fSCK/19
fSCK/20
fSCK/21
fSCK/22
fSCK/23
fSCK/24
fSCK/25
fSCK/26
fSCK/27
fSCK/28
fSCK/29
fSCK/30
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
k
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The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or
a signal scaled from the clock input from the ASCK pin.
(i) Generation of baud rate transmit/receive clock by means of main system clock
The transmit/receive clock is generated by scaling the main system clock. The baud rate generated
from the main system clock is obtained with the following expression.
[Baud rate] = [Hz]
fX: Main system clock oscillation frequency
fXX: Main system clock frequency (fx or fx/2)
n: Value set in TPS0 to TPS3 (1 ≤ n ≤ 11)
k: Value set in MDL0 to MDL3 (0 ≤ k ≤14)
Table 17-5. Relationships Between Main System Clock and Baud Rate
fx = 5.0 MHz fx = 4.19 MHz
MCS = 1 MCS = 0 MCS = 1 MCS = 0
BRGC Set Value Error (%) BRGC Set Value Error (%) BRGC Set Value Error (%) BRGC Set Value Error (%)
75 —00H 1.73 0BH 1.14 EBH 1.14
110 06H 0.88 E6H 0.88 03H –2.01 E3H –2.01
150 00H 1.73 E0H 1.73 EBH 1.14 DBH 1.14
300 E0H 1.73 D0H 1.73 DBH 1.14 CBH 1.14
600 D0H 1.73 C0H 1.73 CBH 1.14 BBH 1.14
1200 C0H 1.73 B0H 1.73 BBH 1.14 ABH 1.14
2400 B0H 1.73 A0H 1.73 ABH 1.14 9BH 1.14
4800 A0H 1.73 90H 1.73 9BH 1.14 8BH 1.14
9600 90H 1.73 80H 1.73 8BH 1.14 7BH 1.14
19200 80H 1.73 70H 1.73 7BH 1.14 6BH 1.14
31250 74H 0 64H 0 71H –1.31 61H –1.31
38400 70H 1.73 60H 1.73 6BH 1.14 5BH 1.14
76800 60H 1.73 50H 1.73 5BH 1.14 ——
MCS: Oscillation mode select register (OSMS) bit 0
Baud
Rate
(bps)
fXX
2n × (k + 16)
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(ii) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin
The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate
generated from the clock input from the ASCK pin is obtained with the following expression.
[Baud rate] = [Hz]
fASCK: Frequency of clock input to ASCK pin
k: Value set in MDL0 to MDL3 (0 ≤ k ≤ 14)
Table 17-6. Relationships Between ASCK Pin Input Frequency and Baud Rate (When BRGC Is Set to 00H)
Baud Rate (bps) ASCK Pin Input Frequency
75 2.4 kHz
110 3.52 kHz
150 4.8 kHz
300 9.6 kHz
600 19.2 kHz
1200 38.4 kHz
2400 76.8 kHz
4800 153.6 kHz
9600 307.2 kHz
19200 614.4 kHz
31250 1000.0 kHz
38400 1228.8 kHz
2 × (k + 16)
fASCK
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(e) Serial interface pin select register (SIPS)
SIPS is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SIPS to 00H.
To select I/O pins, the port mode register and the output latch of the port must be set. For details, refer
to Table 17-2 Serial Interface Channel 2 Operating Mode Settings.
Cautions 1. Select I/O pins after stopping serial transmission/reception.
2. Port 11 has a function to detect the falling edge. To use the TxD/P113 or RxD/P114 pin
as the I/O pin of serial interface channel 2, the falling edge detection function must be
disabled by using the key return mode register (KRM). For details, refer to Figure 6-21
Key Return Mode Register Format.
65432107
Symbol
SIPS 0 0
SIPS21 SIPS20
0000FF75H 00H R/W
Address After Reset R/W
SIPS21
0
1
Selects I/O Pin of Asynchronous Serial Interface
Input pin: RxD/SI2/P70
Output pin: TxD/SO2/P71
Input pin: RxD/P114
Output pin: TxD/P113
SIPS20
0
1
Input pin: RxD/P114
Output pin: TxD/SO2/P71
01
1Input pin: RxD/SI2/P70
Output pin: TxD/P113
0
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(2) Communication operation
(a) Data format
Figure 17-8 shows the format of the transmit/receive data.
Figure 17-8. Asynchronous Serial Interface Transmit/Receive Data Format
One data frame consists of the following bits:
•Start bit ................... 1 bit
•Character bits ......... 7 bits/8 bits
•Parity bits ................ Even parity/odd parity/0 parity/no parity
•Stop bit(s) ............... 1 bit/2 bits
The specification of character bit length, parity selection, and specification of stop bit length for each data
frame is carried out with the asynchronous serial interface mode register (ASIM).
When 7 bits are selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in
transmission the most significant bit (bit 7) is ignored, and in reception the most significant bit (bit 7) is
always "0".
The serial transfer rate is selected by means of the ASIM and the baud rate generator control register
(BRGC).
If a serial data receive error occurs, the receive error contents can be determined by reading the status
of the asynchronous serial interface status register (ASIS).
D0 D1 D2 D3 D4 D5 D6 D7 Parity
bit Stop bit
Start
bit
One data frame
Character bit
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(b) Parity types and operation
The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity
bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd
number) error can be detected. With 0 parity and no parity, an error cannot be detected.
(i) Even parity
• At transmission
Control is executed so that the number of bits with a value of "1" contained in the transmit data including
parity bit is an even number. The parity bit value should be as follows.
The number of bits with a value of "1" is an odd number in transmit data: 1
The number of bits with a value of "1" is an even number in transmit data: 0
• At reception
The number of bits with a value of "1" contained in the receive data including parity bit are counted,
and if this is an odd number, a parity error occurs.
(ii) Odd parity
• At transmission
Conversely to the situation with even parity, control is executed so that the number of bits with a value
of "1" contained in the transmit data including parity bit is an odd number. The parity bit value should
be as follows.
The number of bits with a value of "1" is an odd number in transmit data: 0
The number of bits with a value of "1" is an even number in transmit data: 1
• At reception
The number of bits with a value of "1" contained in the receive data including parity bit are counted,
and if this is an even number, a parity error occurs.
(iii) 0 Parity
When transmitting, the parity bit is set to "0" irrespective of the transmit data.
At reception, a parity bit check is not performed. Therefore, no parity errors will occur, irrespective of
whether the parity bit is set to "0" or "1".
(iv) No parity
A parity bit is not added to the transmit data. At reception, data is received assuming that there is no
parity bit. Since there is no parity bit, no parity errors will occur.
377
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(c) Transmission
A transmit operation is started by writing transmit data to the transmit shift register (TXS). The start bit,
parity bit and stop bit(s) are added automatically.
When the transmit operation starts, the data in the TXS is shifted out, and when the TXS is empty, a
transmit completion interrupt request (INTST) is generated.
Figure 17-9. Asynchronous Serial Interface Transmit Completion Interrupt Request Timing
(a) Stop bit length: 1
(b) Stop bit length: 2
Caution Rewriting of the asynchronous serial interface mode register (ASIM) should not be
performed during a transmit operation. If rewriting of the ASIM register is performed
during transmission, subsequent transmit operations may not be possible (the normal
state is restored by RESET input).
It is possible to determine whether transmission is in progress by software by using a
transmit completion interrupt request (INTST) or the interrupt request flag (STIF) set by
the INTST.
D1 D2 D6 D7 ParityD0TxD (Output)
INTST
STOP
START
D1 D2 D6 D7 ParityD0TxD (Output)
INTST
STOP
START
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(d) Reception
When the RXE bit of the asynchronous serial interface mode register (ASIM) is set (to 1), a receive
operation is enabled and sampling of the RxD pin input is performed.
RxD pin input sampling is performed using the serial clock specified by ASIM.
When the RxD pin goes low, the 5-bit counter of the baud rate generator (refer to Figure 17-2) starts
counting. When the time half the set baud rate has elapsed, a signal to start data sampling is output.
If the RxD pin input sampled again as a result of this start timing signal is low, it is identified as a start
bit, the 5-bit counter is initialized and starts counting, and data sampling is performed. When character
data, a parity bit and one stop bit are detected after the start bit, reception of one frame of data ends.
When one frame of data has been received, the receive data in the shift register is transferred to the receive
buffer register (RXB), and a receive completion interrupt request (INTSR) is generated.
Even if an error occurs, the receive data responsible for the error is transferred to RXB. If bit 1 (ISRM)
of ASIM is cleared to 0 on occurrence of the error, INTSR is generated.
If the ISRM bit is set to 1, INTSR is not generated.
If the RXE bit is reset (to 0) during the receive operation, the receive operation is stopped immediately.
In this case, the contents of RXB and asynchronous serial interface status register (ASIS) are not changed,
and INTSR and INTSER are not generated.
Figure 17-10. Asynchronous Serial Interface Receive Completion Interrupt Request Timing
Caution The receive buffer register (RXB) must be read even if a receive error occurs. If RXB
is not read, an overrun error will occur when the next data is received, and the receive
error state will continue indefinitely.
D1 D2 D6 D7 ParityD0RxD (Input)
INTSR
STOP
START
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(e) Receive errors
Three kinds of errors can occur during a receive operation: a parity error, framing error, or overrun error.
The data reception result error flag is set in the asynchronous serial interface status register (ASIS) and
a receive error interrupt (INTSER) is generated. The receive error interrupt occurs earlier than the receive
completion interrupt (INTSR). Receive error causes are shown in Table 17-7.
It is possible to determine what kind of error occurred during reception by reading the contents of the ASIS
in the receive error interrupt servicing (INTSER) (see Figures 17-10 and 17-11).
The contents of ASIS are reset (to 0) by reading the receive buffer register (RXB) or receiving the next
data (if there is an error in the next data, the corresponding error flag is set).
Table 17-7. Receive Error Causes
Receive Errors Cause
Parity error Transmission-time parity specification and reception data parity do not match
Framing error Stop bit not detected
Overrun error Reception of next data is completed before data is read from receive register buffer
Figure 17-11. Receive Error Timing
Note INTSR does not occur if a receive error occurs while bit 1 (ISRM) of the asynchronous serial
interface mode register (ASIM) is set to 1.
Cautions 1. The contents of the asynchronous serial interface status register (ASIS) are reset (to
0) by reading the receive buffer register (RXB) or receiving the next data. To ascertain
the error contents, ASIS must be read before reading RXB.
2. The receive buffer register (RXB) must be read even if a receive error occurs. If RXB
is not read, an overrun error will occur when the next data is received, and the receive
error state will continue indefinitely.
RxD (Input) D0 D1 D2 D6 D7 Parity STOP
START
INTSRNote
INTSER
(When framing/overrun
error occurs)
INTSER
(When parity error occurs)
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(3) UART mode cautions
(a) If the transmission under execution has been stopped by clearing bit 7 of the asynchronous serial interface
mode register (ASIM) to 0, be sure to set the transmit shift register (TXS) to FFH and TXE to 1 before
executing the next transmission.
(b) If the reception under execution has been stopped by clearing bit 6 (REX) of the asynchronous serial
interface mode register (ASIM) to 0, the status of the receive buffer register (RXB) and whether the receive
completion interrupt request (INTSR) occurs differ depending on the reception stop timing.
Figure 17-12. Status of Receive Buffer Register (RXB) and Generation of
Interrupt Request (INTSR) When Reception is Stopped
When RXE is set to 0 at a time indicated by <1>, RXB holds the previous data and does not generate INTSR.
When RXE is set to 0 at a time indicated by <2>, RXB renews the data and does not generate INTSR.
When RXE is set to 0 at a time indicated by <3>, RXB renews the data and generates INTSR.
ParityRxD pin
RXB
INTSR
<3><1>
<2>
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17.4.3 3-wire serial I/O mode
The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate
a conventional synchronous clocked serial interface, such as the 75X/XL Series, 78K Series, 17K Series, etc.
Communication is performed using three lines: the serial clock (SCK2), serial output (SO2), and serial input (SI2).
In the 3-wire serial I/O mode, the P113/TxD and P114/RxD pins can be used as ordinary I/O port pins.
(1) Register setting
3-wire serial I/O mode settings are performed using serial operating mode register 2 (CSIM2), the asynchro-
nous serial interface mode register (ASIM), and the baud rate generator control register (BRGC).
(a) Serial operating mode register 2 (CSIM2)
CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM2 to 00H.
Caution Ensure that bit 0 and bit 3 to bit 6 are set to 0.
65432107
Symbol
CSIM2 CSIE2 0 0 0 0 CSIM
22
CSCK 0
CSCK
0
1
Clock Selection in 3-wire Serial I/O Mode
Input clock from off-chip to SCK2 pin
Dedicated baud rate generator output
CSIM22
0
1
First Bit Specification
MSB
LSB
CSIE2
0
1
Operation Control in 3-wire Serial I/O Mode
Operation stopped
Operation enabled
FF72H 00H R/W
Address After Reset R/W
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(b) Asynchronous serial interface mode register (ASIM)
ASIM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM to 00H.
When the 3-wire serial I/O mode is selected, 00H should be set in ASIM.
65432107
Symbol
ASIM TXE RXE PS1 PS0 CL SL ISRM SCK FF70H 00H R/W
Address After Reset R/W
SCK
0
1
Clock Selection in Asynchronous Serial Interface Mode
Input clock from off-chip to ASCK pin
Dedicated baud rate generator output
ISRM
0
1
Control of Receive Completion Interrupt When Error Occurs
Receive completion interrupt generated when an error occurs
Receive completion interrupt not generated when an error occurs
SL Transmit Data Stop Bit Length Specification
CL
1
Character Length Specification
7 bits
8 bits
RXE
0
1
Receive Operation Control
Receive operation stopped
Receive operation enabled
TXE
0
1
Transmit Operation Control
Transmit operation stopped
Transmit operation enabled
PS1
0
1
0 1 bit
1 2 bits
0
Parity Bit Specification
No parity
Even parity
PS0
0
1
0 parity always added in transmission
No parity test in reception (parity errors do not occur)
01
1 Odd parity
0
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(c) Baud rate generator control register (BRGC)
BRGC is set with an 8-bit memory manipulation instruction.
RESET input clears BRGC to 00H.
Remarks 1. fX: Main system clock oscillation frequency
2. MCS: Oscillation mode select register bit 0
3. n: Value set in TPS0 to TPS3 (1 ≤ n ≤ 11)
4. Figures in parentheses apply to operation with fX = 5.0 MHz.
(continued)
65432107
Symbol
BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 FF73H 00H R/W
Address After Reset R/W
Selects Source Clock of 5-bit Counter
TPS3 TPS2 TPS1 TPS0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
MCS = 1
fX (5.0 MHz)
fX/210 (4.9 kHz)
fX/2 (2.5 MHz)
fX/22 (1.25 MHz)
fX/23 (625 kHz)
fX/24 (313 kHz)
fX/25 (156 kHz)
fX/26 (78.1 kHz)
fX/27 (39.1 kHz)
fX/28 (19.5 kHz)
fX/29 (9.8 kHz)
MCS = 0
fX/211 (2.4 kHz)
fX/2 (2.5 MHz)
fX/22 (1.25 MHz)
fX/23 (625 kHz)
fX/24 (313 kHz)
fX/25 (156 kHz)
fX/26 (78.1 kHz)
fX/27 (39.1 kHz)
fX/28 (19.5 kHz)
fX/29 (9.8 kHz)
fX/210 (4.9 kHz)
Other than above Setting prohibited
11
1
2
3
4
5
6
7
8
9
10
n
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Caution When a write is performed to BRGC during a communication operation, baud rate
generator output is disrupted and communication cannot be performed normally.
Therefore, BRGC must not be written to during a communication operation.
Remark fSCK: 5-bit counter source clock
k: Value set in MDL0 to MDL3 (0 ≤ k ≤14)
Baud Rate Generator Input Clock SelectionMDL3 MDL2 MDL1 MDL0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
fSCK/16
fSCK/17
fSCK/18
fSCK/19
fSCK/20
fSCK/21
fSCK/22
fSCK/23
fSCK/24
fSCK/25
fSCK/26
fSCK/27
fSCK/28
fSCK/29
fSCK/30
fSCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
—
k
385
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When the internal clock is used as the serial clock in the 3-wire serial I/O mode, set BRGC as described below.
BRGC setting is not required if an external serial clock is used.
(i) When the baud rate generator is not used:
Select a serial clock frequency with TPS0 to TPS3. Be sure then to set MDL0 to MDL3 to 1, 1, 1, 1.
The serial clock frequency is half the source clock frequency of the 5-bit counter.
(ii) When the baud rate generator is used:
Select a serial clock frequency with MDL0 to MDL3 and TPS0 to TPS3. Be sure then to set MDL0 to MDL3
to a value other than 1, 1, 1, 1.
The serial clock frequency is calculated by the following formula:
Serial clock frequency = [Hz]
fX: Main system clock oscillation frequency
fXX: Main system clock frequency (fX or fX/2)
n: Value set in TPS0 to TPS3 (1 ≤ n ≤ 11)
k: Value set in MDL0 to MDL3 (0 ≤ k ≤ 14)
fXX
2n × (k + 16)
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(2) Communication operation
In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Each bit of data is
transmitted or received in synchronization with the serial clock.
Transmit shift register (TXS/SIO2) and receive shift register (RXS) shift operations are performed in
synchronization with the falling edge of the serial clock (SCK2). Then transmit data is held in the SO2 latch
and output from the SO2 pin. Also, receive data input to the SI2 pin is latched in the receive buffer register
(RXB/SIO2) at the rising edge of SCK2.
At the end of an 8-bit transfer, the operation of the transmit shift register (TXS/SIO2) or receive shift register
(RXS) stops automatically, and the interrupt request flag (SRIF) is set.
Figure 17-13. 3-Wire Serial I/O Mode Timing
SI2
SCK2 12345678
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SO2 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
SRIF
Transfer start at the falling edge of SCK2
End of transfer
387
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(3) MSB/LSB switching as the start bit
The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB.
Figure 17-14 shows the configuration of the transmit shift register (TXS/SIO2) and internal bus. As shown
in the figure, MSB/LSB can be read/written in reverse form.
MSB/LSB switching as the start bit can be specified with bit 2 (CSIM22) of serial operating mode register 2
(CSIM2).
Figure 17-14. Circuit of Switching in Transfer Bit Order
Start bit switching is realized by switching the bit order for data write to SIO2. The SIO2 shift order remains
unchanged.
Thus, switching between MSB-first and LSB-first must be performed before writing data to the shift register.
(4) Transfer start
Serial transfer is started by setting transfer data to the transmit shift register (TXS/SIO2) when the following
two conditions are satisfied.
•Serial interface channel 2 operation control bit (CSIE2) = 1
•Internal serial clock is stopped or SCK2 is at high level after 8-bit serial transfer.
Caution If CSIE2 is set to "1" after data write to TXS/SIO2, transfer does not start.
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (SRIF) is
set.
7
6
Internal bus
1
0
LSB-first
MSB-first Read/write gate
SI2
Transmit shift register (TXS/SIO2)
Read/write gate
SO2
SCK2
DQ
SO2 latch
388
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17.4.4 Limitations of UART mode
In the UART mode, the receive completion interrupt (INTSR) occurs a certain time after the receive error interrupt
(INTSER) occurred and cleared. Consequently, the following phenomenon may take place.
•Description
If bit 1 (ISRM) of the asynchronous serial interface mode register (ASIM) is set to 1, the receive completion
interrupt (INTSR) does not occur when a receive error occurs. If the receive buffer register (RXB) is read at
certain timing (a in Figure 17-15) while the receive error interrupt (INTSER) is serviced, the internal error flag
is cleared to 0. Therefore, it is judged that the receive error does not occur, and INTSR, which must not occur,
occurs. This is illustrated in Figure 17-15.
Figure 17-15. Receive Completion Interrupt Generation Timing (When ISRM = 1)
Remark ISRM: Bit 1 of asynchronous serial interface mode register (ASIM)
fSCK: Source clock of 5-bit counter of baud rate generator
RXB: Receive buffer register
To prevent this phenomenon, take the following measures:
•Preventive measures
•In case of framing error or overrun error
Disable reading the receive buffer register (RXB) for a certain time (T2 in Figure 17-16) after the receive error
interrupt (INTSER) has occurred.
•In case of parity error
Disable reading the receive buffer register (RXB) for a certain time (T1 + T2 in Figure 17-16) after the receive
error interrupt (INTSER) has occurred.
It is judged that receive error does not
occur, and INTSR occurs.
f
SCK
INTSER (When framing/
overrun error occurs)
Error flag
(Internal flag)
INTSR
Interrupt servicing
routine of CPU
a
Cleared when
RXB is read
RXB is read
389
CHAPTER 17 SERIAL INTERFACE CHANNEL 2
User’s Manual U11377EJ3V0UD
Figure 17-16. Disabling Reading Receive Buffer Register
T1: Time of one data of baud rate selected by baud rate generator control register (BRGC) (1/baud rate)
T2: Time of two clocks of source clock (fSCK) of 5-bit counter selected by BRGC
•Example of preventive measures
Here is an example of preventive measures.
[Condition]
fX = 5.0 MHz
Processor clock control register (PCC) = 00H
Oscillation mode select register (OSMS) = 01H
Baud rate generator control register (BRGC) = B0H (baud rate: 2400 bps)
TCY = 0.4
µ
s (tCY = 0.2
µ
s)
T1 = = 416.7
µ
s
T2 = 12.8 × 2 = 25.6
µ
s
= 2212 (clock)
RxD (Input) D0 D1 D2 D6 D7 Parity STOP
START
INTSR
INTSER
(When framing/overrun
error occurs)
INTSER
(When parity error occurs)
T1 T2
1
2400
T1 + T2
tCY
390
CHAPTER 17 SERIAL INTERFACE CHANNEL 2
User’s Manual U11377EJ3V0UD
[Example]
Main processing
UART receive error
interrupt (INTSER) servicing
EI
MOV A,RXB
RETI
INTSER occurs
Seven CPU clocks (MIN.) (Time
from generation of interrupt
request to processing)
Instructions of
2205 CPU clocks
(MIN.) are
necessary.
391User’s Manual U11377EJ3V0UD
CHAPTER 18 SERIAL INTERFACE CHANNEL 3
18.1 Serial Interface Channel 3 Functions
Serial interface channel 3 operates in the following two modes.
• Operation stop mode
• 3-wire serial I/O mode
(1) Operation stop mode
This mode is used when serial interface channel 3 does not perform serial transfer, to reduce the power
consumption.
(2) 3-wire serial I/O mode (MSB/LSB first selectable)
In this mode, 8-bit data are transferred by using three lines: serial clock (SCK3), serial output (SO3), and serial
input (SI3).
Because transmission and reception can be carried out simultaneously in this mode, the data transfer time
can be shortened.
Because whether the 8-bit data to be transferred is transferred starting from its MSB or LSB can be selected
in this mode, serial interface channel 3 can be connected to any device.
The 3-wire serial I/O mode is effective for connecting peripheral I/Os and display controllers that have the
conventional clocked serial interface, such as the 75X/XL Series, 78K Series, and 17K Series.
18.2 Serial Interface Channel 3 Configuration
Serial interface channel 3 consists of the following hardware.
Table 18-1. Configuration of Serial Interface Channel 3
Item Configuration
Register Serial I/O shift register 3 (SIO3)
Control register Timer clock select register 4 (TCL4)
Serial operating mode register 3 (CSIM3)
Port mode register 11 (PM11)Note
Note Refer to Figure 6-15 P110, P114 to P117 Block Diagram and Figure 6-
16 P111 Block Diagram.
392
CHAPTER 18 SERIAL INTERFACE CHANNEL 3
User’s Manual U11377EJ3V0UD
Figure 18-1. Serial Interface Channel 3 Block Diagram
Remark fXX = fX/2 (MCS = 0), fXX = fX (MCS = 1)
P111 output latch
SCK3/P112
Internal bus
Selector
fxx/2 to fXX/28
Serial clock
counter
TCL47 TCL46 TCL45 TCL44
4
Timer clock
select
register 4
Serial operating
mode register 3
DIR
Serial I/O shift
register (SIO3)
SO3/P111
PM111
SI3/P110
Internal bus
Selector
Selector
PM112
Q
R
S
P112 output latch
SIO3 write
INTCSI3
Clear
CSIE3 DIR3
CSIM31 CSIM30
393
CHAPTER 18 SERIAL INTERFACE CHANNEL 3
User’s Manual U11377EJ3V0UD
(1) Serial I/O shift register 3 (SIO3)
This is an 8-bit register that performs parallel-to-serial conversion and serial transmission/reception (shift
operation) in synchronization with the serial clock.
SIO3 is set with an 8-bit memory manipulation instruction.
Serial operation is started by writing data to SIO3 when bit 7 (CSIE3) of serial operating mode register 3
(CSIM3) is 1.
During transmission, the data written to SIO3 is output to the serial output line (SO3). During reception, data
is read from the serial input line (SI3) to SIO3.
RESET input makes SIO3 undefined.
(2) Serial clock counter
This counter counts the serial clock output or input during transmission or reception to check whether 8-bit
data has been transmitted or received.
18.3 Serial Interface Channel 3 Control Registers
Serial interface channel 3 is controlled by the following two registers.
• Timer clock select register 4 (TCL4)
• Serial operating mode register 3 (CSIM3)
(1) Timer clock select register 4 (TCL4)
This register sets the serial clock of serial interface channel 3.
TCL4 is set with an 8-bit memory manipulation instruction.
RESET input sets TCL4 to 88H.
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User’s Manual U11377EJ3V0UD
Figure 18-2. Timer Clock Select Register 4 Format
Cautions 1. Set bit 0 to bit 2 to 0, and bit 3 to 1.
2. When rewriting TCL4 to other data, stop the serial transfer operation beforehand.
Remarks 1. fX: Main system clock oscillation frequency
2. MCS: Oscillation mode select register bit 0
3. Figures in parentheses apply to operation with fX = 5.0 MHz.
Symbol
TCL4
7
TCL47
6
TCL46
5
TCL45
4
TCL44
3
1
2
0
1
00
Address
FF44H
After Reset
88H
R/W
R/W
TCL47 TCL46 TCL45 TCL44
Selects Serial Clock of Serial Interface Channel 3
MCS = 1 MCS = 0
Setting prohibited f
X
/2
2
(1.25 MHz)
0110
f
X
/2
2
(1.25 MHz) f
X
/2
3
(625 kHz)
0111
f
X
/2
3
(625 kHz) f
X
/2
4
(313 kHz)
1000
f
X
/2
4
(313 kHz) f
X
/2
5
(156 kHz)
1001
f
X
/2
5
(156 kHz) f
X
/2
6
(78.1 kHz)
1010
f
X
/2
6
(78.1 kHz) f
X
/2
7
(39.1 kHz)
1011
f
X
/2
7
(39.1 kHz) f
X
/2
8
(19.5 kHz)
1100
f
X
/2
8
(19.5 kHz) f
X
/2
9
(9.8 kHz)
1101
Other than above Setting prohibited
0
395
CHAPTER 18 SERIAL INTERFACE CHANNEL 3
User’s Manual U11377EJ3V0UD
(2) Serial operating mode register 3 (CSIM3)
This register sets the serial clock of serial interface channel 3, and enables or disables the operation of the
interface channel.
CSIM3 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM3 to 00H.
Figure 18-3. Serial Operating Mode Register 3 Format
Notes 1. Be sure to clear bit 5 to 0.
2. These pins can be used freely as port pins.
3. This pin can be used as P110 (CMOS I/O) when only transmitting data.
Caution Port 11 has a function to detect the falling edge. To use the SI3/P110, SO3/P111, and SCK3/
P112 pins as the I/O pins of serial interface channel 3, the falling edge detection function
must be disabled by using the key return mode register (KRM). For details, refer to Figure
6-21 Key Return Mode Register Format.
Remark ×: don’t care
PM××: Port mode register
P××: Port output latch
SCK3 (Input)
Enables
operation
Controls Operation
of Serial Interface
Channel 3
Controls Operation
of Serial Clock
Counter
SI3/P110
Pin Functions
SO3/P111
Pin Functions
SCK3/P112
Pin Functions
Count
operation
SI3
Note 3
(Input)
SO3
(CMOS output)
SCK3
(CMOS output)
Clear
Stops
operation
P110
(CMOS I/O)
P111
(CMOS I/O)
P112
(CMOS I/O)
DIR3
0
1
First Bit
MSB
LSB
0
CSIE3
0
1
CSIM
31
PM110
P110
PM111
P111
PM112
P112
×
11×00
1×
1
Note 3 Note 3
65432107
Symbol
CSIM3 CSIE3 DIR3 0 0 0
CSIM31 CSIM30
FF6CH 00H R/W
Address After Reset R/W
0
Note 1
×
Note 2
×
Note 2
×
Note 2
×
Note 2
×
Note 2
×
Note 2
0
CSIM31
0
1
Selects Clock of Serial Interface Channel 3
Clock specified with bits 0 to 3 of timer clock select register 4 (TCL4)
Other than above
Setting prohibited
CSIM30
×
1
SI3/P110 Pin Functions
SI3
Note 3
(input)
SO3/P111 Pin Functions
SO3 (CMOS output)
Input clock to SCK3 pin from off-chip
396
CHAPTER 18 SERIAL INTERFACE CHANNEL 3
User’s Manual U11377EJ3V0UD
18.4 Serial Interface Channel 3 Operation
The operating mode of serial interface channel 3 has the following two types.
• Operation stop mode
• 3-wire serial I/O mode
18.4.1 Operation stop mode
In the operation stop mode, serial transfer is not performed, and therefore current consumption can be reduced.
In addition, serial I/O shift register 3 (SIO3) does not perform the shift operation, and therefore, this register can
be used as an ordinary 8-bit register.
In the operation stop mode, the P110/SI3, P111/SO3, and P112/SCK3 pins can be used as normal I/O ports.
(1) Register setting
Operation stop mode settings are performed using serial operating mode register 3 (CSIM3).
CSIM3 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM3 to 00H.
Notes 1. Be sure to clear bit 5 to 0.
2. These pins can be used freely as port pins.
3. This pin can be used as P110 (CMOS I/O) when only transmitting data.
Caution Port 11 has a function to detect the falling edge. To use the SI3/P110, SO3/P111, and SCK3/
P112 pins as the I/O pins of serial interface channel 3, the falling edge detection function
must be disabled by using the key return mode register (KRM). For details, refer to Figure
6-21 Key Return Mode Register Format.
Remark ×: don’t care
PM××: Port mode register
P××: Port output latch
SCK3 (Input)
Enables
operation
Controls Operation
of Serial Interface
Channel 3
Controls Operation
of Serial Clock
Counter
SI3/P110
Pin Functions
SO3/P111
Pin Functions
SCK3/P112
Pin Functions
Count
operation
SI3Note 3
(Input)
SO3
(CMOS output)
SCK3
(CMOS output)
Clear
Stops
operation
P110
(CMOS I/O)
P111
(CMOS I/O)
P112
(CMOS I/O)
0
CSIE3
0
1
CSIM
31
PM110
P110
PM111
P111
PM112
P112
×
11×00
1×
1
Note 3 Note 3
65432107
Symbol
CSIM3 CSIE3 DIR3 0 0 0
CSIM31 CSIM30
FF6CH 00H R/W
Address After Reset R/W
0
Note 1
×
Note 2
×
Note 2
×
Note 2
×
Note 2
×
Note 2
×
Note 2
0
397
CHAPTER 18 SERIAL INTERFACE CHANNEL 3
User’s Manual U11377EJ3V0UD
18.4.2 3-wire serial I/O mode
The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate
a conventional synchronous clocked serial interface, such as the 75X/XL Series, 78K Series, and 17K Series, etc.
In this mode, communication is performed by using three lines: serial clock (SCK3), serial output (SO3), and serial
input (SI3).
(1) Register setting
The 3-wire serial I/O mode is set by using serial operating mode register 3 (CSIM3).
CSIM3 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM3 to 00H.
Notes 1. Be sure to clear bit 5 to 0.
2. These pins can be used freely as port pins.
3. This pin can be used as P110 (CMOS I/O) when only transmitting data.
Caution Port 11 has a function to detect the falling edge. To use the SI3/P110, SO3/P111, and SCK3/
P112 pins as the I/O pins of serial interface channel 3, the falling edge detection function
must be disabled by using the key return mode register (KRM). For details, refer to Figure
6-21 Key Return Mode Register Format.
Remark ×: don’t care
PM××: Port mode register
P××: Port output latch
SCK3 (Input)
Enables
operation
Controls Operation
of Serial Interface
Channel 3
Controls Operation
of Serial Clock
Counter
SI3/P110
Pin Functions
SO3/P111
Pin Functions
SCK3/P112
Pin Functions
Count
operation
SI3
Note 3
(Input)
SO3
(CMOS output)
SCK3
(CMOS output)
Clear
Stops
operation
P110
(CMOS I/O)
P111
(CMOS I/O)
P112
(CMOS I/O)
DIR3
0
1
First Bit
MSB
LSB
0
CSIE3
0
1
CSIM
31
PM110
P110
PM111
P111
PM112
P112
×
11×00
1×
1
Note 3 Note 3
65432107
Symbol
CSIM3 CSIE3 DIR3 0 0 0 CSIM31 CSIM30 FF6CH 00H R/W
Address After Reset R/W
0
Note 1
×
Note 2
×
Note 2
×
Note 2
×
Note 2
×
Note 2
×
Note 2
0
CSIM31
0
1
Selects Clock of Serial Interface Channel 3
Clock specified with bits 0 to 3 of timer clock select register 4 (TCL4)
Other than above
Setting prohibited
CSIM30
×
1
SI3/P110 Pin Functions
SI3
Note 3
(Input)
SO3/P111 Pin Functions
SO3 (CMOS output)
Input clock to SCK3 pin from off-chip
398
CHAPTER 18 SERIAL INTERFACE CHANNEL 3
User’s Manual U11377EJ3V0UD
(2) Communication operation
In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Each bit of data is
transmitted or received in synchronization with the serial clock.
Serial I/O shift register 3 (SIO3) performs its shift operation in synchronization with the falling edge of the serial
clock (SCK3). The transmit data is held in the SO3 latch, and output from the SO3 pin. Also, receive data
input to the SI3 pin is latched to SIO3 at the rising edge of SCK3.
At the end of an 8-bit transfer, the operation of the SIO3 stops automatically, and the interrupt request flag
(CSIIF3) is set.
Figure 18-4. 3-Wire Serial I/O Mode Timing
Caution Do not set 0 to CSIE3 during serial transfer; otherwise, an undefined value will be output.
SI3
SCK3 12345678
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SO3 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
CSIIF3
Transfer start at the falling edge of SCK3
End of transfer
Writing to SIO3
399
CHAPTER 18 SERIAL INTERFACE CHANNEL 3
User’s Manual U11377EJ3V0UD
(3) MSB/LSB switching as the start bit
The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB.
Figure 18-5 shows the configuration of serial I/O shift register 3 (SIO3) and internal bus. As shown in the figure,
MSB/LSB can be read/written in reverse form.
MSB/LSB switching as the start bit can be specified with bit 2 (CSIM32) of serial operating mode register 3
(CSIM3).
Figure 18-5. Circuit of Switching in Transfer Bit Order
Start bit switching is realized by switching the bit order for data write to SIO3. The SIO3 shift order remains
unchanged.
Thus, switching between MSB-first and LSB-first must be performed before writing data to the shift register.
(4) Transfer start
Serial transfer is started by setting transfer data to serial I/O shift register 3 (SIO3) when the following two
conditions are satisfied.
•Serial interface channel 3 operation control bit (CSIE3) = 1
•Internal serial clock is stopped or SCK3 is at high level after 8-bit serial transfer.
Caution If CSIE3 is set to "1" after data write to SIO3, transfer does not start.
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIE3)
is set.
7
6
Internal bus
1
0
LSB-first
MSB-first Read/write gate
SI3 Serial I/O shift register 3 (SIO3)
Read/write gate
SO3
SCK3
DQ
SO3 latch
400 User’s Manual U11377EJ3V0UD
CHAPTER 19 LCD CONTROLLER/DRIVER
19.1 LCD Controller/Driver Functions
The functions of the LCD controller/driver incorporated in the
µ
PD780308, 780308Y Subseries are shown below.
(1) Automatic output of segment signals and common signals is possible by automatic reading of the display
data memory.
(2) Any of five display modes can be selected.
• Static
• 1/2 duty (1/2 bias)
• 1/3 duty (1/2 bias)
• 1/3 duty (1/3 bias)
• 1/4 duty (1/3 bias)
(3) Any of four frame frequencies can be selected in each display mode.
(4) Maximum of 40 segment signal outputs (S0 to S39); 4 common signal outputs (COM0 to COM3).
Sixteen of the segment signal outputs can be switched to I/O ports in units of 2 (P80/S39 to P87/S32, P90/
S31 to P97/S24).
(5) In mask ROM versions, split resistors for LCD drive voltage generation can be incorporated by mask option.
(6) Operation on the subsystem clock is also possible.
The maximum number of displayable pixels in each display mode is shown in Table 19-1.
Table 19-1. Maximum Number of Display Pixels
Bias Method Time Division
Common Signals Used
Maximum Number of Pixels Note
— Static COM0 (COM1, 2, 3) 40 (40 segments × 1 common) 1
1/2 2 COM0, COM1 80 (40 segments × 2 commons) 2
3 COM0 to COM2 120 (40 segments × 3 commons) 3
1/3 3
4 COM0 to COM3 160 (40 segments × 4 commons) 4
Notes 1. 5 digits on type LCD panel with 8 segments/digit.
2. 10 digits on type LCD panel with 4 segments/digit.
3. 13 digits on type LCD panel with 3 segments/digit.
4. 20 digits on type LCD panel with 2 segments/digit.
401
CHAPTER 19 LCD CONTROLLER/DRIVER
User’s Manual U11377EJ3V0UD
19.2 LCD Controller/Driver Configuration
The LCD controller/driver consists of the following hardware.
Table 19-2. LCD Controller/Driver Configuration
Item Configuration
Display outputs Segment signals: 40 Dedicated segment signals: 24
Segment signal/I/O port dual function: 16
Common signals: 4 (COM0 to COM3)
Control registers LCD display mode register (LCDM)
LCD display control register (LCDC)
Figure 19-1. LCD Controller/Driver Block Diagram
Note Segment driver
FA58H
7 6 5 4 3 2 1 0
FA67H
7 6 5 4 3 2 1 0
FA68H
7 6 5 4 3 2 1 0
FA7FH
7 6 5 4 3 2 1 0
3 2 1 0
Selector
3 2 1 0
Selector
3 2 1 0
Selector
3 2 1 0
Selector
... ... ... ... ... ...
Note Note Note Note
S23S0
... ... ... ... ... ...
... ... ... ... ... ... ... ...
S24/P97
P80 output
buffer
P97 output
buffer
S39/P80
LCD drive
mode selector
LCDM3
COM0 COM3COM1 COM2 V
LC2
BIASV
LC1
V
LC0
LDON
LCDM6 LCDM5 LCDM4 LCDM3 LCDM2 LCDM1 LCDM0
f
LCD
3 3
LCDC6 LCDC5 LCDC4
LEPS
LIPS
4 2
... ... ... ... ... ... ... ...
LCDC7
Internal bus
Display data memory LCD display mode register LCD display control register
LCD clock selector
Timing controller
Segment selector
Common driver
LCD drive voltage controller
402
CHAPTER 19 LCD CONTROLLER/DRIVER
User’s Manual U11377EJ3V0UD
Figure 19-2. LCD Clock Selector Block Diagram
Remarks 1. The watch timer includes the circuit enclosed with the dotted line.
2. LCDCL: LCD clock
3. fLCD: LCD clock frequency
4. fXX = fX/2 (MCS = 0), fXX = fX (MCS = 1)
fXX/28
fXT
fW
Clear
Prescaler
fW/26
Prescaler
fLCD/23
fLCD/22
fLCD/2
fLCD
TCL24 TMC21
LCDM6 LCDM5 LCDM4
3
LCDCL
LCD display
mode register
Watch timer mode
control register
Timer clock
select register 2
Internal bus
Selector
Selector
403
CHAPTER 19 LCD CONTROLLER/DRIVER
User’s Manual U11377EJ3V0UD
19.3 LCD Controller/Driver Control Registers
The LCD controller/driver is controlled by the following two registers.
• LCD display mode register (LCDM)
• LCD display control register (LCDC)
(1) LCD display mode register (LCDM)
This register sets display operation enabling/disabling, the LCD clock, frame frequency, display mode, and
operating mode.
LCDM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears LCDM to 00H.
404
CHAPTER 19 LCD CONTROLLER/DRIVER
User’s Manual U11377EJ3V0UD
Figure 19-3. LCD Display Mode Register Format
Notes 1. The LCD clock is supplied from the watch timer. When LCD display is performed, 1 should be set
in bit 1 (TMC21) of the watch timer mode control register (TMC2).
2. To reduce the power consumption, clear LCDM3 to 0 when LCD display is not performed. Before
manipulating LCDM3, be sure to turn off the LCD display.
If TMC21 is cleared to 0 during LCD display, the LCD clock supply will be stopped and the display
will be disrupted.
Remarks 1. fW: Watch timer clock frequency (fXX/27 or fXT)
2. fXX: Main system clock frequency (fX or fX/2)
3. fX: Main system clock oscillation frequency
4. fXT: Subsystem clock oscillation frequency
Symbol
LCDM LDON
6
LCDM6
5
LCDM5
4
LCDM4
3
LCDM3
2
LCDM2
1
LCDM1
0
LCDM0
Address
FFB0H
After Reset
00H
R/W
R/W
7
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
LCDM2 LCDM1 LCDM0
Time Division
4
3
2
3
Static display mode
Setting prohibited
Bias Mode
1/3
1/3
1/2
1/2
Selects Display Mode of LCD Controller/Driver
0
1
LCDM3
Low-voltage operation
Normal operation
1/3 Bias Mode
2.5 to 5.5 V
1/2 Bias Mode
2.7 to 5.5 V
Static Display Mode
2.0 to 5.5 V
2.0 to 3.4 V
Operating Mode of
LCD Controller/Driver
0
0
0
0
0
0
1
1
0
1
0
1
LCDM6 LCDM5 LCDM4
Setting prohibited
f
W
/2
9
(76 Hz)
f
W
/2
8
(153 Hz)
f
W
/2
7
(305 Hz)
f
W
/2
6
(610 Hz)
f
XX
= 4.19 MHz
f
W
/2
8
(128 Hz)
f
W
/2
7
(256 Hz)
f
W
/2
9
(64 Hz)
f
W
/2
6
(512 Hz)
f
XT
= 32.768 kHz
f
W
/2
8
(128 Hz)
f
W
/2
7
(256 Hz)
f
W
/2
9
(64 Hz)
f
W
/2
6
(512 Hz)
Selects LCD Clock
Note 1
0
1
LDON Enables/Disables LCD Display
Display ON
Display OFF (all segment outputs are unselect signals)
Other than above
f
XX
= 5.0 MHz
Other than above
Note 2
Supply Voltage of LCD Controller/Driver
405
CHAPTER 19 LCD CONTROLLER/DRIVER
User’s Manual U11377EJ3V0UD
Table 19-3. Frame Frequencies (Hz)
LCDCL fW/29fW/28fW/27fW/26
Duty (64 Hz) (128 Hz) (256 Hz) (512 Hz)
Static 64 128 256 512
1/2 32 64 128 256
1/3 21 43 85 171
1/4 16 32 64 128
Remarks 1. Figures in parentheses apply to operation with fXX = 4.19 MHz or fXT = 32.768 kHz.
2. fW: Watch timer clock frequency (fXX/27 or fXT)
3. fXX: Main system clock frequency (fX or fX/2)
4. fX: Main system clock oscillation frequency
5. fXT: Subsystem clock oscillation frequency
406
CHAPTER 19 LCD CONTROLLER/DRIVER
User’s Manual U11377EJ3V0UD
(2) LCD display control register (LCDC)
This register sets cutoff of the current flowing to split resistors for LCD drive voltage generation and
switchover between segment output and I/O port functions.
LCDC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears LCDC to 00H.
Figure 19-4. LCD Display Control Register Format
Cautions 1. Pins which perform segment output cannot be used as output port pins even if 0 is set in
the port mode register.
2. If a pin which performs segment output is read as a port, its value will be 0.
3. Pins set as segment outputs by LCDC cannot have an internal pull-up resistor used
regardless of the value of bits 0 and 1 (PUO8 and PUO9) of pull-up resistor option register
H.
Symbol
LCDC
7
LCDC7
6
LCDC6
5
LCDC5
4
LCDC4
3
0
2
0
1
LEPS LIPS
Address
FFB2H
After Reset
00H
R/W
R/W
LEPS LIPS LCD Driving Power Supply Selection
0 0 Does not supply power to LCD.
0 1 Supplies power to LCD from V
DD
pin.
1 0 Supplies power to LCD from BIAS pin. (Shorts BIAS and V
LC0
pins internally.)
1 1 Setting prohibited
LCDC7 LCDC6 LCDC5 LCDC4
P80/S39 to P97/S24 Pin Functions
Port Pins Segment Pins
P80 to P97 None
0000
P80 to P95 S24, S25
0001
P80 to P93 S24 to S27
0010
P80 to P91 S24 to S29
0011
P80 to P87 S24 to S31
0100
P80 to P85 S24 to S33
0101
P80 to P83 S24 to S35
0110
P80 to P81 S24 to S37
0111
None S24 to S39
1000
Other than above Setting prohibited
0
407
CHAPTER 19 LCD CONTROLLER/DRIVER
User’s Manual U11377EJ3V0UD
19.4 LCD Controller/Driver Settings
LCD controller/driver settings should be performed as shown below. When the LCD controller/driver is used,
the watch timer should be set to the operational state beforehand.
<1> Set “watch operation enabled” in timer clock select register 2 (TCL2) and the watch timer mode control
register (TMC2).
<2> Set the initial value in the display data memory (FA58H to FA7FH).
<3> Set the pins to be used as segment outputs in the LCD display control register (LCDC).
<4> Set the display mode, operating mode, and the LCD clock in the LCD display mode register (LCDM).
Next, set data in the display data memory according to the display contents.
408
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19.5 LCD Display Data Memory
The LCD display data memory is mapped onto addresses FA58H to FA7FH. The data stored in the LCD display
data memory can be displayed on an LCD panel by the LCD controller/driver.
Figure 19-5 shows the relationship between the LCD display data memory contents and the segment outputs/
common outputs.
Any area not used for display can be used as normal RAM.
Figure 19-5. Relationship Between LCD Display Data Memory
Contents and Segment/Common Outputs
Caution The higher 4 bits of the LCD display data memory do not incorporate memory. Be sure to
set them to 0.
S0FA7FH
S1FA7EH
S2FA7DH
S3FA7CH
S37/P82FA5AH
S38/P81FA59H
S39/P80FA58H
COM3 COM2 COM1 COM0
b7b6b5b4b3b2b1b0
Address
409
CHAPTER 19 LCD CONTROLLER/DRIVER
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19.6 Common Signals and Segment Signals
An individual pixel on an LCD panel lights when the potential difference of the corresponding common signal
and segment signal reaches or exceeds a given voltage (the LCD drive voltage VLCD).
As an LCD panel deteriorates if a DC voltage is applied in the common signals and segment signals, it is driven
by AC voltage.
(1) Common signals
For common signals, the selection timing order is as shown in Table 19-4 according to the number of time
divisions set, and operations are repeated with these as the cycle. In the static display mode, the same
signal is output to COM0 to COM3.
With 2-time-division operation, pins COM2 and COM3 are left open, and with 3-time-division operation, the
COM3 pin is left open.
Table 19-4. COM Signals
(2) Segment signals
Segment signals correspond to a 40-byte LCD display data memory (FA58H to FA7FH). Each display data
memory bit 0, bit 1, bit 2, and bit 3 is read in synchronization with the COM0, COM1, COM2 and COM3 timings
respectively, and if the value of the bit is 1, it is converted to the selection voltage. If the value of the bit
is 0, it is converted to the non-selection voltage and output to a segment pin (S0 to S39) (S24 to S39 have
a dual function as I/O port pins).
Consequently, it is necessary to check what combination of front surface electrodes (corresponding to the
segment signals) and rear surface electrodes (corresponding to the common signals) of the LCD display
to be used form the display pattern, and then write bit data corresponding on a one-to-one basis with the
pattern to be displayed.
In addition, because LCD display data memory bits 1 and 2 are not used with the static display mode, bits
2 and 3 are not used with the 2-time-division method, and bit 3 is not used with the 3-time-division method,
these can be used for other than display purposes.
Bits 4 to 7 are fixed at 0.
COM signal
Time division
Static
2-time division
3-time division
4-time division
Open Open
Open
COM0 COM1 COM2 COM3
410
CHAPTER 19 LCD CONTROLLER/DRIVER
User’s Manual U11377EJ3V0UD
(3) Common signal and segment signal output waveforms
The voltages shown in Table 19-5 are output in the common signals and segment signals.
The ±VLCD ON voltage is only produced when the common signal and segment signal are both at the selection
voltage; other combinations produce the OFF voltage.
Table 19-5. LCD Drive Voltages
(a) Static display mode
Segment Select Non-select
Common VSS1, VLC0 VLC0, VSS1
VLC0, VSS1 –VLCD, +VLCD 0 V, 0 V
(b) 1/2 bias method
Segment Select Non-select
Common VSS1, VLC0 VLC0, VSS1
Select level VLC0, VSS1 –VLCD, +VLCD 0 V, 0 V
Non-select level VLC1 = VLC2 –1/2VLCD, +1/2VLCD +1/2VLCD, –1/2VLCD
(c) 1/3 bias method
Segment Select Non-select
Common VSS1, VLC0 VLC1, VLC2
Select level VLC0, VSS1 –VLCD, +VLCD –1/3VLCD, +1/3VLCD
Non-select level VLC2, VLC1 –1/3VLCD, +1/3VLCD –1/3VLCD, +1/3VLCD
411
CHAPTER 19 LCD CONTROLLER/DRIVER
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Figure 19-6 shows the common signal waveform, and Figure 19-7 shows the common signal and segment signal
voltages and phases.
Figure 19-6. Common Signal Waveform
(a) Static display mode
Remarks 1. T: One LCDCL cycle
2. TF: Frame frequency
(b) 1/2 bias method
Remarks 1. T: One LCDCL cycle
2. TF: Frame frequency
(c) 1/3 bias method
Remarks 1. T: One LCDCL cycle
2. TF: Frame frequency
COMn
(Static)
T
F
= T
V
LC0
V
SS1
V
LCD
COMn
(Divided by 2)
T
F
= 2 × T
V
LC0
V
SS1
V
LCD
V
LC2
COMn
(Divided by 3)
T
F
= 3 × T
V
LC0
V
SS1
V
LCD
V
LC2
COMn
(Divided by 3)
TF = 3 × T
VLC0
VSS1
VLCD
VLC1
VLC2
TF= 4 × T
COMn
(Divided by 4)
VLC0
VSS1
VLCD
VLC1
VLC2
412
CHAPTER 19 LCD CONTROLLER/DRIVER
User’s Manual U11377EJ3V0UD
Figure 19-7. Common Signal and Static Signal Voltages and Phases
(a) Static display mode
Remark T: One LCDCL cycle
(b) 1/2 bias method
Remark T: One LCDCL cycle
(c) 1/3 bias method
Remark T: One LCDCL cycle
Selected Not selected
Common signal
Segment signal
V
LC0
V
SS1
V
LCD
V
LC0
V
SS1
V
LCD
TT
Selected Not selected
Common signal
Segment signal
V
LC0
V
SS1
V
LCD
V
LC0
V
SS1
V
LCD
TT
V
LC2
V
LC2
Selected Not selected
Common signal
Segment signal
VLC0
VSS1
VLCD
VLC0
VSS1
VLCD
TT
VLC2
VLC2
VLC1
VLC1
413
CHAPTER 19 LCD CONTROLLER/DRIVER
User’s Manual U11377EJ3V0UD
19.7 Supply of LCD Drive Voltages VLC0, VLC1, VLC2
Split resistors for producing the LCD drive voltages can be incorporated in the mask ROM versions (
µ
PD780306,
780308, 780306Y, and 780308Y) by mask option (the PROM versions (
µ
PD78P0308, 78P0308Y) do not incorporate
split resistors). Incorporating the split resistors makes it possible to produce LCD drive voltages appropriate to the
various bias methods shown in Table 19-6 without using external split resistors.
Also, an LCD drive voltage can be externally supplied from the BIAS pin to produce other LCD drive voltages.
Table 19-6. LCD Drive Voltages (with On-Chip Split Resistor)
Bias Method No Bias 1/2 1/3
LCD (Static Mode) Bias Bias
Drive Voltage
VLC0 VLCD VLCD VLCD
VLC1 2/3 VLCD 1/2 VLCDNote 2/3 VLCD
VLC2 1/3 VLCD 1/3 VLCD
Note With the 1/2 bias method, the VLC1 pin and VLC2 pin must be connected
externally.
Remarks 1. When the BIAS pin and VLC0 pin are open, VLCD = 3/5 VDD (with on-
chip split resistor).
2. When the BIAS pin and VLC0 pin are connected, VLCD = VDD1.
Examples of internal supply of the LCD drive voltage in accordance with Table 19-6 are shown in Figures 19-
8 and 19-9. An example of supply of the LCD drive voltage from off-chip is shown in Figure 19-10. Stepless LCD
drive voltages can be supplied by means of variable resistor r.
414
CHAPTER 19 LCD CONTROLLER/DRIVER
User’s Manual U11377EJ3V0UD
Figure 19-8. LCD Drive Power Supply Connection Examples (with On-Chip Split Resistor)
(a) 1/3 bias method and static display mode (b) 1/2 bias method mode
(Example with VDD1 = 5 V, VLCD = 3 V) (Example with VDD1 = 5 V, VLCD = 5 V)
(c) 1/3 bias method and static display mode
(Example with VDD1 = 5 V, VLCD = 5 V)
2R
LEPS
(= 0)
LIPS
V
DD1
BIAS pin
R
R
R
V
LC0
V
LC1
V
LC2
V
SS1
V
LCD
V
LCD
= 3/5V
DD1
P-ch
P-ch
V
SS1
2R
LEPS
(= 0)
LIPS
V
DD1
BIAS pin
R
R
R
V
LC0
V
LC1
V
LC2
V
SS1
V
LCD
V
LCD
= V
DD1
P-ch
P-ch
V
SS1
P-ch
2R
LEPS
(= 0)
LIPS
V
DD1
BIAS pin
R
R
R
V
LC0
V
LC1
V
LC2
V
SS1
V
LCD
V
LCD
= V
DD1
P-ch
V
SS1
415
CHAPTER 19 LCD CONTROLLER/DRIVER
User’s Manual U11377EJ3V0UD
Figure 19-9. LCD Drive Power Supply Connection Examples (with External Split Resistor)
(a) Static display modeNote (b) Static display mode
(Example with VDD1 = 5 V, VLCD = 5 V) (Example with VDD1 = 5 V, VLCD = 3 V)
Note LIPS should always be set to 1 (including in standby mode).
(c) 1/2 bias method (d) 1/3 bias method
(Example with VDD1 = 5 V, VLCD = 3 V) (Example with VDD1 = 5 V, VLCD = 3 V)
P-ch
LEPS
(= 0)
LIPS
V
DD1
BIAS pin
V
LC0
V
LC1
V
LC2
V
SS1
V
LCD
V
LCD
= 3/5V
DD1
P-ch 2R
3R
V
SS1
P-ch
LEPS
(= 0)
LIPS
V
DD1
BIAS pin
V
LC0
V
LC1
V
LC2
V
SS1
V
LCD
V
LCD
= 3/5V
DD1
P-ch 4R
3R
3R
V
SS1
P-ch
LEPS
(= 0)
LIPS
VDD1
BIAS pin
VLC0
VLC1
VLC2
VSS1
VLCD
VLCD = 3/5VDD1
P-ch 2R
R
R
R
VSS1
P-ch
LEPS
(= 0)
LIPS
VDD1
BIAS pin
VLC0
VLC1
VLC2
VSS1
VLCD
VLCD = VDD1
P-ch
VSS1
416
CHAPTER 19 LCD CONTROLLER/DRIVER
User’s Manual U11377EJ3V0UD
Figure 19-10. Example of LCD Drive Voltage Supply from Off-Chip
P-ch
LEPS
LIPS
(= 0)
VDD1
BIAS pin
R
R
R
VLC0
VLC1
VLC2
VSS1
VLCD
VLCD =VDD1
P-ch
VDD1
3R + r
3R
r
VSS1
417
CHAPTER 19 LCD CONTROLLER/DRIVER
User’s Manual U11377EJ3V0UD
19.8 Display Modes
19.8.1 Static display example
Figure 19-12 shows the connection of a static type 5-digit LCD panel with the display pattern shown in Figure
19-11 with the
µ
PD780308, 780308Y Subseries segment (S0 to S39) and common (COM0) signals. The display
example is “123.45,” and the display data memory contents (addresses FA58H to FA7FH) correspond to this.
An explanation is given here taking the example of the third digit “3.” ( ). In accordance with the display pattern
in Figure 19-11, selection and non-selection voltages must be output to pins S16 to S23 as shown in Table 19-7
at the COM0 common signal timing.
Table 19-7. Selection and Non-Selection Voltages (COM0)
Segment S16 S17 S18 S19 S20 S21 S22 S23
Common
COM0 SSSSNSSNSS
S: Selection, NS: Non-selection
From this, it can be seen that 10101111 must be prepared in bit 0 of the display data memory (addresses FA68H
to FA6FH) corresponding to S16 to S23.
The LCD drive waveforms for S19, S20, and COM0 are shown in Figure 19-13. When S19 is at the selection
voltage at the timing for selection with COM0, it can be seen that the +VLCD/–VLCD AC square wave, which is the
LCD illumination (ON) level, is generated.
Shorting the COM0 to COM3 lines increases the current drive capability because the same waveform as COM0
is output to COM1 to COM3.
Figure 19-11. Static LCD Display Pattern and Electrode Connections
n = 0 to 4
S8n + 3
S8n + 2
S8n + 5
S8n + 1
S8n
S8n + 4
S8n + 6
S8n + 7
COM0
418
CHAPTER 19 LCD CONTROLLER/DRIVER
User’s Manual U11377EJ3V0UD
Figure 19-12. Static LCD Panel Connection Example
Timing strobes
COM3
COM2
COM1
COM0
BIT0
BIT1
BIT2
BIT3
S0
S1
S2
S3
0
×
FA7FH
1
E
0
D
1
CS4
S5
S6
S7
1
B
1
A
0
9
1
8S8
S9
S10
S11
0
7
1
6
1
5
0
4S12
S13
S14
S15
1
3
1
2
0
1
0
0S16
S17
S18
S19
1
FA6FH
1
E
1
D
1
CS20
S21
S22
S23
0
B
1
A
0
9
1
8S24
S25
S26
S27
0
7
0
6
1
5
1
4S28
S29
S30
S31
0
3
0
2
1
1
1
0S32
S33
S34
S35
0
FA5FH
1
E
1
D
0
CS36
S37
S38
S39
0
B
0
A
0
9
0
FA58H
Can be shorted.
Data memory addresses
LCD panel
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
419
CHAPTER 19 LCD CONTROLLER/DRIVER
User’s Manual U11377EJ3V0UD
Figure 19-13. Static LCD Drive Waveform Examples
T
F
V
LC0
V
SS1
COM0
V
LC0
V
SS1
S19
V
LC0
V
SS1
S20
+V
LCD
0
COM0 to S20
–V
LCD
+V
LCD
0
COM0 to S19
–V
LCD
420
CHAPTER 19 LCD CONTROLLER/DRIVER
User’s Manual U11377EJ3V0UD
19.8.2 2-time-division display example
Figure 19-15 shows the connection of a 2-time-division type 10-digit LCD panel with the display pattern shown
in Figure 19-14 with the
µ
PD780308, 780308Y Subseries segment signals (S0 to S39) and common signals (COM0,
COM1). The display example is “123456.7890,” and the display data memory contents (addresses FA58H to
FA7FH) correspond to this.
An explanation is given here taking the example of the eighth digit “3” ( ). In accordance with the display pattern
in Figure 19-14, selection and non-selection voltages must be output to pins S28 to S31 as shown in Table 19-8
at the COM0 and COM1 common signal timings.
Table 19-8. Selection and Non-Selection Voltages (COM0, COM1)
Segment S28 S29 S30 S31
Common
COM0 S S NS NS
COM1 NS S S S
S: Selection, NS: Non-selection
From this, it can be seen that, for example, ××10 must be prepared in the display data memory (address FA60H)
corresponding to S31.
Examples of the LCD drive waveforms between S31 and the common signals are shown in Figure 19-16. When
S31 is at the selection voltage at the COM1 selection timing, it can be seen that the +VLCD/–VLCD AC square wave,
which is the LCD illumination (ON) level, is generated.
Figure 19-14. 2-Time-Division LCD Display Pattern and Electrode Connections
n = 0 to 9
;;
;;
;
;;
;;;
;;
;;
;;;
;;
;;
S
4n + 2
S
4n + 3
S
4n + 1
S
4n
COM0
COM1
421
CHAPTER 19 LCD CONTROLLER/DRIVER
User’s Manual U11377EJ3V0UD
Figure 19-15. 2-Time-Division LCD Panel Connection Example
Remark ×: Any data can be stored because this is a 2-time-division display.
Timing strobes
COM3
COM2
COM1
COM0
BIT0
BIT1
BIT2
BIT3
S0
S1
S2
S3
1
FA7FH
1
E
1
D
1
CS4
S5
S6
S7
1
B
1
A
1
9
0
8S8
S9
S10
S11
1
7
1
6
1
5
1
4S12
S13
S14
S15
1
3
1
2
1
1
0
0S16
S17
S18
S19
1
FA6FH
0
E
1
D
1
CS20
S21
S22
S23
1
B
0
A
1
9
0
8S24
S25
S26
S27
1
7
1
6
1
5
0
4S28
S29
S30
S31
1
3
1
2
0
1
0
0S32
S33
S34
S35
0
FA5FH
1
E
0
D
1
CS36
S37
S38
S39
1
B
1
A
0
9
0
FA58H
Open
Data memory addresses
LCD panel
Open
0011011001110010111101110100011101110000
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
422
CHAPTER 19 LCD CONTROLLER/DRIVER
User’s Manual U11377EJ3V0UD
Figure 19-16. 2-Time-Division LCD Drive Waveform Examples (1/2 Bias Method)
T
F
V
LC0
V
SS1
COM0
V
LC0
V
SS1
V
LC0
V
SS1
S31
+V
LCD
0COM1 to S31
–V
LCD
+V
LCD
0COM0 to S31
–V
LCD
V
LC1
(V
LC2
)
COM1
+1/2V
LCD
+1/2V
LCD
–1/2V
LCD
–1/2V
LCD
V
LC1
(V
LC2
)
V
LC1
(V
LC2
)
423
CHAPTER 19 LCD CONTROLLER/DRIVER
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19.8.3 3-time-division display example
Figure 19-18 shows the connection of a 3-time-division type 13-digit LCD panel with the display pattern shown
in Figure 19-17 with the
µ
PD780308, 780308Y Subseries segment signals (S0 to S38) and common signals (COM0
to COM2). The display example is “123456.7890123,” and the display data memory contents (addresses FA59H
to FA7FH) correspond to this.
An explanation is given here taking the example of the eighth digit “6.” ( ). In accordance with the display pattern
in Figure 19-17, selection and non-selection voltages must be output to pins S21 to S23 as shown in Table 19-9
at the COM0 to COM2 common signal timings.
Table 19-9. Selection and Non-Selection Voltages (COM0 to COM2)
Segment S21 S22 S23
Common
COM0 NS S S
COM1 S S S
COM2 S S —
S: Selection, NS: Non-selection
From this, it can be seen that ×110 must be prepared in the display data memory (address FA6AH) corresponding
to S21.
Examples of the LCD drive waveforms between S21 and the common signals are shown in Figure 19-19 (1/2
bias method) and Figure 19-20 (1/3 bias method). When S21 is at the selection voltage at the COM1 selection
timing, and S21 is at the selection voltage at the COM2 selection timing, it can be seen that the +VLCD/–VLCD AC
square wave, which is the LCD illumination (ON) level, is generated.
Figure 19-17. 3-Time-Division LCD Display Pattern and Electrode Connections
n = 0 to 12
;
;
;
;
;
;;;
;;;
;;
;;
;;
;
;
;
S3n + 2 S3n
COM0
COM2
S3n + 1
COM1
424
CHAPTER 19 LCD CONTROLLER/DRIVER
User’s Manual U11377EJ3V0UD
Figure 19-18. 3-Time-Division LCD Panel Connection Example
Remarks 1. ×: Any data can be stored because they have no corresponding segment in the LCD panel.
2. ×: Any data can be stored because this is a 3-time-division display.
Timing strobes
COM3
COM2
COM1
COM0
BIT0
BIT1
BIT2
BIT3
S0
S1
S2
S3
1
0
FA7FH
1
1
E
0
D
1
0
C
S4
S5
S6
S7
1
1
B
0
A
1
0
9
0
0
8S8
S9
S10
S11
0
7
1
0
6
1
1
5
1
4S12
S13
S14
S15
1
0
3
1
0
2
1
1
1
0
0S16
S17
S18
S19
1
1
FA6FH
1
E
1
0
D
1
0
CS20
S21
S22
S23
1
B
0
1
A
1
1
9
1
8S24
S25
S26
S27
0
0
7
1
1
6
1
5
1
0
4S28
S29
S30
S31
0
0
3
1
2
1
0
1
1
1
0S32
S33
S34
S35
0
FA5FH
1
0
E
1
1
D
0
CS36
S37
S38
1
0
B
0
0
A
0
9
FA58H
Data memory addresses
LCD panel
Open
110011100101110111100111110110110011100
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×'
×'
×'×'×'×'
×'×'
×'×'
×'
×'×'
425
CHAPTER 19 LCD CONTROLLER/DRIVER
User’s Manual U11377EJ3V0UD
Figure 19-19. 3-Time-Division LCD Drive Waveform Examples (1/2 Bias Method)
TF
VLC0
VSS1
COM0
VLC0
VSS1
VLC0
VSS1
COM2
+VLCD
0COM1 to S21
–VLCD
+VLCD
0COM0 to S21
–VLCD
COM1
+1/2VLCD
+1/2VLCD
–1/2VLCD
–1/2VLCD
VLC0
VSS1
S21
+VLCD
0COM2 to S21
–VLCD
+1/2VLCD
–1/2VLCD
VLC1 (VLC2)
VLC1 (VLC2)
VLC1 (VLC2)
VLC1 (VLC2)
426
CHAPTER 19 LCD CONTROLLER/DRIVER
User’s Manual U11377EJ3V0UD
Figure 19-20. 3-Time-Division LCD Drive Waveform Examples (1/3 Bias Method)
VLC0
VLC2
COM0
+VLCD
0COM0 to S21
–VLCD
VLC1
+1/3VLCD
–1/3VLCD
VSS1
VLC0
VLC2
COM1 VLC1
VSS1
VLC0
VLC2
COM2 VLC1
VSS1
VLC0
VLC2
S21 VLC1
VSS1
+VLCD
0
COM1 to S21
–VLCD
+1/3VLCD
–1/3VLCD
+VLCD
0
COM2 to S21
–VLCD
+1/3VLCD
–1/3VLCD
TF
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CHAPTER 19 LCD CONTROLLER/DRIVER
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19.8.4 4-time-division display example
Figure 19-22 shows the connection of a 4-time-division type 20-digit LCD panel with the display pattern shown
in Figure 19-21 with the
µ
PD780308, 780308Y Subseries segment signals (S0 to S39) and common signals (COM0
to COM3). The display example is “123456.78901234567890,” and the display data memory contents (addresses
FA58H to FA7FH) correspond to this.
An explanation is given here taking the example of the 15th digit “6.” ( ). In accordance with the display pattern
in Figure 19-21, selection and non-selection voltages must be output to pins S28 and S29 as shown in Table 19-
10 at the COM0 to COM3 common signal timings.
Table 19-10. Selection and Non-Selection Voltages (COM0 to COM3)
Segment S28 S29
Common
COM0 S S
COM1 NS S
COM2 S S
COM3 S S
S: Selection, NS: Non-selection
From this, it can be seen that 1101 must be prepared in the display data memory (address FA63H) corresponding
to S28.
Examples of the LCD drive waveforms between S28 and the COM0 and COM1 signals are shown in Figure 19-
23 (for the sake of simplicity, waveforms for COM2 and COM3 have been omitted). When S28 is at the selection
voltage at the COM0 selection timing, it can be seen that the +VLCD/–VLCD AC square wave, which is the LCD
illumination (ON) level, is generated.
Figure 19-21. 4-Time-Division LCD Display Pattern and Electrode Connections
n = 0 to 18
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
COM0
S2n
COM1
S2n + 1
COM2
COM3
428
CHAPTER 19 LCD CONTROLLER/DRIVER
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Figure 19-22. 4-Time-Division LCD Panel Connection Example
Timing strobes
COM3
COM2
COM1
COM0
BIT0
BIT1
BIT2
BIT3
S0
S1
S2
S3
1
1
0
FA7FH
1
1
1
E
1
1
0
D
1
0
0
CS4
S5
S6
S7
1
1
0
B
1
1
1
A
1
1
0
9
1
0
0
8S8
S9
S10
S11
1
1
0
7
1
1
1
6
1
1
0
5
1
0
1
4S12
S13
S14
S15
0
1
0
3
1
0
0
2
1
1
0
1
0
0
1
0S16
S17
S18
S19
1
0
0
FA6FH
0
1
1
E
0
1
0
D
0
0
0
CS20
S21
S22
S23
1
1
0
B
1
1
1
A
1
1
0
9
1
0
0
8S24
S25
S26
S27
1
1
0
7
1
1
1
6
1
1
0
5
1
0
0
4S28
S29
S30
S31
1
1
1
3
1
1
1
2
1
1
0
1
1
0
1
0S32
S33
S34
S35
0
1
0
FA5FH
1
0
0
E
1
1
0
D
0
0
1
CS36
S37
S38
S39
1
0
0
B
0
1
1
A
0
1
0
9
0
0
0
FA58H
Data memory addresses
LCD panel
1011111001011111111010111110010111111110
429
CHAPTER 19 LCD CONTROLLER/DRIVER
User’s Manual U11377EJ3V0UD
Figure 19-23. 4-Time-Division LCD Drive Waveform Examples (1/3 Bias Method)
;
;
;
;
TF
VLC0
VLC2
COM0
+VLCD
0
COM0 to S28
–VLCD
VLC1
+1/3VLCD
–1/3VLCD
VSS1
VLC0
VLC2
COM1 VLC1
VSS1
VLC0
VLC2
COM2 VLC1
VSS1
VLC0
VLC2
COM3 VLC1
VSS1
+VLCD
0
COM1 to S28
–VLCD
+1/3VLCD
–1/3VLCD
VLC0
VLC2
S28 VLC1
VSS1
430 User’s Manual U11377EJ3V0UD
CHAPTER 20 INTERRUPT AND TEST FUNCTIONS
20.1 Interrupt Function Types
The following three types of interrupt functions are used.
(1) Non-maskable interrupt
This interrupt is acknowledged unconditionally (that is, even in interrupt disabled state). It does not undergo
interrupt priority control and is given top priority over all other interrupt requests.
It generates a standby release signal.
One interrupt request from the watchdog timer is provided as a non-maskable interrupt.
(2) Maskable interrupts
These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group
and a low interrupt priority group by setting the priority specify flag register (PR0L, PR0H, and PR1L).
Multiple high priority interrupts can be applied to low priority interrupts. If two or more interrupts with the same
priority are simultaneously generated, each interrupt has a predetermined priority (see Table 20-1).
A standby release signal is generated.
Six external interrupt requests and 13 internal interrupt requests are provided as maskable interrupts.
(3) Software interrupt
This is a vectored interrupt to be generated by executing the BRK instruction. It is acknowledged even in
interrupt disabled state. The software interrupt does not undergo interrupt priority control.
431
CHAPTER 20 INTERRUPT AND TEST FUNCTIONS
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20.2 Interrupt Sources and Configuration
Twenty-one non-maskable, maskable, and software interrupts are provided as interrupt sources (see Table 20-
1).
Table 20-1. Interrupt Source List
Interrupt
Default
Interrupt Source Internal/ Vector Table
Basic Configuration
Type Priority
Note 1
Name Trigger External Address
Type
Note 2
Non- — INTWDT Watchdog timer overflow (with watchdog Internal 0004H (A)
maskable timer mode 1 selected)
Maskable 0 INTWDT Watchdog timer overflow (with interval (B)
timer mode selected)
1 INTP0 Pin input edge detection External 0006H (C)
2 INTP1 0008H (D)
3 INTP2 000AH
4 INTP3 000CH
5 INTP4 000EH
6 INTP5 0010H
7 INTCSI0 End of serial interface channel 0 Internal 0014H (B)
transfer
8 INTSER Serial interface channel 2 UART reception 0018H
error occurrence
9 INTSR End of serial interface channel 2 001AH
UART reception
INTCSI2 End of serial interface channel 2
3-wire transfer
10 INTST End of serial interface channel 2 001CH
UART transfer
11 INTTM3 Reference time interval signal from 001EH
watch timer
12 INTTM00 Generation of 16-bit timer register, 0020H
capture/compare register 00 (CR00)
match signal
13 INTTM01 Generation of 16-bit timer register, 0022H
capture/compare register 01 (CR01)
match signal
14 INTTM1 Generation of 8-bit timer/event 0024H
counter 1 match signal
15 INTTM2 Generation of 8-bit timer/event 0026H
counter 2 match signal
16 INTAD End of A/D converter conversion 0028H
17 INTCSI3 End of serial interface channel 3 002AH
transfer
Software — BRK BRK instruction execution – 003EH (E)
Notes 1. Default priorities are intended for two or more simultaneously generated maskable interrupt requests.
0 is the highest priority and 17 is the lowest priority.
2. Basic configuration types (A) to (E) correspond to (A) to (E) of Figure 20-1.
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CHAPTER 20 INTERRUPT AND TEST FUNCTIONS
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Figure 20-1. Basic Configuration of Interrupt Function (1/2)
(A) Internal non-maskable interrupt
(B) Internal maskable interrupt
(C) External maskable interrupt (INTP0)
Internal bus
Priority
controller
Vector table
address
generator
Standby
release signal
Interrupt
request
Internal bus
IE PR ISPMK
IF
Interrupt
request
Priority
controller
Vector table
address
generator
Standby
release signal
Internal bus
IE PR ISPMK
IF
Priority
controller
Vector table
address
generator
Standby
release signal
Interrupt
request
Sampling
clock
Edge
detector
Sampling clock
select register
(SCS)
External interrupt mode
register (INTM0)
433
CHAPTER 20 INTERRUPT AND TEST FUNCTIONS
User’s Manual U11377EJ3V0UD
Figure 20-1. Basic Configuration of Interrupt Function (2/2)
(D) External maskable interrupt (except INTP0)
IF: Interrupt request flag
IE: Interrupt enable flag
ISP: In-service priority flag
MK: Interrupt mask flag
PR: Priority specify flag
(E) Software interrupt
External interrupt
mode register
(INTM0, INTM1)
Edge
detector
Interrupt
request
IE PR ISPMK
IF
Priority
controller
Vector table
address
generator
Standby
release signal
Internal bus
Internal bus
Priority
controller
Vector table
address
generator
Interrupt
request
434
CHAPTER 20 INTERRUPT AND TEST FUNCTIONS
User’s Manual U11377EJ3V0UD
20.3 Interrupt Function Control Registers
The following six types of registers are used to control the interrupt functions.
•Interrupt request flag register (IF0L, IF0H, IF1L)
•Interrupt mask flag register (MK0L, MK0H, MK1L)
•Priority specify flag register (PR0L, PR0H, PR1L)
•External interrupt mode register (INTM0, INTM1)
•Sampling clock select register (SCS)
•Program status word (PSW)
Table 20-2 gives a listing of interrupt request flags, interrupt mask flags, and priority specify flags corresponding
to interrupt request sources.
Table 20-2. Various Flags Corresponding to Interrupt Request Sources
Interrupt Source Interrupt Request Flag Interrupt Mask Flag Priority Specify Flag
Register Register Register
INTWDT TMIF4 IF0L TMMK4 MK0L TMPR4 PR0L
INTP0 PIF0 PMK0 PPR0
INTP1 PIF1 PMK1 PPR1
INTP2 PIF2 PMK2 PPR2
INTP3 PIF3 PMK3 PPR3
INTP4 PIF4 PMK4 PPR4
INTP5 PIF5 PMK5 PPR5
INTCSI0 CSIIF0 IF0H CSIMK0 MK0H CSIPR0 PR0H
INTSER SERIF SERMK SERPR
INTSR/INTCSI2 SRIF SRMK SRPR
INTST STIF STMK STPR
INTTM3 TMIF3 TMMK3 TMPR3
INTTM00 TMIF00 TMMK00 TMPR00
INTTM01 TMIF01 TMMK01 TMPR01
INTTM1 TMIF1 IF1L TMMK1 MK1L TMPR1 PR1L
INTTM2 TMIF2 TMMK2 TMPR2
INTAD ADIF ADMK ADPR
INTCSI3 CSIIF3 CSIMK3 CSIPR3
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CHAPTER 20 INTERRUPT AND TEST FUNCTIONS
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(1) Interrupt request flag registers (IF0L, IF0H, IF1L)
The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction
is executed. It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request
or upon application of RESET input.
IF0L, IF0H, and IF1L are set with a 1-bit or 8-bit memory manipulation instruction. If IF0L and IF0H are used
as a 16-bit register IF0, use a 16-bit memory manipulation instruction for the setting.
RESET input clears these registers to 00H.
Figure 20-2. Interrupt Request Flag Register Format
Note WTIF is test input flag. Vectored interrupt request is not generated.
Cautions 1. TMIF4 flag is R/W enabled only when a watchdog timer is used as an interval timer. If
a watchdog timer is used in watchdog timer mode 1, set TMIF4 flag to 0.
2. Set always 0 in IF1L bits 4 to 6, IF0L bit 7, and IF0H bit 1.
3. When manipulating a flag of the interrupt request flag register, use a 1-bit memory
manipulation instruction (CLR1). When describing in C language, use a bit manipulation
instruction such as “IF0L.0 = 0;” or “_asm(“clr1 IF0L, 0”);” because the compiled
assembler must be a 1-bit memory manipulation instruction (CLR1).
If a program is described in C language using an 8-bit memory manipulation instruction
such as “IF0L &= 0xfe;” and compiled, it becomes the assembler of three instructions.
mov a, IF0L
and a, #0FEH
mov IF0L, a
In this case, even if the request flag of another bit of the same interrupt request flag
register (IF0L) is set to 1 at the timing between “mov a, IF0L” and “mov IF0L, a”, the flag
is cleared to 0 at “mov IF0L, a”. Therefore, care must be exercised when using an 8-bit
memory manipulation instruction in C language.
7
0
Symbol
IF0L
6
PIF5
5
PIF4
4
PIF3
3
PIF2
2
PIF1
1
PIF0
0
TMIF4
Address
FFE0H 00H
After Reset R/W
R/W
××IF
0
1
Interrupt Request Flag
No interrupt request signal
Interrupt request signal is generated; Interrupt request state
7
TMIF01
IF0H
6
TMIF00
5
TMIF3
4
STIF
3
SRIF
2
SERIF
1
0
0
CSIIF0
7
WTIF
Note
IF1L
6
0
5
0
4
0
3
CSIIF3
2
ADIF
1
TMIF2
0
TMIF1
FFE1H 00H R/W
FFE2H 00H R/W
<R>
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CHAPTER 20 INTERRUPT AND TEST FUNCTIONS
User’s Manual U11377EJ3V0UD
(2) Interrupt mask flag registers (MK0L, MK0H, MK1L)
The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service.
MK0L, MK0H, and MK1L are set with a 1-bit or 8-bit memory manipulation instruction. If MK0L and MK0H
are used as a 16-bit register MK0, use a 16-bit memory manipulation instruction for the setting.
RESET input sets these registers to FFH.
Figure 20-3. Interrupt Mask Flag Register Format
Note WTMK controls standby mode release enable/disable. This bit does not control the interrupt function.
Cautions 1. If TMMK4 flag is read when a watchdog timer is used in watchdog timer mode 1, MK0 value
becomes undefined.
2. Because port 0 has a dual function as the external interrupt request input, when the
output level is changed by specifying the output mode of the port function, an interrupt
request flag is set. Therefore, 1 should be set in the interrupt mask flag before using the
output mode.
3. Set always 1 in MK1L bits 4 to 6, MK0L bit 7, and MK0H bit 1.
7
1
Symbol
MK0L
6
PMK5
5
PMK4
4
PMK3
3
PMK2
2
PMK1
10 Address
FFE4H FFH
After
Reset R/W
R/W
××MK
0
1
Interrupt Servicing Control
Interrupt servicing enabled
Interrupt servicing disabled
7
MK0H
654
STMK
3
SRMK
21
1
0
7
WTMKNote
MK1L
6
1
5
1
4
1
3
CSIMK3
210
FFE5H FFH R/W
FFE6H FFH R/W
ADMK
TMMK2 TMMK1
CSIMK0
SERMK
TMMK3
TMMK00TMMK01
TMMK4
PMK0
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CHAPTER 20 INTERRUPT AND TEST FUNCTIONS
User’s Manual U11377EJ3V0UD
(3) Priority specify flag registers (PR0L, PR0H, and PR1L)
The priority specify flag is used to set the corresponding maskable interrupt priority orders.
PR0L, PR0H, and PR1L are set with a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are
used as a 16-bit register PR0, use a 16-bit memory manipulation instruction for the setting.
RESET input sets these registers to FFH.
Figure 20-4. Priority Specify Flag Register Format
Cautions 1. When a watchdog timer is used in watchdog timer mode 1, set 1 in TMPR4 flag.
2. Set always 1 in PR1L bits 4 to 7, PR0L bit 7, and PR0H bit 1.
7
1
Symbol
PR0L
6
PPR5
5
PPR4
4
PPR3
3
PPR2
2
PPR1
1
PPR0
0Address
FFE8H FFH
After
Reset R/W
R/W
0
1
Priority Level Selection
High priority level
Low priority level
7
PR0H
654
STPR
3
SRPR
21
1
0
7
1PR1L
6
1
5
1
4
1
3
CSIPR3
2
ADPR
10
FFE9H FFH R/W
FFEAH FFH R/W
××PR
TMPR1TMPR2
SERPR
TMPR4
TMPR01
TMPR00
TMPR3 CSIPR0
438
CHAPTER 20 INTERRUPT AND TEST FUNCTIONS
User’s Manual U11377EJ3V0UD
(4) External interrupt mode register (INTM0, INTM1)
These registers set the valid edge for INTP0 to INTP5.
INTM0 and INTM1 are set with an 8-bit memory manipulation instruction.
RESET input clears these registers to 00H.
Figure 20-5. External Interrupt Mode Register 0 Format
Caution Set the valid edges of the INTP0/TI00 pin after setting 16-bit timer mode control register bit 1 to
bit 3 (TMC01 to TMC03) to 0, 0, 0 and stopping the timer operation.
Address
FFECH 00H
After
Reset R/W
R/W
0
0
1
1
INTP0 Valid Edge Selection
Falling edge
Rising edge
Setting prohibited
Both falling and rising edges
ES11
7
ES31
Symbol
INTM0
6
ES30
5
ES21
4
ES20
3
ES11
2
ES10
1
0
0
0
0
1
0
1
ES10
0
0
1
1
INTP1 Valid Edge Selection
Falling edge
Rising edge
Setting prohibited
Both falling and rising edges
ES21
0
1
0
1
ES20
0
0
1
1
INTP2 Valid Edge Selection
Falling edge
Rising edge
Setting prohibited
Both falling and rising edges
ES31
0
1
0
1
ES30
439
CHAPTER 20 INTERRUPT AND TEST FUNCTIONS
User’s Manual U11377EJ3V0UD
Figure 20-6. External Interrupt Mode Register 1 Format
Address
FFEDH 00H
After
Reset R/W
R/W
0
0
1
1
INTP3 Valid Edge Selection
Falling edge
Rising edge
Setting prohibited
Both falling and rising edges
ES41
7
0
Symbol
INTM1
6
0
5
ES61
4
ES60
3
ES51
2
ES50
1
ES41
0
ES40
0
1
0
1
ES40
0
0
1
1
INTP4 Valid Edge Selection
Falling edge
Rising edge
Setting prohibited
Both falling and rising edges
ES51
0
1
0
1
ES50
0
0
1
1
INTP5 Valid Edge Selection
Falling edge
Rising edge
Setting prohibited
Both falling and rising edges
ES61
0
1
0
1
ES60
440
CHAPTER 20 INTERRUPT AND TEST FUNCTIONS
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(5) Sampling clock select register (SCS)
This register is used to set the valid edge clock sampling clock to be input to INTP0. When remote controlled
data reception is carried out using INTP0, digital noise is eliminated with sampling clocks.
SCS is set with an 8-bit memory manipulation instruction.
RESET input clears SCS to 00H.
Figure 20-7. Sampling Clock Select Register Format
Caution fXX/2N is a clock to be supplied to the CPU and fXX/25, fXX/26 and fXX/27 are clocks to be supplied
to the peripheral hardware. fXX/2N stops in the HALT mode.
Remarks 1. N: Value (N = 0 to 4) at bits 0 to 2 (PCC0 to PCC2) of processor clock control register
2. fXX: Main system clock frequency (fX or fX/2)
3. fX: Main system clock oscillation frequency
4. MCS: Oscillation mode select register bit 0
5. Values in parentheses when operated with fX = 5.0 MHz.
Address
FF47H 00H
After
Reset R/W
R/W
0
0
1
1
INTP0 Sampling Clock Selection
SCS1
7
0
Symbol
SCS
6
0
5
0
4
0
3
0
2
0
1
SCS1
0
SCS0
0
1
0
1
SCS0 MCS = 1 MCS = 0
f
XX
/2
N
f
X
/2
7
(39.1 kHz)
f
X
/2
5
(156.3 kHz)
f
X
/2
6
(78.1 kHz)
f
X
/2
8
(19.5 kHz)
f
X
/2
6
(78.1 kHz)
f
X
/2
7
(39.1 kHz)
441
CHAPTER 20 INTERRUPT AND TEST FUNCTIONS
User’s Manual U11377EJ3V0UD
The noise eliminator sets the interrupt request flag (PIF0) to 1 if the input level of the sampled INTP0 is active
twice in succession.
Figure 20-8 shows the noise eliminator I/O timing.
Figure 20-8. Noise Eliminator I/O Timing (During Rising Edge Detection)
(a) When input is less than the sampling cycle (tSMP)
(b) When input is equal to or twice the sampling cycle (tSMP)
(c) When input is twice or more than the sampling cycle (tSMP)
t
SMP
Sampling clock
INTP0
PIF0 "L"
PIF0 output remains low because the level of INTP0 is not high when
it is sampled.
t
SMP
Sampling clock
INTP0
PIF0
PIF0 flag is set to 1 because the sampled INTP0 level is high twice
in succession.
12
t
SMP
Sampling clock
INTP0
PIF0
PIF0 flag is set to 1 when INTP0 goes high two or more times in succession.
442
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(6) Program status word (PSW)
The program status word is a register to hold the instruction execution result and the current status for interrupt
request. The IE flag to set maskable interrupt request enable/disable and the ISP flag to control multiple
interrupt servicing are mapped.
Besides 8-bit unit read/write, this register can carry out operations with a bit manipulation instruction and
dedicated instructions (EI and DI). When a vectored interrupt request is acknowledged or when the BRK
instruction is executed, the contents of the PSW are automatically saved into the stack, and the IE flag is reset
to 0. If a maskable interrupt request is acknowledged contents of the priority specify flag of the acknowledged
interrupt are transferred to the ISP flag. The contents of the PSW are also saved to the stack by the PUSH
PSW instruction. It is reset from the stack with the RETI, RETB, and POP PSW instructions.
RESET input sets PSW to 02H.
Figure 20-9. Program Status Word Format
7
IEPSW
6
Z
5
RBS1
4
AC
3
RBS0
2
0
1
ISP
0
CY 02H
After Reset
ISP
0
Used when normal instruction is executed
Priority of Interrupt Currently Being Serviced
High-priority interrupt servicing
(low-priority interrupt disable)
1Interrupt request not acknowledged or low-priority
interrupt servicing
(all maskable interrupts enable)
IE Interrupt Request Acknowledge Enable/Disable
0 Disable
1 Enable
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CHAPTER 20 INTERRUPT AND TEST FUNCTIONS
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20.4 Interrupt Request Servicing Operations
20.4.1 Non-maskable interrupt request acknowledge operation
A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledge
disable state. It does not undergo interrupt priority control and has highest priority over all other interrupts.
If a non-maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW,
then PC, the IE flag and ISP flag are reset (0), and the contents of the vector table are loaded into the PC and branched.
Due to this, acknowledgment of multiple interrupts is prohibited.
A new non-maskable interrupt request generated during execution of a non-maskable interrupt servicing program
is acknowledged after the current execution of the non-maskable interrupt servicing program is terminated (following
RETI instruction execution) and one main routine instruction is executed. If a new non-maskable interrupt request
is generated twice or more during non-maskable interrupt service program execution, only one non-maskable interrupt
request is acknowledged after termination of the non-maskable interrupt service program execution.
Figure 20-10 shows the flowchart illustrating generation and acknowledgment of the non-maskable interrupt
request. Figure 20-11 shows the timing of acknowledging the non-maskable interrupt request. Figure 20-12 illustrates
how nested non-maskable interrupt requests are acknowledged.
Caution Be sure to use the RETI instruction to return from a non-maskable interrupt.
<R>
<R>
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CHAPTER 20 INTERRUPT AND TEST FUNCTIONS
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Figure 20-10. Non-Maskable Interrupt Request Acknowledge Flowchart
WDTM: Watchdog timer mode register
WDT: Watchdog timer
Figure 20-11. Non-Maskable Interrupt Request Acknowledge Timing
WDTM4 = 1
(with watchdog timer
mode selected)?
Overflow in WDT?
WDTM3 = 0
(with non-maskable
interrupt request
selected)?
Interrupt request generation
WDT interrupt servicing?
Interrupt control
register unaccessed?
Interrupt
service start
Interrupt request
held pending
Reset processing
Interval timer
No
Ye s
Ye s
No
Ye s
No
Ye s
No
Ye s
No
Start
Instruction Instruction CPU processing
TMIF4
PSW and PC save, jump
to interrupt servicing
Interrupt servicing
program
Interrupt request generated during this interval is acknowledged at .
TMIF4: Watchdog timer interrupt request flag
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Figure 20-12. Non-Maskable Interrupt Request Acknowledge Operation
(a) If a new non-maskable interrupt request is generated during
non-maskable interrupt servicing program execution
(b) If two non-maskable interrupt requests are generated during
non-maskable interrupt servicing program execution
Main routine
NMI request <1>
Execution of 1 instruction
NMI request <2>
Execution of NMI request <1>
NMI request <2> held pending
Servicing of NMI request <2> that was pended
Main routine
NMI request <1>
Execution of 1 instruction
Execution of NMI request <1>
NMI request <2> held pending
NMI request <3> held pending
Servicing of NMI request <2> that was pended
NMI request <3> not acknowledged
(Although two or more NMI requests have been generated,
only one request is acknowledged.)
NMI request <2>
NMI request <3>
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20.4.2 Maskable interrupt request acknowledge operation
A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and a mask
(MK) flag of the interrupt is cleared to 0. A vectored interrupt request is acknowledged in an interrupt enable state
(with IE flag set to 1). However, a low-priority interrupt is not acknowledged during high-priority interrupt request
service (with ISP flag reset to 0).
Moreover, even if the EI instruction is executed during execution of a non-maskable interrupt servicing program,
neither non-maskable interrupt requests nor maskable interrupt requests are acknowledged.
Table 20-3 shows the time required until interrupt servicing is executed since a maskable interrupt request has
been generated.
For the interrupt request acknowledge timing, refer to Figures 20-14 and 20-15.
Table 20-3. Times from Maskable Interrupt Request Generation to Interrupt Service
Minimum Time Maximum TimeNote
When ××PR = 0 7 clock cycles 32 clock cycles
When ××PR = 1 8 clock cycles 33 clock cycles
Note If an interrupt request is generated just before a divide instruction, the wait time is maximized.
Remark 1 clock cycle = 1/fCPU (fCPU: CPU clock)
If two or more maskable interrupt requests are generated simultaneously, the request specified for higher priority
with the priority specify flag is acknowledged first. If the same priorities are specified by the priority specify flag, the
interrupt with the highest default priority is acknowledged first.
The interrupt requests that are held pending are acknowledged when they become acknowledgeable.
Figure 20-13 shows interrupt request acknowledge algorithms.
If a maskable interrupt request is acknowledged, the contents are saved in the stacks, program status word (PSW)
and program counter (PC), in that order, the IE flag is reset to 0, and the acknowledged interrupt priority specify flag
contents are transferred to the ISP flag. Further, the vector table data determined for each interrupt request is loaded
into PC and branched.
Return from the interrupt is possible with the RETI instruction.
<R>
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Figure 20-13. Interrupt Request Acknowledge Processing Algorithm
××IF: Interrupt request flag
××MK: Interrupt mask flag
××PR: Priority specify flag
IE: Flag controlling acknowledgment of maskable interrupt request (1 = Enabled, 0 = Disabled)
ISP: Flag indicating priority of interrupt currently being serviced (0 = Interrupt with high priority is serviced,
1 = No interrupt request is acknowledged, or interrupt with low priority is serviced).
Start
××IF = 1?
××MK = 0?
××PR = 0?
Any
simultaneously
generated ×× PR = 0
interrupt
requests?
Any
simultaneously
generated high-priority
interrupt
requests?
IE = 1?
ISP = 1?
Vectored interrupt
servicing
Interrupt request
held pending
Interrupt request
held pending
Interrupt request
held pending
Interrupt request
held pending
Interrupt request
held pending
Interrupt request
held pending
Interrupt request
held pending Vectored interrupt
servicing
Any high-
priority interrupt request
among simultaneously generated
××
PR = 0 interrupt
requests?
IE = 1?
Yes (High priority)
Ye s
No
Ye s
No
No
No
Yes (Interrupt request
generation)
No
Ye s
No (Low priority)
Ye s
Ye s
No
Ye s
Ye s
No
No
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Figure 20-14. Interrupt Request Acknowledge Timing (Minimum Time)
Remark 1 clock cycle = 1/fCPU (fCPU: CPU clock)
Figure 20-15. Interrupt Request Acknowledge Timing (Maximum Time)
Remark 1 clock cycle = 1/fCPU (fCPU: CPU clock)
Instruction Divide instruction
PSW and PC save,
jump to interrupt
servicing
6 clocks
Interrupt
servicing
program
33 clocks
32 clocks
CPU processing
××IF
(××PR = 1)
××IF
(××PR = 0)
25 clocks
Instruction Instruction
PSW and PC save,
jump to interrupt
servicing
6 clocks
Interrupt
servicing
program
8 clocks
7 clocks
CPU processing
××IF
(××PR = 1)
××IF
(×× PR = 0)
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20.4.3 Software interrupt request acknowledge operation
A software interrupt request is acknowledged by BRK instruction execution. Software interrupt cannot be disabled.
If a software interrupt request is acknowledged, the contents are saved in the stacks, program status word (PSW)
and program counter (PC), in that order, the IE flag is reset to 0 and the contents of the vector tables (003EH and
003FH) are loaded into PC and branched.
Return from the software interrupt is possible with the RETB instruction.
Caution Do not use the RETI instruction for returning from the software interrupt.
20.4.4 Multiple interrupt request servicing
Multiple interrupts occur when another interrupt request is acknowledged during execution of an interrupt.
Multiple interrupts do not occur unless the interrupt request acknowledge enable state is selected (IE = 1) (except
non-maskable interrupts). Also, when an interrupt request is received, interrupt requests acknowledge becomes
disabled (IE = 0). Therefore, to enable multiple interrupts, it is necessary to set (to 1) the IE flag with the EI instruction
during interrupt servicing to enable interrupt acknowledge.
Moreover, even if interrupts are enabled, multiple interrupts may not be enabled, this being subject to interrupt
priority control. Two types of priority control are available: default priority control and programmable priority control.
Programmable priority control is used for multiple interrupts.
In the interrupt enable state, if an interrupt request with a priority equal to or higher than that of the interrupt currently
being serviced is generated, it is acknowledged for multiple interrupt servicing. If an interrupt with a priority lower
than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for
multiple interrupt servicing. Interrupt requests that are not enabled because of the interrupt disable state or they have
a lower priority are held pending. When servicing of the current interrupt ends, the pended interrupt request is
acknowledged following execution of one main processing instruction execution.
Multiple interrupt servicing is not possible during non-maskable interrupt servicing.
Table 20-4 shows interrupt requests enabled for multiple interrupt servicing, and Figure 20-14 shows multiple
interrupt examples.
Table 20-4. Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing
Maskable Interrupt Request
PR = 0 PR = 1
Interrupt Servicing IE = 1 IE = 0 IE = 1 IE = 0
Non-maskable interrupt D D D D D
Maskable interrupt ISP = 0 E E D D D
ISP = 1 E E D E D
Software interrupt E E D E D
Remarks 1. E: Multiple interrupt enable
2. D: Multiple interrupt disable
3. ISP and IE are the flags contained in PSW.
ISP = 0: An interrupt with higher priority is being serviced
ISP = 1: An interrupt request is not acknowledged or an interrupt with lower priority is being
serviced
IE = 0: Interrupt request acknowledge is disabled
IE = 1: Interrupt request acknowledge is enabled
4. PR is a flag contained in PR0L, PR0H, and PR1L.
PR = 0: Higher priority level
PR = 1: Lower priority level
Non-maskable
Interrupt
Request
Multiple Interrupt
Request
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Figure 20-16. Multiple Interrupt Example (1/2)
Example 1. Two multiple interrupts generated
During interrupt INTxx servicing, two interrupt requests, INTyy and INTzz are acknowledged, and a
multiple interrupt is generated. An EI instruction is issued before each interrupt request acknowledge,
and the interrupt request acknowledge enable state is set.
Example 2. Multiple interrupt is not generated by priority control
The interrupt request INTyy generated during interrupt INTxx servicing is not acknowledged because
the interrupt priority is lower than that of INTxx, and a multiple interrupt is not generated. INTyy
request is held pending and acknowledged after 1 instruction execution of the main processing.
PR = 0: Higher priority level
PR = 1: Lower priority level
IE = 0: Interrupt request acknowledge disable
Main processing
EI
INTxx
(PR = 1)
INTyy
(PR = 0)
IE = 0
EI
RETI
INTxx
servicing
INTzz
(PR = 0)
IE = 0
EI
RETI
INTyy
servicing
IE = 0
RETI
INTzz
servicing
Main processing INTxx
servicing
INTyy
servicing
INTxx
(PR = 0)
1 instruction
execution IE = 0
INTyy
(PR = 1)
EI IE = 0
EI
RETI
RETI
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Figure 20-16. Multiple Interrupt Example (2/2)
Example 3. A multiple interrupt is not generated because interrupts are not enabled
Because interrupts are not enabled in interrupt INTxx servicing (an EI instruction is not issued),
interrupt request INTyy is not acknowledged, and a multiple interrupt is not generated. The INTyy
request is held pending and acknowledged after 1 instruction execution of the main processing.
PR = 0: Higher priority level
IE = 0: Interrupt request acknowledge disable
Main processing INTxx
servicing
INTyy
servicing
INTxx
(PR = 0)
1 instruction
execution
IE = 0
INTyy
(PR = 0)
IE = 0
RETI
RETI
EI
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20.4.5 Interrupt request hold
Some instructions keep an interrupt request, if any, pending until the completion of execution of the next instruction.
These instructions (that keep an interrupt request pending) are listed below.
•MOV PSW, #byte
•MOV A, PSW
•MOV PSW, A
•MOV1 PSW.bit, CY
•MOV1 CY, PSW.bit
•AND1 CY, PSW.bit
•OR1 CY, PSW.bit
•XOR1 CY, PSW.bit
•SET1 PSW.bit
•CLR1 PSW.bit
•RETB
•RETI
•PUSH PSW
•POP PSW
•BT PSW.bit, $addr16
•BF PSW.bit, $addr16
•BTCLR PSW.bit, $addr16
•EI
•DI
•Manipulate instructions for IF0L, IF0H, IF1L, MK0L, MK0H, MK1L, PR0L, PR0H, PR1L, INTM0, and INTM1
registers
Caution The BRK instruction does not belong to the above group of instructions. However, the software
interrupt that is started by execution of the BRK instruction clears the IE flag to 0. Therefore,
even if a maskable interrupt request is generated, it is not acknowledged when the BRK
instruction is executed. However, a non-maskable interrupt request is acknowledged.
The timing with which interrupt requests are held pending is shown in Figure 20-17.
Figure 20-17. Interrupt Request Hold
Remarks 1. Instruction N: Interrupt request hold instruction
2. Instruction M: Instructions other than interrupt request hold instruction
3. The ××PR (priority level) values do not affect the operation of ××IF (interrupt request).
CPU processing
××IF
Instruction N Instruction M PSW and PC save,
jump to interrupt servicing
Interrupt servicing
program
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20.5 Test Functions
The test function sets the corresponding test input flag to 1 and generates a standby release signal when the watch
timer overflows and when the falling edge of port 4 is detected.
Unlike the interrupt function, this function does not perform vector processing.
There are two test input factors as shown in Table 20-5. The basic configuration is shown in Figure 20-18.
Table 20-5. Test Input Factors
Test Input Factors Internal/
Name Trigger External
INTWT Watch timer overflow Internal
INTPT11 Falling edge detection at port 11 External
Figure 20-18. Basic Configuration of Test Function
IF: Test input flag
MK: Test mask flag
20.5.1 Registers controlling test function
The test function is controlled by the following three registers.
•Interrupt request flag register 1L (IF1L)
•Interrupt mask flag register 1L (MK1L)
•Key return mode register (KRM)
The names of the test input flags and test mask flags corresponding to the test input signals are listed in Table
20-6.
Table 20-6. Flags Corresponding to Test Input Signals
Test Input Signal Name Test Input Flag Test Mask Flag
INTWT WTIF WTMK
INTPT11 KRIF KRMK
Internal bus
MK
IF
Test input
signal
Standby
release signal
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(1) Interrupt request flag register 1L (IF1L)
This register indicates whether a watch timer overflow is detected or not.
IF1L is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears IF1L to 00H.
Figure 20-19. Format of Interrupt Request Flag Register 1L
Caution Be sure to set bits 4 to 6 to 0.
(2) Interrupt mask flag register 1L (MK1L)
This register is used to set the standby mode enable/disable at the time the standby mode is released by the
watch timer.
MK1L is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets MK1L to FFH.
Figure 20-20. Format of Interrupt Mask Flag Register 1L
Caution Be sure to set bits 4 to 6 to 1.
7
WTIF
Symbol
IF1L
6
0
5
0
4
0
3
CSIIF3
2
ADIF
1
TMIF2
0
TMIF1
Address
FFE2H 00H
After Reset R/W
R/W
0
1
Watch Timer Overflow Detection Flag
Not detected
Detected
WTIF
7
WTMK
Symbol
MK1L
6
1
5
1
4
1
3
CSIMK3
210 Address
FFE6H FFH
After Reset R/W
R/W
0
1
Standby Mode Control by Watch Timer
Enables releasing the standby mode.
Disables releasing the standby mode.
WTMK
ADMK
TMMK2 TMMK1
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(3) Key return mode register (KRM)
This register is used to set enable/disable of standby function release by key return signal (port 11 falling edge
detection), and selects port 11 falling edge input.
KRM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets KRM to 02H.
Figure 20-21. Key Return Mode Register Format
Caution When port 11 falling edge detection is used, be sure to clear KRIF to 0 (not cleared to 0
automatically).
7
0
Symbol
KRM
6
0
5
0
4
0
3
KRM3
2
KRM2
1
KRMK
0
KRIF
Address
FFB8H 02H
After Reset R/W
R/W
0
1
Key Return Signal Detection Flag
Not detected
Detected (port 11 falling edge detection)
KRIF
0
1
Standby Mode Control by Key Return Signal
Standby mode release enabled
Standby mode release disabled
KRMK
KRM3
Selection of Port 11 Falling Edge Input
0
0
P117
KRM2
0
1
1
1
0
1
P114 to P117
P112 to P117
P110 to P117
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20.5.2 Test input signal acknowledge operation
(1) Internal test input signal (INTWT)
The internal test input signal (INTWT) is generated when the watch timer overflows. This signal sets the WTIF
flag. At this time, the standby release signal is generated if it is not masked by the interrupt mask flag (WTMK).
By checking the WTIF flag in a cycle shorter than the overflow cycle of the watch timer, a watch function can
be realized.
(2) External test input signal (INTPT4)
The external test input signal (INTPT4) is generated when the falling edge is input to the pins of port 4 (P40
to P47). As the result, the KRIF flag is set. At this time, the standby release signal is generated if it is not
masked by the KRMK flag. By using port 4 to input the key return signal of a key matrix, the presence or absence
of key input can be checked according to the status of the KRIF flag.
457User’s Manual U11377EJ3V0UD
CHAPTER 21 STANDBY FUNCTION
21.1 Standby Function and Configuration
21.1.1 Standby function
The standby function is designed to decrease power consumption of the system. The following two modes are
available.
(1) HALT mode
HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock.
System clock oscillator continues oscillation. In this mode, current consumption cannot be decreased as in
the STOP mode. The HALT mode is valid to restart immediately upon interrupt request and to carry out
intermittent operations such as in watch applications.
(2) STOP mode
STOP instruction execution sets the STOP mode. In the STOP mode, the main system clock oscillator stops
and the whole system stops. CPU current consumption can be considerably decreased.
Data memory low-voltage hold (down to VDD = 1.8 V) is possible. Thus, the STOP mode is effective to hold
data memory contents with ultra-low current consumption. Because this mode can be released upon interrupt
request, it enables intermittent operations to be carried out.
However, because a wait time is necessary to secure an oscillation stabilization time after the STOP mode
is released, select the HALT mode if it is necessary to start processing immediately upon interrupt request.
In any mode, all the contents of the register, flag and data memory just before standby mode setting are held. The
I/O port output latch and output buffer statuses are also held.
Cautions 1. The STOP mode can be used only when the system operates with the main system clock
(subsystem clock oscillation cannot be stopped). The HALT mode can be used with either
the main system clock or the subsystem clock.
2. When proceeding to the STOP mode, be sure to stop the peripheral hardware operation and
execute the STOP instruction.
3. The following sequence is recommended for power consumption reduction of the A/D
converter when the standby function is used: first clear bit 7 (CS) of A/D converter mode
register (ADM) to 0 to stop the A/D conversion operation, and then execute the HALT or STOP
instruction.
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21.1.2 Standby function control register
A wait time after the STOP mode is released upon interrupt request till the oscillation stabilizes is controlled with
the oscillation stabilization time select register (OSTS).
OSTS is set with an 8-bit memory manipulation instruction.
RESET input sets OSTS to 04H. However, it takes 217/fX, not 218/fX, until the STOP mode is released by RESET
input.
Figure 21-1. Oscillation Stabilization Time Select Register Format
Caution The wait time after STOP mode release does not include the time (see "a" in the illustration below)
from STOP mode release to clock oscillation start, regardless of release by RESET input or by
interrupt request generation.
Remarks 1. fX: Main system clock oscillation frequency
2. MCS: Oscillation mode select register bit 0
3. Values in parentheses apply to operating at fX = 5.0 MHz
Address
FFFAH 04H
After Reset R/W
R/W
0
0
0
0
1
Selection of Oscillation Stabilization Time when STOP Mode is Released
OSTS2
7
0
Symbol
OSTS
6
0
5
0
4
0
3
0
2
OSTS2
1
OSTS1
0
OSTS0
0
0
1
1
0
Other than above
OSTS1
MCS = 1 MCS = 0
212/fx(819 s)
214/fx(3.28 ms)
215/fx(6.55 ms)
216/fx(13.1 ms)
217/fx(26.2 ms)
213/fx(1.64 ms)
215/fx(6.55 ms)
216/fx(13.1 ms)
217/fx(26.2 ms)
218/fx(52.4 ms)
µ
0
1
0
1
0
OSTS0
Setting prohibited
STOP mode release
X1 pin
voltage
waveform
VSS1
a
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21.2 Standby Function Operations
21.2.1 HALT mode
(1) HALT mode set and operating status
The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the
subsystem clock.
The operating status in the HALT mode is described below.
Table 21-1. HALT Mode Operating Status
HALT Mode Setting HALT Execution During Main HALT Execution During Subsystem
System Clock Operation Clock Operation
Without Subsystem
With Subsystem
Main System
Main System
Item
Clock
Note 1
ClockNote 2
Clock Oscillates
Clock Stops
Clock generator Both main system and subsystem clocks can be oscillated. Clock supply to the CPU stops.
CPU Operation stop.
Port (output latch) Status before HALT mode setting is held.
16-bit timer/event counter Operable. Operable when watch timer output
with fXT selected as count clock (fXT
is selected as count clock for watch
timer).
8-bit timer/event counter Operable. Operable when TI1 or TI2 is
selected as count clock.
Watch timer Operable if fXX/27Operable. Operable if fXT is selected as
is selected as count clock.
count clock.
Watchdog timer Operable. Operation stops.
A/D converter Operable. Operation stops.
Serial interface Operable Operable at external SCK.
LCD controller/driver Operable if fXX/27Operable. Operable if fXT is selected as
is selected as count clock.
count clock.
External INTP0 Operable when a clock (fXX/25, fXX/26, fXX/27) for the Operation stops.
interrupt peripheral hardware is selected as sampling clock.
INTP1 to INTP5 Operable.
Notes 1. Including case when external clock is not supplied.
2. Including case when external clock is supplied.
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(2) HALT mode release
The HALT mode can be released with the following four types of sources.
(a) Release by unmasked interrupt request
An unmasked interrupt request is used to release the HALT mode. If interrupt request acknowledge is
enabled, vectored interrupt request service is carried out. If disabled, the next address instruction is
executed.
Figure 21-2. HALT Mode Release by Interrupt Request Generation
Remarks 1. The broken line indicates the case when the interrupt request which has released the
standby status is acknowledged.
2. Wait time will be as follows:
• When vectored interrupt service is carried out: 8 to 9 clocks
• When vectored interrupt service is not carried out: 2 to 3 clocks
(b) Release by non-maskable interrupt request
The HALT mode is released and vectored interrupt request service is carried out whether interrupt request
acknowledge is enabled or disabled.
(c) Release by unmasked test input
The HALT mode is released by unmasked test input and the next address instruction of the HALT
instruction is executed.
HALT
instruction Wait
Standby
release signal
Operating
mode
Clock
HALT mode Wait
Oscillation
Operating mode
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(d) Release by RESET input
As is the case with normal reset operation, a program is executed after branch to the reset vector address.
Figure 21-3. HALT Mode Release by RESET Input
Remarks 1. fX: Main system clock oscillation frequency
2. Time value in parentheses is when fX = 5.0 MHz.
Table 21-2. Operation after HALT Mode Release
Release Source MK×× PR×× IE ISP Operation
Maskable interrupt 0 0 0 ×Next address instruction execution
request 001×Interrupt service execution
0 1 0 1 Next address instruction execution
01×0
0 1 1 1 Interrupt service execution
1×××HALT mode hold
Non-maskable interrupt ––××Interrupt service execution
request
Test input 0 –××Next address instruction execution
1–××HALT mode hold
RESET input ––××Reset processing
×: don't care
HALT
instruction
RESET
signal
Operating
mode
Clock
Reset
periodHALT mode
Oscillation
Oscillation
stop
Oscillation
stabilization
wait status
Operating
mode
Oscillation
Wait
(217/fX: 26.2 ms)
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21.2.2 STOP mode
(1) STOP mode set and operating status
The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock.
Cautions 1. When the STOP mode is set, the X2 pin is internally connected to VDD1 via a pull-up
resistor to minimize the leakage current at the crystal oscillator. Thus, do not use
the STOP mode in a system where an external clock is used for the main system clock.
2. Because the interrupt request signal is used to release the standby mode, if there
is an interrupt source with the interrupt request flag set and the interrupt mask flag
reset, the standby mode is immediately released if set. Thus, the STOP mode is reset
to the HALT mode immediately after execution of the STOP instruction. After the wait
set using the oscillation stabilization time select register (OSTS), the operating mode
is set.
The operating status in the STOP mode is described below.
Table 21-3. STOP Mode Operating Status
STOP Mode Setting
With Subsystem Clock Without Subsystem Clock
Item
Clock generator Only main system clock stops oscillation.
CPU Operation stop.
Port (output latch) Status before STOP mode setting is held.
16-bit timer/event counter Operable when watch timer output with fXT selected Operation stops.
is selected as count clock (fXT is selected as count
clock for watch timer).
8-bit timer/event counter Operable when TI1 and TI2 are selected for the count clock.
Watch timer Operable when fXT is selected for the count clock. Operation stops.
Watchdog timer Operation stops.
A/D converter Operation stops.
Serial
Other than UART
Operable when externally supplied clock is specified as the serial clock.
interface UART Operation stops.
LCD controller/driver Operable when fXT is selected for the count clock. Operation stops.
External INTP0 Operation is impossible.
interrupt INTP1 to INTP5 Operable.
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(2) STOP mode release
The STOP mode can be released with the following three types of sources.
(a) Release by unmasked interrupt request
An unmasked interrupt request is used to release the STOP mode. If interrupt request acknowledge is
enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out. If interrupt
request acknowledge is disabled, the next address instruction is executed.
Figure 21-4. STOP Mode Release by Interrupt Request Generation
Remark The broken line indicates the case when the interrupt request which has released the standby
status is acknowledged.
(b) Release by unmasked test input
The STOP mode is released by unmasked test input. After the lapse of oscillation stabilization time, the
instruction at the next address of the STOP instruction is executed.
STOP
instruction
Wait
(Time set by OSTS)
Oscillation stabilization
wait status
Operating
mode
Oscillation
Operating
mode STOP mode
Oscillation stopOscillation
Standby
release signal
Clock
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(c) Release by RESET input
The STOP mode is released and after the lapse of oscillation stabilization time, reset operation is carried
out.
Figure 21-5. STOP Mode Release by RESET Input
Remarks 1. fX: Main system clock oscillation frequency
2. Time value in parentheses is when fX = 5.0 MHz.
Table 21-4. Operation after STOP Mode Release
Release Source MK×× PR×× IE ISP Operation
Maskable interrupt request 0 0 0 ×Next address instruction execution
001×Interrupt service execution
0 1 0 1 Next address instruction execution
01×0
0 1 1 1 Interrupt service execution
1×××STOP mode hold
Test input 0 –××Next address instruction execution
1–××STOP mode hold
RESET input ––××Reset processing
×: don't care
RESET
signal
Operating
mode
Clock
Reset
periodSTOP mode
Oscillation stop
Oscillation
stabilization
wait status
Operating
mode
Oscillation
Wait
(2
17
/f
X
: 26.2 ms)
STOP
instruction
Oscillation
465User’s Manual U11377EJ3V0UD
CHAPTER 22 RESET FUNCTION
22.1 Reset Function
The following two operations are available to generate the reset signal.
(1) External reset input with RESET pin
(2) Internal reset by watchdog timer program loop time detection
External reset and internal reset have no functional differences. In both cases, program execution starts at the
address at 0000H and 0001H by RESET input.
When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each hardware
is set to the status as shown in Table 22-1. Each pin has high impedance during reset input or during oscillation
stabilization time just after reset release.
When a high level is input to the RESET input, the reset is released and program execution starts after the lapse
of oscillation stabilization time (217/fX). The reset applied by watchdog timer overflow is automatically released after
a reset and program execution starts after the lapse of oscillation stabilization time (217/fX) (see Figures 22-2 to 22-
4).
Cautions 1. For an external reset, input a low level for 10
µ
s or more to the RESET pin.
2. During reset input, main system clock oscillation remains stopped but subsystem clock
oscillation continues.
3. When the STOP mode is released by reset, the STOP mode contents are held during reset
input. However, the port pin becomes high-impedance.
Figure 22-1. Block Diagram of Reset Function
RESET
Count clock
Reset controller
Watchdog timer
Stop
Over-
flow
Reset
signal
Interrupt
function
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Figure 22-2. Timing of Reset Input by RESET Input
Figure 22-3. Timing of Reset due to Watchdog Timer Overflow
Figure 22-4. Timing of Reset Input in STOP Mode by RESET Input
X1
Normal operation
Watchdog
timer
overflow
Internal
reset signal
Port pin
Reset period
(Oscillation
stop)
Oscillation
stabilization
time wait
Normal operation
(Reset processing)
Hi-Z
RESET
Internal
reset signal
Port pin
Delay Delay
Hi-Z
X1
Normal operation
Reset period
(Oscillation
stop)
Oscillation
stabilization
time wait
Normal operation
(Reset processing)
Stop status
(Oscillation
stop)
STOP instruction execution
RESET
Internal
reset signal
Port pin
Delay
Delay
Hi-Z
X1
Normal operation Reset period
(Oscillation
stop)
Oscillation
stabilization
time wait
Normal operation
(Reset processing)
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Table 22-1. Hardware Status After Reset (1/2)
Hardware Status After Reset
Program counter (PC)Note 1 The contents of reset vector
tables (0000H and 0001H) are
set.
Stack pointer (SP) Undefined
Program status word (PSW) 02H
RAM Data memory UndefinedNote 2
General-purpose register UndefinedNote 2
Ports 0 to 3, 7 to 11 (P0 to P3, P7 to P11) (output latch) 00H
Port mode register (PM0 to PM3, PM7 to PM11) FFH
Pull-up resistor option register (PUOH, PUOL) 00H
Processor clock control register (PCC) 04H
Oscillation mode select register (OSMS) 00H
Internal memory size switching register (IMS) Note 3
Internal expansion RAM size switching register (IXS) 0AH
Oscillation stabilization time select register (OSTS) 04H
16-bit timer/event counter Timer register (TM0) 0000H
Capture/compare register (CR00, CR01) Undefined
Clock select register (TCL0) 00H
Mode control register (TMC0) 00H
Capture/compare control register 0 (CRC0) 04H
Output control register (TOC0) 00H
8-bit timer/event counter Timer register (TM1, TM2) 00H
Compare register (CR10, CR20) Undefined
Clock select register (TCL1) 00H
Mode control register (TMC1) 00H
Output control register (TOC1) 00H
Notes 1. During reset input or oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined. All other hardware statuses remains unchanged after reset.
2. The post-reset status is held in the standby mode.
3. The values after reset depend on the product.
µ
PD780306, 780306Y: CCH,
µ
PD780308, 780308Y: CFH,
µ
PD78P0308, 78P0308Y: CFH
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Table 22-1. Hardware Status After Reset (2/2)
Hardware Status After Reset
Watch timer Mode control register (TMC2) 00H
Clock select register (TCL2) 00H
Watchdog timer Mode register (WDTM) 00H
Serial interface Clock select register (TCL3, TCL4) 88H
Shift register (SIO0, SIO3) Undefined
Mode register (CSIM0, CSIM2, CSIM3) 00H
Serial bus interface control register (SBIC) 00H
Slave address register (SVA) Undefined
Asynchronous serial interface mode register (ASIM) 00H
Asynchronous serial interface status register (ASIS) 00H
Baud rate generator control register (BRGC) 00H
Serial interface pin select register (SIPS) 00H
Transmit shift register (TXS) FFH
Receive buffer register (RXB)
Interrupt timing specify register (SINT) 00H
A/D converter Mode register (ADM) 01H
Conversion result register (ADCR) Undefined
Input select register (ADIS) 00H
LCD controller/driver Display mode register (LCDM) 00H
Display control register (LCDC) 00H
Interrupt Request flag register (IF0L, IF0H, IF1L) 00H
Mask flag register (MK0L, MK0H, MK1L) FFH
Priority specify flag register (PR0L, PR0H, PR1L) FFH
External interrupt mode register (INTM0, INTM1) 00H
Key return mode register (KRM) 02H
Sampling clock select register (SCS) 00H
469User’s Manual U11377EJ3V0UD
CHAPTER 23
µ
PD78P0308, 78P0308Y
The
µ
PD78P0308, 78P0308Y replace the internal mask ROM of the
µ
PD780308, 780308Y with one-time PROM
or EPROM. Table 23-1 lists the differences among the
µ
PD78P0308, 78P0308Y and the mask ROM versions
(
µ
PD780306, 780306Y, 780308, 780308Y).
Table 23-1. Differences among
µ
PD78P0308, 78P0308Y, and Mask ROM Versions
Item
µ
PD78P0308, 78P0308Y Mask ROM Versions
ROM structure One-time PROM/EPROM Mask ROM
ROM capacity 60 KB
µ
PD780306, 780306Y: 48 KB
µ
PD780308, 780308Y: 60 KB
Changing internal ROM PossibleNote Impossible
capacity by memory size
select register
IC pin None Available
VPP pin Available None
On-chip mask option None Available
split resistors for LCD
driving power supply
Electrical characteristics Refer to Data Sheet of individual product.
Note The internal PROM capacity is set to 60 KB at RESET.
Caution There are differences in noise immunity and noise radiation between the PROM and mask ROM
versions. When pre-producing an application set with the PROM version and then mass
producing it with the mask ROM version, be sure to conduct sufficient evaluations on the
commercial samples (CS) (not engineering samples (ES)) of the mask ROM versions.
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µ
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23.1 Internal Memory Size Switching Register
The
µ
PD78P0308, 78P0308Y allows users to define its internal ROM and high-speed RAM sizes using the internal
memory size switching register (IMS), so that the same memory mapping as that of a mask ROM version with a
different-size internal ROM and high-speed RAM is possible.
IMS is set with an 8-bit memory manipulation instruction.
RESET input sets IMS to CFH.
Figure 23-1. Internal Memory Size Switching Register Format
The IMS settings to give the same memory map as mask ROM versions are shown in Table 23-2.
Table 23-2. Examples of Internal Memory Size Switching Register Settings
Relevant Mask ROM Version IMS Setting
µ
PD780306, 780306Y CCH
µ
PD780308, 780308Y CFH
7
RAM2
Symbol
IMS
6
RAM1
5
RAM0
4
0
3
ROM3
2
ROM2
1
ROM1
0
ROM0
Address
FFF0H CFH
After
Reset R/W
R/W
Internal ROM Capacity SelectionROM3 ROM2 ROM1 ROM0
Setting prohibitedOther than above
Internal High-Speed RAM Capacity SelectionRAM2 RAM1 RAM0
Setting prohibitedOther than above
1
1
48 KB
60 KB
1
1
0
1
0
1
1024 bytes110
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µ
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23.2 Internal Expansion RAM Size Switching Register
The
µ
PD78P0308 and 78P0308Y can select the internal expansion RAM size by using the internal expansion RAM
size switching register (IXS). By setting IXS, the memory mapping of the
µ
PD78P0308 and 78P0308Y can be made
the same as that of the mask ROM versions with a different internal expansion RAM capacity.
IXS is set with an 8-bit memory manipulation instruction.
RESET input sets IXS to 0AH.
Figure 23-2. Internal Expansion RAM Size Switching Register Format
The IXS settings to give the same memory map as mask ROM versions are shown in Table 23-3.
Table 23-3. Examples of Internal Expansion RAM Size Switching Register Settings
Relevant Mask ROM Version IXS Setting
µ
PD780306, 780306Y 0AH
µ
PD780308, 780308Y
7
0
Symbol
IXS
6
0
5
0
4
0
3
IXRAM3
2
IXRAM2
1
IXRAM1
0
IXRAM0
Address
FFF4H 0AH
After
Reset R/W
W
Internal Expansion RAM Capacity Selection
IXRAM3 IXRAM2 IXRAM1 IXRAM0
Setting prohibitedOther than above
1 1024 bytes010
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µ
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RESET VPP VDD CE OE PGM D0 to D7
23.3 PROM Programming
The
µ
PD78P0308 and 78P0308Y each incorporate a 60 KB PROM as program memory. To write a program
into the
µ
PD78P0308 or 78P0308Y PROM, make the device enter the PROM programming mode by setting the
levels of the VPP and RESET pins as specified. For the connection of unused pins, see (2) PROM programming
mode in 1.5 or 2.5.
Caution Write the program in the range of addresses 0000H to EFFFH (specify the last address as
EFFFH).
The program cannot be correctly written by a PROM programmer which does not have a write
address specification function.
23.3.1 Operating modes
When +5 V or +12.5 V is applied to the VPP pin and a low-level signal is applied to the RESET pin, the
µ
PD78P0308
and
µ
PD78P0308Y are set to the PROM programming mode. This is one of the operating modes shown in Table
23-4 below according to the setting of the CE, OE, and PGM pins.
The PROM contents can be read by setting the read mode.
Table 23-4. PROM Programming Operating Modes
Pin
Operating Mode
Page data latch L +12.5 V +6.5 V H L H Data input
Page write H H L High impedance
Byte write L H L Data input
Program verify L L H Data output
Program inhibit ×H H High impedance
×LL
Read +5 V +5 V L L H Data output
Output disabled L H ×High impedance
Standby H ××High impedance
×: L or H
(1) Read mode
Read mode is set by setting CE to L and OE to L.
(2) Output disable mode
If OE is set to H, data output becomes high impedance and the output disable mode is set.
Therefore, if multiple
µ
PD78P0308s or 78P0308Ys are connected to the data bus, data can be read from any
one device by controlling the OE pin.
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µ
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(3) Standby mode
Setting CE to H sets the standby mode.
In this mode, data output becomes high impedance irrespective of the status of OE.
(4) Page data latch mode
Setting CE to H, PGM to H, and OE to L at the start of the page write mode sets the page data latch mode.
In this mode, 1-page 4-byte data is latched in the internal address/data latch circuit.
(5) Page write mode
After a 1-page 4-byte address and data are latched by the page data latch mode, a page write is executed
by applying a 0.1 ms program pulse (active-low) to the PGM pin while CE = H and OE = H. After this, program
verification can be performed by setting CE to L and OE to L.
If programming is not performed by one program pulse, repeated write and verify operations are executed
X times (X ≤ 10).
(6) Byte write mode
A byte write is executed by applying a 0.1 ms program pulse (active-low) to the PGM pin while CE = L and
OE = H. After this, program verification can be performed by setting OE to L.
If programming is not performed by one program pulse, repeated write and verify operations are executed
X times (X ≤ 10).
(7) Program verify mode
Setting CE to L, PGM to H, and OE to L sets the program verify mode.
After writing is performed, this mode should be used to check whether the data was written correctly.
(8) Program inhibit mode
The program inhibit mode is used when the OE pins, VPP pins and pins D0 to D7 of multiple
µ
PD78P0308s
or 78P0308Ys are connected in parallel and any one of these devices must be written to.
The page write mode or byte write mode described above is used to perform a write. At this time, the write
is not performed on the device which has the PGM pin driven high.
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µ
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23.3.2 PROM write procedure
Figure 23-3. Page Program Mode Flowchart
Start
Address = G
V
DD
= 6.5 V, V
PP
= 12.5 V
X = 0
Latch
Address = Address + 1
Latch
Address = Address + 1
Latch
Address = Address + 1
Latch
X = X + 1
0.1 ms program pulse
Verify 4 bytes
Pass
Address = N?
No
Pass
V
DD
= 4.5 to 5.5 V, V
PP
= V
DD
All bytes verified?
End of write
Address = Address + 1
No
Ye s
X = 10?
Fail
Fail
Ye s
All Pass
Defective product
G = Start address
N = Last address of program
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µ
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Figure 23-4. Page Program Mode Timing
Page data latch
Page
program Program verify
Data input Data output
A2 to A16
A0, A1
D0 to D7
V
PP
V
DD
V
PP
V
DD
+ 1.5
V
DD
V
DD
V
IH
CE
PGM
OE
V
IL
V
IH
V
IL
V
IH
V
IL
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µ
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Figure 23-5. Byte Program Mode Flowchart
Start
Address = G
V
DD
= 6.5 V, V
PP
= 12.5 V
X = 0
X = X + 1
0.1 ms program pulse
Verify
Address = N?
V
DD
= 4.5 to 5.5 V, V
PP
= V
DD
All bytes verified?
End of write
Fail
Fail
Pass
Ye s
All Pass
No
Pass
Defective product
No
Ye s
X = 10?
Address = Address + 1
G = Start address
N = Last address of program
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µ
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Figure 23-6. Byte Program Mode Timing
Cautions 1. Be sure to apply VDD before applying VPP, and cut it off after cutting VPP.
2. VPP must not exceed +13.5 V including overshoot voltage.
3. Disconnecting/inserting the device from/to the on-board socket while +12.5 V is being applied
to the VPP pin may have an adverse affect on device reliability.
A0 to A16
D0 to D7
Program Program verify
Data input Data output
V
PP
V
DD
V
DD
+ 1.5
V
DD
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
PP
V
DD
CE
PGM
OE
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µ
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23.3.3 PROM reading procedure
PROM contents can be read onto the external data bus (D0 to D7) using the following procedure.
(1) Fix the RESET pin low, and supply +5 V to the VPP pin. Unused pins are handled as shown in (2) PROM
programming mode in 1.5 or 2.5.
(2) Supply +5 V to the VDD and VPP pins.
(3) Input the address of data to be read to pins A0 to A16.
(4) Read mode is entered.
(5) Data is output to pins D0 to D7.
The timing for steps (2) to (5) above is shown in Figure 23-7.
Figure 23-7. PROM Read Timing
Address inputA0 to A16
CE (Input)
OE (Input)
D0 to D7
Hi-Z
Data output
Hi-Z
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µ
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23.4 Screening of One-Time PROM Versions
One-time PROM versions cannot be fully tested by NEC Electronics before shipment due to the structure
of one-time PROM. Therefore, after users have written data into the PROM, screening should be implemented
by user: that is, store devices at high temperature for one day as specified below, and verify their contents after
the devices have returned to room temperature.
Storage Temperature Storage Time
125°C 24 hours
480 User’s Manual U11377EJ3V0UD
CHAPTER 24 INSTRUCTION SET
This chapter describes each instruction set of the
µ
PD780308 and 780308Y Subseries as list table. For details
of its operation and operation code, refer to the 78K/0 Series Instructions User’s Manual (U12326E).
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24.1 Conventions
24.1.1 Operand identifiers and description methods
Operands are described in “Operand” column of each instruction in accordance with the description method of the
instruction operand identifier (refer to the assembler specifications for detail). When there are two or more description
methods, select one of them. Alphabetic letters in capitals and symbols, #, !, $ and [ ] are key words and must be
described as they are. Each symbol has the following meaning.
• #: Immediate data specification
• !: Absolute address specification
• $: Relative address specification
• [ ]: Indirect address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to
describe the #, !, $, and [ ] symbols.
For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in
parentheses in the table below, R0, R1, R2, etc.) can be used for description.
Table 24-1. Operand Identifiers and Description Methods
Identifier Description Method
r X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)
rp AX (RP0), BC (RP1), DE (RP2), HL (RP3)
sfr Special-function register symbolNote
sfrp Special-function register symbol (16-bit manipulatable register even addresses only)Note
saddr FE20H to FF1FH Immediate data or labels
saddrp FE20H to FF1FH Immediate data or labels (even address only)
addr16 0000H to FFFFH Immediate data or labels
(Only even addresses for 16-bit data transfer instructions)
addr11 0800H to 0FFFH Immediate data or labels
addr5 0040H to 007FH Immediate data or labels (even address only)
word 16-bit immediate data or label
byte 8-bit immediate data or label
bit 3-bit immediate data or label
RBn RB0 to RB3
Note Addresses from FFD0H to FFDFH cannot be accessed with these operands.
Remark For special-function register symbols, refer to Table 5-3 Special-Function Register List.
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24.1.2 Description of “operation” column
A: A register; 8-bit accumulator
X: X register
B: B register
C: C register
D: D register
E: E register
H: H register
L: L register
AX: AX register pair; 16-bit accumulator
BC: BC register pair
DE: DE register pair
HL: HL register pair
PC: Program counter
SP: Stack pointer
PSW: Program status word
CY: Carry flag
AC: Auxiliary carry flag
Z: Zero flag
RBS: Register bank select flag
IE: Interrupt request enable flag
( ): Memory contents indicated by address or register contents in parentheses
×H, ×L: Higher 8 bits and lower 8 bits of 16-bit register
: Logical product (AND)
: Logical sum (OR)
: Exclusive logical sum (exclusive OR)
: Inverted data
addr16: 16-bit immediate data or label
jdisp8: Signed 8-bit data (displacement value)
24.1.3 Description of “flag operation” column
(Blank): Not affected
0: Cleared to 0
1: Set to 1
×: Set/cleared according to the result
R: Previously saved value is restored
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Mnemonic Operands Byte Operation
24.2 Operation List
Clock Flag
Note 1 Note 2 ZACCY
r, #byte 2 4 – r ← byte
saddr, #byte 3 6 7 (saddr) ← byte
sfr, #byte 3 – 7 sfr ← byte
A, r Note 3 12 –A ← r
r, A Note 3 12 –r ← A
A, saddr 2 4 5 A ← (saddr)
saddr, A 2 4 5 (saddr) ← A
A, sfr 2 – 5 A ← sfr
sfr, A 2 – 5 sfr ← A
A, !addr16 3 8 9 A ← (addr16)
!addr16, A 3 8 9 (addr16) ← A
PSW, #byte 3 – 7 PSW ← byte ×××
A, PSW 2 – 5 A ← PSW
PSW, A 2 – 5 PSW ← A ×××
A, [DE] 1 4 5 A ← (DE)
[DE], A 1 4 5 (DE) ← A
A, [HL] 1 4 5 A ← (HL)
[HL], A 1 4 5 (HL) ← A
A, [HL + byte] 2 8 9 A ← (HL + byte)
[HL + byte], A 2 8 9 (HL + byte) ← A
A, [HL + B] 1 6 7 A ← (HL + B)
[HL + B], A 1 6 7 (HL + B) ← A
A, [HL + C] 1 6 7 A ← (HL + C)
[HL + C], A 1 6 7 (HL + C) ← A
XCH A, r Note 3 12 –A ↔ r
A, saddr 2 4 6 A ↔ (saddr)
A, sfr 2 – 6 A ↔ sfr
A, !addr16 3 8 10 A ↔ (addr16)
A, [DE] 1 4 6 A ↔ (DE)
A, [HL] 1 4 6 A ↔ (HL)
A, [HL + byte] 2 8 10 A ↔ (HL + byte)
A, [HL + B] 2 8 10 A ↔ (HL + B)
A, [HL + C] 2 8 10 A ↔ (HL + C)
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed.
3. Except "r = A"
Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control
register (PCC) register.
Instruction
Group
MOV
8-bit data
transfer
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CHAPTER 24 INSTRUCTION SET
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Clock Flag
Note 1 Note 2 ZACCY
MOVW rp, #word 3 6 – rp ← word
saddrp, #word 4 8 10 (saddrp) ← word
sfrp, #word 4 – 10 sfrp ← word
AX, saddrp 2 6 8 AX ← (saddrp)
saddrp, AX 2 6 8 (saddrp) ← AX
AX, sfrp 2 – 8 AX ← sfrp
sfrp, AX 2 – 8 sfrp ← AX
AX, rp Note 3 1 4 – AX ← rp
rp, AX Note 3 1 4 – rp ← AX
AX, !addr16 3 10 12 AX ← (addr16)
!addr16, AX 3 10 12 (addr16) ← AX
XCHW AX, rp Note 3 1 4 – AX ↔ rp
ADD A, #byte 2 4 – A, CY ← A + byte ×××
saddr, #byte 3 6 8 (saddr), CY ← (saddr) + byte ×××
A, r Note 4 2 4 – A, CY ← A + r ×××
r, A 2 4 – r, CY ← r + A ×××
A, saddr 2 4 5 A, CY ← A + (saddr) ×××
A, !addr16 3 8 9 A, CY ← A + (addr16) ×××
A, [HL] 1 4 5 A, CY ← A + (HL) ×××
A, [HL + byte] 2 8 9 A, CY ← A + (HL + byte) ×××
A, [HL + B] 2 8 9 A, CY ← A + (HL + B) ×××
A, [HL + C] 2 8 9 A, CY ← A + (HL + C) ×××
ADDC A, #byte 2 4 – A, CY ← A + byte + CY ×××
saddr, #byte 3 6 8 (saddr), CY ← (saddr) + byte + CY ×××
A, r Note 4 2 4 – A, CY ← A + r + CY ×××
r, A 2 4 – r, CY ← r + A + CY ×××
A, saddr 2 4 5 A, CY ← A + (saddr) + CY ×××
A, !addr16 3 8 9 A, CY ← A + (addr16) + CY ×××
A, [HL] 1 4 5 A, CY ← A + (HL) + CY ×××
A, [HL + byte] 2 8 9 A, CY ← A + (HL + byte) + CY ×××
A, [HL + B] 2 8 9 A, CY ← A + (HL + B) + CY ×××
A, [HL + C] 2 8 9 A, CY ← A + (HL + C) + CY ×××
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Only when rp = BC, DE or HL
4. Except "r = A"
Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control
register (PCC) register.
Mnemonic Operands Byte Operation
Instruction
Group
16-bit
data
transfer
8-bit
operation
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Clock Flag
Note 1 Note 2 ZACCY
SUB A, #byte 2 4 – A, CY ← A – byte ×××
saddr, #byte 3 6 8 (saddr), CY ← (saddr) – byte ×××
A, r Note 3 2 4 – A, CY ← A – r ×××
r, A 2 4 – r, CY ← r – A ×××
A, saddr 2 4 5 A, CY ← A – (saddr) ×××
A, !addr16 3 8 9 A, CY ← A – (addr16) ×××
A, [HL] 1 4 5 A, CY ← A – (HL) ×××
A, [HL + byte] 2 8 9 A, CY ← A – (HL + byte) ×××
A, [HL + B] 2 8 9 A, CY ← A – (HL + B) ×××
A, [HL + C] 2 8 9 A, CY ← A – (HL + C) ×××
SUBC A, #byte 2 4 – A, CY ← A – byte – CY ×××
saddr, #byte 3 6 8 (saddr), CY ← (saddr) – byte – CY ×××
A, r Note 3 2 4 – A, CY ← A – r – CY ×××
r, A 2 4 – r, CY ← r – A – CY ×××
A, saddr 2 4 5 A, CY ← A – (saddr) – CY ×××
A, !addr16 3 8 9 A, CY ← A – (addr16) – CY ×××
A, [HL] 1 4 5 A, CY ← A – (HL) – CY ×××
A, [HL + byte] 2 8 9 A, CY ← A – (HL + byte) – CY ×××
A, [HL + B] 2 8 9 A, CY ← A – (HL + B) – CY ×××
A, [HL + C] 2 8 9 A, CY ← A – (HL + C) – CY ×××
AND A, #byte 2 4 – A ← A byte ×
saddr, #byte 3 6 8 (saddr) ← (saddr) byte ×
A, r Note 3 24 –A ← A r×
r, A 2 4 – r ← r A×
A, saddr 2 4 5 A ← A (saddr) ×
A, !addr16 3 8 9 A ← A (addr16) ×
A, [HL] 1 4 5 A ← A(HL) ×
A, [HL + byte] 2 8 9 A ← A (HL + byte) ×
A, [HL + B] 2 8 9 A ← A (HL + B) ×
A, [HL + C] 2 8 9 A ← A (HL + C) ×
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except "r = A"
Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control
register (PCC) register.
Mnemonic Operands Byte Operation
Instruction
Group
8-bit
operation
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Clock Flag
Note 1 Note 2 ZACCY
OR A, #byte 2 4 – A ← A byte ×
saddr, #byte 3 6 8 (saddr) ← (saddr) byte ×
A, r Note 3 24 –A ← A r×
r, A 2 4 – r ← r A×
A, saddr 2 4 5 A ← A (saddr) ×
A, !addr16 3 8 9 A ← A (addr16) ×
A, [HL] 1 4 5 A ← A (HL) ×
A, [HL + byte] 2 8 9 A ← A (HL + byte) ×
A, [HL + B] 2 8 9 A ← A (HL + B) ×
A, [HL + C] 2 8 9 A ← A (HL + C) ×
XOR A, #byte 2 4 – A ← A byte ×
saddr, #byte 3 6 8 (saddr) ← (saddr) byte ×
A, r Note 3 24 –A ← A r×
r, A 2 4 – r ← r A×
A, saddr 2 4 5 A ← A (saddr) ×
A, !addr16 3 8 9 A ← A (addr16) ×
A, [HL] 1 4 5 A ← A (HL) ×
A, [HL + byte] 2 8 9 A ← A (HL + byte) ×
A, [HL + B] 2 8 9 A ← A (HL + B) ×
A, [HL + C] 2 8 9 A ← A (HL + C) ×
CMP A, #byte 2 4 – A – byte ×××
saddr, #byte 3 6 8 (saddr) – byte ×××
A, r Note 3 24 –A – r ×××
r, A 2 4 – r – A ×××
A, saddr 2 4 5 A – (saddr) ×××
A, !addr16 3 8 9 A – (addr16) ×××
A, [HL] 1 4 5 A – (HL) ×××
A, [HL + byte] 2 8 9 A – (HL + byte) ×××
A, [HL + B] 2 8 9 A – (HL + B) ×××
A, [HL + C] 2 8 9 A – (HL + C) ×××
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except "r = A"
Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control
register (PCC) register.
Mnemonic Operands Byte Operation
Instruction
Group
8-bit
operation
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Clock Flag
Note 1 Note 2 ZACCY
ADDW AX, #word 3 6 – AX, CY ← AX + word ×××
SUBW AX, #word 3 6 – AX, CY ← AX – word ×××
CMPW AX, #word 3 6 – AX – word ×××
MULU X 2 16 – AX ← A × X
DIVUW C 2 25 – AX (Quotient), C (Remainder) ← AX ÷ C
INC r12–r ← r + 1 ××
saddr 2 4 6 (saddr) ← (saddr) + 1 ××
DEC r12–r ← r – 1 ××
saddr 2 4 6 (saddr) ← (saddr) – 1 ××
INCW rp 1 4 – rp ← rp + 1
DECW rp 1 4 – rp ← rp – 1
Rotate ROR A, 1 1 2 – (CY, A7 ← A0, Am – 1 ← Am) × 1 time ×
ROL A, 1 1 2 – (CY, A0 ← A7, Am + 1 ← Am) × 1 time ×
RORC A, 1 1 2 – (CY ← A0, A7 ← CY, Am – 1 ← Am) × 1 time ×
ROLC A, 1 1 2 – (CY ← A7, A0 ← CY, Am + 1 ← Am) × 1 time ×
A3 – 0 ← (HL)3 – 0, (HL)7 – 4 ← A3 – 0,
(HL)3 – 0 ← (HL)7 – 4
A3 – 0 ← (HL)7 – 4, (HL)3 – 0 ← A3 – 0,
(HL)7 – 4 ← (HL)3 – 0
Decimal Adjust Accumulator after
Addition
Decimal Adjust Accumulator after
Subtract
MOV1 CY, saddr.bit 3 6 7 CY ← (saddr.bit) ×
CY, sfr.bit 3 – 7 CY ← sfr.bit ×
CY, A.bit 2 4 – CY ← A.bit ×
CY, PSW.bit 3 – 7 CY ← PSW.bit ×
CY, [HL].bit 2 6 7 CY ← (HL).bit ×
saddr.bit, CY 3 6 8 (saddr.bit) ← CY
sfr.bit, CY 3 – 8 sfr.bit ← CY
A.bit, CY 2 4 – A.bit ← CY
PSW.bit, CY 3 – 8 PSW.bit ← CY ××
[HL].bit, CY 2 6 8 (HL).bit ← CY
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control
register (PCC) register.
Mnemonic Operands Byte Operation
Instruction
Group
16-bit
operation
Increment/
decrement
ROR4 [HL] 2 10 12
ROL4 [HL] 2 10 12
ADJBA 24 – ×××
ADJBS 24 – ×××
BCD
adjust
Bit
manipulate
Multiply/
divide
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Clock Flag
Note 1 Note 2 ZACCY
AND1 CY, saddr.bit 3 6 7 CY ← CY (saddr.bit) ×
CY, sfr.bit 3 – 7 CY ← CY sfr.bit ×
CY, A.bit 2 4 – CY ← CY A.bit ×
CY, PSW.bit 3 – 7 CY ← CY PSW.bit ×
CY, [HL].bit 2 6 7 CY ← CY (HL).bit ×
OR1 CY, saddr.bit 3 6 7 CY ← CY (saddr.bit) ×
CY, sfr.bit 3 – 7 CY ← CY sfr.bit ×
CY, A.bit 2 4 – CY ← CY A.bit ×
CY, PSW.bit 3 – 7 CY ← CY PSW.bit ×
CY, [HL].bit 2 6 7 CY ← CY (HL).bit ×
XOR1 CY, saddr.bit 3 6 7 CY ← CY (saddr.bit) ×
CY, sfr.bit 3 – 7 CY ← CY sfr.bit ×
CY, A.bit 2 4 – CY ← CY A.bit ×
CY, PSW.bit 3 – 7 CY ← CY PSW.bit ×
CY, [HL].bit 2 6 7 CY ← CY (HL).bit ×
SET1 saddr.bit 2 4 6 (saddr.bit) ← 1
sfr.bit 3 – 8 sfr.bit ← 1
A.bit 2 4 – A.bit ← 1
PSW.bit 2 – 6 PSW.bit ← 1 ×××
[HL].bit 2 6 8 (HL).bit ← 1
CLR1 saddr.bit 2 4 6 (saddr.bit) ← 0
sfr.bit 3 – 8 sfr.bit ← 0
A.bit 2 4 – A.bit ← 0
PSW.bit 2 – 6 PSW.bit ← 0 ×××
[HL].bit 2 6 8 (HL).bit ← 0
SET1 CY 1 2 – CY ← 11
CLR1 CY 1 2 – CY ← 00
NOT1 CY 1 2 – CY ← CY ×
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control
register (PCC) register.
Mnemonic Operands Byte Operation
Instruction
Group
Bit
manipulate
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Clock Flag
Note 1 Note 2 ZACCY
CALL !addr16 3 7 – (SP – 1) ← (PC + 3)H, (SP – 2) ← (PC + 3)L,
PC ← addr16, SP ← SP – 2
CALLF !addr11 2 5 – (SP – 1) ← (PC + 2)H, (SP – 2) ← (PC + 2)L,
PC15 – 11 ← 00001, PC10 – 0 ← addr11,
SP ← SP – 2
CALLT [addr5] 1 6 – (SP – 1) ← (PC + 1)H, (SP – 2) ← (PC + 1)L,
PCH ← (00000000, addr5 + 1),
PCL ← (00000000, addr5),
SP ← SP – 2
BRK 1 6 – (SP – 1) ← PSW, (SP – 2) ← (PC + 1)H,
(SP – 3) ← (PC + 1)L, PCH ← (003FH),
PCL ← (003EH), SP ← SP – 3, IE ← 0
RET 16 –PCH ← (SP + 1), PCL ← (SP),
SP ← SP + 2
RETI 16 –PCH ← (SP + 1), PCL ← (SP), R R R
PSW ← (SP + 2), SP ← SP + 3
RETB 16 –PCH ← (SP + 1), PCL ← (SP), R R R
PSW ← (SP + 2), SP ← SP + 3
PUSH PSW 1 2 – (SP – 1) ← PSW, SP ← SP – 1
rp 1 4 – (SP – 1) ← rpH, (SP – 2) ← rpL,
SP ← SP – 2
POP PSW 1 2 – PSW ← (SP), SP ← SP + 1 R R R
rp 1 4 – rpH ← (SP + 1), rpL ← (SP),
SP ← SP + 2
MOVW SP, #word 4 – 10 SP ← word
SP, AX 2 – 8 SP ← AX
AX, SP 2 – 8 AX ← SP
BR !addr16 3 6 – PC ← addr16
$addr16 2 6 – PC ← PC + 2 + jdisp8
AX 2 8 – PCH ← A, PCL ← X
BC $addr16 2 6 – PC ← PC + 2 + jdisp8 if CY = 1
BNC $addr16 2 6 – PC ← PC + 2 + jdisp8 if CY = 0
BZ $addr16 2 6 – PC ← PC + 2 + jdisp8 if Z = 1
BNZ $addr16 2 6 – PC ← PC + 2 + jdisp8 if Z = 0
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control
register (PCC) register.
Mnemonic Operands Byte Operation
Instruction
Group
Uncondi-
tional
branch
Stack
manipulate
Conditional
branch
Call/return
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Clock Flag
Note 1 Note 2 ZACCY
BT saddr.bit, $addr16 3 8 9 PC ← PC + 3 + jdisp8 if (saddr.bit) = 1
sfr.bit, $addr16 4 – 11 PC ← PC + 4 + jdisp8 if sfr.bit = 1
A.bit, $addr16 3 8 – PC ← PC + 3 + jdisp8 if A.bit = 1
PSW.bit, $addr16 3 – 9 PC ← PC + 3 + jdisp8 if PSW.bit = 1
[HL].bit, $addr16 3 10 11 PC ← PC + 3 + jdisp8 if (HL).bit = 1
BF saddr.bit, $addr16 4 10 11 PC ← PC + 4 + jdisp8 if (saddr.bit) = 0
sfr.bit, $addr16 4 – 11 PC ← PC + 4 + jdisp8 if sfr.bit = 0
A.bit, $addr16 3 8 – PC ← PC + 3 + jdisp8 if A.bit = 0
PSW.bit, $addr16 4 – 11 PC ← PC + 4 + jdisp8 if PSW.bit = 0
[HL].bit, $addr16 3 10 11 PC ← PC + 3 + jdisp8 if (HL).bit = 0
BTCLR saddr.bit, $addr16 4 10 12 PC ← PC + 4 + jdisp8 if (saddr.bit) = 1
then reset (saddr.bit)
sfr.bit, $addr16 4 – 12 PC ← PC + 4 + jdisp8 if sfr.bit = 1
then reset sfr.bit
A.bit, $addr16 3 8 – PC ← PC + 3 + jdisp8 if A.bit = 1
then reset A.bit
PSW.bit, $addr16 4 – 12 PC ← PC + 4 + jdisp8 if PSW.bit = 1 ×××
then reset PSW.bit
[HL].bit, $addr16 3 10 12 PC ← PC + 3 + jdisp8 if (HL).bit = 1
then reset (HL).bit
DBNZ B, $addr16 2 6 – B ← B – 1, then
PC ← PC + 2 + jdisp8 if B ≠ 0
C, $addr16 2 6 – C ← C –1, then
PC ← PC + 2 + jdisp8 if C ≠ 0
saddr, $addr16 3 8 10 (saddr) ← (saddr) – 1, then
PC ← PC + 3 + jdisp8 if (saddr) ≠ 0
SEL RBn 2 4 – RBS1, 0 ← n
NOP 1 2 – No Operation
EI 2 – 6 IE ← 1 (Enable Interrupt)
DI 2 – 6 IE ← 0 (Disable Interrupt)
HALT 2 6 – Set HALT Mode
STOP 2 6 – Set STOP Mode
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control
register (PCC) register.
Mnemonic Operands Byte Operation
Instruction
Group
CPU
control
Condi-
tional
branch
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24.3 Instructions Listed by Addressing Type
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,
ROLC, ROR4, ROL4, PUSH, POP, DBNZ
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Second Operand
#byte A rNote sfr saddr
!addr16
PSW [DE] [HL]
[HL + byte]
$addr16
1 None
[HL + B]
First Operand
[HL + C]
A ADD MOV MOV MOV MOV MOV MOV MOV MOV ROR
ADDC XCH XCH XCH XCH XCH XCH XCH ROL
SUB ADD ADD ADD ADD ADD RORC
SUBC ADDC ADDC ADDC ADDC ADDC ROLC
AND SUB SUB SUB SUB SUB
OR SUBC SUBC SUBC SUBC SUBC
XOR AND AND AND AND AND
CMP OR OR OR OR OR
XOR XOR XOR XOR XOR
CMP CMP CMP CMP CMP
r MOV MOV INC
ADD DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
B, C DBNZ
sfr MOV MOV
saddr MOV MOV DBNZ INC
ADD DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
!addr16 MOV
PSW MOV MOV PUSH
POP
[DE] MOV
[HL] MOV ROR4
ROL4
[HL + byte] MOV
[HL + B]
[HL + C]
X
MULU
C
DIVUW
Note Except r = A
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(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second Operand
First Operand
AX ADDW MOVW MOVW MOVW MOVW MOVW
SUBW XCHW
CMPW
rp MOVW
MOVW
Note INCW
DECW
PUSH
POP
sfrp MOVW MOVW
saddrp MOVW MOVW
!addr16 MOVW
SP MOVW MOVW
Note Only when rp = BC, DE, HL
(3) Bit manipulation instructions
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
Second Operand
First Operand
A.bit MOV1 BT SET1
BF CLR1
BTCLR
sfr.bit MOV1 BT SET1
BF CLR1
BTCLR
saddr.bit MOV1 BT SET1
BF CLR1
BTCLR
PSW.bit MOV1 BT SET1
BF CLR1
BTCLR
[HL].bit MOV1 BT SET1
BF CLR1
BTCLR
CY MOV1 MOV1 MOV1 MOV1 MOV1 SET1
AND1 AND1 AND1 AND1 AND1 CLR1
OR1 OR1 OR1 OR1 OR1 NOT1
XOR1 XOR1 XOR1 XOR1 XOR1
#word AX rpNote sfrp saddrp !addr16 SP None
A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None
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AX !addr16 !addr11 [addr5] $addr16
(4) Call/instructions/branch instructions
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
Second Operand
First Operand
Basic instruction BR CALL CALLF CALLT BR
BR BC
BNC
BZ
BNZ
Compound BT
instruction BF
BTCLR
DBNZ
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
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CHAPTER 25 ELECTRICAL SPECIFICATIONS
Parameter Symbol Conditions Ratings Unit
Supply voltage VDD –0.3 to +7.0 V
VPPNote 1 –0.3 to +13.5 V
AVREF –0.3 to VDD + 0.3 V
AVSS –0.3 to +0.3 V
Input voltage VI1 P00 to P05, P07, P10 to P17, P25 to P27, –0.3 to VDD + 0.3 V
P30 to P37, P70 to P72, P80 to P87, P90 to P97,
P100 to P103, P110 to P117, X1, X2, XT2, RESET
VI2Note 1 A9 PROM programming mode –0.3 to +13.5 V
Output voltage VO–0.3 to VDD + 0.3 V
Analog input voltage VAN P10 to P17 Analog input pin AVSS – 0.3 to AVREF + 0.3 V
Output current, high IOH Per pin –10 mA
Total for P01 to P05, P10 to P17, P25 to P27, –15 mA
P70 to P72, P110 to P117
Total for P30 to P37, P80 to P87, P90 to P97, –15 mA
P100 to P103
Output current, low IOL Per pin Peak value 30 mA
r.m.s. value 15Note 2 mA
Total for P01 to P05, P10 to P17, Peak value 60 mA
P110 to P117 r.m.s. value 40Note 2 mA
Total for P30 to P37, Peak value 140 mA
P100 to P103 r.m.s. value 100Note 2 mA
Total for P25 to P27, P70 to P72, Peak value 50 mA
P80 to P87, P90 to P97 r.m.s. value 20Note 2 mA
Operating ambient temperature
TA–40 to +85 °C
Storage temperature Tstg –65 to +150 °C
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input capacitance CIN f = 1 MHz 15 pF
Output capacitance COUT Unmeasured pins returned 15 pF
I/O capacitance CIO
to 0 V. 15 pF
Absolute Maximum Ratings (TA = 25°C)
Notes 1.
µ
PD78P0308 and 78P0308Y only.
2. The root mean square (r.m.s.) value should be calculated as follows:
[r.m.s. value] = [Peak value] × Duty
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
Capacitance (TA = 25°C, VDD = VSS = 0 V)
√
<R>
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Main System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 2.0Note 5 to 5.5 V)
Notes 1. This is VPP pin in the case of
µ
PD78P0308 and 78P0308Y.
2. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
3. Time required to stabilize oscillation after reset or STOP mode release.
4. After VDD reaches oscillation voltage range MIN.
5. However, oscillation start voltage or higher and VDD = 2.0 V or higher (for external clock, VDD = 2.0 V or
higher).
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS1.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the system is operating on the subsystem clock,
wait until the oscillation stabilization time has been secured by the program before switching
back to the main system clock.
Remark For the resonator selection and oscillator constant of the
µ
PD78P0308 and 78P0308Y, customers are
required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
Resonator Recommended Parameter Conditions MIN. TYP. MAX. Unit
Circuit
Ceramic Oscillation VDD = Oscillation 1.0 5.0 MHz
resonator frequency (fX)Note 2 voltage range
Oscillation After VDD reaches 4 ms
stabilization timeNote 3 oscillation voltage range MIN.
Crystal Oscillation VDD = Oscillation 1 5 MHz
resonator frequency (fX)Note 2 voltage range
Oscillation 4.5 V ≤ VDD ≤ 5.5 VNote 4 10 ms
stabilization timeNote 3 2.0 V ≤ VDD < 4.5 VNote 4 30
External clock X1 input 1.0 5.0 MHz
frequency (fX)Note 2
X1 input high-/low- 85 500 ns
level width (tXH, tXL)
X1
X2
X1
X2
ICNote 1
C1
C2
R1
X1
X2
ICNote 1
C1
C2
R1
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CHAPTER 25 ELECTRICAL SPECIFICATIONS
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XT1 XT2
Subsystem Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 2.0Note 5 to 5.5 V)
Notes 1. This is VPP pin in the case of
µ
PD78P0308 and 78P0308Y.
2. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
3. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN.
4. After VDD reaches oscillation voltage range MIN.
5. However, oscillation start voltage or higher and VDD = 2.0 V or higher (for external clock, VDD = 2.0 V or
higher).
Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figure to avoid an adverse effect from wiring capacitance.
•Keep the wiring length as short as possible.
•Do not cross the wiring with the other signal lines.
•Do not route the wiring near a signal line through which a high fluctuating current flows.
•Always make the ground point of the oscillator capacitor the same potential as VSS1.
•Do not ground the capacitor to a ground pattern through which a high current flows.
•Do not fetch signals from the oscillator.
2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current
consumption, and is more prone to malfunction due to noise than the main system clock
oscillator. Particular care is therefore required with the wiring method when the subsystem
clock is used.
Remark For the resonator selection and oscillator constant, customers are required to either evaluate the oscillation
themselves or apply to the resonator manufacturer for evaluation.
Resonator Recommended Parameter Conditions MIN. TYP. MAX. Unit
Circuit
Crystal Oscillation VDD = Oscillation 32 32.768 35 kHz
resonator frequency (fXT)Note 2 voltage range
Oscillation 4.5 V ≤ VDD ≤ 5.5 VÑote 4 1.2 2 s
stabilization timeNote 3
2.0 V ≤ VDD < 4.5 VNote 4 10
External clock XT1 input 32 100 kHz
frequency (fXT)Note 2
XT1 input high-/low- 5 15
µ
s
level width (tXTH, tXTL)
R2
XT2
XT1
ICNote 1
C4
C3
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CHAPTER 25 ELECTRICAL SPECIFICATIONS
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Main system clock: Ceramic resonator (TA = –40 to +85°C):
µ
PD780306, 780306Y, 780308, 780308Y only
Manufacturer Product Name Frequency Recommended Circuit Constant Oscillation Voltage Range
(MHz) C1 (pF) C2 (pF) R1 (kΩ) MIN. (V) MAX. (V)
Matsushita EFOEC2004A5 2.00 On-chip On-chip 4.7 2.0 5.5
Electronics EFOEC3584A4 3.58 On-chip On-chip 0 2.0 5.5
Components
EFOEC4194A4 4.19 On-chip On-chip 0 2.0 5.5
Co., Ltd.
EFOEC4914A4 4.91 On-chip On-chip 0 2.0 5.5
EFOEC5004A4 5.00 On-chip On-chip 0 2.0 5.5
TDK Corp. CCR1000K2 1.00 150 150 0 2.0 5.5
CCR3.58MC3 3.58 On-chip On-chip 0 2.0 5.5
CCR4.19MC3 4.19 On-chip On-chip 0 2.0 5.5
CCR4.91MC3 4.91 On-chip On-chip 0 2.0 5.5
CCR5.0MC3 5.00 On-chip On-chip 0 2.0 5.5
Murata Mfg. CSB1000J 1.00 100 100 2.2 2.0 5.5
Co., Ltd. CSA2.00MG040 2.00 100 100 0 2.0 5.5
CST2.00MG040 2.00 On-chip On-chip 0 2.0 5.5
CSA3.58MG 3.58 30 30 0 2.0 5.5
CST3.58MGW 3.58 On-chip On-chip 0 2.0 5.5
CSA4.19MG 4.19 30 30 0 2.0 5.5
CST4.19MGW 4.19 On-chip On-chip 0 2.0 5.5
CSA4.91MG 4.91 30 30 0 2.0 5.5
CST4.91MGW 4.91 On-chip On-chip 0 2.0 5.5
CSA5.00MG 5.00 30 30 0 2.0 5.5
CST5.00MGW 5.00 On-chip On-chip 0 2.0 5.5
Caution The oscillator constant is a reference value based on evaluation in specific environments by the
resonator manufacturer. If the oscillator characteristics need to be optimized in the actual application,
request the resonator manufacturer for evaluation on the implementation circuit.
Note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the
oscillator. Use the internal operation conditions of the
µ
PD780308, 780308Y Subseries within the
specifications of the DC and AC characteristics.
Recommended Oscillator Constant
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DC Characteristics (TA = –40 to +85°C, VDD = 2.0 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input voltage, VIH1 P10 to P17, P30 to P32, 2.7 V ≤ VDD ≤ 5.5 V 0.7VDD VDD V
high P35 to P37, P80 to P87,
P90 to P97, P100 to P103 2.0 V ≤ VDD < 2.7 V 0.8VDD VDD V
VIH2 P00 to P05, P25 to P27, 2.7 V ≤ VDD ≤ 5.5 V 0.8VDD VDD V
P33, P34, P70 to P72,
P110 to P117, RESET 2.0 V ≤ VDD < 2.7 V 0.85VDD VDD V
VIH3 X1, X2 2.7 V ≤ VDD ≤ 5.5 V VDD – 0.5 VDD V
2.0 V ≤ VDD < 2.7 V VDD – 0.2 VDD V
VIH4 XT1/P07, XT2 4.5 V ≤ VDD ≤ 5.5 V 0.8VDD VDD V
2.7 V ≤ VDD < 4.5 V 0.9VDD VDD V
2.0 V ≤ VDD < 2.7 VNote 0.9VDD VDD V
Input voltage, VIL1 P10 to P17, P30 to P32, 2.7 V ≤ VDD ≤ 5.5 V 0 0.3VDD V
low P35 to P37, P80 to P87,
P90 to P97, P100 to P103 2.0 V ≤ VDD < 2.7 V 0 0.2VDD V
VIL2 P00 to P05, P25 to P27, 2.7 V ≤ VDD ≤ 5.5 V 0 0.2VDD V
P33, P34, P70 to P72,
P110 to P117, RESET 2.0 V ≤ VDD < 2.7 V 0 0.15VDD V
VIL3 X1, X2 2.7 V ≤ VDD ≤ 5.5 V 0 0.4 V
2.0 V ≤ VDD < 2.7 V 0 0.2 V
VIL4 XT1/P07, XT2 4.5 V ≤ VDD ≤ 5.5 V 0 0.2VDD V
2.7 V ≤ VDD < 4.5 V 0 0.1VDD V
2.0 V ≤ VDD < 2.7 VNote 0 0.1VDD V
Output voltage, VOH VDD = 4.5 to 5.5 V, IOH = –1 mA VDD – 1.0 VDD V
high IOH = –100
µ
AVDD – 0.5 VDD V
Output voltage, VOL1 P100 to P103 VDD = 4.5 to 5.5 V, 0.6 2.0 V
low IOL = 15 mA
P01 to P05, P10 to P17, VDD = 4.5 to 5.5 V, 0.4 V
P25 to P27, P30 to P37, IOL = 1.6 mA
P70 to P72, P80 to P87,
P90 to P97, P110 to P117
VOL2 SB0, SB1, SCK0 VDD = 4.5 to 5.5 V, 0.2VDD V
open-drain,
pulled up (R = 1 kΩ)
VOL3 IOL = 400
µ
A 0.5 V
Note When the XT1/P07 pin is used as P07, input the inverse phase of P07 to the XT2 pin.
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
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CHAPTER 25 ELECTRICAL SPECIFICATIONS
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Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input leakage ILIH1 VIN = VDD P00 to P05, P10 to P17, P25 to P27, 3
µ
A
current, high P30 to P37, P70 to P72, P80 to P87,
P90 to P97, P100 to P103,
P110 to P117, RESET
ILIH2 X1, X2, XT1/P07, XT2 20
µ
A
Input leakage ILIL1 VIN = 0 V P00 to P05, P10 to P17, P25 to P27, –3
µ
A
current, low P30 to P37, P70 to P72, P80 to P87,
P90 to P97, P100 to P103,
P110 to P117, RESET
ILIL2 X1, X2, XT1/P07, XT2 –20
µ
A
Output leakage ILOH VOUT = VDD 3
µ
A
current, high
Output leakage ILOL VOUT = 0 V –3
µ
A
current, low
Software R VIN = 0 V P01 to P05, P10 to P17, P25 to P27, 15 45 90 kΩ
pull-up P30 to P37, P70 to P72, P80 to P87,
resistance P90 to P97, P100 to P103, P110 to
P117
DC Characteristics (TA = –40 to +85°C, VDD = 2.0 to 5.5 V)
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
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DC Characteristics (TA = –40 to +85°C, VDD = 2.0 to 5.5 V):
µ
PD780306, 780306Y, 780308, 780308Y only
Parameter Symbol Conditions MIN. TYP. MAX. Unit
IDD1 VDD = 5.0 V ±10%Note 4 412mA
VDD = 3.0 V ±10%Note 5 0.6 1.8 mA
VDD = 2.2 V ±10%Note 5 0.35 1.05 mA
VDD = 5.0 V ±10%Note 4 6.5 19.5 mA
VDD = 3.0 V ±10%Note 5 0.8 2.4 mA
IDD2 VDD = 5.0 V ±10% 1.4 4.2 mA
VDD = 3.0 V ±10% 500 1500
µ
A
VDD = 2.2 V ±10% 280 840
µ
A
VDD = 5.0 V ±10% 1.6 4.8 mA
VDD = 3.0 V ±10% 650 1950
µ
A
IDD3 VDD = 5.0 V ±10% 60 120
µ
A
VDD = 3.0 V ±10% 32 64
µ
A
VDD = 2.2 V ±10% 24 48
µ
A
IDD4 VDD = 5.0 V ±10% 25 55
µ
A
VDD = 3.0 V ±10% 5 15
µ
A
VDD = 2.2 V ±10% 2.5 12.5
µ
A
IDD5 VDD = 5.0 V ±10% 1 30
µ
A
VDD = 3.0 V ±10% 0.5 10
µ
A
VDD = 2.2 V ±10% 0.3 10
µ
A
IDD6 VDD = 5.0 V ±10% 0.1 30
µ
A
VDD = 3.0 V ±10% 0.05 10
µ
A
VDD = 2.2 V ±10% 0.05 10
µ
A
5.00 MHz crystal oscillation
(fXX = 2.5 MHz)Note 2
operating mode
5.00 MHz crystal oscillation (fXX =
5.0 MHz)Note 3 operating mode
5.00 MHz crystal oscillation (fXX
= 2.5 MHz)Note 2
HALT mode
5.00 MHz crystal oscillation (fXX =
5.0 MHz)Note 3 HALT mode
32.768 kHz crystal oscillation
operating modeNote 6
32.768 kHz crystal oscillation
HALT modeNote 6
XT1 = VDD
STOP mode
When feedback resistor is connected
XT1 = VDD
STOP mode
When feedback resistor is disconnected
Supply
currentNote 1
Notes 1. Current flowing to the VDD pin. Not including the current flowing to the A/D converter, ports, on-chip
pull-up resistors, or LCD dividing resistors.
2. Main system clock fXX = fX/2 operation (when oscillation mode select register (OSMS) is set to 00H)
3. Main system clock fXX = fX operation (when OSMS is set to 01H)
4. High-speed mode operation (when processor clock control register (PCC) is set to 00H)
5. Low-speed mode operation (when PCC is set to 04H)
6. When the main system clock is stopped.
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DC Characteristics (TA = –40 to +85°C, VDD = 2.0 to 5.5 V):
µ
PD78P0308, 78P0308Y only
Parameter Symbol Conditions MIN. TYP. MAX. Unit
IDD1 VDD = 5.0 V ±10%Note 4 515mA
VDD = 3.0 V ±10%Note 5 0.7 2.1 mA
VDD = 2.2 V ±10%Note 5 0.4 1.2 mA
VDD = 5.0 V ±10%Note 4 927mA
VDD = 3.0 V ±10%Note 5 13mA
IDD2 VDD = 5.0 V ±10% 1.4 4.2 mA
VDD = 3.0 V ±10% 500 1500
µ
A
VDD = 2.2 V ±10% 280 840
µ
A
VDD = 5.0 V ±10% 1.6 4.8 mA
VDD = 3.0 V ±10% 650 1950
µ
A
IDD3 VDD = 5.0 V ±10% 135 270
µ
A
VDD = 3.0 V ±10% 95 190
µ
A
VDD = 2.2 V ±10% 70 140
µ
A
IDD4 VDD = 5.0 V ±10% 25 55
µ
A
VDD = 3.0 V ±10% 5 15
µ
A
VDD = 2.2 V ±10% 2.5 12.5
µ
A
IDD5 VDD = 5.0 V ±10% 1 30
µ
A
VDD = 3.0 V ±10% 0.5 10
µ
A
VDD = 2.2 V ±10% 0.3 10
µ
A
IDD6 VDD = 5.0 V ±10% 0.1 30
µ
A
VDD = 3.0 V ±10% 0.05 10
µ
A
VDD = 2.2 V ±10% 0.05 10
µ
A
5.00 MHz crystal oscillation
(fXX = 2.5 MHz)Note 2
operating mode
5.00 MHz crystal oscillation (fXX =
5.0 MHz)Note 3 operating mode
5.00 MHz crystal oscillation
(fXX = 2.5 MHz)Note 2
HALT mode
5.00 MHz crystal oscillation (fXX =
5.0 MHz)Note 3 HALT mode
32.768 kHz crystal oscillation
operating modeNote 6
32.768 kHz crystal oscillation
HALT modeNote 6
XT1 = VDD
STOP mode
When feedback resistor is connected
XT1 = VDD
STOP mode
When feedback resistor is disconnected
Supply
currentNote 1
Notes 1. Current flowing to the VDD pin. Not including the current flowing to the A/D converter, ports, on-chip pull-
up resistors, or LCD dividing resistors.
2. Main system clock fXX = fX/2 operation (when oscillation mode select register (OSMS) is set to 00H)
3. Main system clock fXX = fX operation (when OSMS is set to 01H)
4. High-speed mode operation (when processor clock control register (PCC) is set to 00H)
5. Low-speed mode operation (when PCC is set to 04H)
6. When the main system clock is stopped.
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CHAPTER 25 ELECTRICAL SPECIFICATIONS
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Parameter Symbol Conditions MIN. TYP. MAX. Unit
LCD drive voltage VLCD 2.5 VDD V
LCD dividing resistor RLCD 60 100 150 kΩ
LCD output voltage VODC IO = ±5
µ
AVLCD0 = VLCD 0±0.2 V
deviationNote (common) VLCD1 = VLCD × 2/3
LCD output voltage VODS IO = ±1
µ
AVLCD2 = VLCD × 1/3 0 ±0.2 V
deviationNote (segment) 2.5 V ≤ VLCD ≤ VDD
LCD Controller/Driver Characteristics (at Normal Operation)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
LCD drive voltage VLCD 2.0 VDD V
LCD dividing resistor RLCD 60 100 150 kΩ
LCD output voltage VODC IO = ±5
µ
AVLCD0 = VLCD 0±0.2 V
deviation
Note
(common) 2.0 V ≤ VLCD ≤ VDD
LCD output voltage VODS IO = ±1
µ
A0±0.2 V
deviation
Note
(segment)
(1) Static display mode (TA = –10 to +85°C, VDD = 2.0 to 5.5 V)
Note The voltage deviation is the difference between the output voltage and the corresponding ideal value of the
segment or common output (VLCDn; n = 0, 1, 2).
(2) 1/3 bias method (TA = –10 to +85°C, VDD = 2.5 to 5.5 V)
Note The voltage deviation is the difference between the output voltage and the corresponding ideal value of the
segment or common output (VLCDn; n = 0, 1, 2).
Parameter Symbol Conditions MIN. TYP. MAX. Unit
LCD drive voltage VLCD 2.7 VDD V
LCD dividing resistor RLCD 60 100 150 kΩ
LCD output voltage VODC IO = ±5
µ
AVLCD0 = VLCD 0±0.2 V
deviation
Note
(common) VLCD1 = VLCD × 1/2
LCD output voltage VODS IO = ±1
µ
AVLCD2 = VLCD1 0±0.2 V
deviationNote (segment) 2.7 V ≤ VLCD ≤ VDD
(3) 1/2 bias method (TA = –10 to +85°C, VDD = 2.7 to 5.5 V)
Note The voltage deviation is the difference between the output voltage and the corresponding ideal value of the
segment or common output (VLCDn; n = 0, 1, 2).
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CHAPTER 25 ELECTRICAL SPECIFICATIONS
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Parameter Symbol Conditions MIN. TYP. MAX. Unit
LCD drive voltage VLCD 2.0 VDD V
LCD dividing resistor RLCD 60 100 150 kΩ
LCD output voltage VODC IO = ±5
µ
AVLCD0 = VLCD 0±0.2 V
deviation
Note
(common) VLCD1 = VLCD × 2/3
LCD output voltage VODS IO = ±1
µ
AVLCD2 = VLCD × 1/3 0 ±0.2 V
deviation
Note
(segment) 2.0 V ≤ VLCD ≤ VDD
LCD Controller/Driver Characteristics (at Low-Voltage Operation)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
LCD drive voltage VLCD 2.0 VDD V
LCD dividing resistor RLCD 60 100 150 kΩ
LCD output voltage VODC IO = ±5
µ
AVLCD0 = VLCD 0±0.2 V
deviation
Note
(common) 2.0 V ≤ VLCD ≤ VDD
LCD output voltage VODS IO = ±1
µ
A0±0.2 V
deviation
Note
(segment)
(1) Static display mode (TA = –10 to +85°C, 2.0 V ≤ VDD < 3.4 V)
Note The voltage deviation is the difference between the output voltage and the corresponding ideal value of the
segment or common output (VLCDn; n = 0, 1, 2).
(2) 1/3 bias method (TA = –10 to +85°C, 2.0 V ≤ VDD < 3.4 V)
Note The voltage deviation is the difference between the output voltage and the corresponding ideal value of the
segment or common output (VLCDn; n = 0, 1, 2).
Parameter Symbol Conditions MIN. TYP. MAX. Unit
LCD drive voltage VLCD 2.0 VDD V
LCD dividing resistor RLCD 60 100 150 kΩ
LCD output voltage VODC IO = ±5
µ
AVLCD0 = VLCD 0±0.2 V
deviation
Note
(common) VLCD1 = VLCD × 1/2
LCD output voltage VODS IO = ±1
µ
AVLCD2 = VLCD1 0±0.2 V
deviation
Note
(segment) 2.0 V ≤ VLCD ≤ VDD
(3) 1/2 bias method (TA = –10 to +85°C, 2.0 V ≤ VDD < 3.4 V)
Note The voltage deviation is the difference between the output voltage and the corresponding ideal value of the
segment or common output (VLCDn; n = 0, 1, 2).
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CHAPTER 25 ELECTRICAL SPECIFICATIONS
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Parameter Symbol Conditions MIN. TYP. MAX. Unit
Cycle time TCY Operating on main system clock 2.7 V ≤ VDD ≤ 5.5 V 0.8 64
µ
s
(Min. instruction (fXX = 2.5 MHz)Note 1 2.0 V ≤ VDD < 2.7 V 2.0 64
µ
s
execution time) Operating on main system clock 3.5 V ≤ VDD ≤ 5.5 V 0.4 32
µ
s
(fXX = 5.0 MHz)Note 2 2.7 V ≤ VDD < 3.5 V 0.8 32
µ
s
Operating on subsystem clock 40Note 3 122 125
µ
s
TI00 input fTI00 tTI00 = tTIH00 + tTIL00 0 1/tTI00 MHz
frequency
TI00 input high-/ tTIH00, 3.5 V ≤ VDD ≤ 5.5 V
2/f
sam
+ 0.1
Note 4
µ
s
low-level width tTIL00 2.7 V ≤ VDD < 3.5 V
2/f
sam
+ 0.2
Note 4
µ
s
2.0 V ≤ VDD < 2.7 V
2/f
sam
+ 0.5
Note 4
µ
s
TI01 input fTI01 2.7 V ≤ VDD ≤ 5.5 V 0 100 kHz
frequency 2.0 V ≤ VDD < 2.7 V 0 50 kHz
TI01 input high-/ tTIH01, 2.7 V ≤ VDD ≤ 5.5 V 10
µ
s
low-level width tTIL01 2.0 V ≤ VDD < 2.7 V 20
µ
s
TI1, TI2 input fTI1 4.5 V ≤ VDD ≤ 5.5 V 0 4 MHz
frequency 2.0 V ≤ VDD < 4.5 V 0 275 kHz
TI1, TI2 input high-/
tTIH1, 4.5 V ≤ VDD ≤ 5.5 V 100 ns
low-level width
tTIL1 2.0 V ≤ VDD < 4.5 V 1.8
µ
s
Interrupt request tINTH, INTP0 3.5 V ≤ VDD ≤ 5.5 V
2/f
sam
+ 0.1
Note 4
µ
s
input high-/low- tINTL 2.7 V ≤ VDD < 3.5 V
2/f
sam
+ 0.2
Note 4
µ
s
level width 2.0 V ≤ VDD < 2.7 V
2/f
sam
+ 0.5
Note 4
µ
s
INTP1 to INTP5, P110 to P117 2.7 V ≤ VDD ≤ 5.5 V 10
µ
s
2.0 V ≤ VDD < 2.7 V 20
µ
s
RESET low-level tRSL 2.7 V ≤ VDD ≤ 5.5 V 10
µ
s
width 2.0 V ≤ VDD < 2.7 V 20
µ
s
AC Characteristics
(1) Basic operation (TA = –40 to +85°C, VDD = 2.0 to 5.5 V)
Notes 1. Main system clock fXX = fX/2 operation (when oscillation mode select register (OSMS) is set to 00H)
2. Main system clock fXX = fX operation (when OSMS is set to 01H)
3. This is the value when the external clock is used. The value is 114
µ
s (min.) when the crystal resonator
is used.
4. In combination with bits 0 (SCS0) and 1 (SCS1) of the sampling clock select register (SCS), selection of
fsam is possible between fXX/2N, fXX/32, fXX/64, and fXX/128 (when N = 0 to 4).
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CHAPTER 25 ELECTRICAL SPECIFICATIONS
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TCY vs. VDD (at main system clock fXX = fX/2 operation) TCY vs. VDD (at main system clock fXX = fX operation)
60
10
2.0
1.0
1023456
0.8
0.4
60
10
2.0
1.0
1023456
0.8
0.4
Supply voltage V
DD
[V]
Cycle time T
CY
[ s]
µ
Guaranteed
operation range
Supply voltage V
DD
[V]
Cycle time T
CY
[ s]
µ
Guaranteed
operation range
32
2.7 3.5
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CHAPTER 25 ELECTRICAL SPECIFICATIONS
User’s Manual U11377EJ3V0UD
(2) Serial interface (TA = –40 to +85°C, VDD = 2.0 to 5.5 V)
(a) Serial interface channel 0
(i) 3-wire serial I/O mode (SCK0...internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK0 cycle time tKCY1 4.5 V ≤ VDD ≤ 5.5 V 800 ns
2.7 V ≤ VDD < 4.5 V 1600 ns
2.0 V ≤ VDD < 2.7 V 3200 ns
SCK0 high-/low-level width tKH1, 4.5 V ≤ VDD ≤ 5.5 V tKCY1/2 – 50 ns
tKL1 2.0 V ≤ VDD < 4.5 V tKCY1/2 – 100 ns
SI0 setup time (to SCK0↑) tSIK1 4.5 V ≤ VDD ≤ 5.5 V 100 ns
2.7 V ≤ VDD < 4.5 V 150 ns
2.0 V ≤ VDD < 2.7 V 300 ns
SI0 hold time (from SCK0↑)tKSI1 400 ns
SO0 output delay time tKSO1 C = 100 pFNote 300 ns
from SCK0↓
Note C is the load capacitance of SCK0 and SO0 output lines.
Note C is the load capacitance of SO0 output line.
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK0 cycle time tKCY2 4.5 V ≤ VDD ≤ 5.5 V 800 ns
2.7 V ≤ VDD < 4.5 V 1600 ns
2.0 V ≤ VDD < 2.7 V 3200 ns
SCK0 high-/low-level width tKH2, 4.5 V ≤ VDD ≤ 5.5 V 400 ns
tKL2 2.7 V ≤ VDD < 4.5 V 800 ns
2.0 V ≤ VDD < 2.7 V 1600 ns
SI0 setup time (to SCK0↑)tSIK2 100 ns
SI0 hold time (from SCK0↑)tKSI2 400 ns
SO0 output delay time tKSO2 C = 100 pFNote 300 ns
from SCK0↓
SCK0 rise, fall time tR2, 1000 ns
tF2
(ii) 3-wire serial I/O mode (SCK0...external clock input)
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CHAPTER 25 ELECTRICAL SPECIFICATIONS
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(iii) SBI mode (SCK0...internal clock output):
µ
PD780306, 780308, 78P0308 only
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK0 cycle time tKCY3 4.5 V ≤ VDD ≤ 5.5 V 800 ns
2.0 V ≤ VDD < 4.5 V 3200 ns
SCK0 high-/low-level tKH3, 4.5 V ≤ VDD ≤ 5.5 V tKCY3/2 – 50 ns
width tKL3 2.0 V ≤ VDD < 4.5 V
tKCY3/2 – 150
ns
SB0, SB1 setup time tSIK3 4.5 V ≤ VDD ≤ 5.5 V 100 ns
(to SCK0↑) 2.0 V ≤ VDD < 4.5 V 300 ns
SB0, SB1 hold time tKSI3 tKCY3/2 ns
(from SCK0↑)
SB0, SB1 output delay tKSO3 R = 1 kΩ, 4.5 V ≤ VDD ≤ 5.5 V 0 250 ns
time from SCK0↓C = 100 pFNote 2.0 V ≤ VDD < 4.5 V 0 1000 ns
SB0, SB1↓ from SCK0↑tKSB tKCY3 ns
SCK0↓ from SB0, SB1↓tSBK tKCY3 ns
SB0, SB1 high-level tSBH tKCY3 ns
width
SB0, SB1 low-level tSBL tKCY3 ns
width
Note R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output lines.
(iv) SBI mode (SCK0...external clock input):
µ
PD780306, 780308, 78P0308 only
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK0 cycle time tKCY4 4.5 V ≤ VDD ≤ 5.5 V 800 ns
2.0 V ≤ VDD < 4.5 V 3200 ns
SCK0 high-/low-level tKH4, 4.5 V ≤ VDD ≤ 5.5 V 400 ns
width tKL4 2.0 V ≤ VDD < 4.5 V 1600 ns
SB0, SB1 setup time tSIK4 4.5 V ≤ VDD ≤ 5.5 V 100 ns
(to SCK0↑) 2.0 V ≤ VDD < 4.5 V 300 ns
SB0, SB1 hold time tKSI4 tKCY4/2 ns
(from SCK0↑)
SB0, SB1 output delay tKSO4 R = 1 kΩ, 4.5 V ≤ VDD ≤ 5.5 V 0 300 ns
time from SCK0↓C = 100 pFNote 2.0 V ≤ VDD < 4.5 V 0 1000 ns
SB0, SB1↓ from SCK0↑tKSB tKCY4 ns
SCK0↓ from SB0, SB1↓tSBK tKCY4 ns
SB0, SB1 high-level tSBH tKCY4 ns
width
SB0, SB1 low-level tSBL tKCY4 ns
width
SCK0 rise, fall time tR4,1000 ns
tF4
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.
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CHAPTER 25 ELECTRICAL SPECIFICATIONS
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(v) 2-wire serial I/O mode (SCK0...internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK0 cycle time tKCY5 R = 1 kΩ, 2.7 V ≤ VDD ≤ 5.5 V 1600 ns
C = 100 pFNote 2.0 V ≤ VDD < 2.7 V 3200 ns
SCK0 high-level width tKH5 2.7 V ≤ VDD ≤ 5.5 V tKCY5/2 – 160 ns
2.0 V ≤ VDD < 2.7 V tKCY5/2 – 190 ns
SCK0 low-level width tKL5 4.5 V ≤ VDD ≤ 5.5 V tKCY5/2 – 50 ns
2.0 V ≤ VDD < 4.5 V tKCY5/2 – 100 ns
SB0, SB1 setup time tSIK5 4.5 V ≤ VDD ≤ 5.5 V 300 ns
(to SCK0↑) 2.7 V ≤ VDD < 4.5 V 350 ns
2.0 V ≤ VDD < 2.7 V 400 ns
SB0, SB1 hold time tKSI5 600 ns
(from SCK0↑)
SB0, SB1 output delay tKSO5 300 ns
time from SCK0↓
Note R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output lines.
(vi) 2-wire serial I/O mode (SCK0...external clock input)
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK0 cycle time tKCY6 2.7 V ≤ VDD ≤ 5.5 V 1600 ns
2.0 V ≤ VDD < 2.7 V 3200 ns
SCK0 high-level width tKH6 2.7 V ≤ VDD ≤ 5.5 V 650 ns
2.0 V ≤ VDD < 2.7 V 1300 ns
SCK0 low-level width tKL6 2.7 V ≤ VDD ≤ 5.5 V 800 ns
2.0 V ≤ VDD < 2.7 V 1600 ns
SB0, SB1 setup time tSIK6 100 ns
(to SCK0↑)
SB0, SB1 hold time tKSI6 tKCY6/2 ns
(from SCK0↑)
SB0, SB1 output delay tKSO6 R = 1 kΩ, 4.5 V ≤ VDD ≤ 5.5 V 0 300 ns
time from SCK0↓C = 100 pFNote 2.0 V ≤ VDD < 4.5 V 0 500 ns
SCK0 rise, fall time tR6,1000 ns
tF6
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CHAPTER 25 ELECTRICAL SPECIFICATIONS
User’s Manual U11377EJ3V0UD
(vii) I2C bus mode (SCL...internal clock output):
µ
PD780306Y, 780308Y, 78P0308Y only
Note R and C are the load resistance and load capacitance of SCL, SDA0, and SDA1 output lines.
(viii) I2C bus mode (SCL...external clock input):
µ
PD780306Y, 780308Y, 78P0308Y only
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCL cycle time tKCY8 1000 ns
SCL high-/low-level width tKH8, tKL8 400 ns
SDA0, SDA1 setup time tSIK8 200 ns
(to SCL↑)
SDA0, SDA1 hold time tKSI8 0ns
(from SCL↓)
SDA0, SDA1 output delay tKSO8 R = 1 kΩ, 4.5 V ≤ VDD ≤ 5.5 V 0 300 ns
time from SCL↓C = 100 pFNote 2.0 V ≤ VDD < 4.5 V 0 500 ns
SDA0, SDA1↓ from SCL↑tKSB 200 ns
or SDA0, SDA1↑ from
SCL↑
SCL↓ from SDA0, SDA1↓tSBK 400 ns
SDA0, SDA1 high-level tSBH 500 ns
width
SCL rise, fall time tR8, tF8 1000 ns
Note R and C are the load resistance and load capacitance of SDA0 and SDA1 output lines.
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCL cycle time tKCY7 R = 1 kΩ, 2.7 V ≤ VDD ≤ 5.5 V 10
µ
s
C = 100 pFNote 2.0 V ≤ VDD < 2.7 V 20
µ
s
SCL high-level width tKH7 2.7 V ≤ VDD ≤ 5.5 V tKCY7 – 160 ns
2.0 V ≤ VDD < 2.7 V tKCY7 – 190 ns
SCL low-level width tKL7 4.5 V ≤ VDD ≤ 5.5 V tKCY7 – 50 ns
2.0 V ≤ VDD < 4.5 V tKCY7 – 100 ns
SDA0, SDA1 setup time tSIK7 2.7 V ≤ VDD ≤ 5.5 V 200 ns
(to SCL↑) 2.0 V ≤ VDD < 2.7 V 300 ns
SDA0, SDA1 hold time tKSI7 0ns
(from SCL↓)
SDA0, SDA1 output tKSO7 4.5 V ≤ VDD ≤ 5.5 V 0 300 ns
delay time from SCL↓2.0 V ≤ VDD < 4.5 V 0 500 ns
SDA0, SDA1↓ from tKSB 200 ns
SCL↑ or SDA0, SDA1↑
from SCL↑
SCL↓ from SDA0, SDA1↓tSBK 400 ns
SDA0, SDA1 high-level tSBH 500 ns
width
511
CHAPTER 25 ELECTRICAL SPECIFICATIONS
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(b) Serial interface channel 2
(i) 3-wire serial I/O mode (SCK2...internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK2 cycle time tKCY9 4.5 V ≤ VDD ≤ 5.5 V 800 ns
2.7 V ≤ VDD < 4.5 V 1600 ns
2.0 V ≤ VDD < 2.7 V 3200 ns
SCK2 high-/low-level width tKH9, 4.5 V ≤ VDD ≤ 5.5 V tKCY9/2 – 50 ns
tKL9 2.0 V ≤ VDD < 4.5 V tKCY9/2 – 100 ns
SI2 setup time (to SCK2↑) tSIK9 4.5 V ≤ VDD ≤ 5.5 V 100 ns
2.7 V ≤ VDD < 4.5 V 150 ns
2.0 V ≤ VDD < 2.7 V 300 ns
SI2 hold time (from SCK2↑)tKSI9 400 ns
SO2 output delay time tKSO9 C = 100 pFNote 300 ns
from SCK2↓
Note C is the load capacitance of SCK2 and SO2 output lines.
Note C is the load capacitance of SO2 output line.
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK2 cycle time tKCY10 4.5 V ≤ VDD ≤ 5.5 V 800 ns
2.7 V ≤ VDD < 4.5 V 1600 ns
2.0 V ≤ VDD < 2.7 V 3200 ns
SCK2 high-/low-level width tKH10, 4.5 V ≤ VDD ≤ 5.5 V 400 ns
tKL10 2.7 V ≤ VDD < 4.5 V 800 ns
2.0 V ≤ VDD < 2.7 V 1600 ns
SI2 setup time (to SCK2↑)tSIK10 100 ns
SI2 hold time (from SCK2↑)tKSI10 400 ns
SO2 output delay time tKSO10 C = 100 pFNote 300 ns
from SCK2↓
SCK2 rise, fall time tR10,1000 ns
tF10
(ii) 3-wire serial I/O mode (SCK2...external clock input)
512
CHAPTER 25 ELECTRICAL SPECIFICATIONS
User’s Manual U11377EJ3V0UD
Parameter Symbol Conditions MIN. TYP. MAX. Unit
ASCK cycle time tKCY11 4.5 V ≤ VDD ≤ 5.5 V 800 ns
2.7 V ≤ VDD < 4.5 V 1600 ns
2.0 V ≤ VDD < 2.7 V 3200 ns
ASCK high-/low-level tKH11, 4.5 V ≤ VDD ≤ 5.5 V 400 ns
width tKL11 2.7 V ≤ VDD < 4.5 V 800 ns
2.0 V ≤ VDD < 2.7 V 1600 ns
Transfer rate 4.5 V ≤ VDD ≤ 5.5 V 39063 bps
2.7 V ≤ VDD < 4.5 V 19531 bps
2.0 V ≤ VDD < 2.7 V 9766 bps
ASCK rise, fall time tR11,1000 ns
tF11
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate 4.5 V ≤ VDD ≤ 5.5 V 78125 bps
2.7 V ≤ VDD < 4.5 V 39063 bps
2.0 V ≤ VDD < 2.7 V 19531 bps
(iii) UART mode (dedicated baud rate generator output)
(iv) UART mode (external clock input)
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CHAPTER 25 ELECTRICAL SPECIFICATIONS
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(c) Serial interface channel 3
(i) 3-wire serial I/O mode (SCK3...internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK3 cycle time tKCY12 4.5 V ≤ VDD ≤ 5.5 V 800 ns
2.7 V ≤ VDD < 4.5 V 1600 ns
2.0 V ≤ VDD < 2.7 V 3200 ns
SCK3 high-/low-level width tKH12, 4.5 V ≤ VDD ≤ 5.5 V tKCY12/2 – 50 ns
tKL12 2.0 V ≤ VDD < 4.5 V
t
KCY12
/2 – 100
ns
SI3 setup time (to SCK3↑)tSIK12 4.5 V ≤ VDD ≤ 5.5 V 100 ns
2.7 V ≤ VDD < 4.5 V 150 ns
2.0 V ≤ VDD < 2.7 V 300 ns
SI3 hold time (from SCK3↑)tKSI12 400 ns
SO3 output delay time tKSO12 C = 100 pFNote 300 ns
from SCK3↓
Note C is the load capacitance of SCK3 and SO3 output lines.
Note C is the load capacitance of SO3 output line.
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK3 cycle time tKCY13 4.5 V ≤ VDD ≤ 5.5 V 800 ns
2.7 V ≤ VDD < 4.5 V 1600 ns
2.0 V ≤ VDD < 2.7 V 3200 ns
SCK3 high-/low-level width tKH13, 4.5 V ≤ VDD ≤ 5.5 V 400 ns
tKL13 2.7 V ≤ VDD < 4.5 V 800 ns
2.0 V ≤ VDD < 2.7 V 1600 ns
SI3 setup time (to SCK3↑)tSIK13 100 ns
SI3 hold time (from SCK3↑)tKSI13 400 ns
SO3 output delay time tKSO13 C = 100 pFNote 300 ns
from SCK3↓
SCK3 rise, fall time tR13,1000 ns
tF13
(ii) 3-wire serial I/O mode (SCK3...external clock input)
514
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t
TIL1
t
TIH1
1/f
TI1
TI1, TI2
AC Timing Test Points (Excluding X1, XT1 Input)
Clock Timing
TI Timing
0.8V
DD
0.2V
DD
0.8V
DD
0.2V
DD
Test points
t
XL
t
XH
1/f
X
V
IH3
(MIN.)
V
IL3
(MAX.)
t
XTL
t
XTH
1/f
XT
V
IH4
(MIN.)
V
IL4
(MAX.)
X1 input
XT1 input
TI00, TI01
tTIL00, tTIL01 tTIH00, tTIH01
1/fTI00, 01
515
CHAPTER 25 ELECTRICAL SPECIFICATIONS
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Serial Transfer Timing
3-wire serial I/O mode:
tKCYm
tKLm tKHm
SCK0, SCK2,
SCK3
SI0, SI2, SI3
SO0, SO2, SO3
tSIKm tKSIm
tKSOm
Input data
Output data
tRn tFn
m = 1, 2, 9, 10, 12, 13
n = 2, 10, 13
SBI mode (bus release signal transfer,
µ
PD780306, 780308, 78P0308 only):
SBI mode (command signal transfer,
µ
PD780306, 780308, 78P0308 only):
t
SIK3, 4
t
KCY3, 4
t
KL3, 4
t
KH3, 4
SCK0
t
SBL
t
SBH
t
KSB
t
SBK
t
KSI3, 4
t
KSO3, 4
SB0, SB1
t
R4
t
F4
t
SIK3, 4
t
KCY3, 4
t
KL3, 4
t
KH3, 4
SCK0
t
KSB
t
SBK
t
KSI3, 4
t
KSO3, 4
SB0, SB1
t
R4
t
F4
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2-wire serial I/O mode:
I2C bus mode (
µ
PD780306Y, 780308Y, 78P0308Y only):
tKSO5, 6
tSIK5, 6
tKCY5, 6
tKL5, 6 tKH5, 6
SCK0
tKSI5, 6
SB0, SB1
tR6 tF6
tKL7, 8
tSBH tSBK
tKH7, 8
tKSO7, 8
tKSI7, 8 tSBK
tSIK7, 8
tKSB tKSB
tF8 tR8 tKCY7, 8
SCL
SDA0, SDA1
UART mode:
ASCK
t
KCY11
t
KL11
t
KH11
t
R11
t
F11
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CHAPTER 25 ELECTRICAL SPECIFICATIONS
User’s Manual U11377EJ3V0UD
A/D Converter Characteristics (TA = –40 to +85°C, VDD = 2.0 to 5.5 V, AVSS = VSS = 0 V):
µ
PD78P0308, 78P0308Y only
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 888bit
Overall errorNote 1 2.7 V ≤ AVREF ≤ 5.5 V ±0.6 %FSR
2.2 V ≤ AVREF < 2.7 V ±1.4 %FSR
Conversion time tCONV 2.7 V ≤ AVREF ≤ 5.5 V 19.1 200
µ
s
2.2 V ≤ AVREF < 2.7 V 38.2 200
µ
s
Sampling time tSAMP 24/fXX
µ
s
Analog input voltage VIAN AVSS AVREF V
Reference voltage AVREF 2.2 VDD V
AVREF-AVSS resistance RAIREF When A/D conversion not operating 4 14 kΩ
AVREF current AIREF When A/D conversion operatingNote 2 2.5 5.0 mA
When A/D conversion not operatingNote 3 0.5 1.5 mA
Notes 1. Quantization error (±1/2 LSB) is not included. This is expressed as a percentage (%FSR) to the full-scale
value.
2. Indicates current flowing to AVREF pin when the CS bit of the A/D converter mode register (ADM) is 1.
3. Indicates current flowing to AVREF pin when the CS bit of ADM is 0.
A/D Converter Characteristics (TA = –40 to +85°C, VDD = 2.0 to 5.5 V, AVSS = VSS = 0 V):
µ
PD780306, 780306Y, 780308, 780308Y only
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 888bit
Overall errorNote 1 2.7 V ≤ AVREF ≤ 5.5 V ±0.6 %FSR
2.0 V ≤ AVREF < 2.7 V ±1.4 %FSR
Conversion time tCONV 19.1 200
µ
s
Sampling time tSAMP 12/fXX
µ
s
Analog input voltage VIAN AVSS AVREF V
Reference voltage AVREF 2.0 VDD V
AVREF-AVSS resistance RREF When A/D conversion not operating 4 14 kΩ
AVREF current AIREF When A/D conversion operatingNote 2 2.5 5.0 mA
When A/D conversion not operatingNote 3 0.5 1.5 mA
Notes 1. Quantization error (±1/2 LSB) is not included. This is expressed as a percentage (%FSR) to the full-scale
value.
2. Indicates current flowing to AVREF pin when the CS bit of the A/D converter mode register (ADM) is 1.
3. Indicates current flowing to AVREF pin when the CS bit of ADM is 0.
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CHAPTER 25 ELECTRICAL SPECIFICATIONS
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Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention supply VDDDR 1.6 5.5 V
voltage
Data retention supply IDDDR VDDDR = 1.6 V 0.1 10
µ
A
current Subsystem clock stop and feedback
resistor disconnected.
Release signal set time tSREL 0
µ
s
Oscillation stabilization tWAIT Release by RESET 217/fx s
wait time Release by interrupt request Note s
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Note In combination with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS),
selection of 212/fXX and 214/fXX to 217/fXX is possible.
Data Retention Timing (STOP Mode Release by RESET)
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal)
t
SREL
t
WAIT
V
DD
RESET
STOP mode
Data retention mode
Internal reset operation
HALT mode
Operating mode
V
DDDR
STOP instruction execution
t
SREL
t
WAIT
V
DD
STOP instruction execution
STOP mode
Data retention mode
HALT mode
Operating mode
Standby release signal
(interrupt request)
V
DDDR
519
CHAPTER 25 ELECTRICAL SPECIFICATIONS
User’s Manual U11377EJ3V0UD
Interrupt Request Input Timing
RESET Input Timing
t
INTL
t
INTH
INTP0 to INTP5
tRSL
RESET
520
CHAPTER 25 ELECTRICAL SPECIFICATIONS
User’s Manual U11377EJ3V0UD
Characteristic Curves (Reference Value):
µ
PD780306, 780306Y, 780308, 780308Y only
10.0
PCC = 30H
HALT (X1 oscillation, XT1 oscillation)
PCC = 04H
PCC = 03H
PCC = 02H
PCC = 01H
(T
A
= 25°C)
I
DD
vs V
DD
(f
X
= f
XX
= 5.0 MHz)
5.0
1.0
0.5
0.1
Supply current I
DD
(mA)
Supply voltage V
DD
(V)
02345678
0.05
0.01
0.005
0.001
PCC = 00H
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CHAPTER 25 ELECTRICAL SPECIFICATIONS
User’s Manual U11377EJ3V0UD
10.0
PCC = 30H
HALT (X1 oscillation, XT1 oscillation)
HALT (X1 stopped, XT1 oscillation)
PCC = 04H
PCC = 03H
PCC = 02H
PCC = 01H
(T
A
= 25°C)
5.0
1.0
0.5
0.1
Supply current I
DD
(mA)
Supply voltage V
DD
(V)
I
DD
vs V
DD
(f
X
= 5.0 MHz, f
XX
= 2.5 MHz)
02345678
0.05
0.01
0.005
0.001
PCC = 00H
PCC = B0H
522
CHAPTER 25 ELECTRICAL SPECIFICATIONS
User’s Manual U11377EJ3V0UD
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input voltage, high VIH 0.7VDD VDD V
Input voltage, low VIL 0 0.3VDD V
Output voltage, high VOH1 IOH = –1 mA VDD – 1.0 V
VOH2 IOH = –100
µ
AVDD – 0.5 V
Output voltage, low VOL IOL = 1.6 mA 0.4 V
Input leakage current ILI 0 ≤ VIN ≤ VDD –10 +10
µ
A
Output leakage current ILO 0 ≤ VOUT ≤ VDD, OE = VIH –10 +10
µ
A
VPP supply voltage VPP VDD – 0.6 VDD VDD + 0.6 V
VDD supply voltage VDD 4.5 5.0 5.5 V
VPP supply current IPP VPP = VDD 100
µ
A
VDD supply current IDD CE = VIL, VIN = VIH 50 mA
PROM Programming Characteristics:
µ
PD78P0308, 78P0308Y only
DC Characteristics
(1) PROM write mode (TA = 25 ±5°C, VDD = 6.5 ±0.25 V, VPP = 12.5 ±0.3 V)
(2) PROM read mode (TA = 25 ±5°C, VDD = 5.0 ±0.5 V, VPP = VDD ±0.6 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input voltage, high VIH 0.7VDD VDD V
Input voltage, low VIL 0 0.3VDD V
Output voltage, high VOH IOH = –1 mA VDD – 1.0 V
Output voltage, low VOL IOL = 1.6 mA 0.4 V
Input leakage current ILI 0 ≤ VIN ≤ VDD –10 +10
µ
A
VPP supply voltage VPP 12.2 12.5 12.8 V
VDD supply voltage VDD 6.25 6.5 6.75 V
VPP supply current IPP PGM = VIL 50 mA
VDD supply current IDD 50 mA
523
CHAPTER 25 ELECTRICAL SPECIFICATIONS
User’s Manual U11377EJ3V0UD
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Address setup time (to PGM↓) tAS 2
µ
s
OE setup time tOES 2
µ
s
CE setup time (to PGM↓) tCES 2
µ
s
Input data setup time (to PGM↓) tDS 2
µ
s
Address hold time (from OE↑) tAH 2
µ
s
Input data hold time (from PGM↑) tDH 2
µ
s
Data output float delay time from OE↑tDF 0 250 ns
VPP setup time (to PGM↓) tVPS 1.0 ms
VDD setup time (to PGM↓) tVDS 1.0 ms
Program pulse width tPW 0.095 0.105 ms
Valid data delay time from OE↓tOE 1
µ
s
OE hold time tOEH 2
µ
s
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Address setup time (to OE↓) tAS 2
µ
s
OE setup time tOES 2
µ
s
CE setup time (to OE↓) tCES 2
µ
s
Input data setup time (to OE↓) tDS 2
µ
s
Address hold time (from OE↑) tAH 2
µ
s
tAHL 2
µ
s
tAHV 0
µ
s
Input data hold time (from OE↑) tDH 2
µ
s
Data output float delay time from OE↑tDF 0 250 ns
VPP setup time (to OE↓) tVPS 1.0 ms
VDD setup time (to OE↓) tVDS 1.0 250 ms
Program pulse width tPW 0.095 0.105 ms
Valid data delay time from OE↓tOE 1
µ
s
OE pulse width during data latching tLW 1
µ
s
PGM setup time tPGMS 2
µ
s
CE hold time tCEH 2
µ
s
OE hold time tOEH 2
µ
s
AC Characteristics
(1) PROM write mode
(a) Page program mode (TA = 25 ±5°C, VDD = 6.5 ±0.25 V, VPP = 12.5 ±0.3 V)
(b) Byte program mode (TA = 25 ±5°C, VDD = 6.5 ±0.25 V, VPP = 12.5 ±0.3 V)
524
CHAPTER 25 ELECTRICAL SPECIFICATIONS
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Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data output delay time from address tACC CE = OE = VIL 800 ns
Data output delay time from CE↓tCE OE = VIL 800 ns
Data output delay time from OE↓tOE CE = VIL 200 ns
Data output float delay time from OE↑tDF CE = VIL 060ns
Data hold time from address tOH CE = OE = VIL 0ns
(2) PROM read mode (TA = 25 ±5°C, VDD = 5.0 ±0.5 V, VPP = VDD ±0.6 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
PROM programming mode setup time tSMA 10
µ
s
(3) PROM programming mode setting (TA = 25°C, VSS = 0 V)
525
CHAPTER 25 ELECTRICAL SPECIFICATIONS
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PROM Write Mode Timing (Page Program Mode)
A2 to A16
A0, A1
D0 to D7
VDD
VPP
VPP
VDD
VDD + 1.5
VDD
VIL
VIH
CE
VIL
VIH
PGM
VIL
VIH
OE
tAS
Page data latch Page program Program verify
Data
output
Data input
tAHL
tDS tDH
tVPS
Hi-Z Hi-Z
tPGMS
tAHV
tDF
tAHtOE
tOEHtCES
tOES
tCEH
tPW
tVDS
tLW
Hi-Z
526
CHAPTER 25 ELECTRICAL SPECIFICATIONS
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PROM Write Mode Timing (Byte Program Mode)
Notes 1. If you want to read within the tACC range, make the OE input delay time from the fall of CE the maximum
of tACC – tOE.
2. tDF is the time from when either OE or CE first reaches VIH.
Cautions 1. VDD should be applied before VPP, and cut after VPP.
2. VPP should not exceed +13.5 V, including overshoot.
3. Disconnection during application of 12.5 V to VPP may have an adverse effect on reliability.
PROM Read Mode Timing
A0 to A16
D0 to D7
VPP
VPP
VDD
VDD
VDD + 1.5
VDD
CE
VIH
VIL
PGM
VIH
VIL
OE
VIH
VIL
Program Program verify
Data input Data output
Hi-Z Hi-Z Hi-Z
tDF
tAH
tAS
tDS tDH
tVPS
tVDS
tCES tPW
tOEH
tOES tOE
CE
V
IH
V
IL
OE
V
IH
V
IL
D0 to D7
A0 to A16 Valid address
t
CE
Hi-Z Data output Hi-Z
t
ACCNote 1
t
OENote 1
t
OH
t
DFNote 2
527
CHAPTER 25 ELECTRICAL SPECIFICATIONS
User’s Manual U11377EJ3V0UD
PROM Programming Mode Setting Timing
RESET
0
V
DD
V
DD
0
V
DD
V
PP
A0 to A16 Valid address
t
SMA
528 User’s Manual U11377EJ3V0UD
CHAPTER 26 PACKAGE DRAWINGS
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
NOTE
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
D
G
16.00±0.20
14.00±0.20
0.50 (T.P.)
1.00
J
16.00±0.20
K
C 14.00±0.20
I 0.08
1.00±0.20
L0.50±0.20
F 1.00
N
P
Q
0.08
1.40±0.05
0.10±0.05
S100GC-50-8EU, 8EA-2
S 1.60 MAX.
H 0.22+0.05
−0.04
M 0.17+0.03
−0.07
R3°+7°
−3°
125
26
50
100
76
75 51
S
SN
J
detail of lead end
C D
A
B
R
K
M
L
P
I
S
Q
G
F
M
H
<R>
529
CHAPTER 26 PACKAGE DRAWINGS
User’s Manual U11377EJ3V0UD
80
81 50
100
131
30
51
100-PIN PLASTIC QFP (14x20)
HI
J
detail of lead end
M
QR
K
M
L
P
S
SN
G
F
NOTE
Each lead centerline is located within 0.15 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
D
G
23.6±0.4
20.0±0.2
0.30±0.10
0.6
H
17.6±0.4
I
C 14.0±0.2
0.15
J0.65 (T.P.)
K1.8±0.2
L0.8±0.2
F 0.8
P100GF-65-3BA1-4
N
P
Q
0.10
2.7±0.1
0.1±0.1
R5°±5°
S 3.0 MAX.
M 0.15+0.10
−0.05
C D
A
B
S
530 User’s Manual U11377EJ3V0UD
CHAPTER 27 RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the following recommended conditions.
For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales
representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Table 27-1. Surface Mounting Type Soldering Conditions
(1) 100-pin plastic QFP (14 × 20)
µ
PD780306GF-×××-3BA, 780306GF(A)-×××-3BA, 780306YGF-×××-3BA,
µ
PD780308GF-×××-3BA, 780308GF(A)-×××-3BA, 780308YGF-×××-3BA,
µ
PD78P0308GF-3BA, 78P0308YGF-3BA
Soldering Method Soldering Conditions Recommended
Condition Symbol
Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. IR35-00-3
(at 210°C or higher), Count: Three times or less
VPS Package peak temperature: 215°C, Time: 25 to 40 seconds VP15-00-3
(at 200°C or higher), Count: Three times or less
Wave soldering Solder bath temperature: 260°C max., Time: 10 seconds max., WS60-00-1
Count: Once, Preheating temperature: 120°C max. (package surface
temperature)
Partial heating Pin temperature: 350°C max., Time: 3 seconds max. (per pin row) −
(2) 100-pin plastic LQFP (fine pitch) (14 × 14)
µ
PD780306GC-×××-8EU, 780306YGC-×××-8EU,
µ
PD780308GC-×××-8EU, 780308YGC-×××-8EU
Soldering Method Soldering Conditions Recommended
Condition Symbol
Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. IR35-00-2
(at 210°C or higher), Count: Twice or less
VPS Package peak temperature: 215°C, Time: 25 to 40 seconds VP15-00-2
(at 200°C or higher), Count: Twice or less
Partial heating Pin temperature: 350°C max., Time: 3 seconds max. (per pin row) −
Caution Do not use different soldering methods together (except for partial heating).
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CHAPTER 27 RECOMMENDED SOLDERING CONDITIONS
User’s Manual U11377EJ3V0UD
(3) 100-pin plastic LQFP (fine pitch) (14 × 14)
µ
PD78P0308GC-8EU, 78P0308YGC-8EU
Soldering Method Soldering Conditions Recommended
Condition Symbol
Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. IR35-107-2
(at 210°C or higher), Count: Twice or less,
Exposure limit: 7 daysNote (after that, prebake at 125°C for 10 to 72 hours)
VPS Package peak temperature: 215°C, Time: 25 to 40 seconds VP15-107-2
(at 200°C or higher), Count: Twice or less,
Exposure limit: 7 daysNote (after that, prebake at 125°C for 10 to 72 hours)
Partial heating Pin temperature: 350°C max., Time: 3 seconds max. (per pin row) −
(4) 100-pin plastic QFP (14 × 20)
µ
PD780306GF-×××-3BA-A, 780306YGF-×××-3BA-A,
µ
PD780308GF-×××-3BA-A, 780308YGF-×××-3BA-A,
µ
PD78P0308GF-3BA-A, 78P0308YGF-3BA-A
Soldering Method Soldering Conditions Recommended
Condition Symbol
Infrared reflow Package peak temperature: 260°C, Time: 60 seconds max. IR60-203-3
(at 220°C or higher), Count: Three times or less, Exposure limit: 3 daysNote
(after that, prebake at 125°C for 20 to 72 hours)
Wave soldering For details, contact an NEC Electronics sales representative. −
Partial heating Pin temperature: 350°C max., Time: 3 seconds max. (per pin row) −
(5) 100-pin plastic LQFP (fine pitch) (14 × 14)
µ
PD780306GC-×××-8EU-A, 780306YGC-×××-8EU-A,
µ
PD780308GC-×××-8EU-A, 780308YGC-×××-8EU-A,
µ
PD78P0308GC-8EU-A, 78P0308YGC-8EU-A
Soldering Method Soldering Conditions Recommended
Condition Symbol
Infrared reflow Package peak temperature: 260°C, Time: 60 seconds max. IR60-207-3
(at 220°C or higher), Count: Three times or less, Exposure limit: 7 daysNote
(after that, prebake at 125°C for 20 to 72 hours)
Partial heating Pin temperature: 350°C max., Time: 3 seconds max. (per pin row) −
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
Remark Products that have the part numbers suffixed by “-A” are lead-free products.
532 User’s Manual U11377EJ3V0UD
APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for the development of systems which employ the
µ
PD780308,
780308Y Subseries.
Figure A-1 shows the configuration of the development tools.
•Support for PC98-NX series
Unless otherwise specified, products supported by IBM PC/ATTM compatible machines can be used for PC98-
NX series computers. When using PC98-NX series computers, refer to the description for IBM PC/AT
compatible machines.
•Windows
Unless otherwise specified, “Windows” means the following OSs.
• Windows 98
• Windows 2000
• Windows NTTM Ver. 4.0
• Windows XP
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APPENDIX A DEVELOPMENT TOOLS
User’s Manual U11377EJ3V0UD
Figure A-1. Configuration of Development Tools
Notes 1. The C library source file is not included in the software package.
2. The project manager PM plus is included in the assembler package.
PM plus is only used for Windows.
Language processing software
• Assembler package
• C compiler package
• Device file
• C library source file
Note 1
Debugging software
• Integrated debugger
• System simulator
Host machine (PC or EWS)
Interface adapter,
PC card interface, etc.
In-circuit emulator
Emulation board
Emulation probe
Conversion socket or
conversion adapter
Target system
PROM programmer
Programmer
adapter
On-chip PROM
product
• Software package
• Project manager
(Windows only)
Note 2
Software package
PROM
write environment
Control software
I/O board
Performance board
Power supply unit
534
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U11377EJ3V0UD
A.1 Software Package
SP78K0 This package contains various software tools for 78K/0 Series development.
Software package The following tools are included.
RA78K0, CC78K0, ID78K0-NS, SM78K0, and various device files
Part Number:
µ
S××××SP78K0
Remark ×××× in the part number differs depending on the OS used.
µ
S××××SP78K0
×××× Host Machine OS Supply Medium
AB17 PC-9800 series, Windows (Japanese version) CD-ROM
BB17 IBM PC/AT and compatibles Windows (English version)
A.2 Language Processing Software
RA78K0
Assembler package
CC78K0
C compiler package
DF78064Note 1
Device file
CC78K0-LNote 3
C library source file
Notes 1. The DF78064 can be used in common with the RA78K0, CC78K0, SM78K0, ID78K0-NS, and ID78K0.
2. The DF78064 is for the
µ
PD780308, 780308Y, 78064, and 78064Y Subseries.
3. CC78K0-L is not included in the software package (SP78K0).
This assembler converts programs written in mnemonics into object codes executable
with a microcontroller.
Further, this assembler is provided with functions capable of automatically creating
symbol tables and branch instruction optimization.
This assembler should be used in combination with a device file (DF78064) (sold
separately).
<Caution when using RA78K0 in PC environment>
This assembler package is a DOS-based application. It can also be used in Windows,
however, by using PM plus (included in assembler package) in Windows.
Part number:
µ
S××××RA78K0
This compiler converts programs written in C language into object codes executable with
a microcontroller.
This compiler should be used in combination with an assembler package and device file
(both sold separately).
<Caution when using CC78K0 in PC environment>
This C compiler package is a DOS-based application. It can also be used in Windows,
however, by using PM plus (included in assembler package) in Windows.
Part number:
µ
S××××CC78K0
This file contains information peculiar to the device.
This device file should be used in combination with tools (RA78K0, CC78K0, SM78K0,
ID78K0-NS, and ID78K0) (sold separately).
The corresponding OS and host machine differ depending on the tool used.
Part number:
µ
S××××DF78064Note 2
This is a source file of functions configuring the object library included in the C compiler
package.
This file is required to match the object library included in C compiler package to the
user’s specifications.
It does not depend on the operating environment because it is a source file.
Part number:
µ
S××××CC78K0-L
535
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U11377EJ3V0UD
Remark ×××× in the part number differs depending on the host machine and OS used.
µ
S××××RA78K0
µ
S××××CC78K0
µ
S××××CC78K0-L
×××× Host Machine OS Supply Medium
AB17 PC-9800 series, Windows (Japanese version) CD-ROM
BB17
IBM PC/AT and compatibles
Windows (English version)
3P17 HP9000 series 700TM HP-UXTM (Rel. 10.10)
3K17 SPARCstationTM SunOSTM (Rel. 4.1.4),
SolarisTM (Rel. 2.5.1)
µ
S××××DF78064
×××× Host Machine OS Supply Medium
AB13 PC-9800 series, Windows (Japanese version) 3.5-inch 2HD FD
BB13
IBM PC/AT and compatibles
Windows (English version)
A.3 Control Software
PM plus This is control software designed to enable efficient user program development in the
Project manager Windows environment. All operations used in development of a user program, such as
starting the editor, building, and starting the debugger, can be performed from PM plus.
<Caution>
PM plus is included in the assembler package (RA78K0).
It can only be used in Windows.
536
APPENDIX A DEVELOPMENT TOOLS
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A.4 PROM Programming Tools
A.4.1 Hardware
PG-1500Note This PROM programmer allows users to encode the PROM in single-chip microcontrollers
PROM programmer stand-alone or using a host machine. This requires connection of the accompanying board
and separately-sold PROM programmer adapter to the PROM programmer.
Besides internal PROMs, general discrete PROM devices whose capacities range from 256
Kb to 4 Mb can be programmed.
PA-78P0308GC This PROM programmer adapter is for the
µ
PD78P0308 and 78P0308Y, and should be
PROM programmer adapter connected to the PG-1500. This adapter is for a 100-pin plastic LQFP (GC-8EU type).
PA-78P0308GF This PROM programmer adapter is for the
µ
PD78P0308 and 78P0308Y, and should be
PROM programmer adapter connected to the PG-1500. This adapter is for a 100-pin plastic QFP (GF-3BA type).
Note Production discontinued
A.4.2 Software
PG-1500 controllerNote This software allows users to control the PG-1500 from a host machine which is connected
to the PG-1500 via serial/parallel interface cable(s).
Part Number:
µ
S××××PG1500
Note Production discontinued
Remark ×××× in the part number differs depending on the host machine and OS used.
µ
S××××PG1500
×××× Host Machine OS Supply Medium
5A13 PC-9800 series MS-DOS 3.5-inch 2HD
(Ver. 3.30 to Ver. 6.2Note 1)
7B13 IBM PC/AT and compatibles Note 2 3.5-inch 2HD
Notes 1. Although a task swap function is incorporated in MS-DOS Ver. 5.0 or
later, this function cannot be used with the above software.
2. The following OSs for IBM PCs are supported (Ver. 5.0 or later has a
task swap function, but this function cannot be used with the above
software).
OS Version
PC DOS Ver.5.02 to Ver.6.3
J6.1/V to J6.3/V (Only the English version is supported.)
MS-DOS Ver.5.0 to Ver.6.22
5.0/V to 6.2/V (Only the English version is supported.)
IBM DOSTM J5.02/V (Only the English version is supported.)
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A.5 Debugging Tools (Hardware)
A.5.1 When using in-circuit emulator IE-78K0-NS, IE-78K0-NS-A
IE-78K0-NS
In-circuit emulator
IE-78K0-NS-PA
Performance board
IE-78K0-NS-A
In-circuit emulator
IE-70000-MC-PS-B
Power supply unit
IE-70000-CD-IF-A
PC card interface
IE-70000-PC-IF-C
Interface adapter
IE-70000-PCI-IF-A
Interface adapter
IE-780308-NS-EM1
Emulation board
NP-100GC
NP-H100GC-TQ
Emulation probe
TGC-100SDW
Conversion adapter
NP-100GF-TQ
NP-H100GF-TQ
Emulation probe
TGF-100RBP
Conversion adapter
NP-100GF
Emulation probe
EV-9200GF-100
Conversion socket
(See Figures A-3
and A-4)
Remarks 1. NP-100GC, NP-100GF, NP-100GF-TQ, NP-H100GC-TQ, and NP-H100GF-TQ are products of
Naito Densei Machida Mfg. Co., Ltd.
Contact: Naito Densei Machida Mfg. Co., Ltd. +81-45-475-4191
2. TGC-100SDW and TGF-100RBP are products of TOKYO ELETECH CORPORATION.
Inquiry: Daimaru Kogyo, Ltd. Phone: Tokyo Electronics Dept. +81-3-3820-7112
Osaka Electronics 2nd Dept. +81-6-6244-6672
3. EV-9200GF-100 is sold in a set of five units.
4. TGC-100SDW and TGF-100RBP are sold in single units.
The in-circuit emulator serves to debug hardware and software when developing
application systems using a 78K/0 Series product. It can be used with an integrated
debugger (ID78K0-NS). This emulator should be used in combination with a power
supply unit, emulation probe, and interface adapter, which is required to connect this
emulator to the host machine.
This board is used for extending the IE-78K0-NS functions. With the addition of this
board, the addition of a coverage function, enhancement of tracer and timer functions,
and other such debugging function enhancements are possible.
In-circuit emulator that combines the IE-78K0-NS and IE-78K0-NS-PA
This adapter is used for supplying power from a 100 to 240 V AC outlet.
This is the PC card and interface cable required when using a notebook-type computer
as the IE-78K0-NS host machine (PCMCIA socket compatible).
This adapter is required when using an IBM PC/AT compatible computer as the IE-78K0-
NS host machine (ISA bus compatible).
This adapter is required when using a PC with a PCI bus as the IE-78K0-NS host
machine.
This board emulates the operations of the peripheral hardware peculiar to a device.
It should be used in combination with an in-circuit emulator.
This probe is used to connect the in-circuit emulator to the target system and is designed
for a 100-pin plastic LQFP (GC-8EU type). It should be used in combination with the
TGC-100SDW.
This conversion socket connects the NP-100GC or NP-H100GC-TQ to the target system
board designed to mount a 100-pin plastic LQFP (GC-8EU type).
This probe is used to connect the in-circuit emulator to the target system and is designed
for a 100-pin plastic QFP (GF-3BA type). It should be used in combination with the TGF-
100RBP.
This conversion socket connects the NP-100GF-TQ or NP-H100GF-TQ to the target
system board designed to mount a 100-pin plastic QFP (GF-3BA type).
This probe is used to connect the in-circuit emulator to the target system and is
designed for a 100-pin plastic QFP (GF-3BA type).
This conversion socket connects the NP-100GF to the target system board
designed to mount a 100-pin plastic QFP (GF-3BA type).
538
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U11377EJ3V0UD
A.5.2 When using in-circuit emulator IE-78001-R-ANote
IE-78001-R-ANote
In-circuit emulator
IE-70000-98-IF-C
Interface adapter
IE-70000-PC-IF-C
Interface adapter
IE-780308-R-EMNote
Emulation board
EP-78064GC-R
Emulation probe
TGC-100SDW
Conversion adapter
(See Figure A-2)
EP-78064GF-R
Emulation probe
EV-9200GF-100
Conversion socket
(See Figures A-3
and A-4)
Note Production discontinued
Remarks 1. TGC-100SDW is a product of TOKYO ELETECH CORPORATION.
Inquiry: Daimaru Kogyo, Ltd. Phone: Tokyo Electronics Dept. +81-3-3820-7112
Osaka Electronics 2nd Dept. +81-6-6244-6672
2. TGC-100SDW is sold in single units.
3. EV-9200GF-100 is sold in a set of five units.
This is an in-circuit emulator for debugging the hardware and software when an
application system using the 78K/0 Series is developed. It can be used with an
integrated debugger (ID78K0). This emulator is used with an emulation probe and
interface adapter for connecting a host machine.
This adapter is necessary when a PC-9800 series PC (except notebook type) is
used as the host machine for the IE-78001-R-A (C bus compatible).
This adapter is necessary when an IBM PC/AT or compatible machine is used as
the host machine for the IE-78001-R-A (ISA bus compatible).
This board is used with an in-circuit emulator to emulate device-specific peripheral
hardware.
This probe is for a 100-pin plastic LQFP (GC-8EU type) and connects an in-circuit
emulator and the target system.
This conversion adapter connects the EP-78064GC-R to the target system board
designed to mount a 100-pin plastic LQFP (GC-8EU type).
This probe is for a 100-pin plastic QFP (GF-3BA type) and connects an in-circuit
emulator and the target system.
This conversion socket connects the EP-78064GF-R to the target system board
designed to mount a 100-pin plastic QFP (GF-3BA type).
539
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U11377EJ3V0UD
A.6 Debugging Tools (Software)
SM78K0 This is a system simulator for the 78K/0 Series. The SM78K0 is Windows-based
System simulator software.
It is used to perform debugging at the C source level or assembler level while simulating
the operation of the target system on a host machine.
Use of the SM78K0 allows the execution of application logical testing and performance
testing on an independent basis from hardware development, thereby providing higher
development efficiency and software quality.
The SM78K0 should be used in combination with a device file (DF78064) (sold
separately).
Part Number:
µ
S××××SM78K0
ID78K0-NS This debugger supports the in-circuit emulators for the 78K/0 Series. The
Integrated debugger ID78K0-NS is Windows-based software.
(supporting in-circuit emulators It has improved C-compatible debugging functions and can display the results of
IE-78K0-NS and IE-78K0-NS-A) tracing with the source program using an integrating window function that associates
ID78K0 the source program, disassemble display, and memory display with the trace result.
Integrated debugger It should be used in combination with a device file (sold separately).
(supporting in-circuit emulator Part Number:
µ
S××××ID78K0-NS
IE-78001-R-A)
µ
S××××ID78K0
Remark ×××× in the part number differs depending on the host machine and OS used.
µ
S××××SM78K0
µ
S××××ID78K0-NS
µ
S××××ID78K0
×××× Host Machine OS Supply Medium
AB17 PC-9800 series, Windows (Japanese version) CD-ROM
BB17 IBM PC/AT and compatibles Windows (English version)
540
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U11377EJ3V0UD
A.7 Drawing for Conversion Adapter (TGC-100SDWNote)
Figure A-2. TGC-100SDWNote Drawing (For Reference Only)
ITEM MILLIMETERS INCHES
b 1.85±0.25 0.073±0.010
c 3.5 0.138
a 14.45 0.569
d 2.0 0.079
h 16.0 0.630
i 1.125±0.3 0.044±0.012
j 0~5°0.000~0.197°
e 3.9 0.154
f 0.25
g 4.5 0.177
TGC-100SDW-G1E
0.010
k 5.9 0.232
l 0.8 0.031
m 2.4 0.094
n 2.7 0.106
ITEM MILLIMETERS INCHES
B
0.5x24=12 0.020x0.945=0.472
C 0.5 0.020
A 21.55 0.848
D
0.5x24=12 0.020x0.945=0.472
H 10.9 0.429
I 13.3 0.524
J 15.7 0.618
E 15.0 0.591
F 21.55
G 3.55 0.140
0.848
K 18.1 0.713
L 13.75 0.541
M
0.5x24=12.0 0.020x0.945=0.472
Q 10.0 0.394
R 11.3 0.445
S 18.1 0.713
N 1.125±0.3 0.044±0.012
O 1.125±0.2
P 7.5 0.295
0.044±0.008
W 1.8 0.071
X C 2.0 C 0.079
Y 0.9 0.035
T 5.0 0.197
U 5.0
V 4- 1.3 4- 0.051
0.197
Z 0.3 0.012
φ
φφ
φ
φ
φ
φ
φ
φ
φ
φφ
H
A
B
C
I J K
G
F E D
N OL
MX
P Q R S
U
Protrusion height
W
V
k
I
m
n
Z
j
g
i
h
a
e
d
c
b
Y
f
X
T
Note Product of TOKYO ELETECH CORPORATION.
541
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U11377EJ3V0UD
A.8 Drawing and Footprint for Conversion Socket (EV-9200GF-100)
Figure A-3. EV-9200GF-100 Drawing (For Reference Only)
EV-9200GF-100
A
D
EB
F
1
No.1 pin index
M
N O
L
K
S
R
Q
I
H
G
P
C
J
EV-9200GF-100-G0
ITEM MILLIMETERS INCHES
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
24.6
21
15
18.6
4-C 2
0.8
12.0
22.6
25.3
6.0
16.6
19.3
8.2
8.0
2.5
2.0
0.35
2.3
1.5
0.969
0.827
0.591
0.732
4-C 0.079
0.031
0.472
0.89
0.996
0.236
0.654
0.76
0.323
0.315
0.098
0.079
0.014
0.091
0.059
φ
φ
φ
φ
542
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U11377EJ3V0UD
Figure A-4. EV-9200GF-100 Footprint (For Reference Only)
F
H
E
D
A
B
C
I
J
K
L
0.026 × 1.142=0.742
0.026 × 0.748=0.486
EV-9200GF-100-P1
ITEM MILLIMETERS INCHES
A
B
C
D
E
F
G
H
I
J
K
L
26.3
21.6
15.6
20.3
12±0.05
6±0.05
0.35±0.02
2.36±0.03
2.3
1.57±0.03
1.035
0.85
0.614
0.799
0.472
0.236
0.014
0.093
0.091
0.062
0.65±0.02 × 29=18.85±0.05
0.65±0.02 × 19=12.35±0.05
φ
+0.001
–0.002
+0.002
–0.002
+0.001
–0.002
+0.003
–0.002
+0.003
–0.002
+0.003
–0.002
+0.001
–0.001
+0.001
–0.002
φ
+0.001
–0.002
φ
φ
G
φ
φ
The dimensions of the mount pad for EV-9200
and that for target device (QFP) may be different
in some parts. For the recommended mount pad
dimensions for QFP, refer to the “Semiconductor
Device Mount Manual’’ website
(http://www.necel.com/pkg/en/mount/index.html).
Caution
543
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U11377EJ3V0UD
A.9 Notes on Target System Design
The following shows a diagram of the connection conditions between the emulation probe and conversion
adapter. Design your system making allowances for conditions such as the shape of parts mounted on the target
system, as shown below.
Among the products described in this appendix, NP-100GC, NP-H100GC-TQ, NP-100GF-TQ, and NP-
H100GF-TQ are products of Naito Densei Machida Mfg. Co., Ltd., and TGC-100SDW and TGF-100RBP are
products of TOKYO ELETECH CORPORATION.
Table A-1. Distance Between IE System and Conversion Adapter
Emulation Probe Conversion Adapter Distance Between IE System
and Conversion Adapter
NP-100GC TGC-100SDW 170 mm
NP-H100GC-TQ 370 mm
NP-100GF-TQ TGF-100RBP 170 mm
NP-H100GF-TQ 370 mm
Figure A-5. Distance Between IE System and Conversion Adapter (When Using 100GC)
Note Distance when using NP-100GC. This is 370 mm when using NP-H100GC-TQ.
In-circuit emulator
IE-78K0-NS or IE-78K0-NS-A
Emulation board:
IE-780308-NS-EM1
Conversion adapter: TGC-100SDW
Target system
CN5
Emulation probe
NP-100GC, NP-H100GC-TQ
170 mm
Note
544
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U11377EJ3V0UD
Figure A-6. Connection Conditions of Target System (When Using NP-100GC)
Figure A-7. Connection Conditions of Target System (When Using NP-H100GC-TQ)
Emulation probe
NP-100GC
23 mm
25 mm
40 mm 34 mm
Target system
21.55 mm Pin 1
11 mm
Emulation board
IE-780308-NS-EM1
21.55 mm
Conversion adapter
TGC-100SDW
Emulation probe
NP-H100GC-TQ
Emulation board
IE-780308-NS-EM1
23 mm
42 mm 45 mm
Target system
11 mm
25 mm 21.55 mm Pin 1 21.55 mm
Conversion adapter
TGC-100SDW
545
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U11377EJ3V0UD
Figure A-8. Distance Between IE System and Conversion Adapter (When Using 100GF)
Notes 1. Distance when using NP-100GF-TQ. This is 370 mm when using NP-H100GF-TQ.
2. This is the position of pin 1 when using NP-100GF-TQ.
3. This is the position of pin 1 when using NP-H100GF-TQ.
Figure A-9. Connection Conditions of Target System (When Using NP-100GF-TQ)
In-circuit emulator
IE-78K0-NS or IE-78K0-NS-A
Emulation board:
IE-780308-NS-EM1
Target system
CN5
Emulation probe
NP-100GF-TQ, NP-H100GF-TQ
170 mm
Note 1
Conversion adapter: TGF-100RBP
Note 2
Note 2 Note 3
Note 3
Emulation probe
NP-100GF-TQ
40 mm 34 mm
Target system
27.5 mm
Pin 1
11 mm
Emulation board
IE-780308-NS-EM1
21 mm
Conversion adapter
TGF-100RBP
546
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U11377EJ3V0UD
Figure A-10. Connection Conditions of Target System (When Using NP-H100GF-TQ)
Emulation probe
NP-H100GF-TQ
Emulation board
IE-780308-NS-EM1
42 mm 45 mm
Target system
11 mm
21 mm Pin 1 27.5 mm
Conversion adapter
TGF-100RBP
547
User’s Manual U11377EJ3V0UD
APPENDIX B REGISTER INDEX
B.1 Register Name Index
[A]
A/D converter input select register (ADIS) ... 239
A/D converter mode register (ADM) ... 237
A/D conversion result register (ADCR) ... 236
Asynchronous serial interface status register (ASIS) ... 359, 369
Asynchronous serial interface mode register (ASIM) ... 356, 366, 368, 382
[B]
Baud rate generator control register (BRGC) ... 360, 370, 383
[C]
Capture/compare control register 0 (CRC0) ... 155
Capture/compare register 00 (CR00) ... 149
Capture/compare register 01 (CR01) ... 149
Compare register 10 (CR10) ... 192
Compare register 20 (CR20) ... 192
[E]
8-bit timer mode control register (TMC1) ... 195
8-bit timer output control register (TOC1) ... 196
8-bit timer register 1 (TM1) ... 192
8-bit timer register 2 (TM2) ... 192
External interrupt mode register 0 (INTM0) ... 158, 438
External interrupt mode register 1 (INTM1) ... 240, 438
[I]
Internal expansion RAM size switching register (IXS) ... 471
Internal memory size switching register (IMS) ... 470
Interrupt mask flag register 0H (MK0H) ... 436
Interrupt mask flag register 0L (MK0L) ... 436
Interrupt mask flag register 1L (MK1L) ... 436, 454
Interrupt request flag register 0H (IF0H) ... 435
Interrupt request flag register 0L (IF0L) ... 435
Interrupt request flag register 1L (IF1L) ... 435, 454
Interrupt timing specify register (SINT) ... 261, 278, 295, 311, 320, 331
[K]
Key return mode register (KRM) ... 125, 455
548
APPENDIX B REGISTER INDEX
User’s Manual U11377EJ3V0UD
[L]
LCD display control register (LCDC) ... 406
LCD display mode register (LCDM) ... 403
[O]
Oscillation mode select register (OSMS) ... 132
Oscillation stabilization time select register (OSTS) ... 458
[P]
Port 0 (P0) ... 105
Port 1 (P1) ... 107
Port 2 (P2) ... 108, 110
Port 3 (P3) ... 112
Port 7 (P7) ... 113
Port 8 (P8) ... 115
Port 9 (P9) ... 116
Port 10 (P10) ... 117
Port 11 (P11) ... 118
Port mode register 0 (PM0) ... 121
Port mode register 1 (PM1) ... 121
Port mode register 2 (PM2) ... 121
Port mode register 3 (PM3) ... 121, 157, 197, 229, 233
Port mode register 7 (PM7) ... 121
Port mode register 8 (PM8) ... 121
Port mode register 9 (PM9) ... 121
Port mode register 10 (PM10) ... 121
Port mode register 11 (PM11) ... 121
Priority specify flag register 0H (PR0H) ... 437
Priority specify flag register 0L (PR0L) ... 437
Priority specify flag register 1L (PR1L) ... 437
Processor clock control register (PCC) ... 129
Pull-up resistor option register H (PUOH) ... 124
Pull-up resistor option register L (PUOL) ... 124
[R]
Receive buffer register (RXB) ... 354
[S]
Sampling clock select register (SCS) ... 159, 440
Serial bus interface control register (SBIC) ... 259, 264, 276, 295, 309, 315, 320, 329
Serial I/O shift register 0 (SIO0) ... 254, 303
Serial I/O shift register 3 (SIO3) ... 393
549
APPENDIX B REGISTER INDEX
User’s Manual U11377EJ3V0UD
Serial interface pin select register (SIPS) ... 364, 374
Serial operating mode register 0 (CSIM0) ... 257, 263, 275, 294, 307, 314, 319, 328
Serial operating mode register 2 (CSIM2) ... 355, 365, 367, 381
Serial operating mode register 3 (CSIM3) ... 395
16-bit timer mode control register (TMC0) ... 153
16-bit timer output control register (TOC0) ... 156
16-bit timer register (TM0) ... 150
Slave address register (SVA) ... 254, 304
[T]
Timer clock select register 0 (TCL0) ... 151, 227
Timer clock select register 1 (TCL1) ... 193
Timer clock select register 2 (TCL2) ... 212, 220, 231
Timer clock select register 3 (TCL3) ... 256, 306
Timer clock select register 4 (TCL4) ... 393
Transmit shift register (TXS) ... 354
[W]
Watch timer mode control register (TMC2) ... 215
Watchdog timer mode register (WDTM) ... 222
550
APPENDIX B REGISTER INDEX
User’s Manual U11377EJ3V0UD
B.2 Register Symbol Index
[A]
ADCR: A/D conversion result register ... 236
ADIS: A/D converter input select register ... 239
ADM: A/D converter mode register ... 237
ASIM: Asynchronous serial interface mode register ... 356, 366, 368, 382
ASIS: Asynchronous serial interface status register ... 359, 369
[B]
BRGC: Baud rate generator control register ... 360, 370, 383
[C]
CR00: Capture/compare register 00 ... 149
CR01: Capture/compare register 01 ... 149
CR10: Compare register 10 ... 192
CR20: Compare register 20 ... 192
CRC0: Capture/compare control register 0 ... 155
CSIM0: Serial operating mode register 0 ... 257, 263, 275, 294, 307, 314, 319, 328
CSIM2: Serial operating mode register 2 ... 355, 365, 367, 381
CSIM3: Serial operating mode register 3 ... 395
[I]
IF0H: Interrupt request flag register 0H ... 435
IF0L: Interrupt request flag register 0L ... 435
IF1L: Interrupt request flag register 1L ... 435, 454
IMS: Internal memory size switching register ... 470
INTM0: External interrupt mode register 0 ... 158, 438
INTM1: External interrupt mode register 1 ... 240, 438
IXS: Internal expansion RAM size switching register ... 471
[K]
KRM: Key return mode register ... 125, 455
[L]
LCDC: LCD display control register ... 406
LCDM: LCD display mode register ... 403
[M]
MK0H: Interrupt mask flag register 0H ... 436
MK0L: Interrupt mask flag register 0L ... 436
MK1L: Interrupt mask flag register 1L ... 436, 454
551
APPENDIX B REGISTER INDEX
User’s Manual U11377EJ3V0UD
[O]
OSMS: Oscillation mode select register ... 132
OSTS: Oscillation stabilization time select register ... 458
[P]
P0: Port 0 ... 105
P1: Port 1 ... 107
P2: Port 2 ... 108, 110
P3: Port 3 ... 112
P7: Port 7 ... 113
P8: Port 8 ... 115
P9: Port 9 ... 116
P10: Port 10 ... 117
P11: Port 11 ... 118
PCC: Processor clock control register ... 129
PM0: Port mode register 0 ... 121
PM1: Port mode register 1 ... 121
PM2: Port mode register 2 ... 121
PM3: Port mode register 3 ... 121, 157, 197, 229, 233
PM7: Port mode register 7 ... 121
PM8: Port mode register 8 ... 121
PM9: Port mode register 9 ... 121
PM10: Port mode register 10 ... 121
PM11: Port mode register 11 ... 121
PR0H: Priority specify flag register 0H ... 437
PR0L: Priority specify flag register 0L ... 437
PR1L: Priority specify flag register 1L ... 437
PUOH: Pull-up resistor option register H ... 124
PUOL: Pull-up resistor option register L ... 124
[R]
RXB: Receive buffer register ... 354
[S]
SBIC: Serial bus interface control register ... 259, 264, 276, 295, 309, 315, 320, 329
SCS: Sampling clock select register ... 159, 440
SINT: Interrupt timing specify register ... 261, 278, 295, 311, 320, 331
SIO0: Serial I/O shift register 0 ... 254, 303
SIO3: Serial I/O shift register 3 ... 393
SIPS: Serial interface pin select register ... 364, 374
SVA: Slave address register ... 254, 304
552
APPENDIX B REGISTER INDEX
User’s Manual U11377EJ3V0UD
[T]
TCL0: Timer clock select register 0 ... 151, 227
TCL1: Timer clock select register 1 ... 193
TCL2: Timer clock select register 2 ... 212, 220, 231
TCL3: Timer clock select register 3 ... 256, 306
TCL4: Timer clock select register 4 ... 393
TM0: 16-bit timer register ... 150
TM1: 8-bit timer register 1 ... 192
TM2: 8-bit timer register 2 ... 192
TMC0: 16-bit timer mode control register ... 153
TMC1: 8-bit timer mode control register ... 195
TMC2: Watch timer mode control register ... 215
TOC0: 16-bit timer output control register ... 156
TOC1: 8-bit timer output control register ... 196
TXS: Transmit shift register ... 354
[W]
WDTM: Watchdog timer mode register ... 222
553User’s Manual U11377EJ3V0UD
APPENDIX C REVISION HISTORY
C.1 Major Revisions in This Edition
Page Description
Throughout Deletion of the following part numbers
•
µ
PD780306GC(A)-×××-8EU
•
µ
PD780308GC(A)-×××-8EU
•
µ
PD78P0308KL-T
•
µ
PD78P0308YKL-T
Addition of the following part numbers (lead-free products)
•
µ
PD780306GF-×××-3BA-A
•
µ
PD780306GC-×××-8EU-A
•
µ
PD780306YGF-×××-3BA-A
•
µ
PD780306YGC-×××-8EU-A
•
µ
PD780308GF-×××-3BA-A
•
µ
PD780308GC-×××-8EU-A
•
µ
PD780308YGF-×××-3BA-A
•
µ
PD780308YGC-×××-8EU-A
•
µ
PD78P0308GF-3BA-A
•
µ
PD78P0308GC-8EU-A
•
µ
PD78P0308YGF-3BA-A
•
µ
PD78P0308YGC-8EU-A
p. 9 Modification of related documents
p. 26 Modification of 1.6 78K0 Series Lineup
p. 38 Modification of 2.6 78K0 Series Lineup
p. 82 Modification of Caution in Figure 5-9 Stack Pointer Configuration
p. 241 Modification of description of (5) in 14.4.1 Basic operations of A/D converter
p. 435 Addition of Caution 3 to 20.3 (1) Interrupt request flag registers (IF0L, IF0H, IF1L)
p. 443
Addition of description and Caution to 20.4.1 Non-maskable interrupt request acknowledge operation
p. 446 Addition of description to 20.4.2 Maskable interrupt request acknowledge operation
p. 495 Addition of CHAPTER 25 ELECTRICAL SPECIFICATIONS
p. 528 Addition of CHAPTER 26 PACKAGE DRAWINGS
p. 530 Addition of CHAPTER 27 RECOMMENDED SOLDERING CONDITIONS
p. 532 Modification of APPENDIX A DEVELOPMENT TOOLS
p. 553 Addition of C.1 Major Revisions in This Edition to APPENDIX C REVISION HISTORY
pp. 505 to 507 Deletion of APPENDIX B EMBEDDED SOFTWARE from the old edition
in old edition
<R>
554 User’s Manual U11377EJ3V0UD
APPENDIX C REVISION HISTORY
(1/2)
Edition Major Revision from Previous Edition Applied to:
2nd edition Addition of “
µ
PD780306(A), 780308(A) ... under planning” Throughout
Change of package as follows:
• Deletion of 100-pin plastic QFP (GC-7EA type)
• Addition of 100-pin plastic LQFP (GC-8EU type)
Change of minimum supply voltage from 1.8 to 2.0 V
• Addition of description on following subseries to 1.6 78K/0 Series CHAPTER 1 OUTLINE
Line-up (
µ
PD780308 Subseries)
µ
PD78075B, 78075BY, 780018, 780018Y, 780058, 780058Y,
78058F, 78058FY, 78054, 78054Y, 780964, 780924,
780228, 78044H, 78044F, 78098B, 780973, 78P0914
•2.5 Pin Configuration CHAPTER 2 OUTLINE
Addition of connection diagram of 100-pin plastic LQFP (
µ
PD780308Y Subseries)
(GC-8EU type)
Correction of following text in CHAPTER 5 CPU
• 5.1.4 Data memory addressing ARCHITECTURE
• 5.2.1 Control registers (a) Interrupt enable flag (IE),
(e) In-service priority flag (ISP)
• 5.3.1 Relative addressing
• 5.3.2 Immediate addressing
• 5.3.3 Table indirect addressing
• 5.4.2 Register addressing
• 5.4.6 Register indirect addressing
• 5.4.7 Based addressing
• 5.4.8 Based indexed addressing
• 7.3 Clock Generator Control Register CHAPTER 7 CLOCK
Change of Figure 7-3 Processor Clock Control Register Format GENERATOR
Addition of Table 7-2 Relation between CPU Clock and
Minimum Instruction Execution Time
• 9.4.1 8-bit timer/event counter mode CHAPTER 9 8-BIT TIMER/
Addition of Figure 9-10 Square Wave Output Operation Timing EVENT COUNTERS 1 AND 2
• Correction of text in 9.4.2 16-bit timer/event counter mode
Addition of Figure 9-13 Square Wave Output Operation Timing
• 11.2 Watchdog Timer Configuration CHAPTER 11 WATCHDOG
Change of Figure 11-1 Watchdog Timer Block Diagram TIMER
• 14.2 A/D Converter Configuration CHAPTER 14 A/D
Correction of Figure 14-1 A/D Converter Block Diagram CONVERTER
Addition of caution on voltage
• 15.1 Serial Interface Channel 0 Functions CHAPTER 15 SERIAL
Addition of caution on operation mode INTERFACE CHANNEL 0
• 15.3 Serial Interface Channel 0 Control Registers (
µ
PD780308 Subseries)
Addition of caution on operation mode
C.2 Revision History up to Previous Edition
Revisions up to the previous edition are shown below. The “Applied to:” column indicates the chapter in each edition
to which the revision was applied.
555User’s Manual U11377EJ3V0UD
APPENDIX C REVISION HISTORY
(2/2)
Edition Major Revision from Previous Edition Applied to:
2nd edition • 16.1 Serial Interface Channel 0 Functions CHAPTER 16 SERIAL
Addition of caution on operation mode INTERFACE CHANNEL 0
• 16.3 Serial Interface Channel 0 Control Registers (
µ
PD780308Y Subseries)
Addition of caution on operation mode
• 17.4.2 Asynchronous serial interface (UART) mode CHAPTER 17 SERIAL
Change of Figure 17-11 Receive Error Timing INTERFACE CHANNEL 2
Correction of description on (3) UART mode cautions
• 17.4.3 3-wire serial I/O mode
Addition of Figure 17-14 Circuit of Switching in Transfer Bit
Order
• Addition of 17.4.4 Limitations of UART mode
• 18.4.2 3-wire serial I/O mode CHAPTER 18 SERIAL
Addition of description on selecting MSB/LSB first INTERFACE CHANNEL 3
Addition of Figure 18-5 Circuit of Switching in Transfer Bit
Order
• 20.3 Interrupt Function Control Registers CHAPTER 20 INTERRUPT
Change of Table 20-2 Various Flags Corresponding to AND TEST FUNCTIONS
Interrupt Request Sources
• 20.4 Interrupt Request Servicing Operations
Correction of Figure 20-11 Non-Maskable Interrupt Request
Acknowledge Timing
Correction of Figure 20-12 Non-Maskable Interrupt Request
Acknowledge Operation
Addition of description on flags to Figure 20-13 Interrupt
Request Acknowledge Processing Algorithm
• Correction of text in 20.4.4 Multiple interrupt request servicing
Correction of Figure 20-16 Multiple Interrupt Example
• Correction of text in 20.4.5 Interrupt request reserve
• 20.5 Test Functions
Correction of text in 20.5.2 Test input signal acknowledge
operation
• A.1 Language Processing Software APPENDIX A DEVELOPMENT
Change of part number of device file from “DF780308” to TOOLS
“DF78064”
• A.3 Debugging Tools
A.3.1 Hardware
Change of conversion adapter name from “EV-9500GC-100” to
“TGC-100SDW”
Deletion of 5-inch supply media supporting Windows
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Tel: 02-558-3737
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For further information,
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