1
LT1248
Power Factor Controller
–
+
–
+
–
+
I
M
=
I
A
2
I
B
200µA
2
V
CC
VA
OUT
16V TO 10V
2.6V/
2.2V
7.5V
7.9V
12µA5V
EA
V
REF
–
+
–
+
–
+
–
+
2.2V
32k
I
A
I
B
7µA
I
M
7.5V
V
REF
–
+
–
+
0.7V
ONE SHOT
200ns OSC
R
R
S
Q
C
SET
R
SET
13
6
11
8
10
79 5432 115
16
1214
SS
OVP
I
AC
V
SENSE
EN/SYNC
M
OUT
I
SENSE
CA
OUT
PK
LIM
V
CC
RUN
CA
RUN
1 6V
GND
–
+
GTDR
1248 BD
SYNC
M1
The LT
®
1248 provides active power factor correction for
universal off-line power systems. By using fixed high
frequency PWM current averaging, without the need for
slope compensation, the LT1248 achieves far lower line
current distortion with a smaller magnetic element than
systems that use either peak-current detection or zero
current switching approaches in both continuous and
discontinuous modes of operation.
The LT1248 uses a multiplier containing a square gain
function from the voltage amplifier to reduce the AC gain
at light output load and thus maintains low line current
distortion and high system stability. The LT1248 also
provides filtering capability to reject line switching noise
which can cause instability when fed into the multiplier.
Line current dead zone is minimized with low bias voltage
at the current input to the multiplier.
The LT1248 provides many protection features including
peak current limiting and overvoltage protection, and can
be operated at frequencies as high as 300kHz.
■
High Power Factor Over Wide Load Range
with Line Current Averaging
■
International Operation Without Switches
■
Instantaneous Overvoltage Protection
■
Minimal Line Current Dead Zone
■
Typical 250µA Start-Up Supply Current
■
Rejects Line Switching Noise
■
Synchronization Capability
■
Low Quiescent Current: 9mA
■
Fast 1.5A Peak Current Gate Driver
■
Universal Power Factor Corrected Power Supplies
■
Preregulators Up To 1500W
, LTC and LT are registered trademarks of Linear Technology Corporation.
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
BLOCK DIAGRA
W
2
LT1248
A
U
G
W
A
W
U
W
ARBSOLUTEXI T
IS
(Note 1)
Supply Voltage ....................................................... 27V
GTDR Current Continuous ..................................... 0.5A
GTDR Output Energy(Per Cycle) .............................. 5µJ
I
AC
, R
SET
, PK
LIM
Input Current............................. 20mA
V
SENSE
, EN/SYNC, OVP Input Voltage................... V
MAX
I
SENSE
, M
OUT
Input Current.................................. ±5mA
Operating Junction Temperature Range
LT1248C................................................ 0°C to 100°C
LT1248I ........................................... –40°C to 125°C
Thermal Resistance (Junction-to-Ambient)
N Package .................................................. 100°C/W
S Package................................................... 120°C/W
Storage Temperature Range ..................–65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
WU
U
PACKAGE/ORDER I FOR ATIO
ELECTRICAL C CHARA TERISTICS
ORDER PART
NUMBER
The
●
denotes specifications which apply over the full operating tempera-
ture range, otherwise specifications are at T
A
= 25°C. Maximum operating voltage (V
MAX
) = 25V, V
CC
= 18V, R
SET
= 15k to GND,
C
SET
= 1nF to GND, I
AC
= 100µA, I
SENSE
= 0V, CA
OUT
= 3.5V, VA
OUT
= 5V, OVP = 7.5V, no load on any outputs, unless otherwise noted.
LT1248CN
LT1248IN
LT1248CS
LT1248IS
T
JMAX
= 125°C, θ
JA
= 100°C/W (N)
T
JMAX
= 125°C, θ
JA
= 120°C/W (S)
Consult factory for Military grade parts.
1
2
3
4
5
6
7
8
TOP VIEW
N PACKAGE
16-LEAD PDIP
S PACKAGE
16-LEAD NARROW PLASTIC SO
16
15
14
13
12
11
10
9
GND
PK
LIM
CA
OUT
I
SENSE
M
OUT
I
AC
VA
OUT
OVP
GTDR
V
CC
C
SET
SS
R
SET
V
SENSE
EN/SYNC
V
REF
PARAMETER CONDITIONS MIN TYP MAX UNITS
Overall
Supply Current (V
CC
in Undervoltage Lockout) V
CC
= Lockout Voltage – 0.2V ●0.25 0.45 mA
Supply Current (Inactive) EN/SYNC = 0V, V
CC
≤ V
MAX
●0.5 1.5 mA
Supply Current, On 11.5V ≤ V
CC
≤ V
MAX
, CA
OUT
= 1V ●8.5 12.0 mA
V
CC
Turn-On Threshold (Undervoltage Lockout) ●15.5 16.5 17.5 V
V
CC
Turn-Off Threshold ●9.5 10.5 11.5 V
EN/SYNC Threshold, Rising ●2.2 2.6 2.85 V
EN/SYNC Threshold Hysteresis 0.40 V
EN/SYNC Input Current EN/SYNC = 0V ●–5 –1 5 µA
3V ≤ EN/SYNC ≤ 7V –50 – 25 50 µA
Voltage Amplifier
Voltage Amp Offset Voltage VA
OUT
= 3.5V ●–8 8 mV
Input Bias Current V
SENSE
= 0V to 7V ●–25 –250 nA
Voltage Gain 70 100 dB
Voltage Amp Unity-Gain Bandwidth 3 MHz
Voltage Amp Output High (Internally Clamped) ●11.3 13.3 V
Voltage Amp Output Low ●1.1 2 V
Voltage Amp Short-Circuit Current VA
OUT
= 0V ●51430 mA
SS Current SS = 2.5V ●51230 µA
Current Amplifier
Current Amp Offset Voltage ●±1±4mV
I
SENSE
Bias Current ●–25 –250 nA
Current Amp Voltage Gain 80 110 dB
Current Amp Unity-Gain Bandwidth 3 MHz
Current Amp Output High ●7.2 8.5 V
Current Amp Output Low ●1.1 2 V
3
LT1248
I
M
I
AC
(VA
OUT
– 2)
2
Note 2: Multiplier Gain Constant: K =
ELECTRICAL C CHARA TERISTICS
The
●
denotes specifications which apply over the full operating tempera-
ture range, otherwise specifications are at T
A
= 25°C. Maximum operating voltage (V
MAX
) = 25V, V
CC
= 18V, R
SET
= 15k to GND,
C
SET
= 1nF to GND, I
AC
= 100µA, I
SENSE
= 0V, CA
OUT
= 3.5V, VA
OUT
= 5V, OVP = 7.5V, no load on any outputs, unless otherwise noted.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired
PARAMETER CONDITIONS MIN TYP MAX UNITS
Current Amplifier
Current Amp Short-Circuit Current CA
OUT
= 0V ●51430 mA
Input Range, I
SENSE
, M
OUT
(Linear Operation) ●–0.3 1 V
Reference
Reference Output Voltage I
REF
= 0mA, T
A
= 25°C 7.39 7.50 7.60 V
V
REF
Load Regulation –5mA < I
REF
< 0mA 5 mV
V
REF
Line Regulation 11.5V < V
CC
< V
MAX
●–20 5 20 mV
V
REF
Short-Circuit Current V
REF
= 0V ●12 28 50 mA
V
REF
Worst Case Load, Line, Temperature ●7.32 7.5 7.68 V
Current Limit
PK
LIM
Offset Voltage ●–15 15 mV
PK
LIM
Input Current PK
LIM
= –0.1V ●–50 –100 µA
PK
LIM
to GTDR Propagation Delay PK
LIM
Falling from 50mV to –50mV 400 ns
Multiplier
Multiplier Output Current I
AC
= 100µA, R
SET
= 15k 35 µA
Multiplier Output Current Offset R
AC
= 1M from I
AC
to GND ●–0.05 –0.5 µA
Multiplier Maximum Output Current I
AC
= 450µA, R
SET
= 15k, VA
OUT
= 7V, M
OUT
= 0V ●–286 –260 –235 µA
Multiplier Gain Constant (Note 2) 0.035 V
–2
I
AC
Input Resistance I
AC
from 50µA to 1mA 15 32 50 kΩ
Oscillator
Oscillator Frequency R
SET
= 15k, C
SET
= 1000pF ●85 100 115 kHz
R
SET
= 15k, C
SET
= 1500pF ●58 68 78 kHz
C
SET
Ramp Peak-to-Peak Amplitude 4.35 4.7 5.0 V
C
SET
Ramp Valley Voltage 1.25 1.4 1.55 V
Synchronization Pulse Threshold on EN/SYNC Pin Pulse Low = 3.5V, High = 7V, Width > 200ns 4.5 5.6 6.5 V
Synchronization Frequency Range R
SET
= 15k, C
SET
= 1000pF ●1.2 1.6 f
NOM
Overvoltage Comparator
Comparator Trip Voltage Ratio (V
TRIP
/V
REF
)●1.04 1.05 1.06
Hysteresis 0.35 V
OVP Bias Current OVP = 7.5V ●–50 –250 nA
OVP Propagation Delay 100 ns
Gate Driver
Max GTDR Output Voltage 0mA Load, 18V < V
CC
●12 15 17.5 V
GTDR Output High –200mA Load, 11.5V ≤ V
CC
≤ 15V ●V
CC
– 3.0 V
GTDR Output Low (Device Unpowered) V
CC
= 0V, 50mA Load (Sinking) ●0.9 1.5 V
GTDR Output Low (Device Active) 200mA Load (Sinking) ●0.5 1 V
10mA Load ●0.2 0.4 V
Peak GTDR Current 10nF from GTDR to GND 2 A
GTDR Rise and Fall Time 1nF from GTDR to GND 25 ns
GTDR Max Duty Cycle 90 96 %
4
LT1248
CCHARA TERISTICS
UW
ATYPICALPER
FORCE
Reference Voltage vs
Temperature
JUNCTION TEMPERATURE (°C)
–75
REFERENCE VOLTAGE (V)
75
7.536
7.524
7.512
7.500
7.488
7.476
7.464
7.452
7.440
7.428
1248 G03
–50 150
–25 0 25 50 100 125
I
AC
(µA)
0
I
M
(µA)
300
150
0
1248 G04
250 500
VA
OUT
= 7V
VA
OUT
= 6.5V
VA
OUT
= 6V
VA
OUT
= 5.5V
VA
OUT
= 5V
VA
OUT
= 4.5V
VA
OUT
= 4V
VA
OUT
= 3.5V
VA
OUT
= 3V
VA
OUT
= 2.5V
SUPPLY VOLTAGE (V)
10
SUPPLY CURRENT (mA)
11
10
9
8
7
6
5
4
3
2
1
0
1248 G05
21 32
T
J
= 25°CT
J
= 125°C
T
J
= –55°C
Supply Current vs Supply Voltage GTDR Source Current
SINK CURRENT (mA)
0
GTDR VOLTAGE (V)
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1248 G07
300
T
A
= 125°C
T
A
= –55°C
60 120 180 240
T
A
= 25°C
FREQUENCY (Hz)
10
GAIN (dB)
100
80
60
40
20
0
–20 100 1k 10k 100k
1148 G01
1M 10M
0
–20
–40
–60
–80
–100
–120
PHASE (DEG)
PHASE
GAIN
Voltage Amplifier Open-Loop
Gain and Phase
FREQUENCY (Hz)
10
GAIN (dB)
100
80
60
40
20
0
–20 100 1k 10k 100k
1148 G02
1M 10M
0
–20
–40
–60
–80
–100
–120
PHASE (DEG)
PHASE
GAIN
Current Amplifier Open-Loop
Gain and Phase
Multiplier Current
SOURCE CURRENT (mA)
0
GTDR VOLTAGE (V)
18.5
18.0
17.5
17.0
16.5
16.0
15.5
15.0
14.5
14.0
13.5
13.0
1248 G06
–300
T
J
= 25°C
T
J
= 125°C
V
CC
= 18V
T
J
= –55°C
–60 –120 –180 –240
GTDR Sink Current
5
LT1248
CCHARA TERISTICS
UW
ATYPICALPER
FORCE
GTDR Rise and Fall Time
M
OUT
VOLTAGE (V)
M
OUT
CURRENT (mA)
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
1248 G15
2.4
1.2
0
–1.2
–2.4
T
J
= 125°C
T
J
= 25°C
T
J
= –55°C
Start-Up Supply Current vs
Supply Voltage
SUPPLY VOLTAGE (V)
0
SUPPLY CURRENT (µA)
550
500
450
400
350
300
250
200
150
100
50
0
1248 G09
20
125°C
–55°C
25°C
481216
2610
14 18
Frequency vs RSET and CSET
Shutdown Mode Supply Current
and Reference Voltage
Synchronization and Shutdown
Thresholds at EN/SYNC Pin
C
SET
CAPACITANCE (pF)
200
FREQUENCY (kHz)
500
450
400
350
300
250
200
150
100
50
0
1248 G10
1400 2200
600 1000 1800
R
SET
= 10k
R
SET
= 15k
R
SET
= 20k
R
SET
= 30k
C
SET
CAPACITANCE (pF)
200
MAXIMUM DUTY CYCLE
1.00
0.99
0.98
0.97
0.96
0.95
0.94
0.93
0.92
0.91
0.90
1248 G11
1400 2200
600 1000 1800
R
SET
= 10k
R
SET
= 15k
R
SET
= 20k
R
SET
= 30k
EN/SYNC VOLTAGE (V)
0
EN/SYNC CURRENT (µA)
–44
–40
–36
–32
–28
–24
–20
–16
–12
–8
–4
0
1248 G13
10
5
T
J
= 125°C
12346789
T
J
= 25°C
T
J
= –55°C
SHUTDOWN
THRESHOLD
SYNCHRONIZATION
THRESHOLD
SS VOLTAGE (V)
0
SS CURRENT (µA)
–22
–20
–18
–16
–14
–12
–10
–8
–6
–4
–2
0
1248 G14
T
J
= 25°C
T
J
= 125°C
T
J
= –55°C
48
MOUT Pin CharacteristicsSS Pin Characteristics
GTDR Maximum Duty Cycle vs
RSET and CSET
LOAD CAPACITANCE (nF)
0
TIME (ns)
400
300
200
100
010 20 30 40
1248 G08
50
RISE TIME
NOTE: GTDR SLEWS
BETWEEN 1V AND 16V
FALL TIME
SUPPLY VOLTAGE (V)
0
SUPPLY CURRENT (mA)
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1248 G12
32
16
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
REFERENCE VOLTAGE (V)
EN/SYNC ≤ 1.8V
REFERENCE VOLTAGE
T
J
≤ 125°C
T
J
= 125°C
–55°C ≤ T
J
≤ 25°C
SUPPLY CURRENT
6
LT1248
CCHARA TERISTICS
UW
ATYPICALPER
FORCE
R
SET
CURRENT (mA)
VR
SET
– V
REF
(mV)
120
100
80
60
40
20
0
–20
–40
–60
–80
–100
1248 G16
–1.0
–0.8
–0.6
–0.4
–0.2
0
T
J
= 125°C
T
J
= 25°C
T
J
= –55°C
PI FU CTIO S
U
UU
Pin 1 (GND).
Pin 2 (PK
LIM
): The threshold of the peak current limit
comparator is GND. To set current limit, a resistor divider
can be connected from V
REF
to current sense resistor.
Pin 3 (CA
OUT
): This is the output of the current amplifier
that senses and forces the line current to follow the
reference signal that comes from the multiplier by com-
manding the pulse width modulator. When CA
OUT
is low,
the modulator has zero duty cycle.
Pin 4 (I
SENSE
): This is the inverting input of the current
amplifier. This pin is clamped at –0.6V by an ESD protec-
tion diode.
Pin 5 (M
OUT
): This is the multiplier high impedance
current output and the noninverting input of the current
amplifier. This pin is clamped at –0.6V and 2V.
Pin 6 (I
AC
): This is the AC line voltage sensing input to the
multiplier. It is a current input that is biased at 2V to
minimize the crossover dead zone caused by low line
voltage. At the pin, a 32k resistor is in series with the
current input, so that a lowpass RC can be used to filter out
the switching noise from the high impedance lines.
Pin 7 (VA
OUT
): This is the output of the voltage error
amplifier. The output is clamped at 13.5V. When the
output goes below 2.5V, the multiplier output current is
zero.
Pin 8 (OVP): This is the input to the overvoltage compara-
tor. The threshold is 1.05 times the reference voltage.
When the comparator trips, the multiplier is quickly inhib-
ited and outputs no current. Figure 4 in the Applications
Information section shows how to set overvoltage thresh-
old with only one additional resistor.
Pin 9 (V
REF
): This is the 7.5V reference. When either V
CC
or EN/SYNC goes low, V
REF
will stay at 0V. V
REF
biases
most of the internal circuity and can source up to 5mA
externally.
Pin 10 (EN/SYNC): This pin has two functions. When it
goes below 2.6V, the chip goes into shutdown mode and
draws little current. Pulses at this pin that go below the 5V
threshold will synchronize the chip. The synchronizing
pulses should have an on-time of at least 200ns for the
LT1248 resetting circuit to work.
Pin 11 (V
SENSE
): This is the inverting input to the voltage
amplifier.
PK
LIM
VOLTAGE (V)
PK
LIM
CURRENT (µA)
–360
–300
–240
–180
–120
–60
0
60
120
180
240
300
1248 G17
0.8
0.4
0
–0.4
–0.8
T
J
= 125°C
T
J
= 25°C
T
J
= –55°C
PKLIM Pin Characteristics
RSET Voltage vs Current
7
LT1248
PI FU CTIO S
U
UU
Pin 12 (R
SET
): A resistor from R
SET
to GND sets the
oscillator charging current and the maximum multiplier
output current which is used to limit the maximum line
current.
I
M(MAX)
= 3.75V/R
SET
Pin 13 (SS): Soft-Start. When either V
CC
or EN/SYNC goes
low, the SS pin will stay at 0V. With a capacitor from the
pin to GND, the 12µA charging current slowly brings up the
SS to 8V; below 7.5V SS is the reference input to the
voltage amplifier. At supply dropout or EN/SYNC low, the
soft start capacitor will be quickly discharged.
Pin 14 (C
SET
): The capacitor from this pin to GND, and
R
SET
, determine oscillator frequency. The oscillator ramp
is 5V, and the frequency = 1.5/(R
SET
• C
SET
).
Pin 15 (V
CC
): This is the supply for the chip. The LT1248
has a very fast gate driver required to fast charge high
power MOSFET gate capacitance. High current spikes
occur during charging. For good supply bypass, a 0.1µF
ceramic capacitor in parallel with a low ESR electrolytic
capacitor, 56µF or higher is required in close proximity to
IC GND.
Pin 16 (GTDR): The MOSFET gate driver is a 1.5A fast
totem pole output. It is clamped at 15V, but capacitive
loads like MOSFET gates may cause overshoot. A gate
series resistor of at least 5Ω will prevent the overshoot.
I
AC
(µA)
0
I
M
(µA)
300
150
0
1248 G04
250 500
VA
OUT
= 7V
VA
OUT
= 6.5V
VA
OUT
= 6V
VA
OUT
= 5.5V
VA
OUT
= 5V
VA
OUT
= 4.5V
VA
OUT
= 4V
VA
OUT
= 3.5V
VA
OUT
= 3V
VA
OUT
= 2.5V
Figure 1. Multiplier Current IM vs IAC and VAOUT
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
Multiplier
The multiplier is a current multiplier with high noise
immunity in a high power switching environment. The
current gain is: I
M
= (I
AC
• I
EA2
)/(200µA)
2
, with I
EA
= (VA
OUT
– 2V)/25k. With a square function, because of the lower
gain at light power load, system stability is maintained and
line current distortion caused by the line frequency AC
Error Amplifier
The error amplifier has a 100dB DC gain and 3MHz unity-
gain frequency. The output is internally clamped at 13.5V.
The noninverting input is tied to the 7.5V V
REF
through a
diode and can be pulled down from the SS (soft-start) pin.
Current Amplifier
The current amplifier has a 110dB DC gain, 3MHz unity-
gain frequency, and a 2V/µs slew rate. It is internally
clamped at 8.5V. Note that in the current averaging opera-
tion, high gain at twice the line frequency is necessary to
minimize line current distortion. Because CA
OUT
may need
to swing 5V over one line cycle at high line condition,
14mV AC will be needed at the inputs of the current
amplifier for a gain of 350 at 120Hz. Especially at light load
when the current loop reference signal is small, lower gain
will distort the reference signal and line current. If signal
gain at switching frequency is too high, the system be-
haves more like a current mode system and can cause
subharmonic oscillation. Therefore, the current amplifier
should be compensated to have a gain of less than 15 at
the switching frequency, but more than 250 at twice the
line frequency.
8
LT1248
ripple fed back to the error amplifier is minimized. Note
that switching ripple on the high impedance lines could get
into the multiplier from the I
AC
pin and cause instability.
The LT1248 provides an internal 25k resistor in series with
the low impedance multiplier current input so that only a
capacitor from the I
AC
pin to GND is needed to filter out the
noise. The maximum multiplier output current, which
limits the system line current, is set by the R
SET
according
to the formula: I
M(MAX)
= 3.75V/R
SET
.
Oscillator Frequency and Maximum Line
Current Settling
Oscillator frequency is set by R
SET
and C
SET
. Ramp ampli-
tude is 5V and C
SET
charging current is set by V
REF
/R
SET
.
Typical discharging time for C
SET
= 1nF is 250ns. R
SET
should always be determined first to set the maximum
multiplier output current for system line current limit. For
a 300W preregulator, with R
SET
= 15k, I
M(MAX)
= 3.75V/15k
= 250µA. With a 4k resistor R
REF
from M
OUT
to the 0.2Ω
line current sense resistor R
S
, the line current limit is: (I
M
• 4k)/R
S
. As a general rule, R
S
is chosen according to:
R
S
= I
M(MAX)
• R
REF
• V
LINE(MIN)
K(1.414)P
OUT(MAX)
where P
OUT(MAX)
is the maximum power output and K is
usually between 1.1 and 1.3 depending on efficiency and
resistor tolerance. With R
SET
selected, C
SET
can then be
determined by: C
SET
= 1.5/(Frequency • R
SET
). For 100kHz,
C
SET
= 1.5/(100kHz • 15k) = 1nF. For optional double
protection, the LT1248 provides a current limit compara-
tor. When the comparator trips at 0V, the GTDR pin quickly
goes low to shut off the MOS switch. A resistor divider
from V
REF
to R
S
(Figure 2) senses the voltage across the
line current sense resistor and the current limit is set by:
I
LINE
= [(7.5V/R1) + 50µA](R2/R
S
), where 50µA is I
PKLIM
.
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
With I
LINE
and R
S
chosen, let R1 = 10k, then R2 =
(I
LINE
• R
S
)/0.8mA.
Always use R
SET
to set the primary line current limit. The
PK
LIM
comparator is only for secondary protection. The
secondary limit should be higher than the primary limit;
6.5A is good (5A for primary limit) for a 300W regulator.
When line current reaches the primary limit, V
OUT
drops to
keep the line current constant, and system stability is still
maintained by the current loop which is controlled by the
current amplifier. When line current reaches the second-
ary limit, the comparator controls the system and loop
hysteresis may occur and can cause audible noise.
Synchronization
The LT1248 can be synchronized to a frequency that is up
to 1.6 times the natural frequency. With a 200ns one-shot
timer on-chip, the LT1248 provides flexibility on the
synchronizing pulse width. Because the EN/SYNC pin also
serves the chip shutdown function, the pulses at the pin
should not go below 3V and must go below 5V with widths
greater than 200ns. The Figure 3 circuit will synchronize
the LT1248.
Figure 2
+
–
I
LINE
R
S
0.2
Ω
I
PKLIM
C1
1nF
7.5V V
REF
PK
LIM
C1 IS TO REJECT NOISE, CURRENT
LIMIT DELAY IS ABOUT 2µs.
R2
1.6k R1
10k
–
+
1248 F02
Overvoltage Protection
Because of the slow loop response necessary for power
factor correction, output overshoot can occur with sudden
load removal or reduction. To protect the power compo-
nents and output load, the LT1248 provides an overvolt-
age comparator which senses the output voltage and
quickly shuts off the current switch. In Figure 4, because
there is no DC current going through R3, R1 and R2 set the
regulator output DC level: V
OUT
= V
REF
[(R1 + R2)/R2], with
R1 = 1M, R2 = 20k, V
OUT
is 382V.
Figure 3
30k
V
REF
200k V
CC
1N4148
1N4685
3.6V
EN/SYNC
VN2222 SYNC PULSE
AT LEAST 200ns
1248 F03
9
LT1248
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
Note that V
SENSE
is the summing node and it stays at 7.5V.
When overshoot occurs on V
OUT
, the overcurrent from R1
will go through R2 as well as R3. Amplifier feedback will
keep V
SENSE
locked at 7.5V. The equivalent AC resistance,
seen by the comparator input pin OVP, is R2 in parallel
with R3, which is 10k. Therefore, with the comparator trip
level of 1.05V
REF
and R3 of 20k, the comparator trips when
V
OUT
overshoot exceeds 10%. Overvoltage trip level:
%%VRR
R
OUT
=+
523
3
M
OUT
is a high impedance current output. In the current
loop, offset line current is determined by multiplier offset
current and input offset voltage of the current amplifier.
A –4mV current amplifier V
OS
translates into 20mA line
current and 5W input power for 250V line if 0.2Ω sense
resistor is used. Under no load or when the load power is
less than this offset input power, V
OUT
would slowly
charge up to an overvoltage state because the overvoltage
comparator can only reduce multiplier output current to
zero. This does not guarantee zero output current if the
current amplifier has offset. To regulate V
OUT
under this
condition, the amplifier M1 (see Block Diagram), becomes
active in the current loop when VA
OUT
goes down to 2.2V.
The M1 can put out up to 7µA to the resistor at the I
SENSE
pin to cancel any current amplifier negative V
OS
and keep
V
OUT
error to within 2V.
Figure 6
V
CC
R1
90k
1W
18V
1248 F06
+
C3
390µFC4
56µF
+
LINE MAIN INDUCTOR
C2
1000pF
D3
D1
D2
Undervoltage Lockout
The LT1248 turns on when V
CC
is higher than 16V and
remains on until V
CC
falls below 10V, whereupon the chip
enters the lockout state. In the lockout state, the LT1248
only draws 250µA, the oscillator is off, and the V
REF
and
the GTDR pins remain low to keep the power MOSFET off.
Start-Up and Supply Voltage
The LT1248 draws only 250µA before the chip starts at
16V on V
CC
. To trickle start, a 90k resistor from the power
line to V
CC
supplies the trickle current and C4 holds the V
CC
up while switching starts. Then the auxiliary winding takes
over and supplies the operating current. Note that D3 and
the large value C3, in both Figures 5 and 6, are only
necessary for systems that have sudden large load varia-
tion down to minimum load and/or very light load condi-
tions. Under these conditions, the loop may exhibit a start/
restart mode because switching remains off long enough
for C4 to discharge below 10V. The C3 will hold V
CC
up
until switching resumes. For less severe load variations,
D3 is replaced with a short and C3 is omitted. The turns
ratio between the primary winding and the auxiliary wind-
ing determines V
CC
according to:
Figure 5
V
CC
N
P
N
S
R1
90k, 1W
C1
2µF
1248 F05
+
+
C2
2µF
C3
390µF
+
C4
56µF
+
LINE MAIN INDUCTOR
D2
D3D1
C1
0.47µF
V
REF
= 7.5V
1.05V
REF
OVERVOLTAGE
COMPARATOR
LT1248
R3
20k
330k
0.047µF
REGULATOR OUTPUT
V
OUT
= 382V
1248 F04
V
SENSE
OVP
VA
OUT
ERROR AMP
R1
1M
R2
20k
–
+
–
+
Figure 4
10
LT1248
The third component is the switching ripple from the load,
if the load is a switching regulator.
I
3RMS
≈ I
LOAD(DC)
For the United Chemicon KMH 400V capacitor series,
ripple current multiplier for currents at 100kHz is 1.43. The
equivalent 120Hz ripple current can be then found:
I
RMS
= (I
1RMS
)
2
+ (I
2RMS
/1.43)
2
+ (I
3RMS
/1.43)
2
For a typical system that runs at an average load of 200W
and 385V output:
I
LOAD(DC)
= 0.52A
I
1RMS
≈ 0.71 • 0.52A = 0.37A
I
2RMS
≈ 0.82A at 120VAC
I
3RMS
≈ I
LOAD(DC)
= 0.52A
I
RMS
= (0.37A)
2
+(0.82A/1.43)
2
+(0.52A/1.43)
2
= 0.77A
The 120Hz ripple current rating at 105°C ambient is 0.95A
for the 180µF KMH 400V capacitor. The expected life of the
output capacitor may be calculated from the thermal
stress analysis:
where:
L: expected life time
L
O
: hours of load life at rated ripple current and rated
ambient temperature.
∆T
K
: Capacitor internal temperature rise at rated condi-
tion. ∆T
K
= (I
2
R)/(KA). Where I is the rated current,
R is capacitor ESR, and KA is a volume constant.
T
A
: Operating ambient temperature.
∆T
O
: Capacitor internal temperature rise at operating
condition.
In our example L
O
= 2000 hours and ∆T
K
= 10°C at rated
0.95A. ∆T
O
can then be
calculated from:
∆T
K
= (I
RMS
/0.95A)
2
•
∆T
K
=
(0.77A/0.95A)
2
•
10°C = 6.6°C
Assuming the operating ambient temperature is 60°C, the
approximate life time is:
For longer life, a capacitor with a higher ripple current
rating or parallel capacitors should be used.
(105°C+∆T
K
) – (T
A
+∆T
O
)
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
V
OUT
/(V
CC
– 2V) = N
P
/N
S
.
For 382V V
OUT
and 18V V
CC
, Np/Ns ≈ 19.
In Figure 6, a new technique for supply voltage eliminates
the need for an extra inductor winding. It uses capacitor
charge transfer to generate a constant current source
which feeds a Zener diode. Current to the Zener is equal
to (VOUT – VZ)(C)(f), where VZ is Zener voltage and f is
switching frequency. For VOUT = 382V, VZ = 18V, C =
1000pF, and f = 100kHz, Zener current will be 36mA. This
is enough to operate the LT1248, including the FET gate
drive. Normally soft-start is not needed because the
LT1248 has overcurrent limit and overvoltage protection.
If soft-start is used with a 0.01µF capacitor on SS pin,
VOUT ramps up slower during start-up. Then C4 has to
hold VCC longer, and the circuit may not start. Increasing
C4 to 100µF ensures start-up, but start-up time will be
extended if the same 90k trickle charge resistor is used.
Output Capacitor
The peak-to-peak 120Hz output ripple is determined by:
V
P-P
= (2) (I
LOAD(DC)
)(Z)
where I
LOAD(DC)
: DC load current.
Z: capacitor impedance at 120Hz.
For 180µF at 300W load, I
LOAD(DC)
= 300W/385V = 0.78A,
V
P-P
= 2 • 0.78A • 7.4Ω = 11.5V. If less ripple is desired,
higher capacitance should be used. The selection of the
output capacitor should also be based on the operating
ripple current through the capacitor. The ripple current
can be divided into three major components. The first is at
120Hz; it’s RMS value is related to the DC load current as
follows:
I
1RMS
≈ 0.71 • I
LOAD(DC)
The second component contains the PF switching fre-
quency ripple current and its harmonics. Analysis of the
ripple is complicated because it is modulated with a 120Hz
signal. However computer numerical integration and Fou-
rier analysis approximate the RMS value reasonably close
to the bench measurements. The RMS value is about 0.82A
at a typical condition of 120VAC, 200W load. This ripple is
line-voltage dependent, and the worst case is at low line.
I
2RMS
= 0.82A at 120VAC, 200W
√
√
L = L
O
•
2
L
O
≈ 2000 • 2 ≈ 57,000 hours
10
(105°C+10°C) – (60°+6.6°C)
10
11
LT1248
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
300W, 382V Preregulator
Kool Mµ is a registered trademark of Magnetics, Inc.
–
+
–
+
IM = IA2 IB
200µA2
VAOUT
7.5V
7.9V
12µA5V
EA
VREF
–
+
–
+–
+
2.2V
32k
IA
IB
7µA
IM
7.5V
VREF
–
+
VCC
16V TO 10V
2.6V/2.2V –
+
0.7V
–
+
OSC
R
R
S
Q
CSET RSET
6
11
10
79 542115
16
12
14
SS
OVP
IAC
VSENSE
EN/SYNC
MOUT ISENSE 3
CAOUT
VCC
RUN
CA
RUN
16V
GND
–
+
GTDR
1000pF
SYNC
1N5819
†
4.7nF
1M
20k 0.47µF
0.047µF
330k
0.1µF1nF
8
0.01µF
13
100pF
PKLIM
20k
1%
RREF
4k
VOUT
180µF
T
90V
TO
270V
EMI
FILTER
+
–
4k
20k
RS
0.2Ω
50k
750µH*
1M
1%
MURH860
VCC = 18V**
56µF
35V
10Ω
15k
–
+
1248 TA01
IRF840
ONE SHOT
200ns
6A
M1
1. COILTRONICS CTX02-12236-1 (TYPE 52 CORE)
AIR MOVEMENT NEEDED AT POWER LEVEL GREATER THAN 250W.
2. COILTRONICS CTX02-12295 (MAGNETICS Kool Mµ® 77930 CORE)
SEE START-UP AND SUPPLY VOLTAGE SECTION FOR VCC GENERATOR.
THIS SCHOTTKY DIODE IS TO CLAMP GTDR WHEN MOS SWITCH
TURNS OFF. PARASITIC INDUCTANCE AND GATE CAPACITANCE MAY
TURN ON CHIP SUBSTRATE DIODE AND CAUSE ERRATIC OPERATIONS
IF GTDR IS NOT CLAMPED.
*
**
†
+
+
U
A
O
PPLICATITYPICAL
12
LT1248
LINEAR TECHNOLOGY CORPORATION 1993
1248fd LT/GP 0799 2K REV D • PRINTED IN USA
PACKAGE DESCRIPTIO
U
Dimensions in inches (millimeters) unless otherwise noted.
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear-tech.com
N Package
16-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LT1103 Off-Line Switching Regulator Universal Off-Line Inputs with Outputs to 100W
LT1249 PFC in SO-8 Simplified PFC Design with Minimal Part Count
LT1508 Power Factor and PWM Controller Voltage Mode PWM, Simplified PFC Design
LT1509 Power Factor and PWM Controller Complete Solution for Universal Off-Line Switching Power Supplies
N16 1098
0.009 – 0.015
(0.229 – 0.381)
0.300 – 0.325
(7.620 – 8.255)
0.325 +0.035
–0.015
+0.889
–0.381
8.255
()
0.255 ± 0.015*
(6.477 ± 0.381)
0.770*
(19.558)
MAX
16
12345678
910
11
12
13
14
15
0.020
(0.508)
MIN
0.125
(3.175)
MIN
0.130 ± 0.005
(3.302 ± 0.127)
0.065
(1.651)
TYP
0.045 – 0.065
(1.143 – 1.651)
0.018 ± 0.003
(0.457 ± 0.076)
0.100
(2.54)
BSC
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
0.016 – 0.050
(0.406 – 1.270)
0.010 – 0.020
(0.254 – 0.508)× 45°
0° – 8° TYP
0.008 – 0.010
(0.203 – 0.254)
S16 1098
12345678
0.150 – 0.157**
(3.810 – 3.988)
16 15 14 13
0.386 – 0.394*
(9.804 – 10.008)
0.228 – 0.244
(5.791 – 6.197)
12 11 10 9
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
0.053 – 0.069
(1.346 – 1.752)
0.014 – 0.019
(0.355 – 0.483)
TYP
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
BSC
