ICS951601AFLFT - IDT, Integrated Device Technology Inc

Integrated

Circuit

Systems, Inc.

ICS951601

Preliminary Product Preview

0663C—10/04/05

Block Diagram

General Purpose Frequency Timing Generator

Recommended Application:

General Purpose Clock Generator

Output Features:

• 17 - PCI clocks selectable,

either 33.33MHz or 66.6MHz @ 3.3V

• 1 - 48MHz @ 3.3V

• 1 - REF @ 3.3V, 14.318MHz.

Features:

• Programable Spread spectrum precentage for EMI

control

• Uses external 14.318MHz crystal

• Select pins for frequency select

PLL2

PLL1

Spread

Spectrum

48MHz

PCI1A (7:0)

PCI2A (2:0)

PCI1B (2:0)

PCI2B (2:0)

XTAL

OSC

PCI

DIVDER

PCI

DIVDER

PCI

DIVDER

PCI

DIVDER

S DATA

SCLK

SELA (2:1)

SELB (2:1)

SPREAD

Control

Logic

Config.

Reg.

REF0

Power Groups:

VDDA = Analog Power

GNDA = Analog Ground

PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to

change without notice.

Key Specifications:

• PCI – PCI output skew within same bank @

33MHz: <170ps

• PCI – PCI output skew within same bank@ 66MHz:

<340ps

• Cycle to Cycle Jitter PCI @ 33MHz: <200ps

• Cycle to Cycle Jitter PCI @ 66MHz: <200ps

• Cycle to Cycle Jitter 48MHz: <350ps

• Cycle to Cycle Jitter REF: <500ps

• Slew Rate: 1.5 - 4 V/ns. (PCI spec.)

Pin Configuration

48-pin SSOP

*120K ohm pull-up to VDD on indicated inputs.

REF0

VDD

GND

SDATA

SCLK

GNDA

VDDA

SEL1A

PCI1A_0

PCI1A_1

VDD33

GND

PCI1A_2

PCI1A_3

GND

VDD33

PCI1A_4

PCI1A_5

VDD33

GND

PCI1A_6

PCI1A_7

48MHz

GND

VDD48

SPREAD

VDDA

GNDA

SEL2B

PCI2B_2

PCI2B_1

GND

VDD66

PCI2B_0

SEL2A

PCI2A_2

PCI2A_1

VDD2A

GND

PCI2A_0

SEL1B

PCI1B_2

PCI1B_1

GND

VDD1B

PCI1B_0

ICS951601

Preliminary Product Preview

0663C—10/04/05

Pin Descriptions

Pin number Pin name Type Description

1 REF0 OUT Reference output

2, 13, 18, 21, 26,

33, 38, 46 VDD PWR 3.3V Power supply

3 X1 IN Crystal input,nominally 14.318MHz.

4 X2 OUT Crystal output, nominally 14.318MHz.

9, 44 VDDA PWR Analog 3.3V Power supply

10, 30, 36, 42 SELxx IN Real time PCI output frequency selection pins

5, 14, 17, 22, 27,

32, 39, 47 GND PWR Ground pins

6SDATA I/O

Data pin for I2C circuitry 5V tolerant

7SCLK IN

Clock input of I2C input

8, 43 GNDA PWR Analog ground pins

24, 23, 20, 19,

16, 15, 12, 11, PCI1A (7:0) OUT PCI clock outputs, selectable to be either

33.33 or 66.66MHz at 3.3V.

29, 28, 25 PCI1B (2:0) OUT PCI clock outputs, selectable to be either

33.33 or 66.66MHz at 3.3V.

35, 34, 31 PCI2A (2:0) OUT PCI clock outputs, selectable to be either

33.33 or 66.66MHz at 3.3V.

41, 40, 37 PCI2B (2:0) OUT PCI clock outputs, selectable to be either

33.33 or 66.66MHz at 3.3V.

45 SPREAD IN Enables Spread Spectrum, default is on.

48 48MHz OUT Fixed 48MHz clock output for USB.

ICS951601

Preliminary Prouct Preview

0663C—10/04/05

1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches

for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.

2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)

3. The input is operating at 3.3V logic levels.

4. The data byte format is 8 bit bytes.

5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the

controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to

stop after any complete byte has been transferred. The Command code and Byte count shown above

must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is

issued.

6. At power-on, all registers are set to a default condition, as shown.

General I2C serial interface information

The information in this section assumes familiarity with I2C programming.

How to Write:

• Controller (host) sends a start bit.

• Controller (host) sends the write address D2 (H)

• ICS clock will

acknowledge

• Controller (host) sends a dummy command code

• ICS clock will

acknowledge

• Controller (host) sends a dummy byte count

• ICS clock will

acknowledge

• Controller (host) starts sending first byte (Byte 0)

through byte 5

• ICS clock will

acknowledge

each byte

one at a

time

How to Read:

• Controller (host) will send start bit.

• Controller (host) sends the read address D3 (H)

• ICS clock will

acknowledge

• ICS clock will send the

byte count

• Controller (host) acknowledges

• ICS clock sends first byte

(Byte 0) through byte

• Controller (host) will need to acknowledge each

byte

Notes:

Controller (Host) ICS (Slave/Receiver)

Start Bit

Address

D3(H)

Byte Count

ACK Byte 0

ACK Byte 1

ACK Byte 2

ACK Byte 3

ACK Byte 4

ACK Byte 5

ACK

Stop Bit

How to Read:

Controller (Ho st) ICS (Slave/Receiv er)

Start Bit

Address

D2(H)

Dummy Command Code ACK

Dummy Byte Count

Byte 0 ACK

Byte 1 ACK

Byte 2 ACK

Byte 3 ACK

Byte 4

Byte 5 ACK

Stop Bit

How to Write:

ICS951601

Preliminary Product Preview

0663C—10/04/05

Byte 0: Functionality and frequency select register (Default = 0)

Serial Configuration Command Bitmap

Bit2 Bit7 Bit6 Bit5 Bit4 66MHZ 33MHz FEATURES

FS4 FS3 FS2 FS1 FS0

0000066 33 -0.25 % down spread

0000166 33 -0.5 % down spread

0001066 33 -1.0 % down spread

0001166 33 -1.5 % down spread

0010066 33 + 0.25 % center spread

0010166 33 +0.5 % center spread

0011066 33 + 1.0 % center spread

00111

66.6 33.3 +1.5 % center spread

01000

67.32 33.66 2% over-clocking

01001

68.64 34.32 4% over-clocking

01010

69.96 34.98 6% over-clocking

01011

72.6 36.3 10% over-clocking

01100

65.27 32.63 2% under- clocking

01101

63.96 31.97 2% under- clocking

01110

62.6 31.3 2% under- clocking

0111160 30 2% under- clocking

10000

66.6 33.3 -1.4 % down spread

10001

66.6 33.3 -1.6 % down spread

10010

66.6 33.3 -1.8 % down spread

10011

66.6 33.3 -2.0 % down spread

10100

66.6 33.3 + 1.4 % center spread

10101

66.6 33.3 + 1.6 % center spread

10110

66.6 33.3 + 1.8 % center spread

10111

66.6 33.3 + 2.0 % center spread

Bit1 0-Normal 1-Spread spectrum Enabled 0

Bit0 0-Running 1-Tristate all outputs 0

Bit PWD

00000

Bit

2,7:4

Bit3 0

0-Frequency and Spread is seleced by hardware select. Latched input

1-Frequency is seleced by Bit2, 7:4

ICS951601

Preliminary Prouct Preview

0663C—10/04/05

Byte 1: PCI1A Stop Clocks Register

(1 = enable, 0 = disable)

Byte 2: PCI2A Stop Clocks

Byte 3: PCI2B Stop Clocks Register

(1 = enable, 0 = disable)

Byte 4: Reserved Register

(1 = enable, 0 = disable)

tiB#niPDWPnoitpircseD

7tiB421 7_A1ICP

6tiB321 6_A1ICP

5tiB021 5_A1ICP

4tiB911 4_A1ICP

3tiB611 3_A1ICP

2tiB511 2_A1ICP

1tiB211 1_A1ICP

0tiB111 0_

A1ICP

tiB#niPDWPnoitpircseD

7tiB

12_A2ICP

6tiB

11_A2ICP

5tiB

10_A2ICP

4tiB

12_B1ICP

3tiB

11_B1ICP

2tiB

10_B1ICP

1tiB

XdevreseR

0tiB

XdevreseR

tiB#niPDWPnoitpircseD

7tiB141 2_B2ICP

6tiB041 1_B2ICP

5tiB731 0_B2ICP

4tiB-X devreseR

3tiB-X devreseR

2tiB-X devreseR

1tiB-X devreseR

0tiB-X dev

reseR

tiB#niPDWPnoitpircseD

7tiB841 zHM84

6tiB110FER

5tiB-X devreseR

4tiB-X devreseR

3tiB-X devreseR

2tiB-X devreseR

1tiB-X devreseR

0tiB-X devreseR

Byte 5: Latched Input Read Back Register

(1= enable, 0 = disable)

tiB#niPDWPnoitpircseD

7tiB-X B2LES

6tiB-X B1LES

5tiB-X A2LES

4tiB-X A1LES

3tiB-X devreseR

2tiB-X devreseR

1tiB-X devreseR

0tiB-X devreseR

Byte 6: Reserved for Byte Count Register

(1= enable, 0 = disable)

tiB#niPDWPnoitpircseD

7tiB-0 daerrofdevreseR

tnuocetyb

6tiB-0 devreseR

5tiB-0 devreseR

4tiB-0 devreseR

3tiB-0 devreseR

2tiB-1 devreseR

1tiB-1 devreseR

0tiB-0 devr

eseR

Note: PWD = Power-Up Default

ICS951601

Preliminary Product Preview

0663C—10/04/05

Absolute Maximum Ratings

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 5.5 V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V

Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C

Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Case Temperature . . . . . . . . . . . . . . . . . . . . . 115°C

Stresses above those listed under

Absolute Maximum Ratings

may cause permanent damage to the device. These

ratings are stress specifications only and functional operation of the device at these or any other conditions above those

listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect product reliability.

Electrical Characteristics - Input/Supply/Common Output Parameters

TA = 0 - 70°C; VDD, VDDL = 3.3 V +/-5% (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input High Voltage VIH 2V

DD + 0.3 V

Input Low Voltage VIL VSS - 0.3 0.8 V

Input High Current IIH VIN = VDD 5mA

Input Low Current IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 mA

Input Low Current IIL2 VIN = 0 V; Inputs with pull-up resistors -200 mA

IDD3.3OP100 CL = 0 pF; Select @ 100 MHz 160 mA

IDD3.3OP133 CL = 0 pF; Select @ 133 MHz 160 mA

Input frequency FiVDD = 3.3 V; 11 14.318 16 MHz

CIN Logic Inputs 5 pF

CINX X1 & X2 pins 27 45 pF

Transition Time1Ttrans To 1st crossing of target Freq. 3 ms

Settling Time1TsFrom 1st crossing to 1% target Freq. 3 ms

Clk Stabilization1TSTAB From VDD = 3.3 V to 1% target Freq. 3ms

1Guaranteed by design, not 100% tested in production.

Input Capacitance1

Operating Supply

Current

Electrical Characteristics - Input/Supply/Common Output Parameters

TA = 0 - 70°C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5% (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Operating IDD2. 5OP 100 CL = 0 pF; Select @ 100 MHz 16 75 mA

Supply Current IDD2. 5OP133 CL = 0 pF; Select @ 133 MHz 1990mA

Power Down Supply

Current IDD2. 5PD CL = 0 pF; PWRDWN# = 0 0.1 100 µA

1Guaranteed by design, not 100% tested in production.

ICS951601

Preliminary Prouct Preview

0663C—10/04/05

Electrical Characteristics - PCI

TA = 0 - 70°C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output High Voltage VOH1 IOH = -11 mA 2.4 V

Output Low Voltage VOL1 IOL = 9.4 mA 0.4 V

Output High Current IOH1 VOH = 2.0 V -22 mA

Output Low Current IOL1 VOL = 0.8 V 16 mA

Rise Time1tr1 VOL = 0.4 V, VOH = 2.4 V 2 ns

Fall Time1tf1 VOH = 2.4 V, VOL = 0.4 V 2 ns

Duty Cycle1dt1 VT = 1.5 V 45 55 %

Skew1tsk1 VT = 1.5 V @ 33.33 170 ps

Skew1tsk2 VT = 1.5 V @ 66.66 340 ps

Jitter, Cycle-to-cycle1Tjcyc-cyc1 VT = 1.5 V 500 ps

1Guaranteed by design, not 100% tested in production.

Electrical Characteristics - 48 MHz

TA = 0 - 70°C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output High Voltage VOH5 IOH = -16 mA 2.4 V

Output Low Voltage VOL5 IOL = 9 mA 0.4 V

Output High Current IOH5 VOH = 2.0 V -22 mA

Output Low Current IOL5 VOL = 0.8 V 16 mA

Rise Time1tr5 VOL = 0.4 V, VOH = 2.4 V 4 ns

Fall Time1tf5 VOH = 2.4 V, VOL = 0.4 V 4 ns

Duty Cycle1dt5 VT = 1.5 V 45 55 %

Jitter, Cycle-to-cycle1Tjcyc-cyc5 VT = 1.5 V 350 ps

1Guaranteed by design, not 100% tested in production.

ICS951601

Preliminary Product Preview

0663C—10/04/05

Electrical Characteristics - REF

TA = 0 - 70°C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output High Voltage VOH5 IOH = -16 mA 2.4 V

Output Low Voltage VOL5 IOL = 9 mA 0.4 V

Output High Current IOH5 VOH = 2.0 V -22 mA

Output Low Current IOL5 VOL = 0.8 V 16 mA

Rise Time1tr5 VOL = 0.4 V, VOH = 2.4 V 4 ns

Fall Time1tf5 VOH = 2.4 V, VOL = 0.4 V 4 ns

Duty Cycle1dt5 VT = 1.5 V 45 55 %

Jitter, Cycle-to-cycle1Tjcyc-cyc5 VT = 1.5 V 500 ps

1Guaranteed by design, not 100% tested in production.

ICS951601

Preliminary Prouct Preview

0663C—10/04/05

Ordering Information

ICS951601yFLF

Lead Free, RoHS Compliant (Optional)

Pattern Number (2 or 3 digit number for parts with ROM code patterns)

Package Type

F=SSOP

Revision Designator

Device Type

Prefix

ICS = Standard Device

Example:

ICS XXXX y F - PPP LF

INDEX

AREA

INDEX

AREA

1 2

h x 45°

E1 E

SEATING

PLANE

SEATING

PLANE

-C-

- C -

.10 (.004) C

300 mil SSOP Package

MIN MAX MIN MAX

A 2.41 2.80 .095 .110

A1 0.20 0.40 .008 .016

b 0.20 0.34 .008 .0135

c 0.13 0.25 .005 .010

E 10.03 10.68 .395 .420

E1 7.40 7.60 .291.299

h 0.38 0.64 .015 .025

L 0.50 1.02 .020 .040

α0° 8° 0° 8°

MIN MAX MIN MAX

48 15.75 16.00 .620 .630

10-0034

SYMBOL

In Millimeters In Inches

COMMON DIMENSIONS COMMON DIMENSIONS

SEE VARIATIONS SEE VARIATIONS

0.635 BASIC 0.025 BASIC

Reference Doc.: JEDE C Publication 95, MO - 118

VARIATIONS

SEE VARIATIONS SEE VARIATIONS

ND mm. D

(

inch

)

ICS951601

Preliminary Product Preview

0663C—10/04/05

Revision History

Rev. Issue Date Description Page #

C 10/4/2005 Added LF to Ordering Information 9