XL93LC56/56A EXEL Microelectronics, Inc. 2,048-Bit Serial Electrically Erasable PROM with 2V Read Capability FEATURES * 2.7 to 5.5V Operation (XL93LC56) 4.5 to 5.5V Operation (XL93LC56A) * Extended Temperature Range: -40C to +85 C * State-of-the-Art Architecture -- Nonvolatile data storage -- Fully TTL compatible inputs and outputs -- Auto increment for efficient data dump * * PIN CONFIGURATIONS Hardware and Software Write Protection -- Defaults to write-disabled state at power up -- Software instructions for write-enable/disable -- VCC lockout inadvertent write protection (XL93LC56A) Low Power Consumption -- 1mA active -- 1A standby * Low Voltage Read Operations -- Reliable read operations down to 2.0 volts * Advanced Low Voltage CMOS E2 PROM Technology * Versatile, Easy-to-Use Interface -- Self-timed programming cycle -- Automatic erase-before-write -- Programming Status Indicator -- Word and chip erasable * Durable and Reliable -- 100-year data retention after 100K write cycles -- Minimum of 100,000 erase/write cycles -- Unlimited read cycles -- ESD protection (EIAJ and JEDEC standard) Plastic Dual-in-line "P" Package CS 1 8 VCC SK 2 7 NC DI 3 6 NC DO 4 5 GND JEDEC Small Outline "RY" Package JEDEC Small Outline "Y" Package CS 1 8 VCC NC 1 8 NC SK 2 7 NC VCC 2 7 GND DI 3 6 CS 3 6 DO DO 4 5 GND SK 4 5 DI NC D0005 ILL A01.1 PIN NAMES CS SK DI DO GND VCC NC Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Supply Not Connected OVERVIEW The XL93LC56/56A is a cost effective 2,048-bit, nonvolatile, serial E2PROM. It is fabricated using EXEL's advanced CMOS E2 PROM technology. The XL93LC56/ 56A provides efficient nonvolatile read/write memory arranged as 128 registers of 16 bits each. Seven 11-bit instructions control the operation of the device, which include read, write, and mode enable functions. The data output pin (DO) indicates the status of the device during the self-timed nonvolatile programming cycle. EXEL Microelectronics, Inc. 2150 Commerce Drive * San Jose, CA 95131 PHONE 408 432-0500 * FAX 408 432-8710 * Internet www.exel.com The self-timed write cycle includes an automatic erasebefore-write capability. To protect against inadvertent writes, the WRITE instruction is accepted only while the chip is in the write enabled state. Data is written in 16 bits per write instruction into the selected register. If Chip Select (CS) is brought HIGH after initiation of the write cycle, the Data Output (DO) pin will indicate the READY/ BUSY status of the chip. D0005 3/96 DVPTD 6931-04 XL93LC56/56A BLOCK DIAGRAM DI DATA REGISTER (16 BITS) INSTRUCTION REGISTER (11 BITS) CS DUMMY BIT DO R/W AMPS INSTRUCTION DECODE, CONTROL AND CLOCK GENERATION ADDRESS REGISTER 1 OF 128 DECODER E2 PROM ARRAY (128x16) SK WRITE ENABLE HIGH VOLTAGE GENERATOR D0005 ILL B01.2 Low Voltage Read The XL93LC56/56A has been designed to ensure that data read operations are reliable in low voltage environments. The XL93LC56/56A is guaranteed to provide accurate data during read operations with VCC as low as 2.0V. APPLICATIONS The XL93LC56/56A is ideal for high volume applications requiring low power and low density storage. This device uses a cost effective, space saving 8-pin package. Candidate applications include robotics, alarm devices, electronic locks, meters and instrumentation settings. Auto Increment Read Operations In order to facilitate memory transfer operations, the XL93LC56/56A has been designed to output a continuous stream of memory content in response to a single read operation instruction. To utilize this function, the system asserts a read instruction specifying a start location address. Once the 16 bits of the addressed word have been clocked out, the data in consecutively higher address locations is output. The address will wrap around continuously with CS HIGH until the Chip Select control pin is brought LOW. This allows for single instruction data dumps to be executed with a minimum of firmware overhead. ENDURANCE AND DATA RETENTION The XL93LC56/56A is designed for applications requiring up to 100,000 erase/write cycles per bit. It provides 100 years of secure data retention without power after the execution of 100,000 write cycles. DEVICE OPERATION The XL93LC56/56A is controlled by seven 11-bit instructions. Instructions are clocked in (serially) on the DI pin. Each instruction begins with a logical "1" (the start bit). This is followed by the opcode (2 bits), the address field (8 bits), and data, if appropriate. The clock signal (SK) may be halted at any time and the XL93LC56/56A will remain in its last state. This allows full static flexibility and maximum power conservation. Write Enable (WEN) The write enable (WEN) instruction must be executed before any device programming can be done. When VCC is applied, this device powers up in the write disabled state. The device then remains in a write disabled state until a WEN instruction is executed. Thereafter the device remains enabled until a WDS instruction is executed or until VCC is removed. (NOTE: Neither the WEN nor the WDS instruction has any effect on the READ instruction. See Figure 3.) Read (READ) The READ instruction is the only instruction that results in serial data on the DO pin. After the read instruction and address have been decoded, data is transferred from the selected memory register into a 16-bit serial shift register. (Please note that one logical "0" bit precedes the actual 16bit output data string). The output on DO changes during the LOW-TO-HIGH transitions of SK. (See Figure 2.) D0005 3/96 DVPTD 6931-04 2 XL93LC56/56A Write (WRITE) The WRITE instruction includes 16 bits of data to be written into the specified register. After the last data bit has been clocked into DI, and before the next rising edge of SK, CS must be brought LOW. The falling edge of CS initiates the self-timed programming cycle. struction is executed. (When VCC is applied, the part powers up in the write disabled state.) To protect data, a WDS instruction should be executed upon completion of each programming operation. (NOTE: Neither the WEN nor the WDS instruction has any effect on the READ instruction. See Figure 6.) After a minimum wait of 250ns from the falling edge of CS (tCS), if CS is brought HIGH, DO will indicate the READY/ BUSY status of the chip: logical "0" means programming is still in progress; logical "1" means the selected register has been written, and the part is ready for another instruction. (See Figure 4.) (NOTE: The combination of CS HIGH, DI HIGH and the rising edge of the SK clock, resets the READY/BUSY flag. Therefore, it is important not to reset the READY/BUSY flag through this combination of control signals, if you want to access it). Before a WRITE instruction can be executed, the device must be write enabled (see WEN). Erase The Erase instruction (ERASE) programs the addressed memory location to all "1s." Once the address is clocked in, the falling edge of CS will initiate the internal programming cycle. After waiting a minimum 250ns, the READY/ BUSY status can be monitored on DO. Erase All (ERAL) Full chip erase is provided for ease of programming. Erasing the entire chip involves setting all bits in the entire memory array to a logical "1." (See Figure 8.) VCC Lockout - Inadvertent Write Protection (XL93LC56A only) To ensure against inadvertent write operations, the XL93LC56A has been equipped with an internal VCC sensor circuit which inhibits data alteration when the supply voltage (VCC) falls below VWI. If the applied VCC is below 3.75V (typical), the XL93LC56A is inhibited from executing write operations thereby protecting the nonvolatile data from inadvertent operations. Write All (WRALL) The write all (WRALL) instruction programs all registers with the data pattern specified in the instruction. As with the WRITE instruction, if CS is brought HIGH after a minimum wait of 250ns (tCS), the DO pin indicates the READY/BUSY status of the chip. (See Figure 5.) Write Disable (WDS) The write disable (WDS) instruction disables all programming capabilities. This protects the entire memory array against accidental modification of data until a WEN in- XL93LC56/56A INSTRUCTION SET Start Bit OP Code Address READ 1 10 X(A6-A0) WEN (Write Enable) 1 00 11XXXXXX WRITE 1 01 X(A6-A0) D15-D0 WRALL (Write All Registers) 1 00 01XXXXXX D15-D0 WDS (Write Disable) 1 00 00XXXXXX ERASE 1 11 X(A6-A0) ERAL (Erase All Registers) 1 00 10XXXX Instruction Input Data D0005 PGM T01.2 3 D0005 3/96 DVPTD 6931-04 XL93LC56/56A ABSOLUTE MAXIMUM RATINGS Temperature under bias: ................................................................................................................... -40C to +85C Storage Temperature ....................................................................................................................... -65C to +150C Lead Soldering Temperature (less than 10 seconds) ...................................................................................... 300C Supply Voltage ............................................................................................................................................. 0 to 6.5V Voltage on Any Pin ........................................................................................................................ -0.3 to Vcc + 0.3V ESD Rating ..................................................................................................................................................... 2000V NOTE: These are STRESS ratings only. Appropriate conditions for operating these devices are given elsewhere in this specification. Stresses beyond those listed here may permanently damage the part. Prolonged exposure to maximum ratings may adversely affect device reliability. DC ELECTRICAL CHARACTERISTICS TA = -40C to +85C Symbol Parameter Conditions ICC1 Operating Current CMOS Input Levels CS = VCC, SK = 250KHz ICC2 Operating Current TTL Input Levels CS = VIH, SK = 1MHz ISB Standby Current ILI Input Leakage VOUT = 0V to VCC, CS = 0V XL93LC56 XL93LC56/56A XL93LC56/56A VCC = 3.0V10% VCC = 5.0V10% VCC = 2.0V (Read Only) Min Max Min Max Min Units Max 2 2 2 mA n/a 5 n/a mA CS = DI = SK =0V 2 2 2 A VIN = 0V to VCC (CS, SK, DI) 1 1 1 A ILO Output Leakage VIL Input Low Voltage VIH Input High Voltage VOL1 Output Low Voltage IOL = 2.1mA TTL VOH1 Output High Voltage IOH = -400A TTL 1 -0.1 0.15VCC 0.8 V CC VCC+0.2 VOH2 Output High Voltage IOH = -10A CMOS VOH2 Output High Voltage IOH = -10A CMOS VWI Write Inhibit Threshold 2 n/a n/a A V VCC+0.2 0.9 VCC VCC+0.2 V 0.8 0.2 n/a n/a 0.2 VCC-0.2 n/a -0.1 0.4 2.4 VCC-0.2 n/a 1 0.1 VCC 1 -0.1 2.7 0.2 VCC-0.2 4.4 n/a V V V V n/a V D0005 PGM T02.1 AC ELECTRICAL CHARACTERISTICS TA = -40C to +85C XL93LC56 Symbol Parameter VCC = 3.0V10% Conditions Min Max 0 250 XL93LC56/56A VCC = 5.0V10% Min Max 0 1000 XL93LC56/56A VCC = 2.0V (Read Only) Min Max 0 250 Units fSK SK Clock Frequency tSKH SK High Time 1000 400 2000 KHz ns tSKL SK Low Time 1000 250 2000 ns tCS Minimum CS Low Time 1000 250 1000 ns tCSS CS Setup Time Relative to SK 200 50 200 ns tDIS DI Setup Time Relative to SK 400 100 400 ns Relative to SK 0 0 0 ns 400 tCSH CS Hold Time tDIH DI Hold Time Relative to SK tPD1 Output Delay to "1" AC Test 2000 500 2000 ns tPD0 Output Delay to "0" AC Test 2000 500 2000 ns tSV CS to Status Valid AC Test CL = 100pF 2000 500 2000 ns tDF CS to DO in 3-state CS = Low to DO = Hi-Z 400 100 400 ns tWP Write Cycle Time CS = Low to DO = Ready 25 10 n/a ms 100 400 ns D0005 PGM T03.1 D0005 3/96 DVPTD 6931-04 4 XL93LC56/56A CAPACITANCE TA = 25C, f = 250KHz Symbol Parameter Max Units CIN Input Capacitance 5 pF COUT Output Capacitance 5 pF D0005 PGM T04.1 t CS CS T* tCSS tSKH t SKL t CSH SK tDIH tDIS DI tPDO t PD1 DO (READ) t DF t SV STATUS VALID DO (WRITE) D0005 ILL F01.1 *T = 1/f SK FIGURE 1. SYNCHRONOUS DATA TIMING t CS CS SK * DI 0 DO 1 1 0 X A6 A0 0 D15 * This leading clock is optional. ** Address pointer automatically cycles to the next register. D0 D15 ** D0005 ILL F02.1 FIGURE 2. READ CYCLE TIMING 5 D0005 3/96 DVPTD 6931-04 XL93LC56/56A t CS CS SK * DI 0 1 0 0 1 DO 1 High impedance D0005 ILL F03.1 * This leading clock is optional. FIGURE 3. WRITE ENABLE (WEN) CYCLE TIMING t CS CS SK * DI 0 1 0 1 X A6 A0 D15 D0 tSV DO BUSY t DF READY t WP * This leading clock is optional. D0005 ILL F04.1 FIGURE 4. WRITE CYCLE TIMING D0005 3/96 DVPTD 6931-04 6 XL93LC56/56A t CS CS SK * DI 0 1 0 0 0 1 D15 D0 t SV DO BUSY READY t WP * This leading clock is optional. D0005 ILL F05.1 FIGURE 5. WRITE ALL (WRALL) CYCLE TIMING t CS CS SK * DI 0 1 0 0 DO 0 0 High impedance * This leading clock is optional. D0005 ILL F06.1 FIGURE 6. WRITE DISABLE (WDS) CYCLE TIMING 7 D0005 3/96 DVPTD 6931-04 XL93LC56/56A t CS CS SK * DI 0 1 1 1 X A6 A0 t SV DO t DF READY BUSY t WP * This leading clock is optional. D0005 ILL F07.1 FIGURE 7. ERASE (REGISTER) CYCLE TIMING t CS CS SK * DI 0 1 0 0 1 0 t DF t SV DO BUSY READY t WP * This leading clock is optional. D0005 ILL F08.1 FIGURE 8. ERASE ALL (ERAL) CYCLE TIMING D0005 3/96 DVPTD 6931-04 8 XL93LC56/56A PACKAGE DIAGRAMS Plastic Dual-in-line (Type "P") Package (PDIP) .375 (9.525) .250 (6.350) PIN 1 INDICATOR .300 (7.620) .070 (1.778) .0375 (0.952) .015 (.381) Min. 5-7TYP. (4 PLCS) 0-15 SEATING PLANE .130 (3.302) .060 .005 (1.524) .127 TYP. .100 (2.54) TYP. .130 (3.302) .018 (.457) TYP. .009 .002 (.229 .051) .350 (8.89) 8pn PDIP/P ILL.3 All dimensions in inches (mm). 8 Pin SOIC (Type "Y," "RY") Package (JEDEC 150 mil body width) .050 (1.27) TYP. .050 (1.270) TYP. 8 Places .157 (4.00) .150 (3.80) .275 (6.99) TYP. .030 (.762) TYP. 8 Places 1 .196 (5.00) .189 (4.80) FOOTPRINT .061 (1.75) .053 (1.35) .020 (.50) x45 .010 (.25) .0192 (.49) .0138 (.35) .0098 (.25) .004 (.127) .05 (1.27) TYP. .035 (.90) .016 (.40) .244 (6.20) .228 (5.80) 8pn JEDEC SOIC ILL. 1 All dimensions in inches (mm). * See cover page for pinout options. 9 D0005 3/96 DVPTD 6931-04 XL93LC56/56A ORDERING INFORMATION Standard Configurations Prefix Type Part Type Voltage Package Range XL 93LC56 3 Volts, 5 Volts P, Y, RY D0005 PGM T05.2 Part Numbers: XL 93LC56 P Package Type Y = SOIC (JEDEC) 150 mil RY = SOIC (JEDEC) 150 mil P = PDIP 300 mil Prefix Part Number 93LC56 D0005 3/96 DVPTD 6931-04 A Voltage Range A = 5 Volts Blank = 3 to 5 Volts 10 XL93LC56/56A MARKING INFORMATION Marking for XL93LC56AP YWW Marking for XL93LC56AY Marking for XL93LC56ARY LC56A LR56A YWW YWW Marking for XL93LC56Y Marking for XL93LC56RY LC56 LR56 YWW YWW XL93LC56AP Marking for XL93LC56P YWW XL93LC56P D0005 ILL C01.2 * See cover page for pinout options. TAPE AND REEL (EMBOSSED) INFORMATION Surface mount devices, which are normally shipped in antistatic plastic tubes, are also available mounted on embossed tape for customers using automatic placement systems. The following diagram provides general information regarding the direction of the IC's. Tape "E2" shall be designated with PIN 1 at the trail direction. PIN 1 E2 Tape un-reel direction T&R Y ILL.2 11 D0005 3/96 DVPTD 6931-04 XL93LC56/56A NOTICE EXEL Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXEL Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user's specific application. While the information in this publication has been carefully checked, EXEL Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. EXEL Microelectronics, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXEL Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of EXEL Microelectronics, Inc. is adequately protected under the circumstances. (c) Copyright 1996 EXEL Microelectronics, Inc. Reproduction in whole or in part, without the prior written consent of EXEL Microelectronics, Inc. is prohibited. D0005 3/96 DVPTD 6931-04 12