Triple Skew-Compensating Video Delay
Line with Analog and Digital Control
Data Sheet
AD8120
Rev. A
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FEATURES
Corrects for unshielded twisted pair (UTP) cable skew
Delay of up to 50 ns per channel
High speed
200 MHz BW @ VOUT = 1.4 V p-p and 0 ns delay
150 MHz BW @ VOUT = 1.4 V p-p and 50 ns delay
Excellent channel-to-channel matching
30 mV offset matching RTI
0.8% gain matching
Low output offset
±30 mV RTI
No external circuitry required to correct for offsets
Independent red, green, and blue delay controls
Drives 4 double-terminated video loads
Digital and analog delay control
6-bit SPI bus
I2C bus
Analog voltage control
Fixed gain of 2
Low noise
High differential input impedance: 500 kΩ
32-lead, 5 mm × 5 mm LFCSP
APPLICATIONS
Keyboard-video-mouse (KVM)
Digital signage
RGB video over UTP cable
Professional video projection and distribution
HD video
Security video
General broadband delay lines
GENERAL DESCRIPTION
The AD8120 is a triple broadband skew-compensating delay line
that corrects for time mismatch between video signals incurred
by transmission in unshielded twisted pairs of Category 5 and
Category 6 type cables. Skew between the individual pairs exists
in most types of multipair UTP cables due to the different twist
rates that are used for each pair to minimize crosstalk between
pairs. For this reason, some pairs are longer than others, and in
long cables, the difference in propagation time between two pairs
can be well into the tens of nanoseconds.
The AD8120 contains three delay paths that provide broadband
delays up to 50 ns, in 0.8 ns increments, using 64 digital control
steps or analog control adjustment. The delay technique used in
the AD8120 minimizes noise and offset at the outputs.
The bandwidth of the AD8120 ranges from 150 MHz to 200 MHz,
depending on the delay setting. This wide bandwidth makes the
AD8120 ideal for use in applications that receive high resolution
video over UTP cables.
The logic circuitry of the AD8120 provides individual delay con-
trols for each channel. The delay times are set independently
using a standard 4-wire SPI bus or a standard I2C bus, or by
applying analog control voltages to the VCR, VCG, and VCB pins.
Analog control offers a simple solution for systems that do not
have digital control available.
The AD8120 is designed to be used with the AD8123 triple
UTP equalizer in video over UTP applications, but it can
also be used in other applications where similar controllable
broadband delays are required.
The AD8120 is available in a 5 mm × 5 mm, 32-lead LFCSP
and is rated to operate over the industrial temperature range
of −40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
Rd
G
B
07839-001
d
d
Figure 1.
AD8120 Data Sheet
Rev. A | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
Maximum Power Dissipation ..................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ..............................................7
Theory of Operation .........................................................................9
Controlling the Delay ...................................................................9
Setting the Delay ............................................................................9
Analog Control ........................................................................... 10
Digital Control ............................................................................ 10
Applications Information .............................................................. 14
Typical Application Circuit for the AD8123 and AD8120 ... 14
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
5/12—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................. 4
Added Power Down Section .......................................................... 10
Updated Outline Dimensions ........................................................ 16
7/09—Revision 0: Initial Version
Data Sheet AD8120
Rev. A | Page 3 of 16
SPECIFICATIONS
TA = 25°C, VS = ±5 V, RL = 150 Ω, 10% to 90% input rise/fall time (tR/tF) = 4 ns, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DELAY CHARACTERISTICS
Total Adjustable Delay Range Delay Code 63 to Delay Code 0 50 ns
Delay Resolution Monotonic, 1 LSB 0.8 ns
Propagation Delay Delay = 0 ns 4.9 ns
Channel-to-Channel Delay Error All channels at maximum delay 0.4 ns
DYNAMIC PERFORMANCE
−3 dB Video Signal Bandwidth VOUT = 1.4 V p-p, delay = 0 ns 200 MHz
VOUT = 1.4 V p-p, delay = 50 ns 150 MHz
−3 dB Small-Signal Bandwidth VOUT = 0.2 V p-p, delay = 0 ns 165 MHz
V
OUT
= 0.2 V p-p, delay = 50 ns
140
MHz
0.1 dB Video Signal Flatness VOUT = 1.4 V p-p, delay = 0 ns 27 MHz
VOUT = 1.4 V p-p, delay = 50 ns 35 MHz
10% to 90% Rise/Fall Time VOUT = 1.4 V step, delay = 0 ns 2.5/3 ns
VOUT = 1.4 V step, delay = 50 ns 3/4.2 ns
Settling Time to 1% VOUT = 1.4 V step, delay = 0 ns 8 ns
VOUT = 1.4 V step, delay = 50 ns 18 ns
Slew Rate VOUT = 1.4 V step, delay = 0 ns, rising edge 550 V/μs
VOUT = 1.4 V step, delay = 0 ns, falling edge 540 V/μs
VOUT = 1.4 V step, delay = 50 ns, rising edge 510 V/μs
VOUT = 1.4 V step, delay = 50 ns, falling edge 360 V/μs
Overshoot VOUT = 1.4 V step, delay = 0 ns 1 %
VOUT = 1.4 V step, delay = 50 ns 20 %
Gain 0 ns to 50 ns delay 1.95 2.01 2.06 V/V
Channel-to-Channel Gain Matching Over all codes, among all channels 0.8 3 %
Hostile Crosstalk Measured on G with R and B driven at 1 MHz,
VOUT = 1.4 V p-p, delay = 0 ns
−80 dB
VIDEO INPUT CHARACTERISTICS RIN, GIN, BIN
Input Bias Current 0.8 1.5 μA
Input Capacitance 1 pF
Input Resistance 500 kΩ
VIDEO OUTPUT CHARACTERISTICS ROUT, GOUT, BOUT
Output Voltage Swing
±3.25
V
Output Current 50 mA
Integrated Output Noise 100 kHz to 160 MHz
Delay = 0 ns 1 mV rms
Delay = 50 ns 4 mV rms
Output Offset Voltage (RTI)
Over all codes
−30
0
+30
mV
Channel-to-Channel Output Offset Voltage
Matching (RTI)
Over all codes, among all channels 30 mV
Output Impedance PD high, at 20 MHz 1.5 Ω
ANALOG CONTROL INPUT CHARACTERISTICS
Input Bias Current VCR, VCG, VCB 1 μA
Operating Range VCR, VCG, VCB 0 2 V
Delay Voltage Step Size in Linear Range ΔVCR, ΔVCG, ΔVCB to move one delay LSB 28 mV
AD8120 Data Sheet
Rev. A | Page 4 of 16
Parameter Test Conditions/Comments Min Typ Max Unit
DIGITAL CONTROL INPUT CHARACTERISTICS
(SEE BELOW FOR POWER DOWN)
SDO/SDA, SCK/SCL, SDI/A1, CS/A0, SER_SEL,
MODE
Input Bias Current 2 μA
Input High Voltage 2.6 V
Input Low Voltage
0.6
V
Output High Voltage 4.5 V
Output Low Voltage 0.6 V
POWER DOWN CHARACTERISTICS
PD
Input High Voltage 4.0 V
Input Low Voltage 0.6 V
SPI TIMING CHARACTERISTICS
Clock Frequency SCK 10 MHz
CS Setup Time, t1 CS to SCK 5 ns
Clock Pulse High, t2 SCK 50 ns
Clock Pulse Low, t3 SCK 50 ns
Data Setup Time, t4 SDI to SCK 5 ns
Data Hold Time, t5 SDI to SCK 5 ns
CS Hold Time, t6 SCK to CS 5 ns
I
2
C TIMING CHARACTERISTICS
Clock Frequency SCL 100 kHz
Start Setup Time, t1 SDA to SCL 10 ns
Clock Pulse High, t2 SCL 5 μs
Clock Pulse Low, t3 SCL 5 μs
Data Setup Time, t4 SDA (input) to SCL 100 ns
Data Hold Time, t5 SDA (input) to SCL 100 ns
Hold Time, t6 SCL to SDA 10 ns
POWER SUPPLY
Positive Supply Range 4.5 5.5 V
Negative Supply Range −5.5 −4.5 V
Positive Quiescent Current Delay = 0 ns 44 mA
Delay = 50 ns 114 mA
Powered down, PD low 4 mA
Negative Quiescent Current Delay = 0 ns 37 mA
Delay = 50 ns 108 mA
Powered down, PD low 0.5 mA
Quiescent Current Drift TMIN to TMAX, delay = 0 ns 0.13 mA/°C
TMIN to TMAX, delay = 50 ns 0.36 mA/°C
+PSRR RL = 150 Ω, delay = 50 ns 56 dB
−PSRR RL = 150 Ω, delay = 50 ns 44 dB
Data Sheet AD8120
Rev. A | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage ±6 V
Internal Power Dissipation
32-Lead LFCSP at TA = 25°C 3.5 W
Input Voltage VS− − 0.3 V to VS+ + 0.3 V
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature
(Soldering 10 sec)
300°C
Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, for a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
θ
JA
θ
JC
Unit
5 mm × 5 mm, 32-Lead LFCSP 36 2 °C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8120 package is
limited by its junction temperature. The maximum safe junction
temperature for plastic encapsulated devices, as determined by
the glass transition temperature of the plastic, is approximately
150°C. Temporarily exceeding this limit may cause a shift in the
parametric performance due to a change in the stresses exerted
on the die by the package. Exceeding a junction temperature of
175°C for an extended period can result in device failure.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power dissipation is the voltage between the supply pins (VS+
and VS−) times the quiescent current (IS). Power dissipated due
to load drive depends upon the particular application. It is cal-
culated by multiplying the load current by the associated voltage
drop across the device. RMS voltages and currents must be used
in these calculations.
Airflow increases heat dissipation by reducing θJA.
To ensure optimal thermal performance, the exposed paddle
must be in an optimized thermal connection with an external
plane layer.
6
5
4
3
2
1
0
–40 –20 020 40 60 80
AMBI E NT TE M P E RATURE ( °C)
MAXIMUM POWER DISSIPATIO N (W)
07839-002
Figure 2. Maximum Power Dissipation vs. Ambient Temperature
on a JEDEC Standard 4-Layer Board
ESD CAUTION
AD8120 Data Sheet
Rev. A | Page 6 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. DNC = DO NO T CO NNE CT.
2. EXPOSED PAD O N UNDE RS IDE O F DEV ICE
MUST BE CO NNE CTED TO P CB P LANE.
07839-003
24 GND
23 V
CR
22 V
CG
21 V
CB
20 V
REF
19 DNC
18 GND
17 V
S+
1
2
3
4
5
6
7
8
GND
SDO/SDA
DNC
DNC
PD
SER_SEL
MODE
GND
9
10
11
12
13
14
15
16
V
S–
GND
B
OUT
GND
G
OUT
GND
R
OUT
V
S+
32
31
30
29
28
27
26
25
GND
CS/A0
SCK/SCL
SDI/A1
B
IN
G
IN
R
IN
V
S+
R
d
G
d
B
d
DIGITAL
CONTROL
ANALOG
CONTROL
AD8120
TOP VIEW
(No t t o Scal e)
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1, 8, 10, 12, 14,
18, 24, 32
GND
Ground.
2 SDO/SDA Serial Data Output for SPI Bus/Bidirectional Serial Data Line for I2C Bus.
3, 4, 19 DNC Do Not Connect.
5 PD Power-Down.
6 SER_SEL Selection of SPI Serial Bus or I2C Serial Bus (I2C = 0, SPI = 1).
7 MODE Selection of Analog Control Mode or Digital Control Mode (Digital = 0, Analog = 1).
9 VS− Negative Power Supply. Connect to −5 V.
11 BOUT Blue Channel Video Output.
13 GOUT Green Channel Video Output.
15 ROUT Red Channel Video Output.
16, 17, 25 VS+ Positive Power Supply. Connect to +5 V.
20 VREF Internal Reference Bypass. Connect a 0.01 μF capacitor between this pin and GND.
21 VCB Analog Delay Control Voltage, Blue Channel.
22 VCG Analog Delay Control Voltage, Green Channel.
23 VCR Analog Delay Control Voltage, Red Channel.
26 RIN Red Channel Video Input.
27
G
IN
Green Channel Video Input.
28 BIN Blue Channel Video Input.
29 SDI/A1 Serial Data Input for SPI Bus/I2C Address Bit 1.
30 SCK/SCL Serial Clock for SPI Bus/Serial Clock for I2C Bus.
31 CS/A0 Chip Select for SPI Bus/I2C Address Bit 0.
Exposed Pad EP Thermal Plane Connection. Connect the exposed pad on the underside of the AD8120 to any PCB
plane with voltage between VS+ and VS−.
Data Sheet AD8120
Rev. A | Page 7 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±5 V, RL = 150 Ω, 10% to 90% input rise/fall time (tR/tF) = 4 ns, unless otherwise noted.
4
2
0
–2
–4
–6
–8
–10
–12
0.3 110 100 1k
FREQUENCY (MHz)
NORM ALIZED GAI N ( dB)
07839-010
DELAY CODE = 63
DELAY CODE = 33
DELAY CODE = 1
DELAY CODE = 2
Figure 4. Small-Signal Frequency Response for Various Delay Settings,
VOUT = 0.2 V p-p
0.25
0.20
0.15
0.10
0.05
0
–0.05
–20 020 40 60 80 100 120
TIME (n s)
AMPLITUDE (V)
07839-012
DELAY CODE = 63
DELAY CODE = 33
DELAY CODE = 0
INPUT
VS = ±5V
LOAD = 150Ω
Figure 5. Small-Signal Pulse Response for Various Delay Settings
50
45
40
35
30
25
20
15
10
5
000.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
112 22 33 44 55 62
ANALOG CONTROL VOLTAGE (V)
DEL AY CODE
RELATIVE DELAY (ns)
07839-021
Figure 6. Relative Delay vs. Delay Code and Analog Control Voltage
4
6
2
0
–2
–4
–6
–8
–10
–12
0.3 110 100 1k
FREQUENCY (MHz)
NORM ALIZED GAI N ( dB)
07839-011
DELAY CODE = 63
DELAY CODE = 33
DELAY CODE = 1
DELAY CODE = 2
Figure 7. Video Signal Frequency Response for Various Delay Settings,
VOUT = 1.4 V p-p
1.8
0.8
1.0
1.2
1.4
1.6
0.6
0.4
0.2
0
–0.2
–20 020 40 60 80 100 120
TIME (n s)
AMPLITUDE (V)
07839-013
DELAY CODE = 63
DELAY CODE = 33
VS = ±5V, LOAD = 150Ω
DELAY CODE = 0
INPUT
Figure 8. Large-Signal Pulse Response for Various Delay Settings
120
110
100
90
80
70
60
50
400 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64
DEL AY CODE
QUIESCE NT CURRENT (mA)
07839-018
TWO CHANNE LS
ONE CHANNE L
THRE E CHANNE LS
Figure 9. Quiescent Current vs. Delay Code
AD8120 Data Sheet
Rev. A | Page 8 of 16
0
–30
–20
–10
–50
–40
–60
–70
–80
–90
–100
0.3 110 100 1k
FREQUENCY (MHz)
OUTPUT LEVEL (dB)
07839-014
DELAY CODE = 63
DELAY CODE = 0
DRIV ING R AND B S IMULT ANE OUSLY
MEAS URING G
Figure 10. Crosstalk on Green Channel vs. Frequency,
VOUT = 1.4 V p-p
10 100 1k 10k 100k 1M 10M 100M 1G
FRE QUENCY ( Hz )
OUTPUT VOLTAGE NOISE DENSITY (nV/ Hz)
07839-016
10k
1k
100
10
DELAY CODE = 63
DELAY CODE = 0
Figure 11. Output Voltage Noise Density vs. Frequency
5
4
3
2
1
00 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64
DEL AY CODE
RISE/FALL TIME (ns)
07839-019
TYPICAL RISE TIME
TYPICAL FALL TIME
Figure 12. 10% to 90% Rise/Fall Time vs. Delay Code,
VOUT = 1.4 V p-p, VIN Rise/Fall = 2 ns
20
10
0
–10
–20
–30
–40
–50
0.3 110 100 1k
FREQUENCY (MHz)
PO WER SUP P LY RE JE CTI ON RAT IO ( dB)
07839-015
VS+ PSRR AT DE LAY CODE 0
VS+ PSRR AT DE LAY CODE 63
VS– PSRR AT DE LAY CODE 0
VS– PSRR AT DE LAY CODE 63
Figure 13. PSRR vs. Frequency
5
4
3
2
1
00DEL AY CODE
4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64
INTEGRATED OUTPUT VOLTAGE NOISE (mV rms)
07839-017
Figure 14. Integrated Output Voltage Noise vs. Delay Code,
100 kHz to 160 MHz
160
140
120
100
80
60
40
20
0
–40 –30 –20 –10 010 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
QUIESCE NT CURRENT (mA)
07839-020
VS+, RGB DE LAY CODE 63
VS+, RGB DE LAY CODE 0
VS+, DIS ABLED
VS+, RG DE LAY CODE 63, B DELAY CO DE 0
VS+, R DEL AY CODE 63, G B DE LAY CODE 0
Figure 15. Quiescent Current vs. Temperature
Data Sheet AD8120
Rev. A | Page 9 of 16
THEORY OF OPERATION
The AD8120 is a triple, digitally controlled analog delay line,
optimized for correcting delay skew between individual channels
in common wired communication media such as unshielded
twisted pair (UTP), shielded twisted pair (STP), and coaxial
cables. In these applications, the AD8120 is used to time-align
three video signals, usually RGB or YPbPr, that arrive at a
receiver at different times due to variations in total delay per
channel. Although its primary application is analog video, the
AD8120 can be applied in other systems that require variable
analog delays up to 50 ns with 0.8 ns resolution.
The three channels consist of cascaded delay sections that are
switched in such a way as to provide a total of 50 ns total delay
difference between channels with 0.8 ns resolution. A fixed
propagation delay is common to all channels, where the associated
delay is set to 0. Therefore, the delay setting for a given channel is
a measure of the relative delay among the channels, rather than
an absolute delay.
There are three options for controlling the delay: serial periph-
eral interface (SPI) serial bus, I2C serial bus, and analog control
voltage. Two pins select the type of control: the MODE pin selects
analog or digital control, and the SER_SEL pin selects the SPI or
I2C serial bus (see Table 5).
Table 5. Modes of Control
PD (Pin 5) MODE (Pin 7) SER_SEL (Pin 6) Control Type
0 X X Power-down
1 0 0 I2C control
1 0 1 SPI control
1 1 X Analog control
In analog control mode, three control voltages, VCR, VCG, and
VCB, control the delay of each channel. These voltages are
converted internally to digital codes with 0.8 ns steps.
Each AD8120 channel has a fixed overall gain of 2 and can
drive up to four double-terminated 75 Ω cables or PCB traces.
A power-down feature can shut down the AD8120 for power
saving when not in use.
CONTROLLING THE DELAY
The delay time of each of the three channels is controlled in one
of three ways. One control option is the application of analog
control voltages to the VCR, VCG, and VCB inputs. The other two
control options are via the SPI or I2C serial digital bus. The delay
is set in discrete amounts with a nominal resolution of 0.8 ns per
quantization level (or LSB), even in the analog control mode.
A delay code is assigned to each quantization level, ranging from
0 to 63 in decimal format. The means of control (analog, SPI, or
I2C) is selected by applying the appropriate logic levels to the
MODE and SER_SEL inputs (see Table 5). All three channels
must use the same delay control option in a given application.
It is important to note that in skew correction applications, the
metric is the relative delay between channels, not the absolute
delay. Each channel of the AD8120 exhibits a constant delay at
its zero delay setting, referred to as its propagation delay. This
propagation delay is well matched between the channels and is
subtracted out when performing skew correction. The delay
codes, therefore, ignore the constant propagation delay and
refer only to adjustable delay beyond the propagation delay.
Delay can be calculated by multiplying the delay code by 0.8 ns.
For example, setting the red delay to 8 ns (delay code = 10), the
green delay to 16 ns (delay code = 20), and the blue delay to 28 ns
(delay code = 35) produces the following relative delays: green
delayed by 8 ns relative to red, blue delayed by 20 ns relative to
red, and blue delayed by 12 ns relative to green. If an application
requires control of absolute delay, the propagation delay must be
added to the delay corresponding to the associated delay code.
SETTING THE DELAY
In most video skew compensation applications, it is best to set
the delay of the path with the longest delay to 0, and then to add
delay to the other paths to match the longest delay. In this way,
the bandwidth of each path is maximized, and the noise of each
path is minimized. Figure 16 illustrates a case where a test step
is applied simultaneously to each cable input, and the green
cable delay is the longest.
RED CABL E OUTP UT
28ns
GRE E N CABLE O UTPUT
BLUE CABLE O UTPUT
40ns
07838-022
Figure 16. Cable Delay Example
In the example in Figure 16, the AD8120 green delay should be
set to 0. The AD8120 red delay is then set to the delay difference
between the green and red outputs, or 40 ns. Finally, the AD8120
blue delay is set to the delay difference between the green and blue
outputs, or 28 ns. Using the digital delay codes, green delay = 0,
red delay = 50, and blue delay = 35.
AD8120 Data Sheet
Rev. A | Page 10 of 16
ANALOG CONTROL
A number of video transmission systems do not have a microcon-
troller embedded or otherwise available to provide digital control.
These systems require analog control. Potentiometer control is
one of the most common ways to implement analog control (see
Figure 25). To select analog control, set the MODE pin high.
The AD8120 has one analog control input for each channel: VCR,
VCG, and VCB. The maximum recommended control voltage range
on these inputs is 0 V to 2.0 V, although the actual control range
where delay changes take effect is smaller and lies within this larger
range. An internal ADC converts the analog control voltages
into binary delay codes; therefore, the analog control is discrete
with nominally 0.8 ns resolution. Figure 6 illustrates the typical
transfer characteristic between control voltage and delay code.
POWER DOWN
The power-down feature is intended to be used to reduce power
consumption when a particular device is not in use and does
not place the output in a high-Z state when asserted. Note that
the input high level for the power-down input is higher than it
is for the other digital inputs. Refer to the Specifications in
Table 1 for details.
DIGITAL CONTROL
Set the MODE pin low to select digital control (SPI or I2C). Set
the SER_SEL pin high to select SPI mode, or set the SER_SEL
pin low to select I2C mode. Table 6 provides the bit values for
reading and writing the red, green, and blue registers.
Table 6. Read/Write Instruction and Color Registers
Operation R/W Bit C1 Bit C0 Bit
Write Red 0 0 0
Read Red 1 0 0
Write Green 0 0 1
Read Green 1 0 1
Write Blue
0
1
0
Read Blue 1 1 0
SPI Control
The SPI bus operates in full-duplex mode and consists of four
digital lines: SDI, SDO, SCK, and CS.
Table 7. AD8120 SPI Pin Descriptions
Pin No.
Pin
Name Description
29 SDI Serial data input, master out slave in (MOSI)
2 SDO Serial data output, master in slave out (MISO)
30 SCK Serial clock from master
31 CS Chip select; active low
The AD8120 is programmed in SPI mode using a 2-byte sequence
(see Table 8). Data is clocked into the SDI pin or clocked out of
the SDO pin on the rising edge of the clock, MSB first. The first
byte contains the read/write (R/W) instruction and the color reg-
ister address (see Table 6). The second byte contains the delay
code to write to the part (R/W = 0) or the stored delay code to
read from the part (R/W = 1).
Figure 17 shows how to write Delay Code 42 to the green
register. Figure 18 shows how to read Delay Code 21 from
the blue register.
Table 8. SPI 2-Byte Sequence
Byte 1 (R/W Bit and Color Register) Byte 2 (Data)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SDI R/W 0 0 0 0 0 C1 C0 X X D5 D4 D3 D2 D1 D0
SDO X X X X X X X X X X D5 D4 D3 D2 D1 D0
Data Sheet AD8120
Rev. A | Page 11 of 16
BYTE 2
DATA
BYTE 1
R/W BIT AND COL OR REG ISTER
START STOP
CS
SCK
SDI
SDO
00000001
XXXXXXXX
X X 1 0 1 0 01
XXXXXXXX
07839-025
Figure 17. Setting the Green Register to Delay Code 42 Using SPI
BYTE 2
DATA
BYTE 1
R/W BIT AND COL OR REG ISTER
START STOP
CS
SCK
SDI
SDO
10000010
X X 0 1 0 1 0 1
X X X X X X XX
XXXXXXXX
07839-026
Figure 18. Reading Delay Code 21 from the Blue Register Using SPI
AD8120 Data Sheet
Rev. A | Page 12 of 16
I2C Control
The I2C interface of the AD8120 is a 2-wire interface consisting
of a clock input and a bidirectional data line. The AD8120
drives the SDA line either to acknowledge the master (ACK) or
to send data during a read operation. The SDA pin for the I2C
port is open drain and requires a 10 kΩ pull-up resistor.
Table 9. AD8120 I2C Pin Descriptions
Pin No. Pin Name Description
2 SDA Serial data input/output
30 SCL Serial clock input
29 A1 I2C Address Bit A1
31
A0
I
2
C Address Bit A0
The AD8120 address consists of a built-in address of 0x38 and the
two address pins, A0 and A1. The two address pins enable up to
four AD8120 devices to be used in a system (see Table 10). Both
address pins must be terminated (high or low) for the AD8120
I2C interface to operate properly.
Table 10. I2C Addresses
A1 Pin A0 Pin I2C Address
0 0 0x38
0 1 0x39
1 0 0x3A
1 1 0x3B
In I2C mode, the AD8120 is programmed with a 3-byte sequence
for a write operation (see Figure 19) and a 4-byte sequence for a
read operation (see Figure 20). The first byte contains the 7-bit
device address and the R/W instruction bit. The second byte con-
tains the color register.
In write mode, the third byte contains the delay code. In read
mode, the third byte contains the device address, and the fourth
byte contains the stored delay code.
ST ART BY
MASTER
STOP BY
MASTER
ACK BY
AD8120 ACK BY
AD8120
ACK BY
AD8120
0
11 99
1 1 1 0 A1 A0 00 0 0 0 0 0 C1 C0
SCL
SDA
SDA (CONTINUED)
SCL ( CONTINUED)
91
X X D5 D4 D3 D2 D1 D0
R/W
07839-023
BYTE 1
I
2
C ADDRESS BYTE 2
COLOR REGISTER
BYTE 3
DEL AY DATA CODE
Figure 19. I2C Write Sequence
ST ART BY
MASTER ACK BY
AD8120 ACK BY
AD8120
R/W
SCL
1 1 99
SDA 0 1 1 1 0
0 1 1 1 0
A1 A0 00 0 0 0 0 0 C1 C0
BYTE 1
I2C ADDRESS BYTE 2
COLOR REGISTER
BYTE 3
I2C ADDRESS BYTE 4
DATA BY TE F ROM AD8120
STOP BY
MASTER
ST ART BY
MASTER ACK BY
AD8120 NO ACK BY
AD8120
SCL
1 1 99
SDA A1 A0 1 X X D5 D4 D3 D2 D1 D0
R/W
07839-024
Figure 20. I2C Read Sequence
Data Sheet AD8120
Rev. A | Page 13 of 16
SPI Timing
Figure 21 shows the SPI 2-byte timing sequence. Table 11 lists
the timing parameters for SPI.
CS
SCK
SDI/SDO
R/W
00000C1 C0 X X D5 D4 D3 D2 D1 D0
07839-005
Figure 21. SPI 2-Byte Timing Sequence
t
6
t
1
t
2
t
4
t
5
t
3
CS
SCK
SDI R/W D1 D0
07839-006
Figure 22. SPI Timing Diagram
Table 11. SPI Timing Parameters
Parameter Description
t1 Setup time, CS to SCK
t2 Clock pulse high, SCK
t3 Clock pulse low, SCK
t4 Setup time, SDI to SCK
t5 Hold time, SDI to SCK
t6 Hold time, SCK to CS
I2C Timing
Figure 23 shows the I2C 3-byte timing sequence. Table 12 lists
the timing parameters for I2C.
SDA 0 1 1 1 0 00 0 00 0 XX
D0
D1
D2
D3
D4
D5
C0
C1
A0
A1
ACK
ACK
ACK
R/W
SCL
07839-007
Figure 23. I2C 3-Byte Timing Sequence
SDA
SCL t1t2t3t5t6
t4
07839-008
Figure 24. I2C Timing Diagram
Table 12. I2C Timing Parameters
Parameter Description
t1 Setup time, SDA to SCL
t2 Clock pulse high, SCL
t3 Clock pulse low, SCL
t4 Setup time, SDA (input) to SCL
t5 Hold time, SDA (input) to SCL
t6 Hold time, SCL to SDA
AD8120 Data Sheet
Rev. A | Page 14 of 16
APPLICATIONS INFORMATION
Most twisted pair (TP) cables used for video transmission are
designed for data communication and typically contain four
individual TP channels. Minimization of crosstalk between pairs
is of paramount importance in data communication applications.
This is accomplished by varying the twist rates (twists per unit
length) of each pair. For a given cable length, signals traveling
on pairs with relatively high twist rates have longer distances to
traverse than signals traveling on pairs with relatively low twist
rates. The longer relative distances translate into longer relative
delays and, similarly, the shorter relative distances translate into
shorter relative delays.
The delay of any TP channel is not flat over frequency, and
an equalizer is generally used at the receiver to produce an
approximately flat delay vs. frequency characteristic as well as
an approximately flat frequency response magnitude over the
bandwidth of interest. The term “group delay” is often used in
the delay vs. frequency context. When the group delay and the
magnitude response have been corrected to the best possible
degree at the receiver, the remaining signals are close approxi-
mations to those sent at the transmit end of the cable, but with
different delays with respect to the signals sent at the transmit
end. The signals, therefore, manifest different delays relative to
each other.
The relative delay difference between any two equalized signals
at the receiver is defined as delay skew, or simply skew, and is
measured in units of time. Some bundled coaxial cables also
exhibit delay skew between channels; these skew levels are
typically much smaller than those encountered among similar
length TP channels.
The AD8120 can be used with RGB and YPbPr, as well as other
video formats. Typically, three video component signals are trans-
mitted over the TP cables, with each component carried on a pair.
For example, with RGB video signals, the red, green, and blue
signals are each transmitted over one pair. If these signals are
carried over a cable with skew larger than a quarter of a pixel
time and are displayed on a video monitor, the three colors will
not be properly aligned and the skew will be visible at the vertical
edges of objects displayed on the monitor. For fractional pixel
time skew levels, a rainbow-like effect appears at the vertical
edges of the objects; for skew levels longer than a pixel time,
vertical lines are visible on the vertical edges of objects. The
vertical lines are due to one color arriving earlier or later than
the others. The best way to observe skew is to view an object
against a black background.
The AD8120 is a triple adjustable delay line, and its primary
application is to realign the received, equalized video compo-
nents. The pixel time of UXGA video with a refresh rate of
60 Hz is approximately 6.2 ns. In this case, the 0.8 ns delay
resolution of the AD8120 represents approximately 13% of
a pixel time.
TYPICAL APPLICATION CIRCUIT FOR THE AD8123
AND AD8120
Figure 25 illustrates a complete receiver application circuit using
sync-on common mode; this circuit comprises the AD8123
triple equalizer and the AD8120. The circuit receives balanced
RGB video signals over TP cable, performs cable equalization
and skew correction, and directly drives 75 Ω coaxial cable. The
6 dB voltage gain in the AD8120 compensates for the 6 dB double
termination loss incurred driving the coaxial cable. The low-pass
filter is optimized for short distances. Refer to the AD8123 data
sheet for details regarding the sync encoding and decoding.
The filter between the AD8123 and the AD8120 is a three-pole
low-pass filter (LPF) with a cutoff frequency of approximately
148 MHz; the LPF is included to provide high frequency noise
reduction. The filter shown in the application circuit performs
well for short to medium length cables. Note that the 1 pF capaci-
tance of each AD8120 input is added to each filter capacitor that
is connected to each AD8120 input. Thus, for the filter shown,
the actual filter capacitance at each AD8120 input is 16 p F.
For longer cables, where much greater high frequency gain is
required from the AD8123, it may be desirable to scale the LPF
bandwidth back to provide greater noise reduction. This can be
done by simply scaling the inductor and capacitor values by the
ratio of the existing cutoff frequency of 140 MHz to the desired
new cutoff frequency. For example, if a new cutoff frequency of
100 MHz is desired, the inductor and capacitor values are scaled
by a factor of (140 MHz/100 MHz) = 1.4. This is summarized in
Table 13.
Table 13. Low-Pass Filter Component Selection
for 100 MHz Cutoff
Original Value
Scale
Factor
New Value
Ideal Standard
5.6 pF
1.4
7.8 pF
7.5 pF
150 nH 1.4 210 nH 220 nH
15 pF + 1 pF1 = 16 pF 1.4 22.4 pF − 1 pF1 = 21.4 pF 22 pF
1 Input capacitance of the AD8120.
Data Sheet AD8120
Rev. A | Page 15 of 16
RED
1
2
0.1µF
11
0.1µF
14
0.1µF
17
0.1µF
22
0.1µF
33
0.1µF
9
0.1µF
13
0.1µF
16
0.1µF
19
0.1µF
29
0.1µF
36
0.1µF
5
49.9Ω
49.9Ω
49.9Ω
49.9Ω
475Ω
RECEIVED
RED VIDEO
POWER-DOWN
CONTROL
ANALOG
CONTROL
INPUTS
GREEN
49.9Ω
49.9Ω
RECEIVED
GREEN VIDEO
BLUE
49.9Ω
49.9Ω
1kΩ
1kΩ
RECEIVED
BLUE V IDEO
47pF
47pF
8
3
2
38
37
35
34
32
31 18
15
12
24, 39
4
6
28
RED CMV
BLUE CM V
GREEN
CMV 7
23 V
OFFSET
V
S+
V
S+
V
S+
V
S+
V
S+
V
S+
_CMP
V
S–
V
S–
V
S–
V
S–
V
S–
V
S–
_CMP
25 VGAIN
27 VPOLE
26 VPEAK
PD
AD8123
GND
OUTR
OUTG
OUTB
OUTCMP1
OUTCMP2
5.6pF 15pF
100Ω
SERIAL BUS
FOR DIGITAL CO NTROL
150nH
5.6pF 15pF
100Ω 150nH
5.6pF 15pF
100Ω 150nH
4700pF 4700pF
–5V
FAIR-RITE
2743021447
4700pF 4700pF
+5V
FAIR-RITE
2743021447
GND
VCR
VCG
VCB
VREF
DNC
GND
VS+
VS–
GND
BOUT
GND
GOUT
GND
ROUT
VS+
GND
SDO/SDA
DNC
DNC
PD
SER_SEL
MODE
GND
241
2
3
4
5
6
7
8
–5V +5V
32 31
10 11 12 13 14 15 16
9
30 29 28 27 26 25
+5V
+5V
23
22
21
20
19
18
17
RED O UT
GRE E N OUT
BLUE OUT
HSYNC OUT
VSY NC OUT
0.1µF
0.1µF
0.1µF 0.1µF
75Ω
75Ω
75Ω
0.1µF
GND
SCK/SCL
SDI/A1
BIN
GIN
RIN
VS+
CS/A0
AD8120
EXPOSED PADDLE
CONNECTED TO GND
CONTROL
INPUTS
+5V
7.5kΩ
5kΩ
RED
+5V
7.5kΩ
5kΩ
GREEN
+5V
7.5kΩ
5kΩ
BLUE
POTENTIOMETERS
FOR ANALOG CONT RO L
07839-004
Figure 25. Typical Application Circuit
AD8120 Data Sheet
Rev. A | Page 16 of 16
OUTLINE DIMENSIONS
3.65
3.50 S Q
3.35
FOR PRO P E R CONNECTI ON O F
THE EXPOSED PAD, REFER TO
THE P IN CONFI GURAT IO N AND
FUNCTION DES CRIPTI ONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JE DE C S TANDARDS MO-220-V HHD- 2
32
98
1
25
24
17 16
COPLANARITY
0.08
3.50 REF
0.50
BSC
PI N 1
INDICATOR
PIN 1
INDICATOR
0.30
0.25
0.18 0.20 REF
12° M AX 0.80 M AX
0.65 TYP
1.00
0.85
0.80 0.05 MAX
0.02 NOM
SEATING
PLANE
0.50
0.40
0.30
5.00
BSC SQ
4.75
BSC SQ
0.60 M AX
0.60 M AX
0.25 M IN
04-13-2012-A
TOP VIEW
EXPOSED
PAD
BOTTOM VIEW
Figure 26. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Temperature Range
Package Description
Package Option
AD8120ACPZ-R2 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-4
AD8120ACPZ-R7 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-4
AD8120ACPZ-RL −40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-4
1 Z = RoHS Compliant Part.
©2009–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07839-0-5/12(A)
