MPC5566 Microcontroller Data Sheet, Rev. 3
Revision History for the MPC5566 Data Sheet
Freescale Semiconductor64
Tabl e 22 , Bus Operation Timing:
• Added a column to the table for 72 MHz minimum and maximum bus frequencies.
• Spec 1: 72 MHz Min. column = 13.3.
• Specs 5 and 6: CLKOUT positive edge to output signals invalid of high: Corrected format to show the bus timing
values for various frequencies with EBTS bit = 0 and EBTS bit = 1.
• Specs 5, and 6: Added the BB signal for arbitration. Added the following calibration signals: CAL_ADDR[9:30],
CAL_CS[0:3], CAL_DATA[0:15], CAL_OE, CAL_RD_WR, CAL_TS, CAL_WE/BE[0:1].
• Spec 5: EBI and Calibration sections, 72 MHz Min column, EBTS = 0 is 1.0, EBTS = 1 is 1.5.
• Spec 6: EBI section, 72 MHz Max column, EBTS = 0 is 5.0, EBTS = 1 is 6.0.
• Spec 6a: Calibration section, 72 MHz Max column, EBTS = 0 is 6.0, EBTS = 1 is 7.0
• Specs 7 and 8: Added the BB signal for arbitration. Added the following calibration signals: CAL_ADDR[9:30],
CAL_DATA[0:15], CAL_RD_WR, CAL_TS.
Tabl e 23 , External Interrupt Timing:
• Footnote 1: Deleted ‘. . FSYS = 132 MHz’, ‘VDD33 and VDDSYN = 3.0–3.6 V’ and ‘ .and CL = 200 pF with SRC =
0b11.’
• Deleted second figure after table ‘External Interrupt Setup Timing.’
Table 24, eTPU Timing
• Footnote 1: Deleted ‘. . .FSYS = 132 MHz’, ‘VDD33 and VDDSYN = 3.0–3.6 V’ and ‘and CL = 200 pF with
SRC = 0b11.’
• Deleted second figure, ‘eTPU Input/Output Timing’ after this table.
• Added Footnote 2: ‘This specification does not include the rise and fall times. When calculating the minimum
eTPU pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad
configuration registers (PCR).’
Tabl e 25 , eMIOS Timing:
• Deleted (MTS) from the heading, table, and footnotes.
• Footnote 1: Deleted ‘. . .FSYS = 132 MHz, ‘VDD33 and VDDSYN = 3.0–3.6 V’ and ‘and CL = 200 pF with
SRC = 0b11.’
• Added Footnote 2: ‘This specification does not include the rise and fall times. When calculating the minimum
eMIOS pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad
configuration registers (PCR).’
Figure 17, eMIOS Timing: Added figure.
Tabl e 26 , DSPI Timing:
• Added 144 MHz column to the table.
• Spec1:SCK Cycle Time: changes to values: 80 MHz, min. = 24.4; 112 MHz, min. = 17.5, max = 2.1;
132 MHz, min. = 14.8, max = 1.8; 144 MHz, min. = 13.6, max = 1.6.
• Spec1:SCK Cycle Time: Added footnote 4 to the 144 MHz min. and max values that reads: Preliminary.
Specification pending final characterization
• Spec 2, PCS to SCK delay, 144 MHz, min. TBD
• Spec 3, After SCK delay, 144 MHz, min. TBD
• Spec 9, Master (MTFE = 1, CPHA = 0), 144 MHz, min. TBD
• Spec 10, Master (MTFE = 1, CPHA = 0), 144 MHz, min. TBD
• Spec 11, Master (MTFE = 1, CPHA = 0), 144 MHz, max TBD
• Spec 12, Master (MTFE = 1, CPHA = 0), 144 MHz, min. TBD
• Added to beginning of footnote 1 ‘All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad
type M or MH. DSPI signals using pad types of S or SH have an additional delay based on the slew rate.’
• Footnote 1: Deleted ‘VDD = 1.35–1.65 V’ and ‘VDD33 and VDDSYN = 3.0–3.6 V.
Table 35. Table and Figure Changes Between Rev. 0.0 and Rev. 1.0 (continued)
Location Description of Changes