Advanced Power
Electronics Corp. APE8977MP
APPLICATION INFORMATION
Input Capacitor and Layout Consideration
Consideration while designs the resistance of voltage divider
Thermal Consideration
4
Make sure the sinking current capability of pull-down NMOS if the lower resistance was
chosen so that the voltage on VREFEN is below 0.15V. In addition, the capacitor and voltage divider
form the lowpass filter. There are two reasons doing this design; one is for output voltage soft-
start while another is for noise immunity.
APE8977MP regulators have internal thermal limiting circuitry designed to protect the device
during overload conditions.For continued operation, do not exceed maximum operation junction
temperature 125oC. The power dissipation definition in device is:
PD = (VIN - VOUT) x IOUT + VIN x IQ
The maximum power dissipation depends on the thermal resistance of IC package, PCB
layout, the rate of surroundings airflow and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by following formula:
PD(MAX) = ( TJ(MAX) -TA ) / Rthja
Where TJ(MAX) is the maximum operation junction temperature 125oC, TAis the ambient
temperature and the Rthja is the junction to ambient thermal resistance. The junction to ambient
thermal resistance (Rthja is layout dependent) for ESOP-8 package (Exposed Pad) is 75oC/W on
standard JEDEC 51-7 (4 layers, 2S2P) thermal test board. The maximum power dissipation at TA
= 25oC can be calculated by following formula:
PD(MAX) = (125oC - 25oC) / 75oC/W = 1.33W
The thermal resistance Rthja of ESOP-8 (Exposed Pad) is determined by the package design
and the PCB design. However, the package design has been decided. If possible, it's useful to
increase thermal performance by the PCB design. The thermal resistance can be decreased by
adding copper under the expose pad of ESOP-8 package. We have to consider the copper
couldn't stretch infinitely and avoid the tin overflow.
Place the input bypass capacitor as close as possible to the APE8977MP. A low ESR
capacitor larger than 470uF is recommended for the input capacitor. Use short and wide traces to
minimize parasitic resistance and inductance.
Inappropriate layout may result in large parasitic inductance and cause undesired oscillation
between APE8977MP and the preceding powe converter.