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Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. "Standard": 8. 9. 10. 11. 12. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. DATA SHEET MOS INTEGRATED CIRCUIT PD8880 (10680 x 10680) PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR DESCRIPTION The PD8880 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The PD8880 has 3 rows of (10680+10680) staggered pixels, and each row has a dual-sided readout type of charge transfer register. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for 2400 dpi/A4 color image scanners, color facsimiles and so on. FEATURES * Valid photocell : (10680+10680) pixels x 3 * Photocell pitch : 4 m * Line spacing : 64 m (16 lines) Red line - Green line, Green line - Blue line 8 m (2 lines) Odd line - Even line (for each color) 7 * Color filter : Primary colors (red, green and blue), pigment filter (with light resistance 10 lx*hour) * Resolution : 96 dot/mm A4 (210 x 297 mm) size (shorter side) 2400 dpi US letter (8.5" x 11") size (shorter side) : * Drive clock level : CMOS output under 5 V operation * Data rate : 8 MHz Max. * Power supply : +12 V * On-chip circuits : Reset feed-through level clamp circuits :: Voltage amplifiers ORDERING INFORMATION <R> Part Number Package PD8880CY-A CCD linear image sensor 32-pin plastic DIP (10.16 mm (400)) Remark The PD8880CY-A is a lead-free product. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S16032EJ4V0DS00 (4th edition) Date Published February 2006 NS CP (N) Printed in Japan 2002 The mark <R> shows major revised points. The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field. PD8880 BLOCK DIAGRAM VOD 29 GND GND 1 16 2L 2 1 19 20 13 18 TG1 (Blue) 17 TG2 (Green) 15 TG3 (Red) D68 D66 D67 D69 S21359 Photocell (Blue) S21360 S1 S2 **** D64 VOUT1 30 (Blue) D65 D14 CCD analog shift register Transfer gate Transfer gate CCD analog shift register D69 D67 D68 D66 S21359 Photocell (Green) S21360 S1 S2 **** D64 VOUT2 31 (Green) D65 D14 CCD analog shift register Transfer gate Transfer gate CCD analog shift register D69 D68 D67 D66 S21359 Photocell (Red) S21360 S1 S2 **** D64 VOUT3 32 (Red) D65 D14 CCD analog shift register Transfer gate Transfer gate CCD analog shift register 3 2 CLB RB 2 14 5 4 1L 2 1 Data Sheet S16032EJ4V0DS PD8880 PIN CONFIGURATION (Top View) CCD linear image sensor 32-pin plastic DIP (10.16 mm (400)) * PD8880CY-A 32 VOUT3 Output signal 3 (Red) Reset gate clock RB 2 31 VOUT2 Output signal 2 (Green) Reset feed-through level clamp clock CLB 3 30 VOUT1 Output signal 1 (Blue) Shift register clock 1 1 4 29 VOD Output drain voltage Shift register clock 2 2 5 28 NC No connection Internal connection IC 6 27 IC Internal connection Internal connection IC 7 26 IC Internal connection No connection NC 8 25 NC No connection No connection NC 9 24 NC No connection No connection NC 10 23 NC No connection Internal connection IC 11 22 IC Internal connection Internal connection IC 12 21 IC Internal connection Shift register clock 1 1 13 20 2 Shift register clock 2 Last stage shift register clock 1 1L 14 19 2L Last stage shift register clock 2 Transfer gate clock 3 (for Red) TG3 15 18 TG1 Transfer gate clock 1 (for Blue) Ground GND 16 17 TG2 Transfer gate clock 2 (for Green) Blue 21360 Green 21360 Red 21360 1 1 1 GND 1 Ground Cautions 1. Leave pins 6 , 7, 11, 12, 21, 22, 26, 27 (IC) unconnected. 2. Connect the No connection pins (NC) to GND. Data Sheet S16032EJ4V0DS 3 PD8880 PHOTOCELL STRUCTURE DIAGRAM 4 m 2 m 2 m Channel stopper Aluminum shield PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing) 4 m 4 m 4 m Blue photocell array Blue photocell array 2 lines (8 m) 14 lines (56 m) 4 m 4 m 4 m Green photocell array Green photocell array 2 lines (8 m) 14 lines (56 m) 4 m 4 m 4 m 4 Red photocell array Red photocell array Data Sheet S16032EJ4V0DS 16 lines (64 m) 2 lines (8 m) 16 lines (64 m) PD8880 ABSOLUTE MAXIMUM RATINGS (TA = +25C) Parameter Symbol Ratings Unit Output drain voltage VOD -0.3 to +15 V Shift register clock voltage V 1, V 2, V 1L, V 2L -0.3 to +8 V Reset gate clock voltage V RB -0.3 to +8 V Reset feed-through level clamp V CLB -0.3 to +8 V V TG1 to V TG3 -0.3 to +8 V clock voltage Transfer gate clock voltage Operating ambient temperature Note Storage temperature TA 0 to +60 C Tstg -40 to +70 C Note Use at the condition without dew condensation. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. RECOMMENDED OPERATING CONDITIONS (TA = +25C) Parameter Symbol Min. Typ. Max. Unit Output drain voltage VOD 11.4 12.0 12.6 V Shift register clock high level V 1_H, V 2_H, V 1LH, V 2LH 4.8 5.0 5.5 V Shift register clock low level V 1_L, V 2_L, V 1LL, V 2LL -0.3 0 +0.2 V Reset gate clock high level V RBH 4.5 5.0 5.5 V Reset gate clock low level V RBL -0.3 0 +0.5 V Reset feed-through level clamp clock V CLBH 4.5 5.0 5.5 V V CLBL -0.3 0 +0.5 V Transfer gate clock high level V TG1H to V TG3H 4.8 V 1_H Transfer gate clock low level V TG1L to V TG3L -0.3 0 +0.15 V CCD Transfer speed f 1, f 2 - 1 6 MHz Data rate f RB - 2 8 MHz high level Reset feed-through level clamp clock low level Note V 1_H Note V Note When Transfer gate clock high level (V TG1H to V TG3H) is higher than Shift register clock high level (V 1_H), Image lag can increase. Data Sheet S16032EJ4V0DS 5 PD8880 ELECTRICAL CHARACTERISTICS TA = +25C, VOD = 12 V, data rate (f RB) = 2 MHz, storage time = 11.0 ms, input signal clock = 5 Vp-p, light source : 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm) Parameter Symbol Test Conditions Min. Typ. Max. Unit Saturation voltage 1 Vsat1 Note 1 2.5 3.5 - V Saturation voltage 2 Vsat2 Note 2 1.5 2.5 - V Photo response non-uniformity PRNU VOUT = 1.0 V - 6 20 % Average dark signal ADS Light shielding - 0.4 4.0 mV Dark signal non-uniformity DSNU Light shielding - 2.0 8.0 mV Power consumption PW - 290 450 mW Output impedance ZO - 0.3 1 k Red RR 2.52 3.60 4.68 V/lx*s Green RG 2.31 3.30 4.29 V/lx*s 1.26 1.80 2.34 V/lx*s - 1.0 7.0 % 4.5 6.0 7.5 V Response Blue Image lag Offset level RB IL Note 3 VOUT = 1.0 V VOS Note 4 td VOUT = 1.0 V - 25 - ns Total transfer efficiency TTE VOUT = 1.0 V, f 1, f 2 = 6 MHz 92 98 - % Register imbalance RI VOUT = 1.0 V - 1.0 4.0 % Red - 630 - nm Green - 540 - nm Blue - 460 - nm Output fall delay time Response peak Dynamic range Reset feed-through noise Random noise (CDS) Note 3 DR1 Vsat1/DSNU, Note 1 - 1750 - times DR2 Vsat1/ CDS, Note 1 - 3500 - times RFTN Light shielding -2000 -500 +500 mV CDS Light shielding - 1.0 - mV Notes 1. Vsat1: f 1, f 2 4 MHz, f RB 8 MHz 2. Vsat2: 4 MHz < (f 1, f 2) < 6 MHz, f RB 8 MHz (refer to TIMING CHART 3) 3. Refer to TIMING CHART 2. 4. When the fall time of 1L (t1') is the Typ. value (refer to TIMING CHART 2). 6 Data Sheet S16032EJ4V0DS PD8880 INPUT PIN CAPACITANCE (TA = +25C, VOD = 12 V) Parameter Shift register clock pin capacitance 1 Symbol Pin name C 1 1 Pin No. Min. Typ. Max. Unit 4 - 1100 - pF - 1100 - pF - 2200 - pF 5 - 1100 - pF 20 - 1100 - pF - 2200 - pF 13 1 total capacitance Shift register clock pin capacitance 2 C 2 2 2 total capacitance Last stage shift register clock pin capacitance 1 C 1L 1L 14 - 70 - pF Last stage shift register clock pin capacitance 2 C 2L 2L 19 - 70 - pF Reset gate clock pin capacitance C RB RB 2 - 20 - pF Reset feed-through level clamp clock pin capacitance C CLB CLB 3 - 20 - pF Transfer gate clock pin capacitance C TG TG1 18 - 200 - pF TG2 17 - 200 - pF TG3 15 - 200 - pF Remarks 1. Pins 4 and 13 ( 1), 5 and 20 ( 2) are each connected inside of the device. 2. C 1 and C 2 show the equivalent capacity of the real drive including the capacity of between 1 and 2. Data Sheet S16032EJ4V0DS 7 8 Data Sheet S16032EJ4V0DS Note Note Set the RB and CLB to high level during this period. VOUT1 to VOUT3 CLB RB 2, 2L 1, 1L TG1 to TG3 21425 21426 21427 21428 21429 21430 Invalid photocell (4 pixels) Valid photocell (21360 pixels) 61 62 63 64 65 66 Invalid photocell (4 pixels) Optical black (48 pixels) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TIMING CHART 1-1 (Bit clamp mode, for each color) Note PD8880 Data Sheet S16032EJ4V0DS Note 21425 21426 21427 21428 21429 21430 Invalid photocell (4 pixels) Valid photocell (21360 pixels) 61 62 63 64 65 66 Invalid photocell (4 pixels) Optical black (48 pixels) Remark Inverse pulse of the TG1 to TG3 can be used as CLB. Note Set the RB to high level during this period. VOUT1 to VOUT3 (TG1 to TG3) CLB RB 2, 2L 1, 1L TG1 to TG3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TIMING CHART 1-2 (Line clamp mode, for each color) Note PD8880 9 PD8880 TIMING CHART 2-1 (Bit clamp mode, for each color) t2 t1 90% 1 10% 90% 2 10% t1' 90% 1L 10% 90% 2L 10% t5 RB t2' t6 t3 t5 t4 t3 t6 t4 90% 10% t7 t9 t7 t9 t8 t10 t11 t8 t10 t11 90% CLB 10% td td RFTN VOUT VOS 10% Symbol 10 Min. Typ. Max. Unit t1, t2 0 30 - ns t1', t2' 0 5 - ns t3 20 100 - ns t4 75 200 - ns t5, t6 0 10 - ns t7 30 100 - ns t8 20 100 - ns t9, t10 0 10 - ns t11 5 25 - ns Data Sheet S16032EJ4V0DS PD8880 TIMING CHART 2-2 (Line clamp mode, for each color) t2 t1 90% 1 10% 90% 2 10% t2' t1' 90% 1L 10% 90% 2L 10% t5 t6 t5 t4 t3 t6 t4 90% RB CLB t3 10% "H" td td RFTN VOUT VOS 10% Symbol Min. Typ. Max. Unit t1, t2 0 30 - ns t1', t2' 0 5 - ns t3 20 100 - ns t4 75 200 - ns t5, t6 0 10 - ns TIMING CHART 3 (Sift Register Pulse 1, 2 = 6 MHz (Max.)) 1 4.8 V or more 30 ns or more 0.2 V or less 2 30 ns or more Data Sheet S16032EJ4V0DS 11 PD8880 TG1 to TG3, 1, 2 TIMING CHART t13 t14 t12 90% 10% t15 TG1 to TG3 t16 90% 1 2 t17 Note 1 t18 90% RB t7 90% CLB (Bit clamp mode) t20 t22 Note 2 t21 t23 90% 10% CLB (Line clamp mode) t9 Symbol t19 t10 Min. Typ. Max. Unit t7 30 100 - ns t9, t10 0 10 - ns 5000 10000 50000 ns t13, t14 0 50 - ns t15, t16 900 1000 - ns t17, t18 200 400 - ns t19 t12 t12 50000 ns t20, t21 0 50 - ns t22, t23 30 350 - ns t12 Notes 1. Set the RB and CLB to high level during this period. 2. Set the RB to high level during this period. Remark Inverse pulse of the TG1 to TG3 can be used as CLB. 12 Data Sheet S16032EJ4V0DS PD8880 1, 2 cross points 2 1 1.5 V to 3.5 V 1.5 V to 3.5 V 1, 2L cross points 1 2 V or more 0.5 V or more 2 V or more 0.5 V or more 2L 2, 1L cross points 2 1L Remark Adjust cross points ( 1, 2), ( 1, 2L) and ( 2, 1L) with input resistance of each pin. Data Sheet S16032EJ4V0DS 13 PD8880 DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage : Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure : SE Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity : PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula. PRNU (%) = x x 100 x x : maximum of xj - x 21360 x j x= j=1 21360 xj : Output voltage of valid pixel number j VOUT Register Dark DC level x x 4. Average dark signal : ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula. 21360 d ADS (mV) = j j=1 21360 dj : Dark signal of valid pixel number j 14 Data Sheet S16032EJ4V0DS PD8880 5. Dark signal non-uniformity : DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV) : maximum of dj - ADS j = 1 to 21360 dj : Dark signal of valid pixel number j VOUT ADS Register Dark DC level DSNU 6. Output impedance : ZO Impedance of the output pins viewed from outside. 7. Response : R Output voltage divided by exposure (lx*s). Note that the response varies with a light source (spectral characteristic). 8. Image lag : IL The rate between the last output voltage and the next one after read out the data of a line. TG ON Light OFF VOUT V1 VOUT IL (%) = V1 x 100 VOUT Data Sheet S16032EJ4V0DS 15 PD8880 9. Register Imbalance : RI The rate of the difference between the averages of the output voltage of Odd and Even bits, against the average output voltage of all the valid pixels. n 2 2 n (V2j -1 - V2j) j=1 RI (%) = x 100 n 1 n Vj j=1 n : Number of valid pixels Vj : Output voltage of each pixel 10. Random noise (CDS) : CDS Random noise CDS is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding). CDS is calculated by the following procedure. 1. One valid photocell in one reading is fixed as measurement point. 2. The output level is measured during the reset feed-through period which is averaged over 100 ns to get "VDi". 3. The output level is measured during the Video Output time averaged over 100 ns to get "VOi". 4. The correlated double sampling output is defined by VCDSi = VDi - VOi 5. Repeat the above procedure (1 to 4) for 100 times (= 100 lines). 6. Calculate the standard deviation CDS using the following formula equation. 100 CDS (mV) = (VCDS - V) i 2 i=1 100 , V= 1 100 VCDS 100 i = 1 Video Output Reset feed-through 16 Data Sheet S16032EJ4V0DS i PD8880 STANDARD CHARACTERISTIC CURVES (Reference Value) DARK OUTPUT TEMPERATURE CHARACTERISTIC STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25C) 8 2 1 Relative Output Voltage 2 1 0.5 0.2 0.25 0.1 0 10 20 30 40 0.1 50 Operating Ambient Temperature TA (C) 1 5 10 Storage Time (ms) TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter and heat absorbing filter ) (TA = +25C) 100 R B G 80 Response Ratio (%) Relative Output Voltage 4 60 40 G 20 B 0 400 500 600 700 800 Wavelength (nm) Data Sheet S16032EJ4V0DS 17 PD8880 APPLICATION CIRCUIT EXAMPLE +5 V + 10 F/16 V PD8880 1 0.1 F 200 2 RB 47 3 CLB 1 4 1 1 5 2 32 GND VOUT3 RB VOUT2 CLB VOUT1 VOD 2 NC IC IC IC IC NC NC 15 + 25 0.1 F 10 F/16 V 24 NC NC NC NC 23 TG 22 IC IC IC IC 1 2 12 4.7 47 F/25 V +5 V 26 11 14 0.1 F 27 10 1L + 28 9 100 B1 29 1 8 13 B2 30 7 1 +12 V 31 6 1 B3 21 1L 2L TG3 TG1 GND TG2 16 20 1 19 100 18 4.7 17 4.7 2 2L Cautions 1. Leave pins 6, 7, 11, 12, 21, 22, 26, 27 (IC) unconnected. 2. Connect the No connection pins (NC) to GND. Remarks 1. The inverters shown in the above application circuit example are the 74HC04 (f RB < 2 MHz, (f 1, f 2) < 1 MHz) or 74AC04 (2 MHz f RB 8 MHz, 1 MHz (f 1, f 2) 6 MHz). 2. The input clock register of RB (2 pin) shown in the above application circuit example are the 200 (74HC04) or 300 (74AC04). 3. Inverters B1 to B3 in the above application circuit example are shown in the figure blow. B1 to B3 EQUIVALENT CIRCUIT +12 V + 100 CCD VOUT 100 2SC945 2 k 18 Data Sheet S16032EJ4V0DS 47 F/25 V PD8880 PACKAGE DRAWING PD8880CY CCD LINEAR IMAGE SENSOR 32-PIN PLASTIC DIP (10.16 mm (400) ) (Unit : mm) 55.20.5 54.80.5 1st valid pixel 5.90.3 1 32 1 9.250.3 9.050.3 17 16 46.7 2.0 12.60.5 4.10.5 10.160.20 4.550.5 1.020.15 (1.80) 2 2.580.3 0.460.1 2.540.25 0.250.05 (5.42) 4.210.5 3 10.16 +0.7 -0.2 Name Dimensions Refractive index Plastic cap 52.2x6.4x0.7 1.5 1 1st valid pixel The center of the pin1 2 The surface of the CCD chip The top of the cap 3 The bottom of the package The surface of the CCD chip 32C-1CCD-PKG4-2 Data Sheet S16032EJ4V0DS 19 PD8880 RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. Type of Through-hole Device PD8880CY-A : CCD linear image sensor 32-pin plastic DIP (10.16 mm (400)) Process Partial heating method Cautions 1. Conditions Pin temperature : 300C or below, Heat time : 3 seconds or less (per pin) During assembly care should be taken to prevent solder or flux from contacting the plastic cap. The optical characteristics could be degraded by such contact. 2. Soldering by the solder flow method may have deleterious effects on prevention of plastic cap soiling and heat resistance. So the method cannot be guaranteed. 20 Data Sheet S16032EJ4V0DS PD8880 NOTES ON HANDLING THE PACKAGES 1 DUST AND DIRT PROTECTING The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. Don't either touch plastic cap surface by hand or have any object come in contact with plastic cap surface. Should dirt stick to a plastic cap surface, blow it off with an air blower. For dirt stuck through electricity ionized air is recommended. And if the plastic cap surface is grease stained, clean with our recommended solvents. CLEANING THE PLASTIC CAP Care should be taken when cleaning the surface to prevent scratches. We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below. Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is recommended that a clean surface or cloth be used. RECOMMENDED SOLVENTS The following are the recommended solvents for cleaning the CCD plastic cap. Use of solvents other than these could result in optical or physical degradation in the plastic cap. Please consult your sales office when considering an alternative solvent. Solvents Ethyl Alcohol Methyl Alcohol Isopropyl Alcohol N-methyl Pyrrolidone Symbol EtOH MeOH IPA NMP 2 MOUNTING OF THE PACKAGE The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't have any object come in contact with plastic cap. You should not reform the lead frame. We recommended to use a IC-inserter when you assemble to PCB. Also, be care that the any of the following can cause the package to crack or dust to be generated. 1. Applying heat to the external leads for an extended period of time with soldering iron. 2. Applying repetitive bending stress to the external leads. 3. Rapid cooling or heating 3 OPERATE AND STORAGE ENVIRONMENTS Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid storage or usage in such conditions. Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the devices are transported from a low-temperature environment to a high-temperature environment. Avoid such rapid temperature changes. For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E) 4 ELECTROSTATIC BREAKDOWN CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes detected. Before handling be sure to take the following protective measures. 1. Ground the tools such as soldering iron, radio cutting pliers of or pincer. 2. Install a conductive mat or on the floor or working table to prevent the generation of static electricity. 3. Either handle bare handed or use non-chargeable gloves, clothes or material. 4. Ionized air is recommended for discharge when handling CCD image sensor. 5. For the shipment of mounted substrates, use box treated for prevention of static charges. 6. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1 M. Data Sheet S16032EJ4V0DS 21 PD8880 [MEMO] 22 Data Sheet S16032EJ4V0DS PD8880 NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Data Sheet S16032EJ4V0DS 23 PD8880 * The information in this document is current as of February, 2006. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. 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The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1