TECHNICAL NOTE For Digital Still Cameras Controller Type System Switching Regulator ICs BD9730KV, BD9731KV, BD9733KN zDescription These 5-channel system switching regulators use external FETs and can be used to create power supplies for use in digital still cameras. Each channel's output voltage can be set externally according to the application. zFeatures 1) Wide input voltage range: 2) 3) 4) 5) 6) 7) 8) 9) 10) 1.5 V to 11 V (BD9733KN) 2.5 V to 11 V (BD9730KV) 2.8 V to 11 V (BD9731KV) High-precision reference voltage: 1% (BD9731KV, BD9733KN) Built-in circuit to shut off output during an overload (timer-latch type) Dead-time control for all channels Oscillating frequency can be set externally. Built-in thermal shutdown circuit Standby mode current: 0 A Channels 1, 4, and 5 support independent on/off control Step-up/step-down switchable (BD9733KN) Built-in sequence control switch circuit (BD9733KN) zApplications Digital still cameras, portable DVD players, digital video cameras zProduct line-up Parameter Input voltage Reference voltage precision Operating frequency range Step-up Step-down Step-up/step-down switchable Operating temperature range Package BD9730KV 2.5 V to 11 V 1 V 1.2% 100 kHz to 700 kHz 1CH 4CH - -20C to +85C VQFP48 BD9731KV 2.8 V to 11 V 1.5 V 1% 100 kHz to 700 kHz 1CH 4CH - -20C to +85C VQFP48 BD9733KN 1.5 V to 11 V 1 V 1% 100 kHz to 1 MHz 3CH 1CH 1CH -25C to +85C QFN48U Apr. 2005 zAbsolute maximum ratings (Ta = 25C) Parameter Power supply voltage BD9730KV, BD9731KV BD9733KN Symbol VCC VBAT,VCC,PVCC1,PVCC2 Range -0.3 to +12 -0.3 to +12 Unit V V VIN1 VIN2 -0.3 to +17 -0.3 to +12 V V VIN3 -9.0 to VREGA V VQFP48 900 *1 Pd mW QFN48U 760 *2 Operating temperature range Topr -20 to +85 C Storage temperature range Tstg -55 to +125 C *1: When mounted on a PCB (70 mm x 70 mm x 1.6 mm [thickness], glass epoxy). Reduced 9.0 mW/C when used at Ta = 25C. *2: When mounted on a PCB (70 mm x 70 mm x 1.6 mm [thickness], glass epoxy). Reduced 7.6 mW/C when used at Ta = 25C. Power dissipation zRecommended Operating Conditions Parameter Symbol BD9730KV Supply voltage VCC 2.5 V to 11 V *3 - VBAT Oscillating frequency fOSC 100 kHz to 700 kHz Driver output current IOUT Up to 30 mA *3: REG output decreases when VCC is lower than 2.6 V to 2.5 V. Parameter NON1, NON5 Pin input voltage Driver peak current BD9731KV 2.8 V to 11 V - 100 kHz to 700 kHz Up to 30 mA BD9733KN 2.5 V to 11 V *3 1.5 V to 11 V 100 kHz to 1 MHz Up to 30 mA BD9730KV Symbol VNON1, VNON5 Range 0.3 to 1.5 BD9733KN IPEAK Up to 200 mA IPG1 IPG2, IPG4 Up to 1 Up to 800 mA mA PG3 pin source current IPG3 Up to 1 mA SWOUT pin sink current ISWOUT Up to 300 mA PG1pin sink current PG2, PG4 pin sink current 2/16 Unit V zElectrical Characteristics BD9730KV, BD9731KV (Unless otherwise specified, Ta = 25C, Vcc = 6 V, fosc = 0.20 MHz, STB1 to STB5 = 3 V) Range Parameter Symbol Unit Conditions Min. Typ. Max. Standby current IST - - 9.5 STB1 to STB5 = 0 V A - 4.8 9.5 (BD9730KV) Circuit current ICC mA - 4.5 9.5 (BD9731KV) [Reference voltage] 0.988 1.0 1.012 IREF = -1 mA (BD9730KV) Output voltage VREF V 1.485 1.5 1.515 IREF = -1 mA (BD9731KV) Line regulation DVLI - 4.0 12.5 mV VCC = 3.0 V to 9.5 V Load regulation DVLO - 1.0 7.5 mV IREF = -0.1 mA to -1 mA Output current when shorted IOS 4 16 - mA VREF = 0 V [Internal regulator] VREGA 2.4 2.5 2.6 V IREG = -1 mA Output voltage REGA, REGD VREGD [Shutoff at overload] VSCP1 to VSCP5 = 1.5 V to 0.5 V 0.90 1.0 1.10 (BD9730KV) VSC1 to V CH1 to CH5 threshold VSC5 VSCP1 to VSCP5 = 2 V to 1 V 1.425 1.5 1.575 (BD9731KV) [Protection circuit] SCP pin detection voltage VTSC 0.90 1.0 1.10 V VSCP = 0 V to 1.5 V Standby voltage VSSC - 22 170 mV SCP pin source current ISCP -6 -4 -2 VSCP = 0.1 V A [Triangular waveform oscillator] Oscillating frequency fOSC1 0.179 0.200 0.221 MHz RT = 24 k, CT = 220 pF Frequency stability Df - 1 5 % VCC = 2.8 V 9.5 V RT pin voltage VRT 0.78 1 1.22 V CT pin sink current ICSO 32.2 46.0 59.8 A VCT = 1.7 V, RT = 24 k CT pin source current ICSI -54.6 -42.0 -29.4 A VCT = 1.7 V, RT = 24 k [Error amp] Low level output voltage VOL - - 0.3 V INV = 2 V VREGA High level output voltage VOH - - V INV = 0 V -0.3V [PWM comparator] - - 1.0 VDT = 1 V (BD9730KV) DTC input current IDT A - -1 -5 VDT = 1V(BD9731KV) VT0 - 1.49 - V 0% duty Input threshold voltage VT100 - 1.95 - V 100% duty [Output circuit] VCC VCC - Io = 10 mA (BD9730KV) -0.4 -0.2 High level output voltage on VSATH V driving VCC VCC - IO = 10 mA (BD9731KV) -0.3 -0.1 - 0.2 0.4 IO = -10mA (BD9730KV) Low level output voltage on VSATL V driving - 0.1 0.3 IO = -10mA (BD9731KV) I OSOURC Max. output source current 30 - - mA E Max. output sink current IOSINK - [STB1 to STB5] STB pin pull-down resistor RSTB 250 ON VSTBH 2.0 STB pin control voltage OFF VSTBL -0.3 This IC is not designed to be radiation-resistant. - -30 mA 400 - - 700 - 0.3 k V V 3/16 zBD9733KN (Unless otherwise specified, Ta = 25C. VBAT = 3 V, VCC = 5 V, RT = 11 k, CT = 180 pF, STB1 to STB5 = 3 V) Range Parameter Symbol Unit Conditions Min. Typ. Max. [Reference voltage ] Output voltage VREF 0.99 1.0 1.01 V IREF = 1 mA Line regulation DVLI - 4.0 12.5 mV VCC = 3.0 V to 9.5 V Load regulation DVLO - 1.0 7.5 mV IREF = 0.1 mA to 1 mA Output current when shorted IOS 4 16 - mA VREF = 0 V [Internal regulator] Output voltage REGA VREGA 2.4 2.5 2.6 V IREG = 1 mA [Under voltage lockout circuit ] Threshold voltage 1 VST1 2.3 2.4 2.5 V VCC monitor Hysteresis width 1 VST1 - 200 - mV Threshold voltage 2 VST2 - 2.0 - V VREGA monitor Hysteresis width 2 VST2 - 50 - mV [Startup circuit block] Oscillating frequency fSTART 50 120 220 kHz Operation start VBAT voltage VST1 - 1.1 1.5 V VBAT pin monitor Soft start charge current ISS 1.1 2.2 3.3 VSS = 0 V A [Short protection circuit ] Timer start 2.1 2.2 2.3 V FB pin monitor VTC threshold voltage SCP pin source current ISCP 0.5 1.0 1.5 VSCP = 0.1 V A SCP pin detection voltage VTSC 0.45 0.50 0.55 V SCP pin standby voltage VSSC - 22 170 mV [Triangular waveform oscillator] Oscillating frequency fOSC1 450 500 550 kHz RT = 11 k, CT = 180 pF Frequency stability Df - 1 5 % VCC = 3.0 V to 9.5 V RT pin voltage VRT 0.78 1.00 1.22 V [Error amp] Low level output voltage VOL - - 0.3 V INV = 2 V VREGA High level output voltage VOH - - V INV = 0 V -0.3 Output sink current IOI 200 700 - FB = 1.0 V, VINV = 1.1 V A Output source current IOO 40 80 - FB = 1.0 V, VINV = 0.9 V A [PWM comparator] VT0 - 1.49 - V 0% duty Input threshold voltage - 1.95 - V 100% duty VT100 MAX DUTY1,4,5 DMAX1 77 85 93 % VINV = 0.9 V, VSCP = 0 V MAX DUTY 2 77 85 93 % VINV = 0.9 V, VSCP = 0 V, UDSEL = 0 V DMAX2 (step-up operation) [Output circuit ] High level output voltage on VCC VCC VSATH - V Io = 10 mA driving -0.3 -0.1 Low level output voltage on VSATL - 0.1 0.3 V IO = -10 mA driving [Step-up/step-down selector ] Step-down VUDDO 2.0 - 11 V UDSEL2 pin control voltage Step-up VUDUP -0.3 - 0.3 V UDSEL2 pin RUDSEL2 250 400 700 k pull-down resistance This IC is not designed to be radiation-resistant. 4/16 zBD9733KN (Unless otherwise specified, Ta = 25C, VBAT = 3 V, VCC = 5 V, RT = 11 k, CT = 180 pF, STB1 to STB5 = 3 V) Range Parameter Symbol Unit Conditions Min. Typ. Max. [ POWERGOOD , Power on switch ] ON VPGON 2.0 11 V PONCNT pin control voltage OFF VPGOFF -0.3 0.3 V PONCNT pin RCTRL 250 400 700 k pull-down resistance POWERGOOD detection voltage VTHPG4 0.72 0.8 0.88 V Detection voltage: low high Hysteresis width VTLPG4 100 200 300 mV DELAY pin detection voltage VTHDE 1.8 2.0 2.2 V Detection voltage: low high Hysteresis width VTHDE 100 200 300 mV Output voltage VSAT1 1.6 3.2 V IO = 500 uA, PONCNT = 3.0 V PG1 Leak current ILEAK1 0 5 VPG = 5 V, PONCNT = 0 V A Output voltage VSAT2 0.1 0.3 V IO = 100 uA, PONCNT = 3.0 V PG2 Leak current ILEAK2 0 5 VPG = 5 V, PONCNT = 0 V A Output voltage VSAT3 0.1 0.3 V IO = 100 uA, PONCNT = 3.0 V PG3 Leak current ILEAK3 0 5 VPG = 0 V, PONCNT = 0 V A PG4 Output voltage VSAT4 - 0.1 0.3 V IO = 100 A, VINV3 = 1.1 V Leak current ILEAK4 - 0 5 A VPG = 5.0 V, STB23 = 0 V - 0.1 0.3 V IO = 100 A, INV3 = 0 V - 0.1 0 0.3 5 V A IO = 100 A, STB23 = 3.0 V Vsout = 5.0 V, STB23 = 0 V 2.0 -0.3 250 2.0 -0.3 250 400 400 11 0.3 700 11 0.3 700 V V k V V k - - 5 A STB1 to STB5 = 0 V - 11 26 mA VBAT = 3 V, VCC = 0 V - 130 400 A VFB = 0 V, VBAT = 3 V, VCC = 5 V - 5 10 mA VFB = 0 V, VBAT = 3 V VCC = 5 V DELAY Output voltage VSATD [ Switch for feedback resistor ] Output voltage VSAT5 SWOUT Leak current ILEAK5 [STB1 to STB5] ON VSTBH1 STB pin control voltage 1 OFF VSTBL1 STB pin pull-down resistance 1 RSTB1 ON VSTBH2 STB pin control voltage 2 OFF VSTBL2 STB pin pull-down resistance 2 RSTB2 [Circuit current] Standby current ISTB Circuit current at startup IST (VBAT1, VBAT2 pin sink current) Circuit current during operation 1 ICC1 (VBAT1, VBAT2 pin sink current) Circuit current during operation 2 (VCC, PVCC1, PVCC2 pin sink ICC2 current) This IC is not designed to be radiation-resistant. 5/16 STB23 STB23 STB1,4,5 STB1,4,5 zBlock Diagram and Application Circuit (1) BD9730KV Connect a capacitor to prevent oscillation to the VREGA pin. (See page 9.) For more information about setting the SCP pin, see page 10. VREGA VCC Set the maximum duty and soft start with the DTC pin. (See pages 10 and 11.) U.V.L.O 34.VREF VREGA VOLTAGE REFERENCE 10F 1M VREF 3.PVCC1 10uF 0.01uF 41.INV1 42.NON1 630k ERRAMP1 SCPcomp1 630k INV3 630k 0.01uF INV4 VREGA 5.RBIAS2 44.PGND1 8.PVCC2 24.FB3 ERRAMP3 25.SCP3 19.DTC4 Pch DRIVER INV2 RTQ025P02 47uH VCC 3. 4V RB161L-40 47uF 20k SCP3 4k COMP.3 10uF ERRAMP4 Pch DRIVER PWM 20.SCP4 SCPcomp4 9.OUT4 INV3 10k RTQ025P02 47uH 3. 7V RB161L-40 33uF 10.RBIAS4 COMP.4 SCP2 10k 7.OUT3 21.FB4 22.INV4 SCP4 8.2k 6.8k VCC 6.RBIAS3 SCPcomp3 2. 5V 10uF PWM SCP3 1M 23k SCP4 VCC 4k INV4 10k VREF SCP5 10uF 13.RBIAS5 VCC 0.047uF 17.INV5 18.NON5 ERRAMP5 Nch DRIVER 15.SCP5 12.OUT5 SCPcomp5 TRIANGLE FORM OSC 7. 0V RB551V-30 57k 33uF SCP5 3k INV5 10k COMP.5 11.PGND2 OSC BUFFER 24k 47uH RTQ020N03 PWM 28.CT 0.1uF 630k INV5 14.DTC5 16.FB5 220pF ON/OFF LOGIC 46.STB4 45.STB5 1M 48.STB1 47.STB23 200k 27.RT 0.1uF COMP.2 26.DTC3 0.047uF INV1 10k RTQ025P02 47uH RB161L-40 33uF VCC 1M 23.INV3 200k Pch DRIVER SCP1 2k PWM SCPcomp2 200k 0.1uF VREGA ERRAMP2 39k 33uF RB161L-40 10uF 4.OUT2 37.SCP2 SCP2 1.RBIAS1 36.FB2 35.INV2 VREGA VCC COMP.1 5. 1V 47uH Pch DRIVER PWM 38.DTC2 0.047uF INV2 RTQ025P02 2.OUT1 39.SCP1 SCP1 VCC 40.FB1 1M 0.01uF TIMER LATCH S Q R 43.DTC1 630k INV1 200k To-Divers To Control Block VCC 200k VREGA 0.1uF REG A VREF 0.01uF 29.SCP 30.GND 32.VCC 4.7uF 33.VREGA 4.7F Connect a capacitor to prevent oscillation to the VREF pin. (See page 10.) Set each channel's output voltage and SCP detection voltage. (See pages 9 and 10.) Set the operating frequency with the RT and CT pins. (See page 10.) This pin is used as the on/off control pin. (See page 9.) Fig. 1 BD9730KV Application Circuit 6/16 zBlock Diagram and Application Circuit (2) BD9731KV Connect a capacitor to prevent oscillation to the VREGA pin. (See page 9.) For more information about setting the SCP pin, see page 10. VREGA U.V.L.O 34.VREF VREGA VOLTAGE REFERENCE 10F 630k INV1 VREF 3.PVCC1 10uF 630k INV3 26.DTC3 0.047uF 1M 630k 0.01uF INV4 VREGA ERRAMP3 Pch DRIVER INV2 RTQ025P02 47uH VCC 3. 4V RB161L-40 47uF 13k SCP3 6k COMP.3 10uF ERRAMP4 9.OUT4 PWM 20.SCP4 SCPcomp4 3. 7V RB161L-40 33uF 10.RBIAS4 COMP.4 INV3 15k RTQ025P02 47uH Pch DRIVER SCP2 15k 7.OUT3 21.FB4 22.INV4 SCP4 VCC 6.RBIAS3 SCPcomp3 100 10k 10uF 24.FB3 16k SCP4 VCC 6k INV4 15k VREF SCP5 47uH 13.RBIAS5 0.047uF 17.INV5 18.NON5 ERRAMP5 Nch DRIVER 15.SCP5 12.OUT5 PWM SCPcomp5 TRIANGLE FORM OSC 220pF 51k RTQ020N03 33uF SCP5 4k INV5 15k COMP.5 11.PGND2 OSC BUFFER 24k 7. 0V RB551V-30 VCC 28.CT 0.1uF 10uF ON/OFF LOGIC Set each channel's output voltage and SCP detection voltage. (See pages 9 and 10.) 46.STB4 45.STB5 1M 630k INV5 14.DTC5 16.FB5 48.STB1 47.STB23 200k 27.RT 0.1uF 44.PGND1 8.PVCC2 25.SCP3 19.DTC4 2. 5V RB161L-40 33uF VCC PWM SCP3 INV1 15k RTQ025P02 47uH PWM COMP.2 SCP1 3k 5.RBIAS2 1M 23.INV3 200k Pch DRIVER SCPcomp2 200k 0.1uF VREGA ERRAMP2 33k 33uF RB161L-40 10uF 4.OUT2 37.SCP2 SCP2 1.RBIAS1 COMP.1 36.FB2 35.INV2 VREGA VCC PWM SCPcomp1 5. 1V 47uH Pch DRIVER 39.SCP1 38.DTC2 0.047uF RTQ025P02 2.OUT1 ERRAMP1 1M INV2 VCC 40.FB1 0.01uF 41.INV1 42.NON1 SCP1 630k TIMER LATCH S Q R 43.DTC1 1M 0.01uF To-Divers To Control Block VCC 200k 200k 4.7F REG A VREF VREGA 31.VREGD REG D Set the maximum duty and soft start with the DTC pin. (See pages 10 and 11.) 0.01uF Connect a capacitor to prevent oscillation to the VREGD pin. (See page 9.) 0.1uF 30.GND 32.VCC 4.7uF 33.VREGA 4.7F VCC 29.SCP Connect a capacitor to prevent oscillation to the VREF pin. (See page 9.) Set the operating frequency with the RT and CT pins. (See page 10.) This pin is used as the on/off control pin. (See page 9.) Fig. 2 BD9731KV Application Circuit 7/16 zBlock Diagram and Application Circuit (3) BD9733KN Connect a capacitor to prevent oscillation to the VREF pin. (See page 9.) For more information about setting the SCP pin, see page 10. Connect a capacitor to prevent oscillation to the VREGA pin. (See page 9.) Set the maximum duty and soft start with the DTC pin. (See pages 10 and 11.) Connect a capacitor for setting the CH2 soft start time. (See page 11.) Select to use CH2 as step-up or stepdown. (See page 9.) Set the POWERGOOD circuit delay time with a resistor and capacitor. (See page 11.) Set each channel's output voltage. (See page 9). Set the operating frequency with the RT and CT pins. (See page 10.) This pin is used as the on/off control pin. (See page 9.) Fig. 3 BD9733KN Application Circuit 8/16 zBD9730KV/BD9731KV Pin No. Pin No. 1, 5, 6, 10, 13 14, 19, 26, 38, 43 15, 20, 25, 37, 39 16, 21, 24, 36, 40 17, 22, 23, 35, 41 18, 42 27 Pin name RBIAS 1, 2, 3, 4, 5 DTC 5, 4, 3, 2, 1 SCP 5, 4, 3, 2, 1 FB 5, 4, 3, 2, 1 INV 5, 4, 3, 2, 1 NON 5, 1 RT Pin No. 28 29 30 31 33 32 34 Pin name CT SCP GND VREGD VREGA VCC VREF Pin No. 44 45, 46, 47, 48 2, 4, 7, 9, 12 3 8 11 Pin name PGND 1 STB 5, 4, 2-3, 1 OUT 1, 2, 3, 4, 5 PVCC 1 PVCC 2 PGND 2 Pin name VBAT1 VBAT2 VCC PVCC 1 PVCC 2 PGND GND VREGA VREF OUT 1, 3, 4, 5 Pin No. 2 5 4 24, 44, 14, 20, 38 22, 41, 16, 17, 40 23, 42, 15, 18, 39 19 43 25 26 Pin name OUT2B OUT2F RBIAS 2 DTC 1, 2, 3, 4, 5 FB 1, 2, 3, 4, 5 INV 1, 2, 3, 4, 5 NON4 SS2 RT CT Pin No. 27 37 47, 46, 45 13 3 32 33, 34, 35, 36 31 Pin name SCP PONCNT PG 1, 2, 3 PG4 SWOUT UDSEL2 STB 1, 23, 4, 5 DELAY zBD9733KN Pin No. Pin No. 48 1 28 12 8 6 21 29 30 10, 7, 11, 9 zExplanation of block diagram and how to set peripheral IC components 1. Voltage reference (VREF) VREF is the reference voltage source of 1.0 V . Connect a tantalum capacitor to prevent oscillation. Set the capacitance from 1.0 F to 10 F. 2. REGA, REGD REGA and REGD are regulators with output voltages of 2.5 V. REGA is used as the power supply for the IC's internal blocks. Connect a tantalum capacitor to prevent oscillation. Set the capacitance from 4.7 F to 10 F. 3. UDSEL (BD9733KN) Put beyond 2V at UDSEL pin, step down mode is enable, and put 0V or open, step up mode is enable. When using the startup circuit, set the pin to step-up mode. 4. On/off logic The voltage applied to the STB pins can be controlled whether each channel is on or off. CH1, CH4, and CH5 can be controlled independently, while CH2 and CH3 can be controlled simultaneously. Applying a voltage of over 2V turns on the corresponding channel(s), while leaving the pin open or applying 0 V turns off the corresponding channel(s). Turning off all channels causes the IC to be standby state. Each pin is connected to GND by 400 k pull-down resistor. 5. POWER ON SW (BD9733KN) The POWER ON SW pin include 3 output. This circuit can be used to as a switch that controls the sequence of 3 output voltages used for a CCD module or other components (for example, +15.2 V, +5.1 V, -7.7 V). The PG1 pin is an NPN open collector (emitter follower) output, the PG2 pin is an NMOS open drain and the PG3 pin is a PMOS open drain. On/off control is possible with the PONCNT pin. Applying a voltage of over 2V turns on, while leaving the pin open or applying 0 V turns off. VOUT 6. Setting the feedback resistance of error amp Feedback resistance order Error amp differential input is formed by a PNP transistor, with the base current of this input flowing into the divider resistor. In the worst case, this current may reach 0.2 A. For this reason, when the resistance of the lower resistor is large, the base current may cause an error in the output voltage. For example, resistance values of 40 k, 20 k, and 10 k result in errors of 1%, 0.5%, and 0.25%, respectively. Refer to the following equation when setting the resistance value: Output voltage = (1 + R1 / R2) x (VREF) 9/16 R1 ERROR AMP INV R2 - VREF BD9733KN GND Fig. 4 Feedback Resistance Setting (BD9733KN) 7. Setting the short protection detection time The detection time can be set with the capacitance connected to the SCP pin. When the detection time is reached, the latch circuit operates, turning off output for all channels. To reset the latch circuit, turn all STB pins off and then back on. Detection time (sec) = CSCP x VTSC / ISCP (CSCP: Capacitance; VTSC: SCP pin detection voltage; ISCP: SCP pin source current) *Set the capacitance connected to the SCP pin from 0.001 F to 10 F. 8. Setting the short protection detection voltage (1) BD9730KV, BD9731KV The detection voltage can be set by applying the resistor-divided switching regulator output voltage to the SCP comparator input pin. The registor can also be shared with a feedback resistor. Detection voltage [V] = (1 + RSCP1 / RSCP2) x VSC1 to VSC5 (RSCP1, RSCP2: Voltage divider resistance values; VSC: CH1 to CH5 threshold) OUT BD9731KV DRIVER Switching regulator output Detection voltage RSCP1 VSC 1 to 5 SCP SCPCOMP RSCP2 VREF Fig. 5 Setting the Short Protection Detection Voltage (2) BD9733KN The error amp's FB pin voltage is monitored, and the timer circuit starts whenever one of the channels rises to 2.2 V or higher. 9. Setting the oscillating frequency The oscillating frequency can be set with the resistance value connected to the RT pin and the capacitance value connected to the CT pin. Oscillating frequency = VRT / (CT x RT) (Unit: Hz) (VRT: RT pin voltage; CT: OSC timing capacitance; RT: OSC timing resistance) *Set the resistance connected to the RT pin from 5 k to 30 k (BD9730KV/BD9731KV), or from 10 k to 30 k (BD9733KN). *Set the capacitance connected to the CT pin from 100 pF to 10,000 pF. 10. Setting MAX DUTY (1) BD9730KV, BD9731KV The MAX ON DUTY can be set by applying the resistor-divided VREGA pin voltage to the DTC pin. Set voltage = RDTC2 / (RDTC1 + RDTC2) x VREGA (Unit: V) (RDTC1, RDTC2: Voltage divider resistance values; VREGA: Output voltage) (2) BD9733KN The DTC voltage is determined by the internal R1 and R2 resistance values. The DTC voltage can be changed by connecting resistance values that are from 1 to 2 digits smaller than the internal R1 (125 k) and R2 (375 k) resistors to the RA and RB pins. *The resistors connected to the RA and RB pins should be at least 5 k. Avoid shorting the VREGA and DTC pins. *When VCC falls to 2.8 V or below, a protection circuit will operate to limit MAX DUTY in order to prevent the IC from malfunctioning when VREGA (the internal circuit power supply) drops. VREGA BD9730KV / BD9731KV VREGA REGA RA RDTC 1 Setting voltage RDTC 2 DTC 1 to 5 DTC OSC FB RB VREGA R1 Approx. 125 k R2 Approx. 375 k PWMCOMP BD9733KN Fig. 6 Setting the DTC Voltage (BD9730KV/BD9731KV) 10/16 Fig. 7 Circuit for Setting the DTC Externally (BD9733KN) 11. Soft start operation triggered by the DTC pin Soft start operation can be set by connecting a capacitor to the DTC pin. Set the STBY pin to high, the capacitor connected to the DTC pin will be charged through the internal pull-up resistor. Startup will begin when this voltage reaches the minimum voltage of the CT pin's triangular waveform. When the desired voltage is reached, the FB pin's voltage will drop and normal feedback operation will begin. *Set the capacitance connected to the DTC pin to 10 F or less. 12. Soft start operation of low-voltage startup circuit (BD9733KN) When the IC is operating on a supply voltage of 1.5 V, the supply voltage is stepped up at both the startup OSC (the startup oscillator) and the BIP-DRIVER that drives the external NPN transistor during startup, and the stepped-up voltage is used as VCC to operate the IC. When VCC reaches approximately 2.6 V or higher, both circuits stop operating, and operation switches to the block controlled by the main PWM. STBY23 (Startup block repeat oscillation prohibited) (Startup block Main) Approx. 0.2 V SS2 Approx. 1.0 V Approx. 0.7 V VCC OSC VCC VREGA OUT2B VREGA FB VREF = 1.0 V Startup OSC (Approx. 100 kHz) OUT2F Fig. 8 Timing Chart The startup channel's soft start can be controlled with the capacitance of the capacitor connected to the SS2 pin. Times can be determined with the following equation: Startup time (sec) = (VSS / ISS) x CSS (VSS: SS pin voltage [= 0.7 V]; ISS: soft start charge current [= 2.0 A]; CSS: Capacitance) Example: When CSS = 0.01 F Startup time = (0.7 / (2.0 x 10-6)) x (0.01 x 10-6) = 3.5 ms *Set the capacitance connected to the SS pin from 0.001 F to 2.2 F. VCC output voltage waveform SS pin voltage waveform Fig. 9 Startup Waveform (Reference Data) 13. POWERGOOD (BD9733KN) This switching circuit is synchronized to CH3 output and includes a delay function. When the INV3 pin reaches a voltage of approximately 0.8 V, the capacitor connected to the DELAY pin begins to charge. Once the pin reaches approximately 2.0 V, the PG4 pin turns on. *Set the capacitance and resistance connected to the DELAY pin from 100 pF to 1 F and from 100 k to 400 k, respectively. *The resistor should be connected to VREGA rather than VCC. Approx. 0.8 V INV3 Delay time Approx. 2.0 V DELAY PG4 OFF ON Fig. 10 POWER GOOD Timing Chart 11/16 CT=100p CT=220p 100k 10k 1k 100k 10k 1.05 1M RT=24k RT=12k 100k 10k 100 1.03 1.01 0.99 0.97 -20 1.55 VREGD [V] VREGA[V] 2 2 1.5 1 0.5 60 2 4 Fig. 14 Reference Voltage VS Temperature (BD9731KV) 90 0 -40 -90 -60 -80 -100 100 OSCILATING FREQUENCY [kHz] Gvo 0 -20 PHASE : [deg] OPEN LOOP GAIN: Gvo[dB] 180 20 10k 100k 1M 330pF 100 10M 10 100 MAX DUTY [%] 90 80 70 60 30 VCC=5V RT=11k CT=180pF 20 10 0 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 VDTC [V] Fig. 20 MAX DUTY VS DTC Voltage (BD9733KN) Fig. 18 Oscillating frequency VS RT Pin Resistance (BD9733KN) 8 10 12 1000 11k 20k 30k 100 100 1000 Fig. 19 Oscillating frequency VS CT Pin Capacitance (BD9733KN) 1 1.05 1.04 1.03 100m 1.02 1.01 1 0.99 0.98 0.97 0.96 0.95 6 CT pin CAPACITANCE [pF] DELAY TIME[s] 100 4 Fig. 16 REGD Output Voltage VS Supply Voltage (BD9730KV, BD9731KV) RT pin RESISTANCE[k] REFERENCE VOLTAGE : VREF[V] Fig. 17 Error Amp Gain, Phase VS Frequency (BD9730KV, BD9731KV) 40 2 0 VCC [V] 180pF FREQUENCY [Hz] 50 12 100pF -180 1k 10 1000 80 60 8 Fig. 15 REGA Output Voltage VS Supply Voltage (BD9730KV, BD9731KV) 270 40 6 Vcc[V] AMBIENT TEMPERATURE: Ta [C] 100 1 0 0 80 OSCILATING FREQUENCY: fosc [kHz] 40 1.5 0.5 0 20 80 2.5 1.49 0 60 3 2.5 1.51 40 Fig. 13 Reference Voltage VS Temperature (BD9730KV) 3 1.53 20 0 AMBIENT TEMPERATURE: Ta [C] Fig. 12 Oscillating Frequency VS CT Pin Capacitance (BD9730KV, BD9731KV) Fig. 11 Oscillating Frequency VS RT Pin Resistance (BD9730KV, BD9731KV) 1.47 -20 0.95 10000 1000 CT pin CAPACITANCE [pF] RT pin RESISTANCE[] REFERENCE VOLTAGE : VREF[V] REFERENCE VOLTAGE : VREF[V] 1M OSCILATING FREQUENCY: fosc [Hz] OSCILATING FREQUENCY: fosc [Hz] zReference Data 10m 1m 100 -20 0 20 40 60 80 Ambient temperature: Ta [C] Fig. 21 Reference Voltage VS Temperature (BD9733KN) 12/16 10 100p 1000p 10000p 0.01 0.1 DELAY pin CAPACITANCE [pF] Fig. 22 Delay Time VS DELAY Pin Capacitance (BD9733KN) 1 zI/O Equivalent Circuit Diagrams PVCC1 to PVCC2 (power supply input) OUT1 to OUT4 (power transistor connection) RBIAS1 to RBIAS4 (power ground, base current setting resistor connection) RBIAS5 (power supply input, base current setting resistor connection) OUT5 (power transistor connection) PGND5 (power ground) VCC DTC1 to DTC5 (dead time control) VCC VCC DTC VCC PVCC1 to PVCC 2 RBIAS5 VCC INV2 to INV4 (error amp inverted input) SCP1 to SCP5 (SCP comparator input) VCC OUT5 OUT1 to OUT4 INV2 to INV4 SCP1 to SCP5 VREGA VCC VCC VCC RBIAS1 to RBIAS FB1 to FB5 (error amp output) PGND2 RT (triangular waveform timing resistor connection) CT (triangular waveform timing capacitor connection) VREGA VREGA VCC VCC FB1 to FB 5 VCC RT 1.0 V CT SCP (capacitor charge for timer latch) VREGA (REGA output) VREGA VCC VCC VCC VREF (reference voltage output) VCC VCC VCC VCC VREGA VREF VCC SCP Fig. 23 I/O Equivalent Circuit Diagrams (1) 13/16 VBAT2 (battery voltage input) OUT2B (2CH power transistor connection) PG1 (power-on switch output) SWOUT (switch output for feedback resistor) PG2 (power-on switch output) PG4 (POWERGOOD switch output) PG1 VBAT2 SWOUT PG2,PG4 VCC OUT2 RBIAS2 (power supply input, base current setting resistor connection) OUT2F (power transistor connection) PGND (power ground) PVCC2 (power supply input) OUT3 (power transistor connection) PGND (power ground) PG3 (power-on switch output) VREGA VCC VCC VCC PG3 PVCC2 RBIAS2 SS2 (CH2 soft start capacitor connection pin) VCC OUT3 VCC VREGA VBAT OUT2F VCC VCC VCC PGND PGND SS2 DELAY (delay time setting pin) UDSEL2 (step-up/step-down select input) STBY1 to STBY5 (CH1 to CH5 on/off control) VCC VCC VCC STBY1 to STBY5 UDSEL2 DELAY Fig. 24 I/O Equivalent Circuit Diagrams (2) 14/16 VCC zPrecautions 1) Absolute maximum ratings Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special mode where the absolute maximum ratings may be exceeded is anticipated. 2) Connecting the power supply connector backward Connecting the power supply connector backwards may result in damage to the IC. Insert external diodes between the power supply and the IC's power supply pins as well as the motor coil to protect against damage from backward connections. 3) Power supply lines Regenerated current may flow as a result of the motor's back electromotive force. Insert capacitors between the power supply and ground pins to serve as a route for regenerated current. 4) GND potential Ensure a minimum GND pin potential in all operating conditions. 5) Thermal design Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. 6) Inter-pin shorts and mounting errors Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in damage to the IC. Shorts between output pins or between output pins and the power supply and GND pin caused by the presence of a foreign object may result in damage to the IC. 7) Operation in a strong electromagnetic field Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction. 8) ASO When using the IC, set the output transistor so that it does not exceed absolute maximum ratings or ASO. 9) Thermal shutdown circuit (TSD circuit) The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee its operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit is assumed. 10) Capacitors connected between output and ground pins When a large capacitor is connected between the output and ground pins and for some reason the VCC falls to 0 V or becomes shorted with the ground pin, the current stored in the capacitor may flow to the output pin, resulting in damage to the IC. Set capacitors connected between the output and ground pins to values that fall within the recommended range. 11) Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. 12) IC pin input This monolithic IC contains P+ isolation and PCB layers between adjacent elements in order to keep them isolated. P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of parasitic elements. { For example, when a resistor and transistor are connected to pins as shown in Fig. 25, the P/N junction functions as a parasitic diode when GND > (Pin A) for the resistor or GND > (Pin B) for the transistor (NPN). { Similarly, when GND > (Pin B) for the transistor (NPN), the parasitic diode described above combines with the N layer of other elements to operate as a parasitic NPN transistor. The formation of parasitic NPN transistors according to the relationships of different IC pins is an inevitable result of the IC's architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will trigger the operation of parasitic elements, such as by the application of voltages lower than the GND (PCB) voltage to I/O pins. 13) Ground wiring patterns Power supply and ground wiring should reflect consideration of the need to lower common impedance and minimize ripple as much as possible (by making wiring as short and thick as possible or rejecting ripple by incorporating inductance and capacitance). 14) STB pin voltage Set the STB pin voltage to 0.3 V or lower when setting channels to a standby state, or to 2.0 V or higher when setting channels to an operational state. Do not fix the STB pin voltage to values higher than 0.3 V and lower than 2.0 V or lengthen transition times. Doing so may cause the IC to malfunction or result in damage. 15) Use a common supply voltage for both the driver block and the main block. The IC is not compatible with applications requiring the driver block to be used while applying user-selected voltages. 16) Setting the MAX DUTY MAX DUTY limitations may not operate when using the IC at high frequencies. When using the IC in such applications, allow for sufficient margins when setting external components. (Pin B) Resistor Transistor (NPN) B (Pin B) E (Pin A) C C B E GND N GND Other Adjacent P P P P P P Elements Parasitic elements N N N N N N (Pin A) PCB Parasitic elements PCB GND Fig. 25 Example of Simple Bipolar IC Architecture Parasitic elements Parasitic elements 15/16 GND zSelecting a Model Name When Ordering B D 9 7 3 3 K - Package type KV = VQFP KN = UQFN Part number 9730, 9731, 9733 ROHM model name N E 2 Taping type E2 = Reel-wound embossed taping VQFP48 <Dimension> <Packing information> 9.00.2 7.00.1 13 12 0.10.05 1.4250.05 1.625Max. 0.75 4 +6 -4 0.08 S 0.50.1 1000pcs Direction of feed Direction of product is fixed in a tray. +0.05 0.145-0.03 1PIN MARK +0.05 0.22-0.04 Tray(with dry pack) Quantity 1pin 48 1.00.2 24 0.40.15 25 0.75 9.00.2 7.00.1 36 37 Container 0.08 M Unit:mm) When you order , please order in times the amount of package quantity. UQFN48 <Tape and Reel information> <Dimension> 7.2 0.1 7.0 0.1 0.6 +0.1 -0.3 (1.4) 36 Tape Embossed carrier tape(with dry pack) Quantity 2500pcs 25 48 13 E2 Direction of feed (The direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand) 12 0.4 0.05 Reel 1pin +0.03 1234 (Unit:mm) 1234 0.05 1234 1234 1234 1234 0.22 0.05 0.20 0.05 0.02 -0.02 0.95MAX 1 (0 .2 0) 5) .4 (0 3- 5) 7.2 0.1 7.0 0.1 24 .5 (0 37 Direction of feed When you order , please order in times the amount of package quantity. The contents described herein are correct as of October, 2005 The contents described herein are subject to change without notice. For updates of the latest information, please contact and confirm with ROHM CO.,LTD. Any part of this application note must not be duplicated or copied without our permission. Application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. Please pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set. Any data, including, but not limited to application circuit diagrams and information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. ROHM CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such infringement, or arising from or connected with or related to the use of such devices. Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by ROHM CO., LTD. is granted to any such buyer. The products described herein utilize silicon as the main material. The products described herein are not designed to be X ray proof. Published by Application Engineering Group Catalog NO.05T342Be '05.10 ROHM C 1000 TSU Appendix Notes No technical content pages of this document may be reproduced in any form or transmitted by any means without prior permission of ROHM CO.,LTD. The contents described herein are subject to change without notice. The specifications for the product described in this document are for reference only. Upon actual use, therefore, please request that specifications to be separately delivered. Application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. Please pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set. Any data, including, but not limited to application circuit diagrams information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. ROHM CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such infringement, or arising from or connected with or related to the use of such devices. Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, no express or implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by ROHM CO., LTD. is granted to any such buyer. Products listed in this document are no antiradiation design. The products listed in this document are designed to be used with ordinary electronic equipment or devices (such as audio visual equipment, office-automation equipment, communications devices, electrical appliances and electronic toys). Should you intend to use these products with equipment or devices which require an extremely high level of reliability and the malfunction of which would directly endanger human life (such as medical instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers and other safety devices), please be sure to consult with our sales representative in advance. It is our top priority to supply products with the utmost quality and reliability. However, there is always a chance of failure due to unexpected factors. Therefore, please take into account the derating characteristics and allow for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in order to prevent possible accidents that may result in bodily harm or fire caused by component failure. ROHM cannot be held responsible for any damages arising from the use of the products under conditions out of the range of the specifications or due to non-compliance with the NOTES specified in this catalog. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact your nearest sales office. ROHM Customer Support System www.rohm.com Copyright (c) 2008 ROHM CO.,LTD. THE AMERICAS / EUROPE / ASIA / JAPAN Contact us : webmaster@ rohm.co. jp 21 Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan TEL : +81-75-311-2121 FAX : +81-75-315-0172 Appendix1-Rev2.0