BD9733KN-E2 - ROHM Co., Ltd. - Datasheet.Directory

TECHNICAL NOTE

For Digital Still Cameras

Controller Type

System Switching Regulator ICs

BD9730KV, BD9731KV, BD9733KN

zDescription

These 5-channel system switching regulators use external FETs and can be used to create power supplies for use in digital

still cameras. Each channel's output voltage can be set externally according to the application.

zFeatures

1) Wide input voltage range: 1.5 V to 11 V (BD9733KN)

2.5 V to 11 V (BD9730KV)

2.8 V to 11 V (BD9731KV)

2) High-precision reference voltage: ±1% (BD9731KV, BD9733KN)

3) Built-in circuit to shut off output during an overload (timer-latch type)

4) Dead-time control for all channels

5) Oscillating frequency can be set externally.

6) Built-in thermal shutdown circuit

7) Standby mode current: 0 µA

8) Channels 1, 4, and 5 support independent on/off control

9) Step-up/step-down switchable (BD9733KN)

10) Built-in sequence control switch circuit (BD9733KN)

zApplications

Digital still cameras, portable DVD players, digital video cameras

zProduct line-up

Parameter BD9730KV BD9731KV BD9733KN

Input voltage 2.5 V to 11 V 2.8 V to 11 V 1.5 V to 11 V

Reference voltage precision 1 V ± 1.2% 1.5 V ± 1% 1 V ± 1%

Operating frequency range 100 kHz to 700 kHz 100 kHz to 700 kHz 100 kHz to 1 MHz

Step-up 1CH 1CH 3CH

Step-down 4CH 4CH 1CH

Step-up/step-down switchable − − 1CH

Operating temperature range −20°C to +85°C −20°C to +85°C −25°C to +85°C

Package VQFP48 VQFP48 QFN48U

Apr. 2005

2/16

zAbsolute maximum ratings (Ta = 25°C)

Parameter Symbol Range Unit

BD9730KV, BD9731KV VCC −0.3 to +12 V

VBAT,VCC,PVCC1,PVCC2 −0.3 to +12 V

VIN1 −0.3 to +17 V

VIN2 −0.3 to +12 V

Power supply voltage

BD9733KN

VIN3 −9.0 to VREGA V

VQFP48 900 *1

Power dissipation

QFN48U Pd 760 *2 mW

Operating temperature range Topr -20 to +85 °C

Storage temperature range Tstg -55 to +125 °C

*1: When mounted on a PCB (70 mm × 70 mm × 1.6 mm [thickness], glass epoxy). Reduced 9.0 mW/°C when used at Ta = 25°C.

*2: When mounted on a PCB (70 mm × 70 mm × 1.6 mm [thickness], glass epoxy). Reduced 7.6 mW/°C when used at Ta = 25°C.

zRecommended Operating Conditions

Parameter Symbol BD9730KV BD9731KV BD9733KN

VCC 2.5 V to 11 V *3 2.8 V to 11 V 2.5 V to 11 V *3

Supply voltage

VBAT − − 1.5 V to 11 V

Oscillating frequency fOSC 100 kHz to 700 kHz 100 kHz to 700 kHz 100 kHz to 1 MHz

Driver output current IOUT Up to 30 mA Up to 30 mA Up to 30 mA

*3: REG output decreases when VCC is lower than 2.6 V to 2.5 V.

Parameter Symbol Range Unit

NON1, NON5 Pin input

voltage

BD9730KV VNON1, VNON5 0.3 to 1.5 V

Driver peak current IPEAK Up to 200 mA

PG1pin sink current IPG1 Up to 1 mA

PG2, PG4 pin sink current IPG2, IPG4 Up to 800 mA

PG3 pin source current IPG3 Up to 1 mA

SWOUT pin sink current

BD9733KN

ISWOUT Up to 300 mA

3/16

zElectrical Characteristics

BD9730KV, BD9731KV (Unless otherwise specified, Ta = 25°C, Vcc = 6 V, fosc = 0.20 MHz, STB1 to STB5 = 3 V)

Range

Parameter Symbol

Min. Typ. Max. Unit Conditions

Standby current IST − − 9.5 µA STB1 to STB5 = 0 V

− 4.8 9.5 (BD9730KV)

Circuit current ICC − 4.5 9.5 mA (BD9731KV)

[Reference voltage]

0.988 1.0 1.012 IREF = −1 mA (BD9730KV)

Output voltage VREF 1.485 1.5 1.515 V IREF = −1 mA (BD9731KV)

Line regulation DVLI − 4.0 12.5 mV VCC = 3.0 V to 9.5 V

Load regulation DVLO − 1.0 7.5 mV IREF = −0.1 mA to −1 mA

Output current when shorted IOS 4 16 − mA VREF = 0 V

[Internal regulator]

Output voltage REGA, REGD VREGA

VREGD 2.4 2.5 2.6 V IREG = −1 mA

[Shutoff at overload]

0.90 1.0 1.10 VSCP1 to VSCP5 = 1.5 V to 0.5 V

(BD9730KV)

CH1 to CH5 threshold VSC1 to

VSC5 1.425 1.5 1.575

V VSCP1 to VSCP5 = 2 V to 1 V

(BD9731KV)

[Protection circuit]

SCP pin detection voltage VTSC 0.90 1.0 1.10 V VSCP = 0 V to 1.5 V

Standby voltage VSSC − 22 170 mV

SCP pin source current ISCP −6 −4 −2 µA VSCP = 0.1 V

[Triangular waveform oscillator]

Oscillating frequency fOSC1 0.179 0.200 0.221 MHz

RT = 24 kΩ, CT = 220 pF

Frequency stability Df − 1 5 %

VCC = 2.8 V → 9.5 V

RT pin voltage VRT 0.78 1 1.22 V

CT pin sink current ICSO 32.2 46.0 59.8 µA VCT = 1.7 V, RT = 24 kΩ

CT pin source current ICSI −54.6 −42.0 −29.4 µA VCT = 1.7 V, RT = 24 kΩ

[Error amp]

Low level output voltage VOL − − 0.3 V INV = 2 V

High level output voltage VOH VREGA

−0.3V − − V INV = 0 V

[PWM comparator]

− − 1.0 VDT = 1 V (BD9730KV)

DTC input current IDT − −1 −5 µA VDT = 1V(BD9731KV)

VT0 − 1.49 − V 0% duty

Input threshold voltage VT100 − 1.95 − V 100% duty

[Output circuit]

VCC

−0.4

VCC

−0.2 − Io = 10 mA (BD9730KV)

High level output voltage on

driving VSATH VCC

−0.3

VCC

−0.1 −

IO = 10 mA (BD9731KV)

− 0.2 0.4 IO = −10mA (BD9730KV)

Low level output voltage on

driving VSATL − 0.1 0.3 V IO = −10mA (BD9731KV)

Max. output source current IOSOURC

E 30 − − mA

Max. output sink current IOSINK − − −30 mA

[STB1 to STB5]

STB pin pull-down resistor RSTB 250 400 700 kΩ

ON VSTBH 2.0 − − V

STB pin

control voltage OFF VSTBL −0.3 − 0.3 V

This IC is not designed to be radiation-resistant.

4/16

zBD9733KN (Unless otherwise specified, Ta = 25°C. VBAT = 3 V, VCC = 5 V, RT = 11 kΩ, CT = 180 pF, STB1 to STB5 = 3 V)

Range

Parameter Symbol

Min. Typ. Max. Unit Conditions

[Reference voltage ]

Output voltage VREF 0.99 1.0 1.01 V IREF = 1 mA

Line regulation DVLI − 4.0 12.5 mV VCC = 3.0 V to 9.5 V

Load regulation DVLO − 1.0 7.5 mV IREF = 0.1 mA to 1 mA

Output current when shorted IOS 4 16 − mA VREF = 0 V

[Internal regulator]

Output voltage REGA VREGA 2.4 2.5 2.6 V IREG = 1 mA

[Under voltage lockout circuit ]

Threshold voltage 1 VST1 2.3 2.4 2.5 V VCC monitor

Hysteresis width 1 ∆ VST1 − 200 − mV

Threshold voltage 2 VST2 − 2.0 − V VREGA monitor

Hysteresis width 2 ∆ VST2 − 50 − mV

[Startup circuit block]

Oscillating frequency fSTART 50 120 220 kHz

Operation start VBAT voltage VST1 − 1.1 1.5 V VBAT pin monitor

Soft start charge current ISS 1.1 2.2 3.3

µA VSS = 0 V

[Short protection circuit ]

Timer start

threshold voltage VTC 2.1 2.2 2.3 V FB pin monitor

SCP pin source current ISCP 0.5 1.0 1.5

µA VSCP = 0.1 V

SCP pin detection voltage VTSC 0.45 0.50 0.55 V

SCP pin standby voltage VSSC − 22 170 mV

[Triangular waveform oscillator]

Oscillating frequency fOSC1 450 500 550 kHz

RT = 11 kΩ, CT = 180 pF

Frequency stability Df − 1 5 % VCC = 3.0 V to 9.5 V

RT pin voltage VRT 0.78 1.00 1.22 V

[Error amp]

Low level output voltage VOL − − 0.3 V INV = 2 V

High level output voltage VOH VREGA

−0.3 − − V INV = 0 V

Output sink current IOI 200 700 − µA FB = 1.0 V, VINV = 1.1 V

Output source current IOO 40 80 − µA FB = 1.0 V, VINV = 0.9 V

[PWM comparator]

VT0 − 1.49 − V 0% duty

Input threshold voltage VT100 − 1.95 − V 100% duty

MAX DUTY1,4,5 DMAX1 77 85 93 % VINV = 0.9 V, VSCP = 0 V

MAX DUTY 2

(step-up operation) DMAX2 77 85 93 % VINV = 0.9 V, VSCP = 0 V, UDSEL = 0 V

[Output circuit ]

High level output voltage on

driving VSATH VCC

−0.3

VCC

−0.1 − V Io = 10 mA

Low level output voltage on

driving VSATL − 0.1 0.3 V IO = −10 mA

[Step-up/step-down selector ]

Step-down VUDDO 2.0 − 11 V

UDSEL2 pin

control voltage Step-up VUDUP −0.3 − 0.3 V

UDSEL2 pin

pull-down resistance RUDSEL2 250 400 700 kΩ

This IC is not designed to be radiation-resistant.

5/16

zBD9733KN (Unless otherwise specified, Ta = 25°C, VBAT = 3 V, VCC = 5 V, RT = 11 kΩ, CT = 180 pF, STB1 to STB5 = 3 V)

Range

Parameter Symbol

Min. Typ. Max. Unit Conditions

[ POWERGOOD , Power on switch ]

ON VPGON 2.0 - 11 V

PONCNT pin

control voltage OFF VPGOFF -0.3 - 0.3 V

PONCNT pin

pull-down resistance RCTRL 250 400 700

kΩ

POWERGOOD detection voltage VTHPG4 0.72 0.8 0.88 V

Detection voltage: low → high

Hysteresis width ∆ VTLPG4 100 200 300 mV

DELAY pin detection voltage VTHDE 1.8 2.0 2.2 V

Detection voltage: low → high

Hysteresis width ∆ VTHDE 100 200 300 mV

Output voltage VSAT1 - 1.6 3.2 V IO = 500 uA, PONCNT = 3.0 V

PG1 Leak current ILEAK1 - 0 5

µA VPG = 5 V, PONCNT = 0 V

Output voltage VSAT2 - 0.1 0.3 V IO = 100 uA, PONCNT = 3.0 V

PG2 Leak current ILEAK2 - 0 5

µA VPG = 5 V, PONCNT = 0 V

Output voltage VSAT3 - 0.1 0.3 V IO = 100 uA, PONCNT = 3.0 V

PG3 Leak current ILEAK3 - 0 5

µA VPG = 0 V, PONCNT = 0 V

Output voltage VSAT4 - 0.1 0.3 V

IO = 100 µA, VINV3 = 1.1 V

PG4 Leak current ILEAK4 - 0 5

µA VPG = 5.0 V, STB23 = 0 V

DELAY Output voltage VSATD - 0.1 0.3 V

IO = 100 µA, INV3 = 0 V

[ Switch for feedback resistor ]

Output voltage VSAT5 - 0.1 0.3 V

IO = 100 µA, STB23 = 3.0 V

SWOUT Leak current ILEAK5 - 0 5

µA Vsout = 5.0 V, STB23 = 0 V

[STB1 to STB5]

ON VSTBH1 2.0 - 11 V

STB pin control

voltage 1 OFF VSTBL1 -0.3 - 0.3 V

STB23

STB pin pull-down resistance 1 RSTB1 250 400 700

kΩ STB23

ON VSTBH2 2.0 - 11 V

STB pin control

voltage 2 OFF VSTBL2 -0.3 - 0.3 V

STB1,4,5

STB pin pull-down resistance 2 RSTB2 250 400 700

kΩ STB1,4,5

[Circuit current]

Standby current ISTB - - 5

µA STB1 to STB5 = 0 V

Circuit current at startup

(VBAT1, VBAT2 pin sink current) IST - 11 26 mA VBAT = 3 V, VCC = 0 V

Circuit current during operation 1

(VBAT1, VBAT2 pin sink current) ICC1 - 130 400

µA VFB = 0 V, VBAT = 3 V, VCC = 5 V

Circuit current during operation 2

(VCC, PVCC1, PVCC2 pin sink

current)

ICC2 - 5 10 mA

VFB = 0 V, VBAT = 3 V

VCC = 5 V

This IC is not designed to be radiation-resistant.

6/16

zBlock Diagram and Application Circuit (1) BD9730KV

18.NON5

16.FB5

17.INV5

21.FB4

22.INV4

23.INV3

24.FB3

36.FB2

35.INV2

Pch DRIVER

Nch DRIVER

REG A

VOLTAGE

REFERENCE

U.V.L.O

TIMER LATCH

SQR

TRIANGLE

OSC

FORM

OSC

BUFFER

ON/OFF

LOGIC

3.PVCC1

2.OUT1

1.RBIAS1

4.OUT2

5.RBIAS2

44.PGND1

8.PVCC2

7.OUT3

6.RBIAS3

9.OUT4

10.RBIAS4

13.RBIAS5

12.OUT5

11.PGND2

15.SCP5

45.STB5

46.STB4

47.STB23

48.STB1

28.CT

27.RT

14.DTC5

20.SCP4

19.DTC4

25.SCP3

26.DTC3

38.DTC2

39.SCP1

42.NON1

41.INV1

40.FB1

43.DTC1

34.VREF

30.GND

32.VCC

33.VREGA

29.SCP

To Control To-Divers

ERRAMP1

ERRAMP2

ERRAMP3

ERRAMP4

ERRAMP5

PWM

COMP.5

PWM

COMP.4

PWM

COMP.3

PWM

COMP.2

PWM

COMP.1

37.SCP2

Block

SCPcomp1

SCPcomp2

SCPcomp3

SCPcomp4

SCPcomp5

4.7μF

10μF

VCC

VREF

VREGA

SCP1

SCP2

SCP3

SCP4

SCP5

VREGA

INV1

INV2

INV3

INV5

INV4

VCC

SCP3

INV3

VCC SCP2

INV2

VCC

SCP1

INV1

VCC

200k

0.01uF 630k

200k

0.01uF

0.01uF 0.047uF

0.047uF

200k

630k

0.1uF

200k

630k

0.1uF 0.01uF

0.047uF

200k

630k

0.1uF

24k 220pF

4.7uF

0.1uF

47uH

39k

10k

47uH

10uF

33uF

10uF

47uH

8.2k

47uF

47uH

10uF

33uF 23k

47uH

10uF

33uF

RTQ020N03

RTQ025P02

630k

RB551V-30

RB161L-40

10uF

RB161L-40

33uF

5 . 1 V

2 . 5 V

3 . 4 V

3 . 7 V

7 . 0 V

6.8k

10k

20k

10k

SCP4

INV4

10k

SCP5

INV5

57k

10k

Fig. 1 BD9730KV Application Circuit

Connect a capacitor to prevent oscillation

to the VREF pin. (See page 10.)

Set the maximum duty

and soft start with the

DTC pin. (See pages

10 and 11.)

Connect a capacitor to prevent oscillation to the

VREGA pin. (See page 9.) For more information about setting

the SCP pin, see page 10.

Set the operating frequency with the

RT and CT pins. (See page 10.)

Set each channel's output

voltage and SCP detection

voltage. (See pages 9 and

10.)

This pin is used as the on/off control pin.

(See page 9.)

7/16

zBlock Diagram and Application Circuit (2) BD9731KV

18.NON5

16.FB5

17.INV5

21.FB4

22.INV4

23.INV3

24.FB3

36.FB2

35.INV2

Pch DRIVER

Nch DRIVER

REG A

VOLTAGE

REFERENCE

U.V.L.O

TIMER LATCH

SQR

TRIANGLE

OSC

FORM

OSC

BUFFER

ON/OFF

LOGIC

3.PVCC1

2.OUT1

1.RBIAS1

4.OUT2

5.RBIAS2

44.PGND1

8.PVCC2

7.OUT3

6.RBIAS3

9.OUT4

10.RBIAS4

13.RBIAS5

12.OUT5

11.PGND2

15.SCP5

45.STB5

46.STB4

47.STB23

48.STB1

28.CT

27.RT

14.DTC5

20.SCP4

19.DTC4

25.SCP3

26.DTC3

38.DTC2

39.SCP1

42.NON1

41.INV1

40.FB1

43.DTC1

34.VREF

30.GND

32.VCC

33.VREGA

29.SCP

To Control To-Divers

ERRAMP1

ERRAMP2

ERRAMP3

ERRAMP4

ERRAMP5

PWM

COMP.5

PWM

COMP.4

PWM

COMP.3

PWM

COMP.2

PWM

COMP.1

37.SCP2

Block

SCPcomp1

SCPcomp2

SCPcomp3

SCPcomp4

SCPcomp5

4.7μF

10μF

VCC

VREF

VREGA

SCP1

SCP2

SCP3

SCP4

SCP5

VREGA

INV1

INV2

INV3

INV5

INV4

VCC

SCP3

INV3

VCC SCP2

INV2

VCC

SCP1

INV1

VCC

200k

0.01uF 630k

200k

0.01uF

0.01uF 0.047uF

0.047uF

200k

630k

0.1uF

200k

630k

0.1uF 0.01uF

0.047uF

200k

630k

0.1uF

24k 220pF

4.7uF

0.1uF

47uH

33k

15k

47uH

10uF

33uF

10uF

47uH

100

47uF

47uH

10uF

33uF 16k

47uH

10uF

33uF

RTQ020N03

RTQ025P02

630k

RB551V-30

RB161L-40

10uF

RB161L-40

33uF

5 . 1 V

2 . 5 V

3 . 4 V

3 . 7 V

7 . 0 V

10k

15k

13k

15k

SCP4

INV4

15k

SCP5

INV5

51k

15k

REG D 31.VREGD

4.7μF

Fig. 2 BD9731KV Application Circuit

Connect a capacitor to prevent oscillation

to the VREF pin. (See page 9.)

Set the maximum duty

and soft start with the

DTC pin. (See pages 10

and 11.)

Connect a capacitor to prevent oscillation to

the VREGA pin. (See page 9.)

For more information about setting

the SCP pin, see page 10.

Set the operating frequency

with the RT and CT pins.

(See page 10.) This pin is used as the on/off control pin.

(See page 9.)

Connect a capacitor to prevent oscillation to

the VREGD pin. (See page 9.)

Set each channel's output

voltage and SCP detection

voltage. (See pages 9 and 10.)

8/16

zBlock Diagram and Application Circuit (3) BD9733KN

＠＠設＠＠

Fig. 3 BD9733KN Application Circuit

Connect a capacitor to prevent oscillation

to the VREF pin. (See page 9.)

Set the maximum duty and

soft start with the DTC pin.

(See pages 10 and 11.)

Connect a capacitor to prevent oscillation to

the VREGA pin. (See page 9.)

For more information about setting

the SCP pin, see page 10.

Connect a capacitor

for setting the CH2

soft start time. (See

page 11.)

Select to use CH2

as step-up or step-

down. (See page 9.)

Set the POWERGOOD

circuit delay time with a

resistor and capacitor.

(See page 11.)

Set the operating frequency with the

RT and CT pins. (See page 10.)

Set each channel's output

voltage. (See page 9). This pin is used as the on/off control pin.

(See page 9.)

9/16

zBD9730KV/BD9731KV Pin No.

Pin No. Pin name Pin No. Pin name Pin No. Pin name

1, 5, 6, 10, 13 RBIAS 1, 2, 3, 4, 5 28 CT 44 PGND 1

14, 19, 26, 38, 43 DTC 5, 4, 3, 2, 1 29 SCP 45, 46, 47, 48 STB 5, 4, 2-3, 1

15, 20, 25, 37, 39 SCP 5, 4, 3, 2, 1 30 GND 2, 4, 7, 9, 12 OUT 1, 2, 3, 4, 5

16, 21, 24, 36, 40 FB 5, 4, 3, 2, 1 31 VREGD 3 PVCC 1

17, 22, 23, 35, 41 INV 5, 4, 3, 2, 1 33 VREGA 8 PVCC 2

18, 42 NON 5, 1 32 VCC 11 PGND 2

27 RT 34 VREF

zBD9733KN Pin No.

Pin No. Pin name Pin No. Pin name Pin No. Pin name

48 VBAT1 2 OUT2B 27 SCP

1 VBAT2 5 OUT2F 37 PONCNT

28 VCC 4 RBIAS 2 47, 46, 45 PG 1, 2, 3

12 PVCC 1 24, 44, 14, 20, 38 DTC 1, 2, 3, 4, 5 13 PG4

8 PVCC 2 22, 41, 16, 17, 40 FB 1, 2, 3, 4, 5 3 SWOUT

6 PGND 23, 42, 15, 18, 39 INV 1, 2, 3, 4, 5 32 UDSEL2

21 GND 19 NON4 33, 34, 35, 36 STB 1, 23, 4, 5

29 VREGA 43 SS2 31 DELAY

30 VREF 25 RT

10, 7, 11, 9 OUT 1, 3, 4, 5 26 CT

zExplanation of block diagram and how to set peripheral IC components

1. Voltage reference (VREF)

VREF is the reference voltage source of 1.0 V .

Connect a tantalum capacitor to prevent oscillation.

Set the capacitance from 1.0 µF to 10 µF.

2. REGA, REGD

REGA and REGD are regulators with output voltages of 2.5 V. REGA is used as the power supply for the IC's internal blocks.

Connect a tantalum capacitor to prevent oscillation.

Set the capacitance from 4.7 µF to 10 µF.

3. UDSEL (BD9733KN)

Put beyond 2V at UDSEL pin, step down mode is enable, and put 0V or open, step up mode is enable. When using the

startup circuit, set the pin to step-up mode.

4. On/off logic

The voltage applied to the STB pins can be controlled whether each channel is on or off.

CH1, CH4, and CH5 can be controlled independently, while CH2 and CH3 can be controlled simultaneously.

Applying a voltage of over 2V turns on the corresponding channel(s), while leaving the pin open or applying 0 V turns off

the corresponding channel(s).

Turning off all channels causes the IC to be standby state.

Each pin is connected to GND by 400 kΩ pull-down resistor.

5. POWER ON SW (BD9733KN)

The POWER ON SW pin include 3 output. This circuit can be used to as a switch that controls the sequence of 3 output

voltages used for a CCD module or other components (for example, +15.2 V, +5.1 V, -7.7 V). The PG1 pin is an NPN open

collector (emitter follower) output, the PG2 pin is an NMOS open drain and the PG3 pin is a PMOS open drain.

On/off control is possible with the PONCNT pin. Applying a voltage of over 2V turns on, while leaving the pin open or

applying 0 V turns off.

6. Setting the feedback resistance of error amp

Feedback resistance order

Error amp differential input is formed by a PNP transistor, with the base

current of this input flowing into the divider resistor.

In the worst case, this current may reach 0.2 µA.

For this reason, when the resistance of the lower resistor is large, the

base current may cause an error in the output voltage.

For example, resistance values of 40 kΩ, 20 kΩ, and 10 kΩ result in

errors of 1%, 0.5%, and 0.25%, respectively. Refer to the following

equation when setting the resistance value:

Output voltage = (1 + R1 / R2) × (VREF)

Fig. 4 Feedback Resistance Setting

(BD9733KN)

VOUT

INV

ERROR AMP

GND

＋

−

VREF

BD9733KN

10/16

7. Setting the short protection detection time

The detection time can be set with the capacitance connected to the SCP pin.

When the detection time is reached, the latch circuit operates, turning off output for all channels.

To reset the latch circuit, turn all STB pins off and then back on.

Detection time (sec) = CSCP × VTSC / ISCP

(CSCP: Capacitance; VTSC: SCP pin detection voltage; ISCP: SCP pin source current)

*Set the capacitance connected to the SCP pin from 0.001 µF to 10 µF.

8. Setting the short protection detection voltage

(1) BD9730KV, BD9731KV

The detection voltage can be set by applying the resistor-divided switching regulator output voltage to the SCP

comparator input pin. The registor can also be shared with a feedback resistor.

Detection voltage [V] = (1 + RSCP1 / RSCP2) × VSC1 to VSC5

(RSCP1, RSCP2: Voltage divider resistance values; VSC: CH1 to CH5 threshold)

(2) BD9733KN

The error amp's FB pin voltage is monitored, and the timer circuit starts whenever one of the channels rises to 2.2 V or

higher.

9. Setting the oscillating frequency

The oscillating frequency can be set with the resistance value connected to the RT pin and the capacitance value

connected to the CT pin.

Oscillating frequency = VRT / (CT × RT) (Unit: Hz)

(VRT: RT pin voltage; CT: OSC timing capacitance; RT: OSC timing resistance)

*Set the resistance connected to the RT pin from 5 kΩ to 30 kΩ (BD9730KV/BD9731KV), or from 10 kΩ to 30 kΩ

(BD9733KN).

*Set the capacitance connected to the CT pin from 100 pF to 10,000 pF.

10. Setting MAX DUTY

(1) BD9730KV, BD9731KV

The MAX ON DUTY can be set by applying the resistor-divided VREGA pin voltage to the DTC pin.

Set voltage = RDTC2 / (RDTC1 + RDTC2) × VREGA (Unit: V)

(RDTC1, RDTC2: Voltage divider resistance values; VREGA: Output voltage)

(2) BD9733KN

The DTC voltage is determined by the internal R1 and R2 resistance values.

The DTC voltage can be changed by connecting resistance values that are from 1 to 2 digits smaller than the internal

R1 (125 kΩ) and R2 (375 kΩ) resistors to the RA and RB pins.

*The resistors connected to the RA and RB pins should be at least 5 kΩ.

Avoid shorting the VREGA and DTC pins.

*When VCC falls to 2.8 V or below, a protection circuit will operate to limit MAX DUTY in order to prevent the IC from

malfunctioning when VREGA (the internal circuit power supply) drops.

BD9731KV

DRIVER

OUT

Switching regulator output

Detection

voltage SCP

RSCP1

RSCP2

SCPCOMP

VREF

VSC

1 to 5

Fig. 5 Setting the Short Protection Detection Voltage

DTC

RDTC 1

PWMCOMP

RDTC 2

1 to 5

Setting voltage

OSC

REGA

BD9730KV / BD9731KV

VREGA

Fig. 6 Setting the DTC Voltage

(BD9730KV/BD9731KV)

RA R1 A

rox. 125 kΩ

VREGA

DTC

R2 A

rox. 375 kΩ

BD9733KN

Fig. 7 Circuit for Setting the DTC Externally

(BD9733KN)

11/16

11. Soft start operation triggered by the DTC pin

Soft start operation can be set by connecting a capacitor to the DTC pin.

Set the STBY pin to high, the capacitor connected to the DTC pin will be charged through the internal pull-up resistor.

Startup will begin when this voltage reaches the minimum voltage of the CT pin's triangular waveform.

When the desired voltage is reached, the FB pin's voltage will drop and normal feedback operation will begin.

*Set the capacitance connected to the DTC pin to 10 µF or less.

12. Soft start operation of low-voltage startup circuit (BD9733KN)

When the IC is operating on a supply voltage of 1.5 V, the supply voltage is stepped up at both the startup OSC (the

startup oscillator) and the BIP-DRIVER that drives the external NPN transistor during startup, and the stepped-up voltage

is used as VCC to operate the IC.

When VCC reaches approximately 2.6 V or higher, both circuits stop operating, and operation switches to the block

controlled by the main PWM.

The startup channel's soft start can be controlled with the capacitance of the capacitor connected to the SS2 pin.

Times can be determined with the following equation:

Startup time (sec) = (VSS / ISS) × CSS

(VSS: SS pin voltage [= 0.7 V]; ISS: soft start charge current [= 2.0 µA]; CSS: Capacitance)

Example: When CSS = 0.01 µF

Startup time = (0.7 / (2.0 × 10-6)) × (0.01 × 10-6)

= 3.5 ms

*Set the capacitance connected to the SS pin from 0.001 µF to 2.2 µF.

13. POWERGOOD (BD9733KN)

This switching circuit is synchronized to CH3 output and includes a delay function. When the INV3 pin reaches a voltage of

approximately 0.8 V, the capacitor connected to the DELAY pin begins to charge. Once the pin reaches approximately 2.0 V,

the PG4 pin turns on.

*Set the capacitance and resistance connected to the DELAY pin from 100 pF to 1 µF and from 100 kΩ to 400 kΩ,

respectively.

*The resistor should be connected to VREGA rather than VCC.

STBY23

SS2

VCC

VREGA

OUT2B

OUT2F

pprox. 0.7 V VCC

VREGA FB

OSC

VREF = 1.0 V

Startup OSC (Approx. 100 kHz)

(Startup block → Main)

pprox.

0.2 V

(Startup block repeat oscillation prohibited)

pprox. 1.0 V

Fig. 8 Timing Chart

VCC output voltage waveform

SS pin voltage waveform

Fig. 9 Startup Waveform (Reference Data)

Approx. 2.0 V

OFF ON

Approx. 0.8 V

INV3

DELAY

PG4

Delay time

Fig. 10 POWER GOOD Timing Chart

12/16

zReference Data

Fig. 11 Oscillating Frequency

VS RT Pin Resistance

(BD9730KV, BD9731KV)

Fig. 13 Reference Voltage

VS Temperature

(BD9730KV)

Fig. 15 REGA Output Voltage

VS Supply Voltage

(BD9730KV, BD9731KV)

Fig. 17 Error Amp Gain, Phase

VS Frequency

(BD9730KV, BD9731KV)

Fig. 14 Reference Voltage

VS Temperature

(BD9731KV)

Fig. 18 Oscillating frequency

VS RT Pin Resistance

(BD9733KN)

Fig. 19 Oscillating frequency

VS CT Pin Capacitance

(BD9733KN)

Fig. 20 MAX DUTY

VS DTC Voltage

(BD9733KN)

Fig. 21 Reference Voltage

VS Temperature

(BD9733KN)

Fig. 22 Delay Time VS

DELAY Pin Capacitance

(BD9733KN)

MBIENT TEMPERATURE: Ta [°C]

0.95

0.97

0.99

1.01

1.03

1.05

-20 0 20 40

60 80

REFERENCE VOLTAGE : VREF[V]

VCC [V]

0.5

1.5

2.5

0 2 4 6 8 10 12

VREGD [V]

100

1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1

VDTC [V]

MAX DUTY [%]

VCC=5V

RT=11kΩ

CT=180pF

mbient temperature: Ta [°C]

0.5

1.5

2.5

0 2 4 6 8 10 12

Vcc[V]

VREGA[V]

CT pin CAPACITANCE [pF]

OSCILATING FREQUENCY: fosc [Hz]

100k

10k

100 1000 10000

RT=24k

RT=12k

-100

-80

-60

-40

-20

100

FREQUENCY [Hz]

-180

-90

180

270

PHASE : φ[deg]

100 1k 10k 100k 1M

10M

OPEN LOOP GAIN: Gvo[dB]

Gvo

MBIENT TEMPERATURE: Ta [°C]

1.47

1.49

1.51

1.53

1.55

-20 0 20 40 80

REFERENCE VOLTAGE : VREF[V]

OSCILATING FREQUENCY [kHz]

RT pin RESISTANCE[kΩ]

100

1000

10 100

100pF

180pF

330pF

100

1000

100 1000

CT pin CAPACITANCE [pF]

OSCILATING FREQUENCY: fosc [kHz]

11kΩ

20kΩ

30kΩ

1µ

100p 1000p 10000p 0.01µ 0.1

10µ

100µ

10m

100m

DELAY pin CAPACITANCE [pF]

DELAY TIME[s]

Fig. 12 Oscillating Frequency

VS CT Pin Capacitance

(BD9730KV, BD9731KV)

Fig. 16 REGD Output Voltage

VS Supply Voltage

(BD9730KV, BD9731KV)

RT pin RESISTANCE[Ω]

OSCILATING FREQUENCY: fosc [Hz]

1k 10k 100k

10k

100k

CT=220p

CT=100p

0.95

0.96

0.97

0.98

0.99

1.01

1.02

1.04

1.05

-20 0 20 40

REFERENCE VOLTAGE : VREF[V]

1.03

13/16

zI/O Equivalent Circuit Diagrams

VCC

1.0 V

Fig. 23 I/O Equivalent Circuit Diagrams (1)

PVCC1 to PVCC2

(power supply input)

OUT1 to OUT4

(power transistor connection)

RBIAS1 to RBIAS4

(power ground, base current

setting resistor connection)

RBIAS5

(power supply input,

base current setting resistor

connection)

OUT5 (power transistor

connection)

PGND5 (power ground)

DTC1 to DTC5

(dead time control)

INV2 to INV4 (error amp inverted input)

SCP1 to SCP5 (SCP comparator input)

FB1 to FB5

(error amp output)

(triangular waveform timing

resistor connection)

(triangular waveform timing

capacitor connection)

VREGA (REGA output) VREF (reference voltage output)

OUT1 to OUT4

RBIAS1 to RBIAS

VCC

PVCC1 to PVCC 2 RBIAS5

OUT5

VCC

PGND2

VCC VCC

DTC

INV2 to INV4

SCP1 to SCP5

VCC

FB1 to FB 5

VREGA

SCP

(capacitor charge for timer latch)

VCC

SCP

VCC VREGA

VREGA

VCC

VRE

VCC VCC VCC

VREF

VCC

VREGA

14/16

Fig. 24 I/O Equivalent Circuit Diagrams (2)

VBAT2 (battery voltage input)

OUT2B

(2CH power transistor connection)

SWOUT

(switch output for feedback resistor)

PG2 (power-on switch output)

PG4 (POWERGOOD switch output)

SWOUT

PG2,PG4

PG1 (power-on switch output)

PG1

PG3 (power-on switch output)RBIAS2

(power supply input, base current

setting resistor connection)

OUT2F

(power transistor connection)

PGND (power ground)

PVCC2

(power supply input)

OUT3

(power transistor connection)

PGND (power ground)

SS2

(CH2 soft start capacitor connection pin)

STBY1 to STBY5

(CH1 to CH5 on/off control)

VCC

STBY1

to STBY5

UDSEL2

(step-up/step-down select input)

VCC

UDSEL2

DELAY

(delay time setting pin)

RBIAS2

OUT2F

PGND

VCC

VREGA

VCC

PG3

VBAT2

OUT2

VCC

SS2

VBAT VREGA

VCC

DELAY

PGND

OUT3

VCC

PVCC2

15/16

zPrecautions

1) Absolute maximum ratings

Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result

in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage

is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special mode where the

absolute maximum ratings may be exceeded is anticipated.

2) Connecting the power supply connector backward

Connecting the power supply connector backwards may result in damage to the IC. Insert external diodes between the power

supply and the IC's power supply pins as well as the motor coil to protect against damage from backward connections.

3) Power supply lines

Regenerated current may flow as a result of the motor's back electromotive force. Insert capacitors between the power

supply and ground pins to serve as a route for regenerated current.

4) GND potential

Ensure a minimum GND pin potential in all operating conditions.

5) Thermal design

Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.

6) Inter-pin shorts and mounting errors

Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in

damage to the IC. Shorts between output pins or between output pins and the power supply and GND pin caused by the

presence of a foreign object may result in damage to the IC.

7) Operation in a strong electromagnetic field

Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction.

8) ASO

When using the IC, set the output transistor so that it does not exceed absolute maximum ratings or ASO.

9) Thermal shutdown circuit (TSD circuit)

The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed

only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee its operation. Do

not continue to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit is

assumed.

10) Capacitors connected between output and ground pins

When a large capacitor is connected between the output and ground pins and for some reason the VCC falls to 0 V or

becomes shorted with the ground pin, the current stored in the capacitor may flow to the output pin, resulting in damage to

the IC. Set capacitors connected between the output and ground pins to values that fall within the recommended range.

11) Testing on application boards

When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.

Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC.

Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process.

12) IC pin input

This monolithic IC contains P+ isolation and PCB layers between adjacent elements in order to keep them isolated. P/N

junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of parasitic

elements.

{ For example, when a resistor and transistor are connected to pins as shown in Fig. 25, the P/N junction functions as

a parasitic diode when GND > (Pin A) for the resistor or GND > (Pin B) for the transistor (NPN).

{ Similarly, when GND > (Pin B) for the transistor (NPN), the parasitic diode described above combines with the N

layer of other elements to operate as a parasitic NPN transistor.

The formation of parasitic NPN transistors according to the relationships of different IC pins is an inevitable result of the IC's

architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC malfunction and

damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will trigger the operation of

parasitic elements, such as by the application of voltages lower than the GND (PCB) voltage to I/O pins.

13) Ground wiring patterns

Power supply and ground wiring should reflect consideration of the need to lower common impedance and minimize ripple as

much as possible (by making wiring as short and thick as possible or rejecting ripple by incorporating inductance and

capacitance).

14) STB pin voltage

Set the STB pin voltage to 0.3 V or lower when setting channels to a standby state, or to 2.0 V or higher when setting

channels to an operational state. Do not fix the STB pin voltage to values higher than 0.3 V and lower than 2.0 V or lengthen

transition times. Doing so may cause the IC to malfunction or result in damage.

15) Use a common supply voltage for both the driver block and the main block.

The IC is not compatible with applications requiring the driver block to be used while applying user-selected voltages.

16) Setting the MAX DUTY

MAX DUTY limitations may not operate when using the IC at high frequencies. When using the IC in such applications, allow

for sufficient margins when setting external components.

Transistor (NPN)

Parasitic elements GND

PCB

N N

P＋

(Pin B) B

GND

(Pin A)

GND

Parasitic elements

Fig. 25 Example of Simple Bipolar IC Architecture

Resistor

PCB

N N

P＋ P＋

(Pin A)

Parasitic

elements

GND

(

Pin B

)

B C

Other Adjacent

Elements Parasitic elements

The contents described herein are correct as of October, 2005

The contents described herein are subject to change without notice. For updates of the latest information, please contact and confirm with ROHM CO.,LTD.

Any part of this application note must not be duplicated or copied without our permission.

Application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. Please pay careful attention to the peripheral conditions when designing circuits and deciding

upon circuit constants in the set.

Any data, including, but not limited to application circuit diagrams and information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. ROHM CO.,LTD. disclaims any

warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such

infringement, or arising from or connected with or related to the use of such devices.

Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, implied right or license to practice or commercially exploit any intellectual property rights or other

proprietary rights owned or controlled by ROHM CO., LTD. is granted to any such buyer.

The products described herein utilize silicon as the main material.

The products described herein are not designed to be X ray proof.

Published by

Application Engineering Group

Catalog NO.05T342Be '05.10 ROHM C 1000 TSU

zSelecting a Model Name When Ordering

B D 9 7 3 3 K N − E2

ROHM model name Part number

9730, 9731, 9733

Package type

KV = VQFP

KN = UQFN

Taping type

E2 = Reel-wound embossed taping

1pin

（Unit:mm)

0.75

9.0±0.2

7.0±0.1

1.625Max.

0.1±0.05

1.425±0.05

9.0±0.2

7.0±0.1

0.08 S

0.5±0.1

0.08

0.22

+0.05

−0.04

° +6°

−4°

0.4±0.15

1.0±0.2

0.145

+0.05

−0.03

1PIN MARK

FP48

※When you order , please order in times the amount of package quantity.

Containe

Quantit

Direction

of feed

Tray(with dry pack)

1000pcs

Direction of product is fixed in a tray.

(The direction is the 1pin of product is at the upper left when you hold

reel on the left hand and you pull out the tape on the right hand)

Tape

Quantity

Direction

of feed

Embossed carrier tape(with dry pack)

2500pcs

※When you order , please order in times the amount of package quantity.

Reel Direction of feed

1pin

1234

(Unit:mm)

UQFN48

(1.4)

7.2± 0.1

7.0± 0.1

24 37

25 36

-0.3

+0.1

0.6

0.4

(0.20)

3-(0.45)

(0.55)

0.22 ± 0.05

0.95MAX

0.02

0.03

−

0.02

0.05

0.20 ± 0.05 0.05

7.0±0.1

7.2±0.1

Notes

No technical content pages of this document may be reproduced in any form or transmitted by any

means without prior permission of ROHM CO.,LTD.

The contents described herein are subject to change without notice. The specifications for the

product described in this document are for reference only. Upon actual use, therefore, please request

that specifications to be separately delivered.

Application circuit diagrams and circuit constants contained herein are shown as examples of standard

use and operation. Please pay careful attention to the peripheral conditions when designing circuits

and deciding upon circuit constants in the set.

Any data, including, but not limited to application circuit diagrams information, described herein

are intended only as illustrations of such devices and not as the specifications for such devices. ROHM

CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any

third party's intellectual property rights or other proprietary rights, and further, assumes no liability of

whatsoever nature in the event of any such infringement, or arising from or connected with or related

to the use of such devices.

Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or

otherwise dispose of the same, no express or implied right or license to practice or commercially

exploit any intellectual property rights or other proprietary rights owned or controlled by

ROHM CO., LTD. is granted to any such buyer.

Products listed in this document are no antiradiation design.

Appendix1-Rev2.0

Thank you for your accessing to ROHM product informations.

More detail product informations and catalogs are available, please contact your nearest sales office.

ROHM Customer Support System THE AMERICAS / EUROPE / ASIA / JAPAN

www.rohm.com

The products listed in this document are designed to be used with ordinary electronic equipment or devices

(such as audio visual equipment, office-automation equipment, communications devices, electrical

appliances and electronic toys).

Should you intend to use these products with equipment or devices which require an extremely high level

of reliability and the malfunction of which would directly endanger human life (such as medical

instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers

and other safety devices), please be sure to consult with our sales representative in advance.

It is our top priority to supply products with the utmost quality and reliability. However, there is always a chance

of failure due to unexpected factors. Therefore, please take into account the derating characteristics and allow

for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in

order to prevent possible accidents that may result in bodily harm or fire caused by component failure. ROHM

cannot be held responsible for any damages arising from the use of the products under conditions out of the

range of the specifications or due to non-compliance with the NOTES specified in this catalog.

21 Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan TEL : +81-75-311-2121

FAX : +81-75-315-0172

Appendix