HYB 39S128400/800/160CT(L)
128-MBit Synchronous DRAM
I NF IN E ON T e ch no logi es 1 9. 0 1
The HYB 39S128400/800/160CT are four bank Synchronous DRAM’s organized as 4
banks ×8MBit x 4, 4 bank s ×4 MBit x 8 an d 4 ban ks ×2Mbit x16 respectively. These synchronous
devices achieve high speed data transfer rates by employing a chip architecture that prefetches
multiple bits and then synchronizes the output data to a system clock. The chip is fabricated using
the Infine on advanced 0. 17 micron process technol ogy.
The device is designed to comply with all industry stand ards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an ex ternally supplied clock.
Ope rat in g th e f o ur me mo ry b ank s i n an in t erle av e f ashi o n a ll ows ran do m ac ce ss oper at ion t o o ccur
at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is
possible depending on burst length, CAS lat ency and speed g rade of the devi ce.
Aut o Refresh ( CBR) and Sel f Refr esh oper ation are supp orted . Thes e devices o perat e with a si ngle
3.3 V ±0.3 V power supply and are available in TSOPII packages.
• Hig h Perfor m a nc e:
• Sin gle Pulsed RA S Interface
• Ful ly Sy nchronous to Posit ive Clock E dge
• 0 to 70 °C operating temp erature
• Four Banks controlled by BA0 & BA1
• Programmable CAS Latency: 2, 3
• Programmable Wrap Sequence: Sequential
or Interle ave
• Pro gr a m ma ble Burst Le ng th :
1, 2, 4, 8 and full page
• Multiple Burst Read with Single Write
Operation
• Automat ic and Controlled Precha rge
Command
• D ata Ma sk fo r R ead /Write Control (x4, x8)
• D ata Ma sk fo r byte control (x16)
• Auto Refr esh ( CBR ) and Self Refresh
• Power Down and C lock Suspend Mode
• 4096 Refresh Cycles / 64 ms
• R andom Column Address every CLK
(1-N Rul e)
• Single 3. 3 V ±0.3 V Pow e r S up pl y
• LVTTL Interface
• Plastic Packages:
P-T SOPII-54 40 0mil x 87 5 mil widt h
(x4, x8, x16)
• -7 for PC 133 2- 2-2 applicati ons
-7.5 for PC 133 3- 3-3 applicati ons
-8 for PC100 2-2-2 applications
-7 -7.5 -8 Units
fCK 143 133 125 MHz
tCK3 77.58ns
tAC3 5.4 5.4 6 ns
tCK2 7.5 10 10 ns
tAC2 5.466ns
128-MBit Synch ronous DRAM
HYB 39S128400/800/160CT(L)
128-MBit Synchronous DRAM
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Ordering Information
Type Function Code Package Description
HYB 39S128400CT-7 PC133-222-520 P-TSOP-54 (400mil) 143MHz 4B × 8M x4 SDRAM
HYB 39S128400CT-7.5 PC133-333-520 P-TSOP-54 (400mil) 133 MHz 4B × 8M x4 SDRAM
HYB 39S128400CT-8 PC100-222-620 P-TSOP-54 (400mil) 100 MHz 4B × 8M x4 SDRAM
HYB 39S128800CT-7 PC133-222-520 P-TSOP-54 (400mil) 143 MHz 4B × 4M x8 SDRAM
HYB 39S128800CT-7.5 PC133-333-520 P-TSOP-54 (400mil) 133 MHz 4B × 4M x8 SDRAM
HYB 39S128800CT-8 PC100-222-620 P-TSOP-54 (400mil) 100 MHz 4B × 4M x8 SDRAM
HYB 39S128160CT-7 PC133-222-520 P-TSOP-54 (400mil) 143 MHz 4B × 2M x16 S DRAM
HYB 39S128160CT-7.5 PC133-333-520 P-TSOP-54 (400mil) 133 MHz 4B × 2M x16 SDRAM
HYB 39S128160CT-8 PC100-222-620 P-TSOP-54 (400mil) 100 MHz 4B × 2M x16 S DRAM
HYB 39S128160CTL-8 PC100-222-620 P-TSOP-54 (400mil) 100 MHz 4B × 2M x16 S DRAM
Low Power (“L”) version
HYB 39S128160CTL-7.5 PC133-333-520 P-TSOP-54 (400mil) 133 MHz 4B × 2M x 16 SDRAM
Low Power (“L”) version
Pin Definitions and Functions
CLK Clock Input DQ Data Input/Output
CKE Clock Enable DQM, LDQM,
UDQM Data Mask
CS Chip Select VDD Pow er (+ 3.3 V)
RAS Row Address Strobe VSS Ground
CAS Column Addres s Strobe VDDQ Power for DQ’s (+ 3.3 V)
WE Write Enable VSSQ Ground for DQ’s
A0 - A11 Address Inputs N.C. Not connec ted
BA0, BA1 Bank Select
HYB 39S128400/800/160CT(L)
128-MBit Synchronous DRAM
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Pin Configuration for x4 , x8 & x16 Organized 1 28M-DRAMs
SPP04121
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VDD
DQ0
A10
A0
A1
A2
A3
VDD
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
CAS
WE
RAS
CS
BA0
BA1 BA1
BA0
CS
RAS
WE
CAS
N.C.
VDD
N.C.
VSSQ
DQ3
N.C.
VDDQ
DQ2
N.C.
VSSQ
DQ1
N.C.
VDDQ
VDD
A3
A2
A1
A0
A10
DQ0
VDD VDD
BA1
BA0
CS
RAS
WE
CAS
N.C.
VDD
N.C.
VSSQ
DQ1
N.C.
VDDQ
N.C.
N.C.
VSSQ
DQ0
N.C.
VDDQ
VDD
A3
A2
A1
A0
A10
N.C. VSS
N.C.
A8
A7
A6
A5
A4
VSS
VSSQ
N.C.
DQ3
VDDQ
N.C.
N.C.
VSSQ
N.C.
DQ2
VDDQ
N.C.
VSS
N.C.
CLK
DQM
CKE
N.C.
A11
A9 A9
A11
N.C.
CKE
DQM
CLK
N.C.
VSS
N.C.
VDDQ
DQ4
N.C.
VSSQ
DQ5
N.C.
VDDQ
DQ6
N.C.
VSSQ
VSS
A4
A5
A6
A7
A8
DQ7
VSS VSS
A9
A11
N.C.
CKE
UDQM
CLK
N.C.
VSS
DQ8
VDDQ
DQ9
DQ10
VSSQ
DQ11
DQ12
VDDQ
DQ13
DQ14
VSSQ
VSS
A4
A5
A6
A7
A8
DQ15
TSOPII-54 (10.16 mm x 22.22 mm, 0.8 mm pitch)
32 M x 4
16 M x 8
8 M x 16
HYB 39S128400/800/160CT(L)
128-MBit Synchronous DRAM
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Func t ion al Bloc k Diag r ams
Block Diagram: 32M x4 SDRAM (12 / 11 / 2 addressing)
Memory
Array
Bank 1
4096
x 2048
x 4 Bit
Memory
Array
Bank 2
4096
x 2048
x 4 Bit
Memory
Array
Bank 3
4096
x 2048
x 4 Bit
SPB04122
Column Address
Counter
Row
Decoder
Memory
Array
Bank 0
4096
x 2048
x 4 Bit
Column Decoder
Sense amplifier & I(O) Bus
Row
Decoder
Sense amplifier & I(O) Bus
Row
Decoder Row
Decoder
Column Decoder
Sense amplifier & I(O) Bus
Row Address
Buffer
Column Address
Buffer Refresh Counter
Sense amplifier & I(O) Bus
A0 - A11,
BA0, BA1
A0 - A9, A11, AP,
BA0, BA1
Column Addresses Row Addresses
Input Buffer Output Buffer
DQ0 - DQ3
Control Logic &
Timing Generator
CLK
CKE
CS
RAS
CAS
WE
DQM
Column Decoder
Column Decoder
HYB 39S128400/800/160CT(L)
128-MBit Synchronous DRAM
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Block Diagram: 16M x8 SDRAM (12 / 10 / 2 addressing)
Memory
Array
Bank 1
4096
x 1024
x 8 Bit
Memory
Array
Bank 2
4096
x 1024
x 8 Bit
Memory
Array
Bank 3
4096
x 1024
x 8 Bit
SPB04123
Column Address
Counter
Row
Decoder
Memory
Array
Bank 0
4096
x 1024
x 8 Bit
Column Decoder
Sense amplifier & I(O) Bus
Row
Decoder
Sense amplifier & I(O) Bus
Row
Decoder Row
Decoder
Column Decoder
Sense amplifier & I(O) Bus
Row Address
Buffer
Column Address
Buffer Refresh Counter
Sense amplifier & I(O) Bus
A0 - A11,
BA0, BA1
A0 - A9, AP,
BA0, BA1
Column Addresses Row Addresses
Input Buffer Output Buffer
DQ0 - DQ7
Control Logic &
Timing Generator
CLK
CKE
CS
RAS
CAS
WE
DQM
Column Decoder
Column Decoder
HYB 39S128400/800/160CT(L)
128-MBit Synchronous DRAM
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Block Diagram: 8 M x16 SDRAM (12 / 9 / 2 addressing)
Memory
Array
Bank 1
4096 x 512
x 16 Bit
Memory
Array
Bank 2
4096 x 512
x 16 Bit
Memory
Array
Bank 3
4096 x 512
x 16 Bit
SPB04124
Column Address
Counter
Row
Decoder
Memory
Array
Bank 0
4096 x 512
x 16 Bit
Column Decoder
Sense amplifier & I(O) Bus
Row
Decoder
Sense amplifier & I(O) Bus
Row
Decoder Row
Decoder
Column Decoder
Sense amplifier & I(O) Bus
Row Address
Buffer
Column Address
Buffer Refresh Counter
Sense amplifier & I(O) Bus
A0 - A11,
BA0, BA1
A0 - A8, AP,
BA0, BA1
Column Addresses Row Addresses
Input Buffer Output Buffer
DQ0 - DQ15
Control Logic &
Timing Generator
CLK
CKE
CS
RAS
CAS
WE
DQMU
DQML
Column Decoder
Column Decoder
HYB 39S128400/800/160CT(L)
128-MBit Synchronous DRAM
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Signal Pin Description
Pin Type Signal Polarity Function
CLK Input Pulse Positive
Edge The system clock input. All of the SDRAM inputs are
sampled on the rising edge of the clo ck.
CKE Input Level Active
High Activates the CLK signal w hen hi gh and deactivates the
CLK signal when low, thereby initiating either the Power
Down mod e, Suspend mode, or the Self Refresh mode .
CS Input Pulse Active
Low CS ena bles the command decoder whe n low and disables
the command decoder when high. When the command
decoder is di sabled, new commands are ignored but
previous operations continue.
RAS
CAS
WE
Input Pulse Active
Low When sampled at the positive rising ed ge of the clock,
CAS, RAS, and WE define the command to be executed by
the SDRAM.
A0 - A11 Input Level –During a Bank Activate command cycle, A 0 - A11 de fine
th e row ad dr e ss (RA 0 - RA11) w he n sa mp le d at the ri si ng
clock edge.
During a Read or Wri te co mmand cycle, A0- An define the
column address (CA0 - CAn) when sample d at the rising
clock edge. C An de pend s up on the S DR A M orga niza ti on :
32M x4 SDRAM CA0 - CA9, CA11
(Page Length = 2048 bit s )
16M x8 SDRAM CA0 - CA 9 (Page Lengt h = 1024 bits)
8M x16 SDRAM CA0 = CA8 (Page Length = 512 bits)
In addition to the column address, A10(= AP) is used to
invoke the autoprec harge operation at the end of the burst
read or write cycle. If A10 is high, autoprecharge is
selected and BA0, BA1 defines the bank to be precharged.
If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10 (= AP) is used in
conjunction with BA0 and BA1 to control which bank(s) to
prech arge. If A10 is high , all four ban ks will be precharged
regardless of the state of BA0 and BA1. If A10 is low, then
BA0 and BA1 are used to define which bank to precharge.
BA0, BA1 Input Level –Bank Select Inputs. Selects which bank is to be active.
DQx Input
Output Level –Data Input/Output pins ope rate in the same manner as on
conventional DRAM s.
HYB 39S128400/800/160CT(L)
128-MBit Synchronous DRAM
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DQM
LDQM
UDQM
Input Pulse Active
High The Data Input/Output mask places the DQ buffers in a
high impedance state when sampled high. In Read mode,
DQ M has a late n c y of tw o cl oc k cycles an d co nt r ol s the
output buffers like an output enable. In Write mode, DQM
has a latency of zero and operates as a word mask by
allowing input dat a to be writ ten i f it is low but b locks the
write op eratio n if DQ M is high .
One DQM input is present in x4 an d x8 SDRAMs, LDQM
and UDQM controls the lower and upper bytes in x16
SDRAMs.
VDD
VSS
Supply –– Po wer an d gro un d for the input bu ffe rs and the cor e logic .
VDDQ
VSSQ
Supply –– Isolated power supply and ground for the output buffers to
pr ov id e im pr o ve d nois e im m un ity .
Signal Pin Description (cont’d)
Pin Type Signal Polarity Function
HYB 39S128400/800/160CT(L)
128-MBit Synchronous DRAM
I NF IN E ON T e ch no logi es 9 9. 0 1
Operation Definition
All of SDRA M operat ions are defined by state s of co ntrol signals CS, RAS, CAS, WE, and DQM at
the po sitive edge of the clock. The fo llowing list shows the truth table for the operation commands.
Operation Device
State CKE
n-1 CKE
nDQM BA0
BA1 AP=
A10 Addr
A11,
A9-0
CS RAS CAS WE
Bank Active Idle3 HXXVVVLLHH
Bank Precharge Any H X X V L X L L H L
Precharge All Any H X X X H X L L H L
Write Active3HXXVLVLHLL
Write with Autoprecharge Active3HXXVHVLHLL
Read Active3HXXVLVLHLH
Read with Autoprecharge Active3HXXVHVLHLH
Mode Register Set Idle H X X V V V L L L L
No Operation Any H X X X X X L H H H
Bur st Stop Active H X X X X X L H H L
Device Deselect Any HXXXXXHXXX
Auto Refresh Idle H H X X X X L L L H
Self Refresh Entry Idle H L X X X X L L L H
S elf R efr esh Exit Idl e
(Self
Refr.) LHXXXXHXXX
LHHX
Power Down Entry
(Precharge or active
standby)
Idle
Active4HLXXXXHXXX
LHHX
Power Down Exit Any
(Power
Down) LHXXXXHXXX
LHHL
Data Write/Output Enable Active H X L X X X X X X X
Data Write/Output Disable Active H X H X X X X X X X
Notes:
1. V = Valid, x = Don’t Ca re, L = Low Level, H = High Le vel.
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock
before the comm ands are provided.
3. This is the state of the banks designated by BA0, BA1 signals.
4. Pow er Down Mode can not entry i n the bu rst cycl e. W hen thi s comman d is as serte d in t he burst
mode cycle the device is in clock suspend mode .
HYB 39S128400/800/160CT(L)
128-MBit Synchronous DRAM
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Address Inputs for Mode Register Set Operation
SPD04125_FP
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Operation Mode CAS Latency BT Burst Length
Address Bus (Ax)
Mode Register (Mx)
BA1 BA0 M11 M10 M9 M8 M7 Mode
0 0 0 0 0 0 0 Burst Read/
Burst Write
M3 Type
0 0 0 0 1 0 0 Burst Read/
Single Write
Operation Mode BurstType
0Sequential
1Interleave
M5 M4 LatencyM6
CAS Latency
0 0 Reserved0
10 0 Reserved
200 1
1 310
1 0 0
11 0 Reserved
01 1
1 11
M1 M0 Length
M2
Burst Length
Sequential
10 0
1
2
00 1
1
4
10
1 0
8
0
11 0 Reserved
01 1
1 11
1
2
4
8
Reserved
Interleave
00 0
Full Page
HYB 39S128400/800/160CT(L)
128-MBit Synchronous DRAM
I NF IN E ON T e ch no logi es 11 9. 0 1
Power On and Initialization
The default power on state of the mode register is supplier specific and may be undefined. The
following power on and initialization sequence guarantees the device is preconditioned to each
us ers sp ec ifi c n ee ds . Like a co nve nti on al DRA M, the S yn chr on ous DRA M m us t be po w ere d up and
initialized in a predefined manner. During power on, all VDD and VDDQ pins must be built up
simultaneously to the specified voltage when the input signals are held in the “NOP” state. The
power on voltage must not ex ceed VDD + 0.3 V on any of the input pins or VDD supplies. The CLK
signal must be started at the same time. After power on, an initial pause of 200 µs is required
follo wed by a p rec harge of a ll ba nks using the prec harge comman d. To prevent data contention on
the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial
paus e pe rio d. O nce all b anks hav e be en p rec harge d, the M ode Re giste r Se t Co mman d mus t be
issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also
required.These may be done before or after programming the Mode Register. Failure to follow these
steps may lead to unpredictable start-up modes.
Programming the Mode Register
The Mod e reg is t er de si gn ates th e op era t io n mo de at th e rea d o r wri t e cy cle . Th is regi st er i s di vi de d
into 4 fields. A Burst Length Field to set the length of the burst, an Addressing Selection bit to
program the column access se quence in a burst cycl e (interleav ed or sequential), a C AS Latency
Field to set the access time at clock cycle and a Operation mode field to differentiate between
normal operat ion (Bu rst read and burst Write) and a spec ial Burst Read an d Single Write mode.
After the initial power up, the mode set operation must be done before any activate command. Any
cont e nt of t h e mode r egi st er c an be al ter ed by r e-e xe cu ting t he mode se t c om man d. A ll b an ks mus t
be i n pr echarg ed st ate an d CKE must be h igh at le ast one cl ock b efore the m ode set oper ation . Aft er
th e mo de r e gi ster is set, a S ta ndby or N O P co mma nd i s r eq ui r ed . L ow s ignal s of R AS, CAS, and
WE at the positive edge of the clock activate the mode set operation. Address input data at this
timing defines parameters to be set as shown in the previous table.
Re ad and Wr ite O per a t io n
When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle
starts. According to address da ta, a word line of the selected ba nk is a ctivate d and all of se nse
am plif i ers as so ci at ed t o th e w ord li ne a re set . A CA S cycle is triggered by setting RAS hi gh and CA S
low at a c lo ck ti min g a fte r a ne ce ssa ry de la y, tRCD, from the RAS timing. WE is us ed to de fi ne ei ther
a read (WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access modes. In a single CAS cycle, se rial data read or
write op er at i on s a r e al lo w ed at up t o a 1 43 M Hz d at a rate. Th e nu m bers o f se r ia l da t a b its ar e the
bur st l engt h p rogr amm ed a t t he m ode set o per atio n, i.e., on e of 1, 2, 4, 8 an d ful l p age. Col umn
addresses are segmented by the burst length and serial data accesses are done within this
boundary. The first column address to be accessed is supplied at the CAS timing and the
subsequent addresses are generated automatically by the programmed burst length and its
sequence. For example, in a burst length of 8 with interleave sequence, if the first address is ‘2’,
then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5.
Full p age burst op eration is only possible us ing seq uential burst type and page length is a func tion
of the I /O o rga nisa tio n an d co lumn add res sing . F ull p age bu rst op era tion do es n ot se lf t ermi nat e
HYB 39S128400/800/160CT(L)
128-MBit Synchronous DRAM
I NF IN E ON T e ch no logi es 12 9. 0 1
once the burst length has been reached. In other words, unlike burst length of 2, 4, and 8, full page
burst continues until it is terminated using another command.
Similar to the page mode of con ventional DRAM’s, burst read o r write ac cesses on any column
addr ess are possible once the RAS cyc le la tche s th e se nse a mpli fier s. Th e max imu m tRAS or t he
refresh interval time limi ts the number of random column accesses. A new burst access can be
done even before the previous burst ends. The interrupt operation at every clock cycle is supported.
Whe n the p re viou s burst i s inter rupt ed, t he r emainin g addre sses ar e overridd en by t he new ad dress
wi th the f ull burst l ength. An i nte rr upt w hich accomp ani es an oper at ion chan ge fr om a rea d to a write
is possible by exploi ting DQM to avoid bus contention.
When two or more banks are activated sequentially, interleaved bank read or write operations are
possible. Wit h the programmed burst length, alternate access and precharge operations on two or
mor e ban ks c an re aliz e fast seri al dat a acce s s mod es am ong m any di ffer ent pa ges . Onc e two o r
more banks are activated, column to column interleave operation can be performed between
di ffe r e nt pa ges.
Refresh Mode
SDR AM ha s two r efr es h mo des, Au to Ref r es h and S el f Re fr esh . Au to R efr es h i s simil a r to th e CA S
-before-RAS refre s h of conventional DRAMs. All of b anks must b e precharged before applying any
refresh m ode. An on-chip address count er increme nts the word and th e bank addresses and no
bank information is required for both refresh modes.
The c hip ente rs the Auto Re fresh mo de, whe n RAS and CAS are h eld lo w and C KE an d WE are
hel d h ig h at a cl ock t imin g. T he mo de r esto res w ord li ne aft er t h e r efr es h an d n o ext er na l pr ec harg e
Burst Length and Sequence
Burst
Length Starting
Address
(A2 A1 A0)
Sequential Burst
Addressing
(decimal)
Interleave Burst
Addressing
(decimal)
2xx0
xx1 0, 1
1, 0 0, 1
1, 0
4x00
x01
x10
x11
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
8000
001
010
011
100
101
110
111
0 1 2 3 4 5 6 7
1 2 3 4 5 6 7 0
2 3 4 5 6 7 0 1
3 4 5 6 7 0 1 2
4 5 6 7 0 1 2 3
5 6 7 0 1 2 3 4
6 7 0 1 2 3 4 5
7 0 1 2 3 4 5 6
0 1 2 3 4 5 6 7
1 0 3 2 5 4 7 6
2 3 0 1 6 7 4 5
3 2 1 0 7 6 5 4
4 5 6 7 0 1 2 3
5 4 7 6 1 0 3 2
6 7 4 5 2 3 0 1
7 6 5 4 3 2 1 0
Full Page nnn Cn, Cn+1, Cn+2.... not supported
HYB 39S128400/800/160CT(L)
128-MBit Synchronous DRAM
I NF IN E ON T e ch no logi es 13 9. 0 1
comma nd is ne ces sary . A mi ni mu m tRC time is required between two automatic refreshes in a burst
ref resh mo de. The sa me rul e appli es to an y acc ess comman d after th e auto matic r efres h operat ion .
The chip has an on-chip t imer a nd th e Self Refresh mo de is avail able. It e nters the mode whe n RAS,
CAS, and CK E are low an d WE is hig h at a clock ti mi ng. A ll of ext er nal cont ro l si gn als in cl ud in g the
cloc k ar e disab l ed . Ret u rni ng C KE to hi gh ena bles th e cl oc k an d ini t ia tes t he ref resh exi t oper at ion .
After the exit command, at leas t one tRC delay is required prior to any acces s command.
DQM Function
DQM has two functions for data I/O read and write operations. During reads, when it turns to “high”
at a cloc k timing, data ou tputs ar e disab led a nd be come high i mpedance a fter two cl ock de lay (D QM
Dat a Dis able Lat ency tDQZ). It al so p rov ides a da ta ma sk funct ion f or wri tes. W hen DQM i s act ivated ,
the wri te operatio n at the next clock is prohibited (DQM Write Mask Latency tDQW = ze ro cl oc ks ) .
Suspend Mode
During normal access mode, CKE is h eld high enabling the cl ock. When CKE is low, it fr eezes the
interna l clock and extends data read and write operat ions. One clo ck dela y is require d for mode
entry and exit (Clock Suspend Latency tCSL).
Power Down
In o r der t o redu ce stan db y po wer c ons um ptio n, a p owe r do w n mode is ava il ab le. Al l ba nks mus t b e
pr ec ha r ge d an d t h e ne ce ss ary P re ch ar g e de lay (tRP) must occur bef ore the SDRAM can enter the
Power Down mode. On ce the Power Down mode is initiated by holding CK E low, all of the receiver
circ uits ex cep t CL K an d CKE a re ga ted o ff. The Po wer D own mod e d oes no t p erf orm a ny re fres h
operations, therefore the device can’t remain in Power Down mode longer than the Refresh period
(tREF) of the device. Exit from this mode is performed by taking CKE “high”. One clock delay is
required for pow er down mode entry and exit.
Auto Precha rge
Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS
timing accepts one extra address, CA10, to determine whether the chip restores or not after the
operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge function
is initiated. If CA10 is high when a Write Command is issued, the Write with Auto-Precharge function
is initiated. The SDRAM automatically enters the precharge operation a time delay equal to tWR
(Write recovery time) after the last data in.
Pr echarge Command
There is also a separate precharge command available. When RAS and WE are lo w and C A S is
hig h at a c lo ck ti ming, i t tri ggers the precha rge ope rati on. T hree ad dress b its , BA0, BA1 an d A10 ar e
used to define banks as shown in the following list . The precharge command can be imposed one
clock before the last data out for CAS latency = 2, two clocks before the last data out for CAS
lat ency = 3 and three c locks bef ore th e last da ta out for CAS latency = 4. Writes require a time delay
tWR from t he last data out to apply the precharge command.
HYB 39S128400/800/160CT(L)
128-MBit Synchronous DRAM
I NF IN E ON T e ch no logi es 14 9. 0 1
Burst Termination
Once a burst read or write operation has been initiated, there are several methods in which to
terminate the burst operation prematurely. These methods include using another Read or Write
Co mm a nd to in te r rupt a n ex is ting bu rs t ope ratio n, us e a Prec ha r g e C o m ma nd to i nt er ru pt a bu rst
cycle and close the active bank, or usin g the Burst Stop Command to terminate the existing burst
oper ation but leave the bank open for future Read or Wri te Commands to the same page of the
ac tiv e ba nk . Whe n i nt err upt in g a burs t wi t h an othe r Rea d or W r ite C o mmand car e must b e t ake n to
avoid DQ contention. The Burst Stop Command, however, has the fewest restrictions making it the
eas i e st m eth od t o us e when te rm inati ng a bur s t op eratio n be fore it ha s been co m ple te d. If a Bur st
Stop command is issued during a burst write operation, then any residual data from the burst writ e
cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is
registered will be written to the memory.
Bank Selection by Address Bits
A10 BA0 BA1
000Bank 0
001Bank 1
010Bank 2
011Bank 3
1xxall Banks
HYB 39S128400/800/160CT(L)
128-MBit Synchronous DRAM
I NF IN E ON T e ch no logi es 15 9. 0 1
Electrical Char acteri stics
Absolute Maximum Ratings
Ope ra tin g Temp era tu r e Ra n ge.. .... .... .... .... ....... .... .... .... ....... .... .... .... ....... .... .... .... .... ....... .0 to + 70 °C
Storage Temperature Range.................................................................................. – 55 to + 150 °C
Inpu t/O u tp ut Voltag e....... .... ....... .... .... .... .... ....... .... .... .... ... ........ .... .... .... ... ........ .. – 0.3 to VDD + 0.3 V
Power Suppl y Voltage VDD/VDDQ.............................................................................. – 0.3 to + 4.6 V
Pow er Dis sipa tio n....... .... .... ... ........ .... .... .... ... ........ .... .... ... .... ........ .... .... ... ........ .... .... ... .... .... .........1 W
Data out Current (short circuit) ............................................................................................... 50 mA
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended
periods may aff ect device rel iability.
Recommended Operation and DC Characteristics
TA = 0 to 70 °C; VSS = 0 V; VDD,VDDQ = 3.3 V ± 0.3 V
Parameter Symbol Limit Values Unit Notes
min. max.
Input High Voltage VIH 2.0 VDD +0.3 V 1, 2
Input Low Voltage VIL –0.3 0.8 V 1, 2
Output High Voltage (IOUT =–4.0 mA) VOH 2.4 –V–
Output Low Voltage (IOUT =4.0mA) VOL –0.4 V –
Input Leakage Current, any input
(0 V < VIN <VDDQ, all other inputs = 0 V) II(L) –55 µA–
Output Leakage Current
(DQ is disabled, 0 V < VOUT <VDD)IO(L) –55 µA–
Notes
1.)All voltages are referenced to VSS.
2.)VIH may overshoot to VDD + 2.0 V for pulse width of < 4 ns with 3.3 V. VIL may undershoot to –2.0 V for pulse
width < 4.0 ns with 3.3 V. Pulse width measured at 50% points with amplitude measured peak to DC reference.
Capacitance
TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz
Parameter Symbol Values Unit
min. max.
Input Capacitance (CLK) CI1 2.5 3.5 pF
Input Capacitance
(A0 - A11, BA0, BA 1, RAS, CAS, WE, CS, CKE, DQM) CI2 2.5 3.8 pF
Input/Output Capacitance (DQ) CIO 4.0 6.0 pF
HYB 39S128400/800/160CT(L)
128-MBit Synchronous DRAM
I NF IN E ON T e ch no logi es 16 9. 0 1
Notes
5. These parameters depend on the cycle rate. These values are measured at 133 MHz for -7 &
-7.5 and at 100 MHz for -8 parts. Input s ignals are changed on ce during tCK.
6. These parame ters are me asured with continuous data stream during read ac cess a nd all DQ
togg ling. CL = 3 and BL = 4 is a ssumed and the VDDQ current is excluded.
Ope rati ng C urr en ts
TA = 0 to 70 °C, VDD = 3.3 V ± 0.3 V
(Recommended Operating Conditions unless otherwise noted)
Parameter & Test Condition Symb. -7 -7.5 -8 Unit Note
max.
Operat ing current
tCK =tCK(MIN.),All bank s op erate d
in random access,all banks
operated in ping-pong manner
–ICC1
170 160 150 mA 3,4
Pr echarge standby current
in Power Down Mode
CS = VIH (MIN.), CKE ≤VIL(MAX.)
tCK =min ICC2P 1.5 mA 3
Pr echarge standby current
in Non Power Down Mode
CS = VIH (MIN.), CKE ≥VIH(MIN.)
tCK =min ICC2N 45 40 35 mA 3
No operating current
tCK = min., CS = VIH (MIN.),
ac tiv e state (max. 4 bank s)
CKE ≥VIH(MIN.) ICC3N 50 50 45 mA 3
CKE ≤VIL(MAX.) ICC3P 10 mA 3
Burst Operating Current
tCK = min,Re ad comman d cycling –ICC4 110 100 90 mA 3, 4
Au to R ef r es h Cur re nt
tCK = mi n, trc = trcmi n.
Au to R ef r es h co m ma nd cycling
–ICC5 250 230 210 mA 3
Se lf R efresh C urr e nt
Se lf R efresh Mo de
CKE = 0.2 V, tck=infinity
standard
version ICC6 1.5 mA
L-version 690 µA
HYB 39S128400/800/160CT(L)
128-MBit Synchronous DRAM
I NF IN E ON T e ch no logi es 17 9. 0 1
AC Char acteri stics 1, 2
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns
Parameter Symb. Limit Values Unit No te
-7 -7.5 -8
min. max. min. max. min. max.
Clock and Clock Enable
Clock Cy cle Time
CAS Latency = 3
CAS Latency = 2 tCK 7
7.5 –
–7.5
10 –
–8
10 –
–ns
ns
–
Clock frequency
CAS Latency = 3
CAS Latency = 2 tCK –
–143
133 –
–133
100 –
–125
100 MHz
MHz
–
Acce ss Time from Clock
CAS Latency = 3
CAS Latency = 2 tAC –
–5.4
5.4 –
–5.4
6–
–6
6ns
ns
2, 3, 6
Clock High Pulse Width tCH 2.5 –2.5 –3–ns –
Clock Low Pulse Width tCL 2.5 –2.5 –3–ns –
Transition Time tT0.3 1.2 0.3 1.2 0.5 10 ns –
Setup an d Ho ld Tim es
Input Setup Time tIS 1.5 –1.5 –2–ns 4
Input Hold Time tIH 0.8 –0.8 –1–ns 4
CKE Setup Time tCKS 1.5 –1.5 –2–ns 4
CKE Hold Time tCKH 0.8 –0.8 –1–ns 4
Mode Re gister Set-up Time tRSC 2–2–2–CLK –
Power Down Mode Entry
Time tSB 0707.508ns–
Comm on Para me te rs
Row to Column Delay Time tRCD 15 –20 –20 –ns 5
Row Precharge Time tRP 15 –20 –20 –ns 5
Row Active Time tRAS 42 100k 45 100k 48 100k ns 5
Row Cycle Time tRC 60 –67 –70 –ns 5
Activate(a) to Activate(b)
Comman d Period tRRD 14 –15 –16 –ns 5
CAS(a) to CAS(b) Command
Period tCCD 1–1–1–CLK –
HYB 39S128400/800/160CT(L)
128-MBit Synchronous DRAM
I NF IN E ON T e ch no logi es 18 9. 0 1
Notes
1. F or proper power-up see the operation sectio n of this data sheet.
2. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between VIH and VIL. All AC measurements assume
tT= 1 ns with the AC output l oad circuit shown in figure below. Sp ecified tAC and tOH pa rameters
are measured with a 50 pF only, without any resistive termination and with a input signal of 1V /
ns edge rate be tween 0.8 V and 2.0 V.
Refresh Cycle
Refresh Period
(40 96 cyc les) tREF –64 –64 –64 ms –
Self Refresh Exit Time tSREX 1–1–1–CLK
Read Cycle
Da ta Out H old T ime tOH 3–3–3–ns 2, 5, 6
Da ta Out to Low Imped an ce
Time tLZ 0–0–0–ns –
Dat a Out t o Hi gh Im pe da nce
Time tHZ 373738ns–
DQM Data Out Disable
Latency tDQZ –2–2–2CLK–
Write Cycle
Write Recovery Time tWR 2–2–2–CLK 7
DQM Writ e Mask Latency tDQW 0–0–0–CLK –
AC Char acteri stics (cont’d)1, 2
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns
Parameter Symb. Limit Values Unit No te
-7 -7.5 -8
min. max. min. max. min. max.
HYB 39S128400/800/160CT(L)
128-MBit Synchronous DRAM
I NF IN E ON T e ch no logi es 19 9. 0 1
3. If clock rising time is longer than 1 ns, a time (tT/2 −0.5) ns has to be added to this parameter.
4. If tT is longer than 1 ns, a time (tT−1) ns has to be added to this parameter.
5. These parameter account for the number of clock cycles and depend on the operating frequency
of the clo ck , as foll ow s :
the number of clock cycles = specified value of timing period (counted in fractions as a whole
number)
6. Access time from clock tac is 4.6 ns for PC133 c omponen ts wi th no termina tion and 0 pF load,
Data out hold time toh is 1.8 ns for PC133 components with no termination and 0 pF load.
7. The wr i te r ec ov e r y t im e twr = 2 C L K c yc les is a d ig ita l int erloc k on th is devi ce . Spe ci al de vi ce s
with twr = 1 C LK for operations at less or equal 83 MHz will be available.
SPT03404
CLOCK 2.4 V
0.4 V
INPUT
HOLD
t
SETUP
t
t
T
OUTPUT 1.4 V
t
LZ
AC
t t
AC
OH
t
HZ
t
1.4 V
CL
t
CH
t
50 pF
I/O
Measurement conditions for
tAC and tOH
HYB 39S128400/800/160CT(L)
128-MBit Synchronous DRAM
I NF IN E ON T e ch no logi es 20 9. 0 1
Package Outlines
GPX09039
22.22
±0.131)
127
54 28
0.35
+0.1
-0.05
0.1
1
0.1
10.16
±0.13
±0.2
11.76
±0.1
0.5
Does not include plastic or metal protrusion of 0.15 max per side
1)
54x
±0.05
±0.05
0.15
-0.03
+0.06
15˚
±5˚
15˚
±5˚
6 max
2.5 max
2)
3)
Does not include plastic protrusion of 0.25 max per side
2)
Does not include dambar protrusion of 0.13 max per side
3)
Index Marking
0.8
20.8
26x 0.8 =0.2
M
54x
Plastic Package, P-TSOPII-54
(400 mil, 0.8 mm lead pitch)
Th in Small Outl ine Pa c kage, SMD
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technolo gies 22
T iming Diagrams
1. Bank Activate Command Cycle page 22
2. Burst Read Operat ion page 23
3. Read Interrupted by a Read page 24
4. Read to Write Interval page 24
4.1 Read to Write Interval page 24
4.2 Minimum Read to Writ e Interval page 25
4.3 Non-Minimum Read to W ri te Interv al page 25
5. Burst Write Operation page 26
6. Write and Read Interrupt page 27
6.1 W ri te Interrupted by a Write page 27
6.2 W ri te Interrupted by Read page 27
7. Burs t Write & Read with Auto-Precharge page 28
7.1 Burst Write with Aut o-Precharge page 28
7.2 Burst Read with Auto-Precharge page 28
8. AC- Par ameters page 29
8.1 AC Parameters for a Write Timing page 29
8.2 AC Parameters for a Read Timing page 30
9. Mode Register Set page 31
10. Power on Sequence and Auto Refresh (CBR) page 32
11. Cl ock Suspension (usin g CKE) page 33
11. 1 Clo ck Suspension During Burst Read CAS Latency = 2 page 33
11. 2 Clo ck Suspension During Burst Read CAS Latency = 3 page 34
11. 3 Clo ck Suspension During Burst Wri te CAS Latency = 2 page 35
11. 4 Clo ck Suspension During Burst Wri te CAS Latency = 3 page 36
12. Power Down Mode and Clock Suspend page 37
13. Sel f Refresh ( Entry and Exit ) page 38
14. Aut o Refr esh ( CBR ) page 39
15. Random Column Read ( Page within same Bank page 40
15.1 CAS Latency = 2 page 40
15.2 CAS Latency = 3 page 41
16. Random Column Write ( Page within sam e Bank) page 42
16.1 CAS Latency = 2 page 42
16.2 CAS Latency = 3 page 43
17. Random Row Read ( Interleaving Banks) wi th Precharge page 44
17.1 CAS Latency = 2 page 44
17.2 CAS Latency = 3 page 45
18. Random Row Wr ite ( Interleaving Banks) with Precharge page 46
18.1 CAS Latency = 2 page 46
18.2 CAS Latency = 3 page 47
19. Precharge Ter mination of a Burst page 48
20. Full Page Burst Operation page 49
20.1 Full Page Burst Read, CAS Latency = 2 page 49
18.2 Full Page Burst Write, C AS Latency = 3 page 50
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technologies 23
1. Bank Activate Command Cycle
2. Burst Read Oper ation
RC
"H" or "L"
t
T0
(CAS latency = 3)
Bank B
Row Addr.
Activate
Bank B
Address
Command
CLK
T
NOPNOP
RCD
t
T1
Col. Addr.
Bank B
with Auto
Precharge
Write B
T
SPT03784
Bank B
Row Addr.
Activate
Bank B
Row Addr.
Bank A
Activate
Bank A
T
NOP
RRD
t
TT
SPT03712
CLK
Read A NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8
Command NOP NOP NOP NOP NOP NOP NOP
DOUT A3
CK2
latency = 2
t, DQ’s DOUT A1DOUT A0 DOUT A2
DOUT A2
CK3
latency = 3
t, DQ’s DOUT A0 DOUT A1 DOUT A3
(Burst Length = 4, CAS latency = 2, 3)
CAS
CAS
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technolo gies 24
3. Read Interrupted by a Read
4. Read to Write Interval
4.1 Read to Write Interval
SPT03713
CLK
Read A
T0 T1 T2 T3 T4 T5 T6 T7 T8
Command
DOUT A0 DOUT B0 DOUT B1 DOUT B2
NOP NOP NOP NOP NOP NOP NOP
latency = 2
, DQ’s
CK2
t
CK3
latency = 3
t, DQ’s
(Burst Length = 4, CAS latency = 2, 3)
CAS
CAS
Read B
DOUT B3
DOUT B1DOUT A0 DOUT B0 DOUT B3DOUT B2
Commands = 4 + 1 = 5 cycles
Minimum delay between the Read and Write
DOUT A0
DQ’s
(Burst Length = 4, CAS latency = 3)
DQMx
Command
CLK
NOP Read A
T0 T1
NOP NOP
T2 T3
the Write Command
Must be Hi-Z before
DIN B0 DIN B1
SPT03787
DIN B2
DQW
NOP
DQZ
t
NOP
t
T4 T5
Write B NOP
T6 T7
NOP
T8
"H" or "L"
Write latency of DQMx
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technologies 25
4 2. Minimum Read to Write Interval
4. 3. Non-Minimum Read to Write Interval
the Write Command
Must be Hi-Z before
Activate
CAS
CK2
latency = 2
t, DQ’s
(Burst Length = 4, CAS latency = 2)
CLK
DQM
Command NOP
T0 T1
Bank A
NOP
DQZ
t
T2 T3
DIN A0 DIN A1 DIN A2
SPT03939
DIN A3
1 Clk Interval
Read A Write A
T4 T5
NOP NOP
T6 T7
NOP
T8
"H" or "L"
t
DQW
NOP
CAS
latency = 3
CK3
CAS
CK2
latency = 2
t
t
, DQ’s
, DQ’s DOUT A0
(Burst Length = 4, CAS latency = 2, 3)
CLK
DQM
Command NOP Read A
T0 T1
NOP NOP
T2 T3
the Write Command
Must be Hi-Z before
DOUT A0
DOUT A1
DIN B0
DIN B0
DIN B1
DIN B1
SPT03940
DIN B2
DIN B2
Read A
DQZ
t
NOP
T4 T5
Write B NOP
T6 T7
NOP
T8
"H" or "L"
tDQW
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technolo gies 26
5. Burst Write Operation
Extra data is ignored after
termination of a Burst.
DIN A3
T4
are registered on the same clock edge.
The first data element and the Write
NOP
(Burst Length = 4, CAS latency = 2, 3)
T0
Command
DQ’s
CLK
DIN A1
T2
NOP
DIN A0
Write A
T1
DIN A2
NOP
T3
SPT03790
T6
NOP NOP
T5
NOP NOP
T7
NOP
T8
don’t care
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technologies 27
6. Write and Read Interrupt
6.1 Write Interrupted by a Write
6.2 Write Interrupted by a Read
1 Clk Interval
SPT03791
CLK
T0 T1 T2 T3 T4 T5 T6 T7 T8
Command NOP NOP NOP NOP NOP NOP
DQ’s
(Burst Length = 4, CAS latency = 2, 3)
NOP Write A
DIN A0 DIN B0 DIN B1 DIN B2 DIN B3
Write B
1 Clk Interval
T5
NOP
DOUT B1
DOUT B0
Input data for the Write is ignored.
, DQ’s
latency = 3
CK3
CAS
t
don’t care
DIN A0
don’t care
(Burst Length = 4, CAS latency = 2, 3)
CLK
, DQ’s
Command
latency = 2
CK2
CAS
t
NOP
T0
DIN A0
Write A
don’t care
Read B
T1 T2
DOUT B0
NOP NOP
T4T3
SPT03719
appears on the outputs to avoid data contention.
DOUT B2
Input data must be removed from the DQ’s
at least one clock cycle before the Read data
DOUT B1 DOUT B3
NOP
DOUT B3
NOP
DOUT B2
T6 T7
NOP
T8
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technolo gies 28
7. Burst Write and Read with Auto Precharge
7.1 Burst Write with Auto-Precharge
7.2 Burst Read with Auto-Precharge
SPT03909 2
CLK
Active
NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8
Command NOP NOP NOP NOP
DQ’s
Bank A
Begin Auto Precharge
Bank can be reactivated after trp
Wri te A
Auto Precharge
DIN A1DIN A0
DIN A1DIN A0
CAS Latency = 2:
DQ’s
CAS Latency = 3:
WR
t
WR
t
RP
t
RP
t
*
*
*
Active
NOPCommand NOP NOP NOP NOP NOP NOP
Bank A W rite A
Auto Precharge
NOP
Activate
(Burst Length = 2, CAS latency = 2, 3 )
Activate
SPT03721_2
CLK
with AP
NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8
Command
DO UT A0 DOUT A1 DOUT A2 DOUT A3
NOP NOP NOP NOP NOP NOP NOP
latency = 2
DQ’s
DOUT A 3
latency = 3
DOUT A1DOUT A0 DOUT A2
(Burst Length = 4, CAS latency = 2, 3)
CAS
CAS
Read A
Bank can be reactivated after trp
Begin Auto Precharge
DQ’s
RP
t
*
*
*
t
RP
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technologies 29
8. AC Parameters
8.1 AC Parameters for a Write Timing
A uto Precharge
Bank B
Command
Writ e wi t h
Activate
Writ e wi t h
Activate
Bank A
Command
Auto Precharge
Bank A
Command Command
Bank B
Addr.
AP
DQM
DQ
BS
Hi-Z
RCD
t
Ax2Ax1Ax0 Ax3
RC
t
RAx
t
AS
t
AH
RBx
CAx
Command
SPT03910_2
Bx1Bx0
CBx
T8
Precharge
Begin Auto
Bank A
CLK
WE
CAS
RAS
CS
CKE
CK2
t
CS
t
CH
CKS
t
CH
t
t
CL
t
T3T0 T2T1 T4 T5 T7T6 T18
B urst Length = 4, CAS Latency = 2
T13T9 T10 T12T11 T14 T15 T17T16 T19 T20 T22T21
RBx
RAx
Activate Write
Command
Bank AB ank A
DS
t
t
DH
RAy
B ank B
Precharge
B egin Auto
RBy
ActivatePrecharge
Command
Bank A Bank A
Command Activate
Bank B
Command
t
WR
t
CKH
RAz
RAz RBy
RAy
RAy
Bx2 Bx3
t
WR RP
t
Ay2Ay1Ay0 Ay3
RP
t
RRD
t
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technolo gies 30
8.2 AC Parameters for a Read Timing
AC2
Hi-Z
DQ
Activate
Command
Bank A
Read
Bank A
Command
DQM
Addr.
AP
t
RCD
t
LZ
t
t
AS
RAx
RAx
t
AH
CAx
RRD
t
Command
Bank B
Read w ith
Auto Precharge
Activate
B ank B
Command
Ax1Ax0 Bx0
Activate
SPT03911_2
Command
B ank A
Bx1
t
AC2
OH
t
HZ
t
t
RAS
RC
t
RBx
RBx
RBx
HZ
t
RAy
RAy
T5
tt
BS
WE
CAS
RAS
t
CS
CKE
CKS
t
CH
t
t
CS
CH
CL
CK2
CLK
T0 T1 T2 T3 T4
Precharge
Bank B
Be gin A uto
t
CKH
B urst Length = 2, CA S Late ncy = 2
T6 T7 T8 T10T9 T11 T13T12
RP
t
Precharge
B ank A
Command
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technologies 31
9. Mode Register Set
Set Command
Mode Register
All Banks
Precharge
Command Any
Command
Address Key
T0 T1 T2 T8
RSC
t
T4
T3 T5 T6 T7 T11T9 T10 T12 T13
SPT03912_2
T19T16T15T14 T17 T18
CAS Latency = 2
T20 T21 T22
BS
Addr.
AP
CS
WE
CAS
RAS
CKE
CLK
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technolo gies 32
10. Power on Sequence and Auto Refresh (CBR)
Inputs must be
200stable for
µ
s
DQM
AP
DQ
Addr.
BS
RP
Command
All Banks
Precharge
Hi-Z
~
~
t
1st Auto Refresh
Command
~
~
~
~
~
~
~
~
~
~
~
~
~
~
SPT03913
Mode Register
Set Command
Address Key
8th Auto Refresh
Command
~
~
t
RC
~
~
~
~
~
~~
~
~
~~
~
~
~
Command
Any
Minimum of 8 Refresh Cycles are required
T8
WE
CAS
RAS
CS
CKE
CLK
required
~
~~
~
~
~
~
~
~
~
~
~
~
~
T3
is
~
~
~
~
LevelHigh
T0 T2T1 T5T4 T7T6 T18
2 Clock min.
~
~~
~
~
~
~
~
~
~
~
~~
~
T13
~
~
~
~
T10T9 T12T11 T14 T15 T17T16 T20T19 T22T21
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technologies 33
11. Clock Suspension ( Using CKE)
11.1 Clock Suspension During Burst Re ad CAS Latency = 2
Command
Bank A
DQM
Addr.
DQ
AP
BS
Read
Command
Bank A
Activate
Hi-Z
Suspend
1 Cycle
Clock
Ax0
CSL
t
Ax1
CAxRAx
RAx
SPT03914
t
Suspend
3 Cycles
Suspend
2 Cycles
Clock
Ax2
CSL
t
Clock
Ax3
HZ
T7
WE
CAS
RAS
CS
CKE
CLK
CK2
t
T0 T1 T2 T3 T4 T6T5 T16T8 T9 T10 T11 T14T12 T13 T15
Burst Length = 4, CAS Latency = 2
T18T17 T19 T20 T21 T22
CSL
t
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technolo gies 34
11.2 Clock Suspension During Burst Read CAS Latency = 3
CSL
DQM
Addr.
DQ
AP
BS
Bank A
Activate
Command
Hi-Z
Command
Bank A
Read
Ax0
t
RAx
RAx
CAx
HZ
t
t
Suspend
1 Cycle
Clock Suspend
2 Cycles
Clock
CSL
Ax1 Ax2
Clock
Suspend
3 Cycles
t
CSL
Ax3
SPT03915
T7
WE
CAS
RAS
CS
CKE
CLK
CK3
t
T0 T1 T2 T3 T4 T6T5 T16T8 T9 T10 T11 T14T12 T13 T15
Burst Length = 4, CAS Latency = 3
T18T17 T19 T20 T21 T22
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technologies 35
11.3 Clock Suspension During Burst Write C AS Latency = 2
Bank A
DQM
Addr.
DQ
AP
BS
DAx0
Command
Write
Activate
Command
Bank A
Hi-Z
Clock Clock
1 Cycle
Suspend Suspend
2 Cycles
DAx1
CAxRAx
RAx
DAx3
Clock
Suspend
3 Cycles
DAx2
SPT03916
T7
WE
CAS
RAS
CS
CKE
CLK
CK2
t
T0 T1 T2 T3 T4 T6T5 T16T8 T9 T10 T11 T14T12 T13 T15
Burst Length = 4, CAS Latency = 2
T18T17 T19 T20 T21 T22
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technolo gies 36
11.4 Clock Suspension During Burst Write CAS Latency = 3
Clock
Suspend
2 Cycles
Bank A
DQMx
Addr.
DQ
A8/AP
BA
Activate
Command
Bank A
Hi-Z
Clock
1 Cycle
Suspend
Command
Write
DAx0 DAx1
RAx
RAx
CAx
Clock
Suspend
3 Cycles
DAx2 DAx3
SPT03917
T7
WE
CAS
RAS
CS
CKE
CLK
CK3
t
T0 T1 T2 T3 T4 T6T5 T16T8 T9 T10 T11 T14T12 T13 T15
Burst Length = 4, CAS Latency = 3
T18T17 T19 T20 T21 T22
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technologies 37
12. Power Down Mode and Clock Suspend
BS
Clock SuspendClock Suspend
Mode Entry Mode Exit
Addr.
DQM
DQ
AP
Standby
Active
Activate
Bank A
Command
Hi-Z
Read
Command
Bank A
RAx
RAx
CAx
Power Down Power Down
Mode ExitMode Entry
SPT03918
End
Clock Mask
Clock Mask
Start
Ax0 Ax1 Ax2
Precharge
Command
Bank A
Ax3
t
HZ
Precharge
Standby Any
Command
T7
CAS
WE
RAS
CS
CKE
CLK
CK2
t
T0 T1 T2
CKS
t
T3 T4 T6T5 T16T8 T9 T10 T11 T14T12 T13 T15
Burst Length = 4, CAS Latency = 2
CKS
t
T18
T17 T19 T20 T21 T22
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technolo gies 38
13 . Self Refresh (E ntry and Exit)
BS
t
S elf Refresh Exit
Comm and issued
Addr.
DQM
DQ
AP
Entry
Self Refres h
mus t be idle
A ll Banks
Hi-Z
SPT03919-2
Exit Com mand
Begin Self Refresh
SREX
t
RC
Self Refresh
Command
Exit
Any
T7
CS
CAS
WE
RAS
CKE
CLK
t
CKS
T0 T1 T2 T3 T4 T6T5 T16
CKS
t
T8 T9 T10 T11 T14T12 T13 T15 T18T17 T19 T20 T21 T22
*)
*)
minimum RAS cycle
time depends on CAS
Latency and trc
~
~
~
~~
~~
~~
~~
~~
~~
~~
~~
~~
~~
~~
~~
~~
~~
~~
~~
~~
~
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technologies 39
14. Auto Refresh (CBR)
(Minimum Interval)
Addr.
DQM
DQ
AP
BS
Auto Refresh
Command
All Banks
Precharge
Command
Hi-Z
t
RP
t
RC
SPT03920_2
RC
t
RAx
RAx
CAx
T7
WE
CAS
RAS
CS
CKE
CLK
CK2
t
T0 T1 T2 T3 T4 T6T5 T16T8 T9 T10 T11 T14T12 T13 T15
Burst Length = 4, CAS Latency = 2
T18T17 T19 T20 T21 T22
Command
Auto Refre sh CommandCommand
Bank A
Activate
Bank A
Read
Ax2Ax0 Ax1 Ax3
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technolo gies 40
15. Random Column Read (Page within same Bank)
15.1 CAS Latency = 2
Ay1
Addr.
BS
DQ
DQM
AP
Activate
Command
ZHi
Bank A
RAw
RAw
Command
Read
Command
Bank A
Read
Bank A
Aw0 Aw1
CAw CAx
Read
Bank A
Command
Aw3Aw2 Ax0 Ax1 Ay0
CAy
CS
WE
CAS
RAS
CKE
CLK
T0
CK2
t
T1 T2 T8T4T3 T5 T6 T7 T11T9 T10 T12 T13
Precharge
Command
Bank A
Ay2 Ay3
Activate
Command
Bank A
RAz
RAz
SPT03921
Read
Bank A
Command
CAz
Burst Length = 4, CAS Latency = 2
T19T16T15T14 T17 T18 T20 T21 T22
Az3Az0 Az1 Az2
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technologies 41
15.2 CAS Latency = 3
Ay3
CAw
Addr.
BS
DQ
DQM
AP
ZHi
Bank A
Activate
Command Read
Command
Bank A
RAw
RAw
Bank A
Command
Aw1Aw0
Read
Bank A
Command
Aw2 Aw3
CAx
Read
Ax1Ax0 Ay0
Precharge
Command
Bank A
Ay1 Ay2
CAy
CS
WE
CAS
RAS
CKE
CLK
T0
CK3
t
T1 T2 T8T4T3 T5 T6 T7 T11T9 T10 T12 T13
Bank A
Read
Command
Activate
Command
Bank A
RAz
RAz
CAz
SPT03922
Burst Length = 4, CAS Latency = 3
T19T16T15T14 T17 T18 T20 T21 T22
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technolo gies 42
16. Random Column write (Page within same Bank)
16.1 CAS Latency = 2
DBy1
Addr.
BS
DQ
DQM
AP
Activate
Command
ZHi
Bank B
RBw
RBw
Command
Write
Command
Bank B
Write
Bank B
DBw0 DBw1
CBw CBx
Write
Bank B
Command
DBw3DBw2 DBx0 DBx1 DBy0
CBy
CS
WE
CAS
RAS
CKE
CLK
T0
CK2
t
T1 T2 T8T4T3 T5 T6 T7 T11T9 T10 T12 T13
Precharge
Command
Bank B
DBy2 DBy3
Activate
Command
Bank B
RBz
RBz
SPT03923_2
Read
Bank B
Command
CBz
Burst Length = 4, CAS Latency = 2
T19T16T15T14 T17 T18 T20 T21 T22
DBz1DBz0 DBz2 DBz3
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technologies 43
16.2. CAS Latency = 3
Command
Write
Bank B
CBz
DBw0
Addr.
BS
DQ
DQM
AP
Bank B
Activate
Command
ZHi
RBz
RBz
Command
Bank B
DBw3DBw1 DBw2
Write
Bank B
Command
DBx0 DBx1
CBx
Write
DBy1DBy0 DBy2
Precharge
Command
Bank B
DBy3
CBy
CS
WE
CAS
RAS
CKE
CLK
T0
CK3
t
T1 T2 T8T4T3 T5 T6 T7 T11T9 T10 T12 T13
Command
Bank B
DBz0
Activate
Command
Bank B
Write
DBz1
RBz
RBz
CBz
SPT03924
Burst Length = 4, CAS Latency = 3
T19T16T15T14 T17 T18 T20 T21 T22
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technolo gies 44
17. Random Row Read (Interleaving Banks) with Precharge
17.1 CAS Latency = 2
Ax2
t
BS
Addr.
DQ
DQM
AP
Bank B
Activate
Command
Hi-Z
Command
Read
Bank B
RBx
RBx
RCD
t
CBx
Read
Activate
Bank A
Command
Command
Bank B
Command
Bx2Bx0
AC2
Bx1
Bank A
Activate
Bx3 Bx4
RAx
RAx
Command
Precharge
Bank B
Bx6Bx5 Bx7 Ax0 Ax1
CAx RBy
RBy
CS
WE
CAS
RAS
CKE
CLK
T0
High
t
CK2
T1 T2 T8T4T3 T5 T6 T7 T11T9 T10 T12 T13
SPT03925_2
Bank B
Command
Ax5Ax3 Ax4
Read
Ax6 Ax7
CBy
By1By0
Burst Length = 8, C AS Latency = 2
T19T16T15T14 T17 T18 T20 T21 T22
RP
t
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technologies 45
17.2 CAS Latency = 3
Activate
Command
Bank A
Addr.
DQM
DQ
AP
BS
Read
Bank B
Command
Command
Bank B
Activate
Hi-Z Bx1Bx0
CBxRBx
RCD
t
RBx
t
AC3
Activate
Command
Bank B
Bx6
Bank A
Command
Read
Bx4Bx3Bx2 Bx5
Bank B
Precharge
Command
Ax0Bx7 Ax2Ax1
RAx CAx
RAx
RP
t
RBy
RBy
Precharge
Bank A
Command
Ax7
Read
Bank B
Command
Ax5Ax4Ax3 Ax6
SPT03926
By0
CBy
T7
WE
CAS
RAS
CS
CKE
CLK
High
CK3
t
T0 T1 T2 T3 T4 T6T5 T16T8 T9 T10 T11 T14T12 T13 T15
Burst Length = 8, CAS Latency = 3
T18T17 T19 T20 T21 T22
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technolo gies 46
18. Random Row Write (Interleaving Banks) with Precharge
18.1 CAS Latency = 2
DBx4DAx1
BS
AP
Addr.
DQ
DQM
Activate
Command
Bank A
Hi-Z
Write
Command
Bank A
DAx0
RAx
RAx
RCD
t
CAx
CommandCommand
Bank B Bank A
Command
DAx4DAx2 DAx3
Bank B
Activate
DAx5 DAx6
RBx
RBx
Command
Precharge
Bank A
Write
DBx0DAx7 DBx1
Activate
DBx2 DBx3
CBx RAy
RAy
CLK
CKE
CS
RAS
CAS
WE
T0
High
CK2
t
T1 T2 T8T4T3 T5 T6 T7 T11T9 T10 T12 T13
Command
Bank A
SPT03927_2
Command
Precharge
Bank B
DBx7DBx5 DBx6
Write
DAy0 DAy1
CAy
WR
t
DAy4DAy3DAy2
T19
Burst Length = 8, CAS Latency = 2
T16T15T14 T17 T18 T20 T21 T22
WR
t
RP
t
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technologies 47
18.2 CAS Latency = 3
DAx4
Addr.
DQM
DQ
AP
BS
Command
Bank A
Bank A
Activate
Command
Hi-Z
Write
DAx0 DAx1 DAx3DAx2
RAx
RCD
t
RAx
CAx
DBx4DBx0
Write
Command
Bank B
Bank B
Activate
Command
DAx6DAx5 DAx7
Precharge
Command
Bank A
DBx2DBx1 DBx3
CBxRBx
RBx
WR
t
RP
t
Command
Bank A
Activate
Command Bank A
Write
DBx5 DBx6 DAy0DBx7
Precharge
Bank B
Command
SPT03928
DAy1 DAy2 DAy3
WR
RAy
t
CAy
RAy
CAS
RAS
CKE
CLK
WE
CS
T2
High
CK3
t
T0 T1 T4T3 T5 T6 T15T7 T8 T9 T10 T11 T12 T13 T14
Burst Length = 8, CAS Latency = 3
T19T17T16 T18 T21T20 T22
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technolo gies 48
19. Precharge termination of a Burst
19.1 CAS Latency = 2
Command
Activate
Bank A
T14
BS
Write Data is masked.
of a Write Burst.
Precharge Termination
Addr.
DQ
DQM
AP
Command
Bank A
Activate
Hi Z
Bank A
Write
Command
DAx0 DAx1
RAx
RAx
CAx
Command
Bank A
Command
Precharge
Bank A
DAx3DAx2
Activate
RAy
RP
t
RAy
Ay0
Command
Bank A
Read
Bank A
Precharge
Command
Ay1 Ay2
CAy
RP
t
T3
CS
WE
CAS
RAS
CKE
CLK
T0
High
CK2
t
T1 T2 T4 T5 T7T6 T8 T10T9 T11 T13T12
Precharge Termination
of a Read Burst.
SPT03933
Bank A
Command
Precharge
Command
Bank A
Read
Az0 Az1
RAz CAz
RAz
Az2
RP
t
Burst Length = 8 or Full Page, CAS Latency = 2
T20
T17T15 T16 T18 T19 T21 T22
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technologies 49
20. Full Page Burst Operation
20.1 Full Page Burst Read, CAS Latency = 2
BS
-
page address back to zero
from the highest order
The burst counter wraps
during this time interval.
Addr.
DQM
DQ
AP
~
~
Hi-Z
CommandCommand
Bank A
Read
Bank A
Activate
Bank BBank B
CommandCommand
Ax
ActivateActivate
Ax
+1 Ax
~
~
+2 Ax
RAx
RAx
CAx
~
~
~
~
RBx
RBx
~
~
~
~
~
~
~
~
SPT03929
bursting beginning with the starting address.
Burst Stop
Command
the burst counter increments and continues
terminate when the burst length is satisfied;
Full Page burst operation does not
Bank B
Command
Ax
Read
-2Ax11Ax+
Bx
Bx+1 Bx+2 +Bx 3 +Bx 4
CBx
Bank B
Command
Activate
Command
Bank B
Precharge
Bx5Bx+ 6+
RBy
t
RP
RBy
CAS
RAS
CKE
CLK
CS
WE
~
~
~
~
~
~
~
~
~
~
~
~
~
~
High
CK2
t
T0 T1 T2
~
~
~
~
T3 T4
~
~
~
~
T5 T6 T15T11T7 T8 T10T9 T13T12 T14
Burst Length = Full Page, CAS Latency = 2
T16 T17 T18 T19 T20 T21 T22
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technolo gies 50
20. Full Page Burst Operation
20.2 Full Page Burst Write, CAS Latency = 3
T14
Bx
Full Page burst operation does not
terminate when the burst length is satisfied;
bursting beginning with the starting address.
the burst counter increments and continues
BS
Command
Bank A
AP
DQM
DQ
Addr.
Command
Activate
Bank A
Hi-Z
Read
RAx
RAx
CAx
page address back to zero
during this time interval.
The burst counter wraps
from the highest order
ActivateActivate
Bank BBank B
CommandCommand
Ax
Ax 1+ 2Ax+ Ax
~
~
~
~
-
RBx
RBx
~
~
~
~
~
~
~
~
~
~
~
~
Ax
Read
Bank B
Command
Ax21-
Ax
1+
Bx
Bx 1+
CBx
T3
CLK
CKE
CS
RAS
WE
CAS
T0
High
CK3
t
T1 T2
~
~
~
~
~
~
~
~
~
~
~
~
~
~
T4 T5
~
~~
~
~
~
T7T6 T8
~
~
T10T9 T11 T13T12
SPT03930
Bank B
Command
Activate
Bank B
Precharge
Command
Burst Stop
Command
++2 Bx Bx34+ 5+Bx
RBy
t
RRD
RBy
T20
Burst Length = Full Page, CAS Latency = 3
T17T15 T16 T18 T19 T21 T22
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technologies 51
TABLE OF CONTENTS
128-MBit Synchronous DRAM page 1
Ordering Information page 2
Pin Def initions and Functions page 2
Pin Configuration for x4, x8 & x16 Organized 128M-DRAMs page 3
Functional Block Diagrams page 4
Block Di agram: 32M x4 SDR AM (12 / 11 / 2 addressing page 4
Block Diagram: 16M x8 SDRAM (12 / 10 / 2 addressing) page 5
Block Di agram: 8M x16 SDRA M (12 / 9 / 2 addressing) pa ge 6
Signal Pin Description page 7
Operation Definition page 9
Ad dres s Inp uts for Mo de Regist er S et Ope r at ion p ag e 1 0
Power On and Initialization page 11
Progra mming the Mode Register page 11
Read and Write Operation page11
Refresh Mode page 12
Burst Length and Sequence page 13
DQM Function page 13
Power Down page 13
Auto Precharge page 13
Precharge C ommand page 13
Burst Termina tio n. page 14
Bank Selection by Address Bits page 14
Electrical Characteristics page 15
Absolute Maximum Ratings page 15
Recomm ended Operat ion and DC Characteristic s page 15
Capacitance page 15
Op er a tin g C urr e nt s page 1 6
AC C ha r ac te ris t i cs pag e 1 7
Package Outlines. page 20
Table of Content. page 21
Timing DIagrams. page 22
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technolo gies 52
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As far as patents or other rights of third parties are concerned, liability is only
assumed for components, not for applications, processes and circuits
implemented within components or assemblies. This infomation describes
the type of components and shall not be considered as assured
characteristics. Terms of delivery and rights to change des ign reserved.
For quest ions on t echnology, d elivery an d prices please c ontact INFINEON
Technologies Offices in Munich or the INFINEON Technologies Sales Offices
and Representatives worldwide.
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substances. For information on the types in question please contact your
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Components used in life-support devices or systems must be expressly
authorized for such pu rpo se!
Ciritcal components1 of INFINEON Technologies, may only be used in life-
support devices or systems2 with the express written approv al of INFINEON
Technologies.
1. A critical component is a component used in a life-support device or system
whose failure can reasonably be expected to cause the failure of that life-
support device or system, or to affect the safety or effectiveness of that device
or syst em.
2. Life support devices or systems are intended (a) to be implanted in the
human body, or (b) to support and/or maintain and sust ain human life. If t hey
fail, it is reasonable to assume that the health of the user may be endangered.
