LTC1257CS8#TRPBF - ANALOG DEVICES

LTC1257

1257fc

TYPICAL APPLICATION

FEATURES DESCRIPTION

Complete Single Supply

12-Bit Voltage Output

DAC in SO-8

The LT C

1257 is a complete single supply, 12-bit voltage

output D/A converter (DAC) in an SO-8 package. The

LTC1257 includes an output buffer amplifier, 2.048V volt-

age reference and an easy to use 3-wire cascadable serial

interface. An external reference can be used to override

the internal reference and extend the output voltage range

to 12V. The power supply current is a low 350µA when

operating from a 5V supply, making the LTC1257 ideal

for battery-powered applications. The space-saving 8-pin

SO package and operation with no external components

provide the smallest 12-bit D/A system available.

Daisy-Chained Control Outputs Differential Nonlinearity

vs Input Code

APPLICATIONS

n 8-Pin SO Package

n Buffered Voltage Output

n Built-In 2.048V Reference

n 500µV/LSB with 2.048V Full Scale

n 1/2LSB Max DNL Error

n Guaranteed 12-Bit Monotonic

n 3-Wire Cascadable Serial Interface

n Wide Single Supply Range: VCC = 4.75V to 15.75V

n Low Power: ICC Typ = 350µA with 5V Supply

n Digital Offset/Gain Adjustment

n Industrial Process Control

n Automatic Test Equipment

L, LT , LT C , LT M , Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

µP

0.1µF

CONTROL OUTPUT 1

CONTROL OUTPUT 2

VCC

VREF

GND

VOUT

DIN

CLK

LOAD

DOUT

LTC1257

VCC

VREF

GND

VOUT

DIN

CLK

LOAD

DOUT

LTC1257

TO NEXT DAC

1257 TA01

CODE

DNL ERROR (LSBs)

0.5

0.0

–0.5

1024 2048 2560

1257 TA05

512 1536 3072 3584 4098

LTC1257

1257fc

ABSOLUTE MAXIMUM RATINGS

VCC to GND ............................................. –0.5V to 16.5V

TTL Input Voltage .......................... –0.5V to VCC + 0.5V

VOUT ................................................ –0.5V to VCC + 0.5V

REF ................................................. –0.5V to VCC + 0.5V

Operating Temperature Range

LTC1257C ................................................ 0°C to 70°C

LTC1257I ............................................. –40°C to 85°C

(Note 1)

ORDER INFORMATION

ELECTRICAL CHARACTERISTICS

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC1257CN8#PBF LTC1257CN8#TRPBF LTC1257CN8 8-Lead PDIP 0°C to 70°C

LTC1257IN8#PBF LTC1257IN8#TRPBF LTC1257IN8 8-Lead PDIP –40°C to 85°C

LTC1257CS8#PBF LTC1257CS8#TRPBF 1257 8-Lead Plastic SO 0°C to 70°C

LTC1257IS8#PBF LTC1257IS8#TRPBF 1257I 8-Lead Plastic SO –40°C to 85°C

Consult LT C Marketing for parts specified with wider operating temperature ranges.

Consult LT C Marketing for information on nonstandard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

TOP VIEW

N8 PACKAGE

8-LEAD PDIP

VCC

VOUT

REF

GND

CLK

DIN

LOAD

DOUT

TJMAX = 125°C, θJA = 100°C/W

TOP VIEW

S8 PACKAGE

8-LEAD PLASTIC SO

VCC

VOUT

REF

GND

CLK

DIN

LOAD

DOUT

TJMAX = 125°C, θJA = 150°C/W

PIN CONFIGURATION

Maximum Junction Temperature

Plastic Package ...................................... –65°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec) ................... 300°C

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = TMIN to TMAX. VCC = 4.75V to 15.75V, internal or external reference

(2.475V ≤ VREF ≤ VCC – 2.7V), unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

DAC

Resolution l12 Bits

DNL Differential Nonlinearity Guaranteed Monotonic (Note 4) l±0.5 LSB

INL Integral Nonlinearity LTC1257C (Note 4)

LTC1257I (Note 4)

±3.5

±4.0

LSB

LTC1257

1257fc

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = TMIN to TMAX. VCC = 4.75V to 15.75V, internal or external reference

(2.475V ≤ VREF ≤ VCC – 2.7V), unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

OFF Offset Error When Using Internal Reference, LTC1257C

When Using Internal Reference, LTC1257I

±8

±10

LSB

When Using External Reference, LTC1257C

When Using External Reference, LTC1257I

±4

±5

OFFTC Offset Error Tempco When Using Internal Reference (Note 2)

When Using External Reference (Note 2)

±0.02

±15

±0.066

±30

LSB/°C

µV/°C

Gain Error l0.5 ±2 LSB

Gain Error Tempco (Note 2) l±0.01 ±0.02 LSB/°C

Reference

Reference Output Voltage IREF = 0, LTC1257C

IREF = 0, LTC1257I

2.028

2.018

2.048 2.068

2.078

Reference Output Tempco IREF = 0 l±0.06 LSB/°C

Reference Line Regulation IREF = 0, LTC1257C

IREF = 0, LTC1257I

±0.4

±0.7

LSB/V

Reference Load Regulation 0µA ≤ IREF ≤ 100µA l±1 LSB

Reference Input Range VCC > VREF + 2.7V l2.475 12 V

Reference Input Resistance l8 14 18 kΩ

Reference Input Capacitance (Note 2) 15 pF

Short-Circuit Current VREF Shorted to GND l90 mA

Power Supply

VCC Positive Supply Voltage For Specified Performance l4.75 15.75 V

ICC Supply Current 4.75V ≤ VCC ≤ 5.25V

4.75V ≤ VCC ≤ 15.75V

350

800

600

1500

µA

Op Amp DC Performance

Short-Circuit Current Low VOUT Shorted to GND l60 mA

Short-Circuit Current High VOUT Shorted to VCC l60 mA

Output Impedance to GND Input Code = 0 l250 500 Ω

AC Performance

Voltage Output Slew Rate 5kΩ in Parallel with 100pF l1.0 V/µs

Voltage Output Settling Time To ±1/2LSB, 5kΩ in Parallel with 100pF, VCC = 4.75V 6 µs

Digital Feedthrough (Notes 2, 3) 50 nV/s

Digital I/O

VIH Digital Input High Voltage l2.4 V

VIL Digital Input Low Voltage l0.8 V

VOH Digital Output High Voltage IOUT = –1mA, DOUT Only lVCC – 1 V

VOL Digital Output Low Voltage IOUT = 1mA, DOUT Only l0.4 V

ILEAK Digital Input Leakage VIN = GND to VCC l±10 µA

CIN Digital Input Capacitance (Note 2) l10 pF

Switching (Note 2)

t1DIN Valid to CLK Setup l100 ns

t2DIN Valid to CLK Hold l25 ns

t3CLK High Time l350 ns

t4CLK Low Time l350 ns

LTC1257

1257fc

TYPICAL PERFORMANCE CHARACTERISTICS

Supply Current

vs Logic Input Voltage Output Swing vs Load Resistance

Pull-Down Voltage

vs Output Sink Current Capability

Minimum Supply Voltage

vs Load Current #1

Minimum Supply Voltage

vs Load Current #2 Supply Current vs Temperature

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = TMIN to TMAX. VCC = 4.75V to 15.75V, internal or external reference

(2.475V ≤ VREF ≤ VCC – 2.7V), unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

t5LOAD Pulse Width l150 ns

t6LSB CLK to LOAD l0 ns

t7LOAD High to CLK l0 ns

t8DOUT Output Delay CLOAD = 15pF l35 150 ns

fCLK Maximum Clock Frequency 1.4 MHz

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: Guaranteed by design; not subject to test.

Note 3: DAC switched from all 1s to all 0s, and all 0s to all 1s code.

Note 4: Guaranteed with internal VREF or with external VREF range of

2.475V to 12V. Tested at 10V.

OUTPUT LOAD CURRENT (mA)

0.01

MINIMUM SUPPLY VOLTAGE (V)

0.1 1 10

1257 G01

5.0

4.8

4.6

4.4

4.2

4.0

3.8

3.6

3.4

3.2

3.0

VREF = INTERNAL

VOUT = FULL SCALE

TA = 25°C

OUTPUT LOAD CURRENT (mA)

0.01

MINIMUM SUPPLY VOLTAGE (V)

0.1 1 10

1257 G02

15.0

14.5

14.0

13.5

13.0

12.5

12.0

11.5

11.0

VREF = 10V

VOUT = FULL SCALE

TA = 25°C

TEMPERATURE (°C)

–50

0.38

0.37

0.36

0.35

0.34

0.33

0.32

0.31

25 75

1257 G03

–25 0 50 100 125

SUPPLY CURRENT (mA)

VCC = 5.25V

VCC = 5V

VCC = 4.75V

LOGIC VOLTAGE (V)

SUPPLY CURRENT (mA)

0.59

0.54

0.49

0.44

0.39

0.34 4

1257 G04

1235

VCC = 5V

TA = 25°C

LOAD RESISTANCE (Ω)

OUTPUT VOLTAGE SWING (V)

100 1k 10k

1257 G05

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

FULL SCALE

RL TIED TO GND

ZERO SCALE

RL TIED TO VCC

VCC = 5V

OUTPUT SINK CURRENT (µA)

OUTPUT PULL-DOWN VOLTAGE (mV)

1000

100

0.1 10 100 1000

1257 G06

HOT

COLD

ROOM

LTC1257

1257fc

TYPICAL PERFORMANCE CHARACTERISTICS

Differential Nonlinearity (DNL)

Reference Compensation

Resistance vs CLBroadband Noise

Full-Scale Voltage

vs Temperature

Zero-Scale Voltage

vs Temperature Integral Nonlinearity (INL)

TEMPERATURE (°C)

–50

FULL-SCALE VOLTAGE (V)

2.0495

2.0490

2.0485

2.0480

2.0475

2.0470

2.0465 25 75

1257 G07

–25 0 50 100 125

VCC = 5V

INTERNAL REFERENCE

TEMPERATURE (°C)

–50 –25 25 50

ZERO-SCALE VOLTAGE (mV)

75 100

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

1257 G08

0 125

VCC = 5V

INTERNAL REFERENCE

CODE

ERROR (LSB)

2.0

1.6

1.2

0.8

0.4

–0.4

–0.8

–1.2

–1.6

–2.0

1024 2048 2560

1257 G09

512 1536 3072 3584 4096

VCC = 5V

INTERNAL REFERENCE

TA = 25°C

CODE

DNL ERROR (LSBs)

0.5

0.0

–0.5

1024 2048 2560

1257 TA05

512 1536 3072 3584 4098

CL (µF)

0.01

REFERENCE COMPENSATION RESISTANCE (Ω)

0.1 1

1257 G11

10 100 TIME = 5ms/DIV

0.1V/DIV

1257 G12

CODE = FFFH

BW = 3Hz TO 1MHz

GAIN = 1100×

PIN FUNCTIONS

CLK (Pin 1): The TTL level input for the serial interface clock.

DIN (Pin 2): The TTL level input for the serial interface

data. Data on the DIN pin is latched into the shift register

on the rising edge of the serial clock.

LOAD (Pin 3): The TTL level input for the serial interface

load control. Data is loaded from the shift register into the

DAC register, thus updating the DAC output when LOAD

is pulled low. The DAC register is transparent as long as

LOAD is held low.

DOUT(Pin 4): The output of the shift register which becomes

valid on the rising edge of the serial clock. The DOUT pin

is driven from GND to VCC by an internal CMOS inverter.

Multiple LTC1257s may be cascaded by connecting the

DOUT pin to the DIN pin of the next chip.

GND (Pin 5): Ground.

REF (Pin 6): The output of the 2.048V reference and the

input to the DAC resistor ladder. An external reference

with voltage from 2.475V to VCC – 2.7V may be used to

override the internal reference.

LTC1257

1257fc

PIN FUNCTIONS

DEFINITIONS

VOUT (Pin 7): The buffered DAC output is capable of

sourcing 2mA over temperature while pulling within 2.7V

of VCC. The output will pull to ground through an internal

250Ω equivalent resistance.

VCC (Pin 8): The positive supply input. 4.75V ≤ VCC ≤

15.75V. Requires a bypass capacitor to ground.

LSB: The least significant bit or the ideal voltage difference

between two successive codes.

LSB = (VFS – VOS)/2n – 1

n = The number of digital input bits

VOS = The zero code error or offset of the DAC

VFS = The full-scale output voltage of the DAC

measured when all bits are set to 1

Resolution: The resolution is the number of DAC output

states (2n) that divide the full-scale range. The resolution

does not imply linearity.

INL: End-point integral nonlinearity is the maximum devia-

tion from a straight line passing through the end-points of

the DAC transfer curve. Because the part operates from

a single supply and the output cannot go below ground,

the linearity is measured between full-scale and the first

code that guarantees a positive output. The INL error at

a given input code is calculated as follows:

INL = (VOUT – VIDEAL)/LSB

VIDEAL = (Code)(LSB) + VOS

VOUT = The output voltage of the DAC measured at

the given input code

DNL: Differential nonlinearity is the difference between

the measured change and the ideal 1LSB change between

any two adjacent codes. The DNL error between any two

codes is calculated as follows:

DNL = (∆VOUT – LSB)/LSB

∆VOUT = The measured voltage difference between two

adjacent codes

Offset Error: The theoretical voltage at the output when

the DAC is loaded with all zeros. The output amplifier can

have a true negative offset, but because the part is oper-

ated from a single supply, the output cannot go below

ground. If the offset is negative, the output will remain

near 0V resulting in the transfer curve shown in Figure 1.

The offset of the part is measured at the first code that

produces an output voltage 0.5LSB greater than the

previous code:

VOS = VOUT – [(Code)(VFS)/(2n – 1)]

Full-Scale Error: Full-scale error is the difference between

the ideal and measured DAC output voltages with all bits

set to one (Code = 4095). The full-scale error includes the

offset error and is calculated as follows:

FSE = (VOUT – VIDEAL)/LSB

VIDEAL = (VREF)(1 – 2–n) – VOS

VREF = The reference voltage, either internal or external

Gain Error: Gain error is the difference between the ideal

and measured slope of the DAC transfer characteristic.

Gain error is equal to full-scale error minus offset error.

Digital Feedthrough: The glitch that appears at the analog

output caused by AC coupling from the digital inputs when

they change state. The area of the glitch is specified in

(nV)(sec).

OUTPUT

VOLTAGE

NEGATIVE

OFFSET

{

DAC CODE 0V

1257 F01

Figure 1. Effect of Negative Offset

LTC1257

1257fc

BLOCK DIAGRAM

TIMING DIAGRAM

–

DAC

5V REGULATOR

12-BIT

SHIFT REGISTER

12-BIT LATCH

2.048V REFERENCE

VCC

DOUT

GND

VOUT

DIN

LOGIC

SUPPLY

CLK

LOAD

REF 12

1257 BD

B10

B11

(PREVIOUS WORD)

B11

MSB B10

LSB

B0 B11

CURRENT WORD

t4t3

CLK

DIN

DOUT

LOAD

1257 TD

LTC1257

1257fc

TYPICAL APPLICATIONS

OPERATION

Serial Interface

The data on the DIN input is loaded into the shift register

on the rising edge of the clock. The MSB is loaded first

and the LSB last. The DAC register loads the data from

the shift register when LOAD is pulled low, and remains

transparent until LOAD is pulled high and the data is latched.

An internal 5V regulator provides the supply for the digital

logic. By limiting the internal digital signal swings to 5V,

digital noise is reduced. The buffered output of the 12-bit

shift register is available on the DOUT pin which will swing

from GND to VCC.

Multiple LTC1257s may be daisy chained together by

connecting the DOUT pin to the DIN pin of the next chip,

while the clock and load signals remain common to all

chips in the daisy chain. The serial data is clocked to all

of the chips, then the LOAD signal is pulled low to update

all of them simultaneously. The maximum clocking rate

is 1.4MHz.

Reference

The LTC1257 includes an internal 2.048V reference, mak-

ing 1LSB equal to 500µV. The internal reference output

is turned off when the pin is forced above the reference

voltage, allowing an external reference to be connected to

the reference pin. The external reference must be greater

than 2.475V and less than VCC – 2.7V, and be capable of

driving the 10k minimum DAC resistor ladder.

If the reference output is driving a large capacitive load, a

series resistor must be added to insure stability. For any

capacitive load greater than 1µF, a 10Ω series resistor

will suffice.

Voltage Output

The LTC1257 voltage output is able to pull within 2.7V of

VCC while sourcing 2mA. A internal NMOS transistor with

a 200Ω equivalent impedance pulls the output to ground.

The output is protected against short circuits and is able

to drive up to a 500pF capacitive load without oscillation.

If digital noise on the output causes a problem, a simple

100Ω, 0.1µF RC circuit can be used to filter the noise.

DAC with External Reference Filtering VREF and VOUT

µP

15V

0.1µF

CONTROL OUTPUT

VCC VREF

GND

VOUT

DIN

CLK

LOAD

DOUT

LTC1257

1257 TA03

OUT

GND

LT1021-10 0.1µF

0.1µF

1µF

VCC

VREF

GND

VOUT VOUT

DIN

CLK

LOAD

DOUT

LTC1257

1257 TA06

10Ω

100Ω

LTC1257

1257fc

TYPICAL APPLICATIONS

Auto Ranging 8-Channel ADC with Shutdown

12-Bit Single 5V Control System with Shutdown

0.1µF VCC

VREF

VOUT

DIN

CLK

LOAD

DOUT

LTC1257

VCC

VREF

GND

VOUT

DIN

CLK

LOAD

DOUT

LTC1257

1257 TA02

0.1µF

100Ω

µP

8 ANALOG

INPUT CHANNELS LTC1296

DOUT

CLK

DIN

CH0

•

CH7

COM

REF+REF–SSO

22µF

50k 50k

VCC

74HC04

GND

1µF

CONTROL

OUTPUT

VCC

VREF

GND

VOUT

DIN

CLK

LOAD

DOUT

LTC1257 1257 TA04

2N3906

–IN CB/POWER DOWN

CLK

DATA

DAC LOAD

–

VCC CS

DOUT

CLK

+IN

LTC1297

ADC

VREF

GND

0.1µF

10µF

VIN

LT1025A

COMMONGND

74k

10µF

–

100k 10k

100k

1µF

47k

LTC1050

µP

LTC1257

1257fc

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

N8 REV I 0711

.065

(1.651)

TYP

.045 – .065

(1.143 – 1.651)

.130 ±.005

(3.302 ±0.127)

.020

(0.508)

MIN

.018 ±.003

(0.457 ±0.076)

.120

(3.048)

MIN

.008 – .015

(0.203 – 0.381)

.300 – .325

(7.620 – 8.255)

.325 +.035

–.015

+0.889

–0.381

8.255

( )

1 2 34

87 65

.255 ±.015*

(6.477 ±0.381)

.400*

(10.160)

MAX

NOTE:

1. DIMENSIONS ARE INCHES

MILLIMETERS

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)

.100

(2.54)

BSC

N Package

8-Lead PDIP (Narrow .300 Inch)

(Reference LTC DWG # 05-08-1510 Rev I)

.016 – .050

(0.406 – 1.270)

.010 – .020

(0.254 – 0.508)× 45°

0°– 8° TYP

.008 – .010

(0.203 – 0.254)

SO8 REV G 0212

.053 – .069

(1.346 – 1.752)

.014 – .019

(0.355 – 0.483)

TYP

.004 – .010

(0.101 – 0.254)

.050

(1.270)

BSC

1234

.150 – .157

(3.810 – 3.988)

NOTE 3

8765

.189 – .197

(4.801 – 5.004)

NOTE 3

.228 – .244

(5.791 – 6.197)

.245

MIN .160 ±.005

RECOMMENDED SOLDER PAD LAYOUT

.045 ±.005

.050 BSC

.030 ±.005

TYP

INCHES

(MILLIMETERS)

NOTE:

1. DIMENSIONS IN

2. DRAWING NOT TO SCALE

3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)

4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE

S8 Package

8-Lead Plastic Small Outline (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1610 Rev G)

LTC1257

1257fc

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

C 12/12 Removed MAX Voltage Output Settling Time value in Electrical Characteristics section 3

(Revision history begins at Rev C)

LTC1257

1257fc

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

 LINEAR TECHNOLOGY CORPORATION 1994

LT 1212 REV C • PRINTED IN USA

RELATED PARTS

TYPICAL APPLICATION

Driving LTC1257 with Opto-Isolators

LT1021-5

VOUT VIN

12V

VREF

GND

CLK

VOUT VOUT

0.1µF

VCC

DIN

CLK

DIN

LOAD

DOUT

LTC1257

MOC5008

LOAD

1257 TA07

PART NUMBER DESCRIPTION COMMENTS

12 Bit

LTC1446/LTC1446L Dual 12-Bit VOUT DACs in SO-8 Package LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V

LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V

LTC1448 Dual 12-Bit VOUT DAC in SO-8 Package, VCC: 2.7V to 5.5V Output Swings from GND to REF, REF Input Can Be

Tied to VCC

LTC1450/LTC1450L Single 12-Bit VOUT DACs with Parallel Interface LTC1450: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V

LTC1450L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V

LTC1451 Single Rail-to-Rail 12-Bit VOUT DAC, Full Scale: 4.095V, VCC: 4.5V to 5.5V,

Internal 2.048V Reference Brought Out to Pin

Low Power, Complete VOUT DAC in SO-8 Package

LTC1452 Single Rail-to-Rail 12-Bit VOUT Multiplying DAC, VCC: 2.7V to 5.5V Low Power, Multiplying VOUT DAC with Rail-to-Rail

Buffer Amplifier in SO-8 Package

LTC1453 Single Rail-to-Rail 12-Bit VOUT DAC, Full Scale: 2.5V, VCC: 2.7V to 5.5V 3V, Low Power, Complete VOUT DAC in SO-8 Package

LTC1454/LTC1454L Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V

LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V

LTC1456 Single Rail-to-Rail Output 12-Bit DAC with Clear Pin, Full Scale: 4.095V,

VCC: 4.5V to 5.5V

Low Power, Complete VOUT DAC in SO-8 Package with

Clear Pin

LTC1458/LTC1458L Quad 12 Bit Rail-to-Rail Output DACs with Added Functionality LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V

LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V

LTC1659 Single Rail-to-Rail 12-Bit VOUT DAC in MSOP-8 Package,

VCC = 2.7V to 5.5V

Output Swings from GND to REF, REF Input Can Be

Tied to VCC

14 Bit

LTC1658 14-Bit Rail-to-Rail Micropower DAC in MSOP, VCC = 2.7V to 5.5V Output Swings from GND to REF, REF Input Can Be

Tied to VCC

LTC1654 Dual 14-Bit VOUT DAC Programmable Speed/Power, SO-8 Footprint

16 Bit

LTC1655(L) Single 16-Bit VOUT DAC with Serial Interface in SO-8 VCC = 5V (3V), Low Power, Deglitched,

VOUT = 0V to 4.096V (0V to 2.5V)